TOA1211

COMPUTER ORGANIZATION AND

ARCHITECTURE

Lec04
Control Unit Operation
 Topics for discussion

How decomposing of the functioning of the processor into

elementary operations (micro operations) is done
- for various cycles with examples
How the control unit causes the sequence to occur?
- Model for the control unit
- Two basic functions (Sequencing/Execution)
- Data paths and Control Signals – An Example
CPU with internal bus – organization

2
 Micro-Operations

Program Execution
Consists of the sequential execution of instructions
subdivided into various instruction cycles
Instruction Cycle
divided into subtasks
Fetch, indirect, execute and interrupt with fetch and execute always occurring
Micro-operations
Each cycle made up of a sequence of more fundamental operations
called micro-operations.
The prefix micro means that each step is very simple and accomplishes very
little.
Functional, or atomic operations of a processor
micro-operations may involve
- transfer between registers
- between registers and external bus
- a simple ALU operation 3
Constituent Elements of Program Execution

4
 Control Unit Tasks
Two tasks performed by the control unit of a processor:
Causes the processor to execute micro-ops in the proper sequence
determined by the program being executed
Generates the control signals that cause each micro-op to be executed.

The control signals generated by the Control Unit

Cause the opening and closing of logic gates
Results in the transfer of data to and from registers and the operation of
the ALU.

5
 Techniques for implementing Control Unit

Hard-wired Implementation:
The Control Unit is a combinatorial circuit.
Its input logic signals, governed by the current machine instruction, are
transferred into a set of output control signals
Microprogrammed Implementation/Control (MI):
The logic of the Control Unit is specified by a microprogram
Each machine language instruction is translated into a sequence of
lower-level control unit instructions
• Called microinstructions
• Process of translation is called microprogramming
A microprogram consists of a sequence of instructions in a
microprogramming language

6
 Micro-Operations – Fetch Cycle (1)...

Fetch cycle occurs at the beginning of each instruction.

In this operation four registers are involved.
Memory Address Register (MAR)
• Connected to address lines of the system bus
• Specifies address for read or write operation
Memory Buffer Register (MBR)
• Connected to data lines of the system bus
• Holds data to stored in memory or the last data read from memory
Program Counter (PC)
• Holds address of next instruction to be fetched
Instruction Register (IR)
• Holds last instruction fetched

7
Micro-Operations – Fetch Cycle (2)...
- Data Flow

8
 Micro-Operations – Fetch Cycle (3)...
- Sequence

STEP 1:Identification of the memory location

The address of next instruction to be executed is in PC
Move that address to the MAR (this is the only register connected to the
address lines of the system bus)
STEP 2: Bringing the instruction from memory
Address (MAR) is placed on address bus
Control unit issues READ command on the control bus
Result (data from memory) appears on data bus
Data from data bus copied into MBR
PC incremented by I (in parallel with data fetch from memory) – I is
the instruction length
STEP 3: Move the contents of the MBR to IR
MBR is now free for further data fetches
9
 Micro-Operations – Fetch Cycle (4)...
- Sequence of events

MAR MAR 0000000001100100 0064H

MBR MBR 0001000000100000 1020H
PC 0000000001100100 0064H PC 0000000001100101 0065H
IR IR
AC AC
(a) Beginning (c) Second Step
MAR 0000000001100100 MAR 0000000001100100 0064H
0064H
MBR MBR 0001000000100000 1020H
PC 0000000001100100 0064H PC 0000000001100101 0065H
IR IR 0001000000100000 1020H
AC AC

(b) First Step (d) Third step

10
 Micro-Operations – Fetch Cycle (5)...
Symbolic Sequence of events

t1: MAR <- (PC) (t1 - first time unit)

t2: MBR <- Memory (t2-second time unit)
PC <- (PC) +I (I-Instruction Length)
t3: IR <- (MBR) (t3-third time unit)
t1, t2, t3 are successive time units.

Or

t1 : MAR <- (PC)

t2 : MBR <- Memory
t3 : PC <- (PC) +I
IR <- (MBR)

11
 Micro-Operations – Fetch Cycle (6)
- Rules to follow

Two Rules for groupings of micro-operations:

Proper sequence of events must be followed
• (MAR <- (PC)) must precede (MBR <- Memory)
– because memory read operation makes use of the address in MAR
Conflicts must be avoided
• Must not read & write with same register at same time-results
unpredictable
• (MBR <- Memory) & (IR <- (MBR)) must not be in same time unit

Note:
PC <- (PC) +I involves addition
Use ALU
May need additional micro-operations

12
 Micro-Operations - Indirect Cycle (1)...

After Instruction Fetch - Indirect Cycle before execute cycle if

the instruction specifies an indirect address
Assume one-address instruction format
Micro-operations for indirect cycle
t1: MAR <- (IRaddress) (move address part of IR contents to MAR)

t2: MBR <- memory

(MAR now is used to fetch the address of the operand
address field of IR is updated from MBR
t3: IRaddress <- (MBRaddress) Now IR contains the direct address)

MBR contains an address

IR is now in same state as if direct addressing had been used
13
Micro-Operations - Indirect Cycle (2)

14
 Micro-Operations - Interrupt cycle (1)...

At the completion of execute cycle, if enabled interrupts have

occurred, microprocessor will enter interrupt cycle
Nature of cycle varies from one machine to another
Simple sequence of events
t1: MBR (PC)
(contents of PC transferred to MBR for saving to enable return from interrupt)
t2: MAR Save_address (MAR with stack address)
PC Routine_address (PC with ISR address)
t3: Memory (MBR) (store the old value of PC into stack )

15
Micro-Operations - Interrupt Cycle (2)

16
 Micro-Operations - Execute Cycle (1)…

The fetch, indirect, and interrupt cycles are simple and predictable.
Each involves a small, fixed sequence of micro-ops that are
repeated each time
The execute cycle is different for each Opcode
machine with n different opcodes - n different sequences of micro-operations
Example 1:
ADD R1, X - add the contents of location X to Register R1
Suppose IR contains the ADD instruction
t1: MAR (IRaddress) (The address portion of IR is loaded into MAR)

t2: MBR memory (The referenced memory location is read)

t3: R1 R1 + (MBR) (The content of R1 and MBR are added by the ALU)

Additional micro-operations may be required

To extract register reference from IR
Store ALU I/O in intermediate registers
17
 Micro-Operations - Execute Cycle (2)…

Example 2:
ISZ X (Increment and Skip if Zero)
(The contents of location X is incremented by 1.
If the result is 0, the next instruction is skipped)
t1: MAR (IRaddress)
t2: MBR Memory
t3: MBR (MBR) +1
t4: Memory (MBR)
If ((MBR)=0) then (PC (PC) + 1)
Test and action - implemented as one micro-operation
updated value storage and test and action can be performed
during the same time unit
18
 Micro-Operations - Execute Cycle (3)

Example 3:
BSA X ( Branch and Save address)
(Subroutine Call Instruction - Address of instruction that
follows the BSA instruction saved in location X and execution
starts from location X+I)
t1: MAR (IRaddress)
MBR (PC)
t2: PC (IRaddress)
Memory (MBR)
t3: PC (PC)+I

19
 Flowchart for Instruction Cycle (1)...
– Complete Sequence of micro-operations
Assume a new 2-bit reg. called instruction cycle code (ICC)
Instruction cycle code (ICC) designates which part of cycle
processor is in
ICC : 00=Fetch, 01=Indirect, 10= Execute,11=Interrupt
Indirect cycle - always followed by execute cycle
Interrupt cycle- always followed by fetch cycle
Fetch cycle- depends upon the state - indirect addressing used
or not
Execute cycle - depends upon whether the enabled interrupt has
occurred or not
Summary: Operation of the processor is defined as the
performance of a sequence of micro-operations
20
 Flowchart for Instruction Cycle (2)
– Complete Sequence of micro-operations

21
 Functional Requirements of the Control Unit
Behavior or functioning of the CPU was decomposed into
elementary operations called micro-operations.
Define the functional requirements of the Control Unit (those
functions that the Control Unit must perform)
Basis for the design and implementation of the control unit
Three-step process that leads to a characterization of the CU:
Define the basic elements of the processor
Describe micro-operations that the processor performs
Determine the functions that the CU must perform to cause a micro-op
to be performed

22
 Basic Elements of Processor
Execution of a program consists of operations involving the
following processor elements
ALU
• Essential functional unit of the CPU
Registers
• Store data internal to the CPU
• e.g. status information to manage instruction sequencing (program status word); data
that go to or come from the ALU, memory and I/O modules
Internal data paths
• Used to move data between registers, and between registers and ALU
External data paths
• Link registers to memory and I/O modules (system bus)
Control Unit
• Causes operation to happen within the CPU

23
 Types of Micro-operation Categories
Operations involving processor elements consists of a sequence
of micro-operations
Categories of micro-operations
Transfer data between registers
Transfer data from register to an external interface
• e.g. system bus
Transfer data from an external interface to a register
Perform arithmetic or logical operations, using registers for input and
output.

24
 Functions of Control Unit (CU)

The control unit performs two basic tasks:

Sequencing
Based on the program being executed, the CPU causes the proper
sequencing of micro-operations
Execution
The Control Unit causes each micro-operation to be performed

This is done by using Control Signals

25
Model of Control Unit (1)...
 Model of Control Unit (2)...
- Control Signals (Input)
Clock
One micro-instruction (or set of parallel micro-instructions) per clock
cycle
Instruction register
Op-code and addressing mode of current instruction
Determines which micro-operations to perform
Flags
To determine the status of CPU
Results of previous operations
Example: ISZ (Increment-and-skip-if-zero) instruction
• Control unit will increment the PC if the zero flag is set
Control Signals from control bus
Interrupts
Acknowledgements
27
 Model of Control Unit (3)
Control Signals - output

Control Signals within the CPU

Signals that cause data movement from one register to another
Signals that activate specific ALU functions
Control Signals to Control Bus
Signals to memory
Signals to I/O modules
These control signals are applied directly as binary inputs to
individual logic gates

28
 Example Control Signal Sequence - Fetch

MAR <- (PC) - transfer the contents of PC into MAR

Control unit activates control signal to open gates between the bits of
PC and the bits of MAR
MBR <- (memory) - read a word from memory into MBR, increment the PC
A control signal that opens gates allowing the contents of MAR onto
the address bus
A memory read control signal on the control bus
A control signal that opens gates, allowing the contents of the data bus
to be stored in the MBR
Control Signals to logic that add 1 to the contents of the PC and store
the result back to PC
IR <- (MBR)
A control signal that opens gates between MBR and IR
29
Data Paths and Control Signals (1)...
- An example

30
 Data Paths and Control Signals (2)...
- An example

Control Unit
Receives inputs from clock, instruction register, and flags
Generate a sequence of control signals that causes micro-operations to
occur.
Uses clock pulse to time the sequence of events

Terminations of Control signals are labeled Ci in the previous slide

For each path to be controlled, there is a switch and indicated by a circle.
Control signal from the control unit temporarily opens the gate to let data
pass

Control signals go to
data paths to control the internal flow of data
ALU to activate various logic circuits and gates
Control lines of system bus
31
 Data Paths and Control Signals (3)
- An example
Micro-Operations and Control Signals
Micro-operations Active Control
Signals
t1: MAR ← (PC) C2

t2: MBR ← Memory

Fetch: C5, CR
PC ← (PC) + 1
t3: IR ← (MBR) C4

t1: MAR ← (IR(Address)) C8

Indirect: t2: MBR ← Memory C5, CR

t3: IR(Address) ← (MBR(Address)) C4

t1: MBR ← (PC) C1

t2: MAR ← Save-address

Interrupt:
PC ← Routine-address
t3: Memory ← (MBR) C12, CW

CR = Read control signal to system bus.

CW = Write control signal to system bus.
32
 CPU with Internal Bus (1)...

Usually a single internal bus

Gates control movement of data onto and off the bus
Control signals control data transfer to and from external
systems bus
Temporary registers needed for proper operation of ALU

33
CPU with Internal Bus (2)...

Temporary registers Y and Z needed for proper

operation of ALU

When an operation involving two operands is

performed, one can be obtained from the internal
bus, but the other must be obtained from another
source
•The AC could be used for this purpose, but this
limits the flexibility of the system
•Y provides temporary storage for the other input

The ALU is a combinatorial circuit with no

internal storage
•When control signals activate an ALU function, the
input to the ALU is transformed to the output
•The output of the ALU cannot be directly
connected to the bus, because it will feed back to the
input
•Z provides temporary output storage
 CPU with Internal Bus (3)
Execution sequence – An example

Operation to perform addition of memory contents with

Accumulator

t1: MAR (IR(address))

t2: MBR Memory
t3: Y (MBR)
t4: Z (AC) + (Y)
t5: AC (Z)

35
END