School of Electronics and Communication

engineering
Course Title: AUTOMOTIVE EMBEDDED SYSTEMS
Course Type: SC (Professional Elective2)
Course Code: B22ENS521
Semester: V Faculty
UNIT: II Dr. A. RAGANNA,
Associate Professor
COURSE DETAILS

Course Automotive Embedded Course SC

Title Systems Type
Course Code B22ENS52 Credits 3 Class V
1 Semester
Contact Work Total Number
LTP Credits Hours Load of
Assessm
Classes ent
Lecture 3 3 3
Per Semester
Tutorial
Course
Structure Practice - - -
Theor Practic IA SEE
- - - - y al

Total 3 3 3 42 - 50% 50%

COURSE OVERVIEW

 The course introduces the general topic of applications of

electronics in automobiles. It also elaborates the concepts
of various sensors, actuators used in the field,
Communication related concepts, Exhaust after treatment
systems and Automotive Instrumentation and diagnostics.
COURSE OBJECTIVES

The objectives of this course are to:

1. Understand the functions of electronic systems in modern automobiles, modern

electronics technology to improve the performance, safety, comfort and related issues.

2. Study the principles of automotive sensors and interfacing techniques, design, model
and simulate interfacing systems with sensors.

3. Know the principles and functionalities of various Automotive Communication Protocols

(ACPs) and Exhaust after treatment systems.

4. Know the industry standard practices for ECU design for automotives, modeling and
analysis of application software for ECU design and development, design of ECUs for
automobiles, design of HIL and fault diagnostics.
COURSE OUTCOMES (CO’S)
On successful completion of this course; the student shall be able to:
BLOOM’S LEVEL OF THE COURSE OUTCOMES
COURSE ARTICULATION MATRIX
CONTENTS OF UNIT-II
 Introduction to ARM Microcontroller

 Overview of ARM and RISC Design Philosophy,

 concept of ARM cortex M- series Microcontroller,

 Advanced Microcontroller Bus Architecture,

 Introduction to STM32H7xxx Microcontroller – Features,

 Architecture,

 Memory Organization,

 Pin Diagram, and I/O configuration.

TEXT BOOKS

1. Yifeng Zhu, Embedded Systems with Arm Cortex-M Microcontrollers in Assembly

Language and C: Third Edition.

2. Andrew Sloss, ARM System Developer's Guide: Designing and Optimizing System
Software (The Morgan Kaufmann Series in Computer Architecture and Design).

3. Andrew N. SLoss, Dominic Symes, Chris Wright., ARM System Developer’s Guide.

REFERENCE BOOK:

4. Programming Embedded Systems in C and C++ by Michael Barr and Anthony J.

Massa.

5. Programming with STM32: Getting Started with the Nucleo-Board and C/C++ by
Donald Norris
COURSE RESOURCES AND READING REF
 https://www.udemy.com/course/embedded-systems-bare-metal-programming/
 https://www.youtube.com/playlist?list=PL0XvCDGTtp12wpZ9QyFNfsEs3DjJnJMuD
 https://
www.edx.org/course/embedded-systems-essentials-with-arm-getting-started
 https://
www.udemy.com/course/matlab-essentials-for-engineering-and-science-students/
 https://www.udemy.com/course/matlabsimulink-biblego-from-zero-to-hero/
 https://
www.udemy.com/course/model-based-development-mbd-for-automotive-using-sim
ulink/

 https//www.udemy.com/course/matlab-simulink-and-stateflow/ https://
www.coursera.org/learn/matlab
 https://in.mathworks.com/help/ecoder/ug/generating-code-using-embedded-coder.
JOURNALS/MAGAZINES / ADDITIONAL SOURCES

 https://nptel.ac.in/courses/108/102/108102121/
WHAT IS MICROCONTROLLER?
 A microcontroller is a single integrated circuit, commonly
with the following features: central processing unit –
ranging from small and simple 4-bit processors to
complex 32-bit or 64-bit processors.

 KEY COMPONENTS OF A MICROCONTROLLER

o Central Processing Unit (CPU):
o Memory:
o I/O Ports:
o Timers and Counters:
o Peripherals:
 Analog-to-Digital Converter (ADC):
 Digital-to-Analog Converter (DAC):
 Communication Interfaces
o Clock:
INTRODUCTION TO ARM MICROCONTROLLERS

 An ARM microcontroller is a type of microcontroller that

is based on the ARM (Advanced RISC Machine)
architecture, which follows the RISC (Reduced
Instruction Set Computing) design.
 ARM microcontrollers are widely used in embedded
systems due to their high performance, low power
consumption, and versatility, making them popular
across many industries such as automotive, consumer
electronics, and industrial automation
INTRODUCTION TO ARM MICROCONTROLLERS

What is an ARM microcontroller and what are its advantages?

 ARM is a Reduced Instruction Set Computing (RISC) architecture, which means it uses a
smaller set of simple instructions for operations.
 Known for its energy efficiency, ARM processors are designed to use less power, making
them ideal for battery-operated devices.
 ARM is a popular low power embedded processor.
 Its core is based on the RISC architecture.
 In 1985 the first prototype was introduced under the name Acorn RISC machine later
renamed as Advanced RISC Machine (ARM).
 Being a RISC machine, the design is simple which means it can be built by less number of
transistors.
HISTORY OF ARM MICROCONTROLLERS
1. The Birth of ARM Architecture (1983-1990s)

o Acorn Computers (1983):

o ARM was originally developed by Acorn Computers in the early 1980s to power their personal
computers.
o The project began when Acorn needed a high-performance, low-power processor for its BBC Micro
series of computers.
o Acorn RISC Machine (ARM1) was the first processor developed in 1985.
o This laid the foundation for ARM's future, with its RISC architecture emphasizing a smaller set of
instructions that could be executed faster and more efficiently than traditional Complex Instruction
Set Computing (CISC) architectures.

o ARM Ltd. is Founded (1990):

o In 1990, ARM Ltd. was established as a separate entity, a joint venture between Acorn Computers,
Apple, and VLSI Technology.
o This marked the transition from a small in-house processor project to a company that would license
HISTORY OF ARM MICROCONTROLLERS CONT..
2. Early Adoption in Embedded Systems (1990s-2000s)

o Early ARM Processors:

o Early ARM processors like ARM6 (released in 1992) and ARM7 (released in 1994) were initially used
in mobile devices, like the Apple Newton (an early PDA).
o These processors’ power efficiency and performance started gaining attention in the embedded
systems world, where low power consumption and cost were critical.

o ARM7TDMI (ARM7 + 16 bit Thumb + JTAG Debug + fast Multiplier + enhanced ICE) (1994):
o One of the most important milestones for ARM in the microcontroller market was the release of the
ARM7TDMI core in 1994.
o This core became widely popular in embedded systems and microcontrollers due to its power
efficiency, performance, and versatility.
o It was adopted by companies like NXP, Texas Instruments, and STMicroelectronics, forming the

foundation for modern microcontrollers.

HISTORY OF ARM MICROCONTROLLERS CONT..
3. Introduction of Cortex-M Series (2004)
o ARM Cortex-M Series:
o In 2004, ARM introduced the Cortex-M series, specifically designed for microcontrollers and
embedded systems.
o This was a significant move, as ARM targeted the vast market for small, low-power, and cost-efficient
embedded controllers.
o The Cortex-M3, introduced in 2004, became the first microcontroller-focused ARM core.
o It was designed to be efficient, scalable, and used in a wide range of applications, from automotive
systems to consumer electronics.
o Cortex-M Series:
o Cortex-M0 (2009): Aimed at ultra-low-power applications, it became the go-to choice for cost-
sensitive, energy-efficient embedded devices.
o Cortex-M4 (2010): With added DSP (Digital Signal Processing) features, this core targeted more
complex embedded systems requiring signal processing and real-time control.
o Cortex-M7 (2014): Designed for high-performance embedded applications, it featured floating-point
HISTORY OF ARM MICROCONTROLLERS CONT..
4. Expansion and Dominance in the Embedded Systems Market (2000s-Present)

o Licensing Model:
o ARM’s licensing model, where ARM licenses its core designs to other manufacturers, was a key factor
in its rapid growth.
o Companies like STMicroelectronics, NXP, Texas Instruments, and Microchip used ARM cores to develop
their own microcontrollers.
o This approach allowed ARM to dominate the embedded systems market, as the licensed cores were
adopted in a wide range of industries including automotive, industrial automation, medical devices,
and IoT.

o Microcontrollers for IoT:

o With the rise of the Internet of Things (IoT), ARM microcontrollers became a dominant force in low-
power, connected devices.
o The Cortex-M0 and Cortex-M3 cores were particularly popular in IoT applications due to their low
energy consumption and integrated communication interfaces (e.g., SPI, I2C, UART).

o ARM Trust Zone (2017):

o ARM introduced Trust Zone technology for Cortex-M microcontrollers, enhancing security features,
especially important for IoT devices.
o This innovation addressed the growing concern about security in connected devices.
HISTORY OF ARM MICROCONTROLLERS CONT..

5. Recent Developments and the Future (2020s-Present)

o Cortex-M55 (2020):
o ARM introduced the Cortex-M55 in 2020, which included enhanced machine learning (ML) and signal
processing capabilities, aimed at next-generation embedded applications, particularly in the fields of
edge computing and AI for IoT devices.
o ARMv8-M Architecture:
o ARM's ARMv8-M architecture introduced more powerful features like Helium technology, improving
DSP and machine learning performance.
o This architecture caters to future needs in industrial automation, smart home devices, and advanced
medical equipment.
o Partnership with Semiconductor Companies:
o ARM continues to expand its partnership with semiconductor companies to create custom
microcontroller solutions. Notable partners include Qualcomm, NXP, STMicroelectronics, and
Microchip.
ARM MICROCONTROLLER FAMILIES
1. ARM7TDMI:
o One of the earliest and most widely adopted ARM cores for microcontrollers.
o It laid the groundwork for the adoption of ARM in embedded systems.
2. Cortex-M0/M0+:
o Ultra-low-power microcontrollers designed for cost-sensitive, low-power applications like
wearables, IoT, and simple automation systems.
3. Cortex-M3:
o One of the most popular ARM microcontroller cores, widely used in automotive,
industrial, and consumer applications.
4. Cortex-M4:
o A higher-performance microcontroller with built-in DSP capabilities for real-time control
and signal processing tasks, like motor control and digital audio.
5. Cortex-M7:
o High-performance microcontroller core used in advanced embedded applications that
require significant processing power, such as automotive control systems and industrial
robotics.
6. Cortex-M33:
o Aimed at secure applications, incorporating TrustZone technology for IoT devices and
secure embedded systems.
EVOLUTION OF ARM PROCESSOR
ARCHITECTURE
• ARM Architecture Overview
• Core Components: Processor,
Memory, Input/Output,
Peripherals.
• Types of ARM Cores:
• Cortex-M: Designed for
microcontroller applications
(embedded systems).
• Cortex-A: Typically used in higher-
end devices (smartphones,
tablets).
• Cortex-R: Real-time applications,
critical in automotive and safety-
ARM POWERED PRODUCTS
RISC DESIGN PHILOSOPHY
What is the RISC design philosophy?
o RISC is a design philosophy aimed at delivering simple but powerful instructions that
execute within a single cycle at a high clock speed.
o The RISC philosophy concentrates on reducing the complexity of instructions performed
by the hardware.
PRINCIPLES OF RISC DESIGN PHILOSOPHY
1. Reduced Instruction Set:
o The RISC design uses a small set of instructions that are simple and uniform in execution.
o Each instruction typically performs a single task, such as arithmetic operations or data
movement, which simplifies the processor design.
o In contrast to CISC, which may have complex instructions that can take multiple cycles to
execute, RISC instructions are designed to execute in a single clock cycle.
2. Load-Store Architecture:
o RISC architectures typically use a load-store model, meaning that only load and store
instructions access memory.
o All other instructions operate on data stored in registers.
o This reduces the complexity of the CPU since data is manipulated in registers rather than
directly from memory.
o This improves efficiency by minimizing memory access, which tends to be slower than
PRINCIPLES OF RISC DESIGN PHILOSOPHY CONT..

3. Simple Addressing Modes:

o RISC processors use simple addressing modes, typically limiting the number of ways the
processor can access memory.
o This helps reduce the complexity of the hardware and speeds up instruction execution.
o Complex addressing modes are generally avoided, and instead, simple modes such as
register direct or immediate addressing are used.
4. Pipelining:
o One of the most important features of RISC design is the use of pipelining.
o This technique allows multiple instructions to overlap in execution, with different stages
of multiple instructions being processed simultaneously.
o This significantly improves the throughput and overall performance of the processor, as
each part of the instruction cycle (fetch, decode, execute) is performed concurrently for
different instructions.
PRINCIPLES OF RISC DESIGN PHILOSOPHY CONT..
5. Uniform Instruction Length:
o RISC processors typically have fixed-length instructions (usually 32 bits), making
instruction decoding faster and easier to implement.
o In contrast, CISC architectures may have variable-length instructions, which can
complicate instruction decoding and slow down execution.
6. Few Instruction Formats:
o RISC uses a limited number of instruction formats, simplifying the decoding process.
o This allows the processor to be more streamlined and efficient in instruction processing,
resulting in faster execution.
7. Hardwired Control Unit:
o The control unit in a RISC processor is often hardwired rather than microprogrammed.
o This makes the execution of instructions faster, as hardwired control provides quicker responses
compared to a microprogrammed control unit, which is typically slower due to the need to interpret
microinstructions.
PRINCIPLES OF RISC DESIGN PHILOSOPHY CONT..

8. Register-Oriented Operations:
o RISC designs heavily emphasize the use of registers for computation. All arithmetic and
logic operations are performed using values stored in the processor’s registers, reducing
the reliance on slower memory operations.
9. Emphasis on Compiler Efficiency:
o The RISC philosophy assumes that complex operations should be handled by the
compiler, rather than the hardware.
o By breaking down complex operations into simpler instructions during compilation, the
processor can execute these instructions more efficiently.
o This allows the hardware to remain simple, while sophisticated optimization is handled by
the compiler, taking advantage of the processor’s features like pipelining.
ADVANTAGES OF RISC ARCHITECTURE

1. Speed and Performance:

o Since RISC processors execute simple instructions in a single clock cycle and use
pipelining, they achieve higher performance levels, especially in tasks that require
repetitive operations.
2. Lower Power Consumption:
o Due to the simplicity of the design and the reduced instruction set, RISC processors tend
to consume less power, making them ideal for mobile and embedded systems where
energy efficiency is critical.
3. Simplified Hardware Design:
o The simpler instruction set and regularity in instruction formats reduce the complexity of
the processor's hardware, leading to easier and faster development, testing, and
debugging of the chip.
4. Scalability and Flexibility:
DISADVANTAGES OF RISC ARCHITECTURE

1. Increased Software Complexity:

o Since complex operations are broken down into simpler instructions, more
instructions are often required to perform a task, which can increase code size.
o This puts more strain on the compiler and may require more memory.
2. Memory Bandwidth:
o While the use of registers reduces the need for memory access, if a large number of
registers are required, it can increase pressure on the system’s memory bandwidth,
which might slow down performance in memory-intensive applications.
COMPARISON: RISC VS CISC

 RISC (Reduced Instruction Set Computing) :

o Focuses on a smaller set of instructions.
o Simple instructions that execute in one clock cycle.
o Fewer addressing modes and simpler design.
o Heavy use of registers and load/store architecture.
o More compiler-dependent for optimizing performance.
 CISC (Complex Instruction Set Computer ):
o Larger and more complex instruction set.
o Instructions can take multiple clock cycles.
o Complex addressing modes and instructions.
o More reliance on memory operations.
o Typically requires more complex hardware, but less reliance on the compiler for
performance optimization.
CONCEPT OF ARM CORTEX M- SERIES
MICROCONTROLLER
o The ARM Cortex-M series microcontrollers are widely used in embedded systems, especially
in automotive, industrial, and IoT applications.
o They belong to the ARM Cortex family, which is a group of 32-bit RISC (Reduced Instruction
Set Computer) processors, designed for low-power, high-performance applications.

Concepts of ARM Cortex-M Series Microcontrollers:

1. Processor Architecture:
o ARMv7-M (for Cortex-M3 and Cortex-M4) and ARMv6-M (for Cortex-M0 and Cortex-M0+) architectures
provide efficient and scalable processing.
o Uses the Thumb-2 instruction set, which is a blend of 16-bit and 32-bit instructions, offering a balance
between performance and code density (reduced memory usage).
2. Low Power Consumption:
o The Cortex-M series is optimized for energy-efficient operations, making it suitable for battery-
powered and resource-constrained environments.
o Integrated low-power modes like sleep, deep sleep, and standby help reduce power consumption
during inactivity.
3. NVIC (Nested Vectored Interrupt Controller):
o An essential feature for real-time applications, the NVIC allows efficient handling of interrupts with
minimal latency.
o It supports multiple priority levels, enabling complex, time-sensitive tasks.
CONCEPT OF ARM CORTEX M- SERIES MICROCONTROLLER
CONT..
1. Hardware Debugging and Trace:
o ARM Cortex-M microcontrollers provide Integrated Debug Access Port (DAP), supporting
real-time debugging with tools like JTAG or SWD (Serial Wire Debug).
o ETM (Embedded Trace Macrocell) allows advanced debugging by tracing instruction
execution and data access in real-time.
2. FPU (Floating Point Unit):
o Some variants, like the Cortex-M4, integrate an optional Floating-Point Unit (FPU), which
is useful for DSP (Digital Signal Processing) applications that require efficient floating-
point operations.
3. DSP Extensions:
o The Cortex-M4, for example, includes DSP extensions, which are particularly useful for
audio, control systems, and other signal processing tasks.
4. Memory Protection Unit (MPU):
o Provides memory access control, allowing the system to manage different memory
regions safely. It is useful in applications with real-time operating systems (RTOS),
where tasks need isolated memory spaces.
CONCEPT OF ARM CORTEX M- SERIES MICROCONTROLLER
CONT..
1. Scalability and Flexibility:
o The Cortex-M series comes in different configurations to meet various
requirements:
 Cortex-M0 and M0+: Basic, ultra-low-power microcontrollers for cost-sensitive, low-
performance applications.
 Cortex-M3: General-purpose microcontroller with enhanced performance and low
power.
 Cortex-M4: Includes DSP instructions and optional FPU for more computationally
demanding applications.
 Cortex-M7: Offers high performance, including higher clock speeds and enhanced FPU
support.
2. Advanced Bus Infrastructure:
o ARM Cortex-M microcontrollers use the AMBA (Advanced Microcontroller Bus
Architecture) for connecting the processor core to peripherals and memory
efficiently.
3. Peripherals:
o Cortex-M microcontrollers typically include a wide array of on-chip peripherals
like GPIOs (General Purpose Input/Output), timers, ADC (Analog to Digital
ARM CORTEX M- 3 ARCHITECTURE

o It is a 32-bit processor
family that is designed
and developed by ARM
Holdings.
o One of the most
prominent features of
the ARM Cortex M
microcontroller is its
ability to reduce power
consumption while also
offering high
performance.
o It is also popular for its
affordability, reliability,
and scalability.
ARM CORTEX M- 3 ARCHITECTURE
o The Cortex-M3 is a 32-bit microprocessor.
o It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces.
o The processor has a Harvard architecture, which means that it has a separate instruction bus and
data bus.
o This allows instructions and data accesses to take place at the same time, and as a result of this,
the performance of the processor increases because data accesses do not affect the instruction
pipeline.
o This feature results in multiple bus interfaces on Cortex-M3, each with optimized usage and the
ability to be used simultaneously.
o However, the instruction and data buses share the same memory space (a unified memory
system).
o In other words, you cannot get 8 GB of memory space just because you have separate bus
interfaces.
o For complex applications that require more memory system features, the Cortex-M3 processor has
an optional Memory Protection Unit (MPU), and it is possible to use an external cache if it’s
ARM CORTEX-M3 FEATURES
1. 32-bit RISC Architecture:
o Based on the ARMv7-M architecture, the Cortex-M3 uses the Thumb-2 instruction set,
which combines 16-bit and 32-bit instructions, providing both high performance and code
efficiency.
2. High Performance and Efficiency:
o Operating at clock frequencies up to 100 MHz, the Cortex-M3 delivers a balance of
performance and energy efficiency, making it suitable for real-time applications.
o Its Harvard architecture separates instruction and data pathways, allowing simultaneous
access to memory and improving execution speed.
3. Low Power Consumption:
o Designed for energy-sensitive applications, the Cortex-M3 offers various power-saving
modes, including sleep and deep sleep modes.
o This helps extend the battery life in portable devices and reduces power usage in
industrial applications.
4. Interrupt Handling with NVIC:
o The Nested Vectored Interrupt Controller (NVIC) supports up to 240 interrupts with
configurable priorities.
o It allows fast and efficient interrupt processing, essential for real-time systems.
o Supports tail-chaining and late-arrival interrupts, which minimize the overhead in
ARM CORTEX-M3 FEATURES
1. Integrated Debugging Features:
o The Cortex-M3 includes integrated debugging capabilities with the use of Serial Wire Debug (SWD)
and JTAG interfaces.
o It supports real-time debugging and analysis through the Instrumentation Trace Macrocell (ITM) and
the Data Watchpoint and Trace (DWT) unit, allowing developers to trace the execution of their
programs.
2. Memory Protection Unit (MPU):
o The MPU provides memory region protection, preventing unauthorized access to specific memory
regions.
o This is particularly useful in embedded systems running an RTOS, where tasks need to be isolated
from each other for reliability and security.
3. Efficient Exception and Fault Handling:
o The Cortex-M3 has an efficient exception mechanism with a fixed 12-cycle latency for interrupt entry
and exit.
o It includes several fault handlers for detecting and managing errors like bus faults, memory
management faults, and usage faults, ensuring system robustness.
4. Bus Architecture:
o It uses the AMBA 3 (Advanced Microcontroller Bus Architecture) AHB-Lite for connecting the core to
high-speed peripherals and memory.
o This ensures that data is transferred efficiently between the core and external peripherals or
memory.
ARM CORTEX-M3 FEATURES
CONT..
1. Rich Set of Peripherals:
o ARM Cortex-M3 microcontrollers often come
with a wide range of on-chip peripherals,
which may include:
 Timers and counters
 Analog-to-Digital Converters (ADC)
 Pulse Width Modulation (PWM)
 UART, SPI, I2C interfaces for
communication
 DMA (Direct Memory Access)) for efficient
data handling
2. Thumb-2 Instruction Set:
o Thumb-2 allows for both 16-bit and 32-bit
instructions, providing a good balance
between performance and code density.
o This helps reduce memory usage while still
maintaining high execution speed for more
complex operations.
Fig. The Relationship between the Thumb Instruction Set in
Thumb-2 Technology and the Traditional Thumb.
ARM CORTEX-M3 FEATURES
CONT..
1. Thumb-2 Instruction Set:
o Thumb (Thumb-1) uses 16-bit instructions to
reduce memory usage, making programs
smaller but with limited functionality compared
to full ARM instructions.
o Thumb-2 extends Thumb by introducing both
16-bit and 32-bit instructions, offering a balance
between code size and performance.
o It allows developers to use compact 16-bit
instructions for simple tasks and powerful 32-bit
instructions for complex operations, without
switching back to ARM mode.
o Thumb-2 is more flexible and performs better,
making it ideal for modern embedded systems
like the ARM Cortex-M series.
ARM CORTEX-M3 FEATURES CONT..

Thumb-2 Instruction Set:

Fig. Switching between ARM Code and Thumb Code in

Traditional ARM Processors Such as the ARM7.
ARM CORTEX-M3 FEATURES
CONT..

Applications:
 Automotive Systems:
 Consumer Electronics:
 Medical Devices:
 IoT Devices:
ARM CORTEX-M3 MEMORY ORGANIZATION

o The memory
organization of the ARM
Cortex-M3 is divided
into various regions to
support efficient
memory access and
operation.

o These regions include

both physical memory
and memory-mapped
peripherals, which
provide flexibility and
speed for embedded
applications.
ARM CORTEX-M3 MEMORY ORGANIZATION CONT..
ARM Cortex-M3 Memory Map Overview:
1. Code and Program Flash (0x00000000 to 0x1FFFFFFF):
o The first 512 MB is reserved for code execution, typically where the main program or firmware is
stored.
o Flash memory is typically mapped here, allowing the processor to fetch instructions and execute
them directly from the flash.
2. SRAM (0x20000000 to 0x3FFFFFFF):
o SRAM (Static Random Access Memory) is located in this region for data storage, including variables,
stack, and heap memory.
o The SRAM region supports both fast data access and efficient execution.
3. Peripheral Space (0x40000000 to 0x5FFFFFFF):
o This region is reserved for memory-mapped peripherals.
o These are hardware components like timers, ADCs, GPIOs, UARTs, etc.
o ARM Cortex-M3 uses a memory-mapped I/O system where each peripheral has its own memory
address range for control and configuration.
4. External RAM and Peripherals (0x60000000 to 0xDFFFFFFF):
o This is where external memory devices (like external SDRAM) or peripherals connected to external
buses (like Ethernet controllers or display controllers) are mapped.
o These addresses are used to interface with hardware that is not part of the internal SoC (System on
Chip).
ARM CORTEX-M3 MEMORY ORGANIZATION CONT..
1. System Control Space (0xE0000000 to 0xFFFFFFFF):
o The last portion of the memory is reserved for system control and debugging.
o This region includes:
 System Control Block (SCB): Controls system functions like the interrupt system, fault handling,
and system reset.
 NVIC (Nested Vectored Interrupt Controller): Handles and prioritizes interrupts.
 Core Debug Registers: Used for debugging and performance monitoring.
Stack Memory and Heap:
 Stack Memory is typically allocated from the SRAM region.
 When a function is called, the system allocates space for local variables and stores return
addresses in this stack.
 Heap Memory is also part of the SRAM and is used for dynamically allocated memory (e.g.,
malloc in C).
Advantages of this Memory Organization:
 Harvard Architecture: The separation of instruction and data memory allows for simultaneous
instruction fetch and data access, improving performance.
 Efficient Interrupt Handling: Memory-mapped NVIC and fault handlers allow for rapid response to
interrupts and exceptions, which is crucial in real-time systems.
 Flexibility: Memory regions for external devices and peripherals allow the system to be easily expanded
with additional memory or specialized components.
 ARM CORTEX-M3 REGISTER
1. General Purpose Registers:
o The R0 through R7 general purpose registers are
also called low registers.
 They can be accessed by all 16-bit Thumb
instructions and all 32-bit Thumb-2 instructions.
 They are all 32 bits; the reset value is
unpredictable.
o The R8 through R12 registers are also called high
registers.
o They are accessible by all Thumb-2 instructions but
not by all 16-bit Thumb instructions.
o These registers are all 32 bits; the reset value is
unpredictable
o The ARM Cortex-M3 processor has a simple and
efficient register set to support high-performance, low-
latency operations and ease of programming.
o It includes 16 general-purpose registers (R0-R15) and
special function registers that control specific functions
like the Program Counter (PC) and Stack Pointer (SP).
ARM CORTEX-M3 REGISTER CONT..
Special-Purpose Registers:
o R13 is the stack pointer (SP).
o In the Cortex-M3 processor, there are two
SPs.
o This duality allows two separate stack
memories to be set up.
o When using the register name R13, you can
only access the current SP; the other one is
inaccessible unless you use special
instructions to move to special register from
general-purpose register (MSR) and move
special register to general-purpose register
(MRS).
ARM CORTEX-M3 REGISTER
CONT..
The two SPs are as follows:

1. Main Stack Pointer (MSP) or SP_main in ARM documentation:

• This is the default SP; it is used by the operating system (OS) kernel, exception handlers, and
all application codes that require privileged access.

2. Process Stack Pointer (PSP) or SP_process in ARM documentation:

• This is used by the base-level application code (when not running an exception handler).
ARM CORTEX-M3 REGISTER
CONT..

Fig. Basic Concept of Stack Memory.

ARM CORTEX-M3 REGISTER CONT..
R14 (Link Register - LR):
o The LR is used to store the return address when a function or subroutine is called.
o On return, the processor retrieves the address from LR and jumps back to the calling function.
o In the case of exceptions, it holds the EXC_RETURN value, which determines the state of the
processor after the exception is handled.
o Example, when you’re using the branch and link (BL) instruction.
 ARM CORTEX-M3 REGISTER
CONT..
R15 (Program Counter - PC)

o R15 is the PC.

o You can access it in assembler code
by either R15 or PC.
o Because of the pipelined nature of
the Cortex-M3 processor, when you
read this register, you will find that
the value is different than the
location of the executing
instruction, normally by 4.

o Example,
0x1000 : MOV R0, PC ; R0 = 0x1004
ARM CORTEX-M3 REGISTER
CONT..
1. SPECIAL REGISTERS
o The special registers in the
Cortex-M3 processor include the
following
i. Program Status registers
(PSRs)
ii. Interrupt Mask registers
(PRIMASK, FAULTMASK, and
BASEPRI)
iii. Control register (CONTROL)
o Special registers can only be
accessed via MSR and MRS
instructions; they do not have
memory addresses:
 ARM CORTEX-M3 REGISTER CONT..
A. Program Status Register (PSR):
o The PSRs are subdivided into three status
registers:
1. Application Program Status register
(APSR)
2. Interrupt Program Status register (IPSR)
Table. Combined Program Status Registers (xPSR) in the Cortex-M3.
3. Execution Program Status register (EPSR)
o The three PSRs can be accessed together or
separately using the special register access
instructions MSR and MRS.
o When they are accessed as a collective item,
the name xPSR is used.
o You can read the PSRs using the MRS
instruction.
o You can also change the APSR using the MSR
instruction, but EPSR and IPSR are read-only.
o For example:

Table. Bit Fields in Cortex-M3 Program Status Registers

ARM CORTEX-M3 REGISTER
CONT..

Table. Current Program Status Registers in Traditional ARM Processors.

o In ARM assembler, when accessing xPSR (all three PSRs as one), the symbol PSR is used:

o If you compare this with the Current Program Status register (CPSR) in ARM7, you might find that some bit
fields that were used in ARM7 are gone.
o The Mode (M) bit field is gone because the Cortex-M3 does not have the operation mode as defined in ARM7.
Thumb-bit (T) is moved to bit 24.
o Interrupt status (I and F) bits are replaced by the new interrupt mask registers (PRIMASKs), which are separated
from PSR.
o For comparison, the CPSR in traditional ARM processors is shown in above Table. Current Program Status
Registers in Traditional ARM Processors.
1..
ARM CORTEX-M3 REGISTER
CONT..
Interrupt mask registers
o PRIMASK: Controls the disabling of all exceptions,
except the Non-Maskable Interrupt (NMI).
o It is useful for critical sections where you need to
ensure that no interrupt disrupts the execution.
o FAULTMASK: If set, it disables all exceptions,
including Hard Faults, but NMI can still occur.
o BASEPRI: It is used to mask interrupts of priority
levels below a certain threshold. It's useful for
allowing higher-priority interrupts while disabling
lower-priority ones.
1. Control Register (CONTROL):
o The CONTROL register determines the current
privilege level (privileged or unprivileged) and
which stack pointer (MSP or PSP) is currently in
use.
o CONTROL [0]: Sets the privilege level (0 for
privileged, 1 for unprivileged).
o CONTROL [1]: Determines the active stack
ARM CORTEX-M3 REGISTER SUMMARY

Register Description
R0-R12 General-purpose registers for holding variables and temporary data
R13 Stack Pointer (SP), points to the top of the current stack
R14 Link Register (LR), stores return addresses
R15 Program Counter (PC), holds the address of the next instruction
PSR Program Status Register, provides status and execution state
PRIMASK Primary Interrupt Mask, enables/disables interrupts
BASEPRI Interrupt priority mask, allows masking of lower-priority interrupts
FAULTMA
Fault Mask, enables/disables all exceptions except NMI
SK
CONTROL Controls stack pointer and privilege level
INSTRUCTION SET
What is an Instruction Set?
o An instruction set is like a list of commands the microcontroller understands.
o These commands are very basic but essential for making the system work. For example:
 ADD: Adds two numbers.
 SUB: Subtracts one number from another.
 MOV: Moves data from one place to another.
o The Cortex-M3 uses Thumb-2 instructions, which come in two sizes: 16-bit and 32-bit.
This makes the processor very efficient because it can use small instructions for simple
tasks and larger instructions for more complex operations.
INSTRUCTION SET CONT..
INSTRUCTION SET CONT..
INSTRUCTION SET CONT..
INSTRUCTION SET CONT..
INSTRUCTION SET CONT..
INSTRUCTION SET CONT..
INSTRUCTION SET CONT..
INSTRUCTION SET CONT..
INSTRUCTION SET CONT..
INSTRUCTION SET CONT..
INSTRUCTION SET CONT..
INSTRUCTION SET CONT..
INSTRUCTION SET CONT..

DATA PROCESSING INSTRUCTIONS

1. These instructions perform operations like adding, subtracting, and comparing
numbers. For example:
 ADD: Adds two numbers.
 SUB: Subtracts one number from another.
 CMP: Compares two numbers and sets flags (for use with conditional
branches).
Example:
1. MOV R0, #5; Put the value 5 into register R0
2. MOV R1, #3; Put the value 3 into register R1
3. ADD R2, R0, R1; Add R0 and R1, store result in R2 (5 + 3 = 8)
INSTRUCTION SET CONT..

B. LOAD AND STORE INSTRUCTIONS

1. These instructions are used to move data between memory and the processor's registers:
 LDR: Load data from memory into a register.
 STR: Store data from a register into memory.

Example:
1. LDR R0, [R1]; Load the value from memory address in R1 into R0
2. STR R2, [R3]; Store the value in R2 into the memory address in R3
INSTRUCTION SET CONT..

C. BRANCH INSTRUCTIONS
1. Branch instructions are used to change the flow of the program.
For example:
 B: Unconditional branch (jump to another part of the program).
 BL: Branch with link (used for function calls).
Example:
B next; Jump to the label "next" next:
MOV R0, #10; This instruction will be executed next
INSTRUCTION SET CONT..

D. CONTROL INSTRUCTIONS
1. These instructions control special processor functions, like entering low-power
mode:
 WFI: Wait for interrupt (puts the processor in a low-power mode until an
interrupt occurs).
 SVC: Supervisor call, used to request system-level services.
Example:
1. WFI; Enter low-power mode until an interrupt occurs
INSTRUCTION SET CONT..
E. BIT MANIPULATION INSTRUCTIONS
1. These instructions allow you to change individual bits in a register. This is
useful in embedded systems when controlling hardware:
 AND: Perform a bitwise AND between two registers.
 ORR: Perform a bitwise OR between two registers.
Example:
1. AND R0, R1, R2; Bitwise AND of R1 and R2, store result in R0
2. ORR R0, R0, R3; Bitwise OR of R0 and R3, store result in R0
INSTRUCTION SET CONT..
3. Instruction Format
In the ARM Cortex-M3, instructions can be 16-bit or 32-bit long:
 16-bit instructions: These are shorter and take up less memory, making the code smaller.
 32-bit instructions: These are more powerful and can do more complex tasks.
Example: simple program to add two numbers and store the result:
i. MOV R0, #5; Move the value 5 into R0
ii. MOV R1, #3; Move the value 3 into R1
iii. ADD R2, R0, R1; Add R0 and R1, store the result (8) in R2
iv. STR R2, [R3]; Store the result in memory location pointed by R3
o The ARM Cortex-M3 instruction set is designed to be simple, fast, and efficient.
o By learning these instructions, understand how to write programs that control real-world
devices, like robots, cars, or IoT devices.
o The balance of 16-bit and 32-bit instructions makes the Cortex-M3 ideal for applications
where performance and power efficiency are key.
o In practical terms, knowing how to use these instructions allows you to work with modern
embedded systems and optimize code for speed and energy consumption, skills highly
valuable in the embedded and automotive industries.
 NVIC (NESTED VECTORED INTERRUPT
CONTROLLER)
What is the NVIC?
o The NVIC is a specialized piece of hardware
inside the ARM Cortex-M processor that
controls how the system handles interrupts.
o It supports nesting and vectoring, which makes
interrupt handling faster and more efficient.
 Interrupts are signals sent by external devices
(like timers, sensors, or communication
modules) to the processor, requesting it to stop
its current task and respond to an event.
 Nesting allows higher-priority interrupts to
interrupt the processing of lower-priority ones,
making sure the most urgent tasks get handled
first.
 Vectoring refers to the automatic jump to the
right code (interrupt service routine or ISR)
when an interrupt occurs.
NVIC CONT..
Features of the NVIC
1. Supports Prioritized Interrupts:
o The NVIC allows each interrupt to be assigned a priority level.
o If two interrupts happen at the same time, the NVIC will process the higher-priority interrupt first.
o It also supports preemption, meaning higher-priority interrupts can "preempt" or interrupt the
processing of lower-priority ones.
2. Fast Response Time:
o The NVIC is tightly integrated with the Cortex-M processor, ensuring minimal delay when an interrupt
occurs.
o Once an interrupt happens, the NVIC immediately directs the processor to the correct interrupt
handler code.
3. Efficient Context Switching:
o The NVIC helps save and restore the processor’s state when switching between different interrupt
handlers, making sure the system can return to the task it was doing before the interrupt.
4. Low Power:
o The NVIC works well in low-power applications, as it can help the system quickly handle interrupts
and go back to a low-power state.
5. Supports up to 240 External Interrupts:
o The NVIC can handle multiple interrupt sources (up to 240 in the Cortex-M3), making it scalable for
complex embedded systems with many input/output devices.
NVIC CONT..
How Does the NVIC Work?
1. Interrupt Triggering:
o When an external event (like a button press, timer timeout, or communication event)
occurs, it generates an interrupt.
o The NVIC detects the interrupt and checks its priority.
2. Vectoring:
o The NVIC uses a vector table, a list of memory addresses where the code for handling
each interrupt is stored.
o The NVIC fetches the address from the vector table and directs the processor to run the
corresponding Interrupt Service Routine (ISR).
3. Handling Interrupts:
o The processor temporarily stops its current task and runs the ISR to handle the interrupt.
o Once the ISR finishes, the processor resumes the task it was working on.
4. Nested Interrupts:
o If a new, higher-priority interrupt occurs while handling a current interrupt, the NVIC
pauses the current ISR, handles the new interrupt, and then returns to the first one when
done. This is called interrupt nesting.
NVIC CONT..
Interrupt Priorities

In ARM Cortex-M processors, each interrupt can be assigned a priority.

The priority levels can be configured using special registers within the NVIC.
o Lower numbers indicate higher priority.
o A higher-priority interrupt can interrupt a lower-priority ISR.
• This makes the NVIC ideal for systems where critical events (like a safety sensor in a car or a real-time
clock) must be handled without delay.

Example: How the NVIC is Used

•Let’s say you are building a project with a Cortex-M3 microcontroller that handles multiple tasks:
 Task 1: Reading sensor data every second (lower priority).
 Task 2: Responding to a button press (medium priority).
 Task 3: Handling emergency stop commands (high priority).
• If a button is pressed while reading sensor data, the button interrupt will pause the sensor reading and
run its interrupt service routine (ISR).
• However, if an emergency stop signal comes in, it will preempt both tasks and handle the emergency first.
Once that ISR is complete, the system will go back to handling the button press and then the sensor
reading.
NVIC CONT..
NVIC Registers

We should understand the key NVIC registers involved in setting up and managing interrupts:
1. ISER (Interrupt Set-Enable Registers):
o These registers enable interrupts in the NVIC. Each bit corresponds to an interrupt.
2. ICER (Interrupt Clear-Enable Registers):
o These registers disable interrupts. Clearing the bit turns off the interrupt.
3. ISPR (Interrupt Set-Pending Registers):
o These registers indicate that an interrupt is pending (waiting to be processed).
4. ICPR (Interrupt Clear-Pending Registers):
o These registers clear the pending status of interrupts.
5. IPR (Interrupt Priority Registers):
o These registers set the priority for each interrupt.
NVIC CONT..

Why is the NVIC Important for Embedded Systems?

1. Real-Time Responsiveness: The NVIC allows systems to react to external events almost
instantly, which is crucial for real-time systems like automotive controllers or medical
devices.
2. Efficient Task Management: The NVIC allows multiple interrupts to be handled without
overloading the processor, managing tasks based on their priority.
3. Low Power Consumption: By using interrupts, the processor can stay idle until an event
occurs, which reduces power consumption, making it ideal for battery-operated devices.
o The Nested Vectored Interrupt Controller (NVIC) is an essential part of ARM Cortex-M
processors, enabling efficient, prioritized handling of interrupts.
o It makes embedded systems responsive and allows them to manage multiple tasks
effectively, while keeping power consumption low.
o Understanding the NVIC will help students design more efficient and responsive embedded
systems, as it allows for flexible handling of real-time events, such as sensor readings,
communication signals, or user inputs.
ARM CORTEX-M3 OPERATION MODES
• The ARM Cortex-M3 microcontroller operates in two primary modes, with additional sub-
modes to manage interrupts, exceptions, and different privilege levels.
• These modes are designed to ensure efficient multitasking, control over system resources,
and fast handling of interrupts and exceptions in real-time embedded systems.

Operation Modes Of ARM Cortex-m3

1. Thread Mode:
o This is the main mode of operation where the user application runs.
o It can be used for both normal execution and low-priority tasks.
o Privilege Levels:
 Privileged: Can access all system resources, including system control and special function
registers. Typically used for system-level tasks.
 Unprivileged: Restricted access to system resources; cannot directly access some critical
registers and memory. Typically used for application tasks that don't need full system control.
 The current privilege level is controlled by the CONTROL register. The processor can switch
between these levels based on the application's needs.
 Privileged: Can access all system resources, including system control and special function
registers. Typically used for system-level tasks.
 Unprivileged: Restricted access to system resources; cannot directly access some critical
registers and memory. Typically used for application tasks that don't need full system control.
ARM CORTEX-M3 OPERATION MODES
CONT..
1.Handler Mode:
o This mode is entered when an exception or interrupt occurs.
o The Cortex-M3 automatically switches to handler mode to handle the interrupt or
exception.
o It always runs in privileged mode, as handling exceptions or interrupts requires access to
critical system resources.
o In this mode, the processor executes code from the exception handler or interrupt
service routine (ISR).
2.Switching Between Modes:
 The processor starts in privileged Thread mode after reset. When an exception occurs (such
as an interrupt), the Cortex-M3 switches to Handler mode.
 When returning from the interrupt or exception handler, the processor returns to the mode it
was in before the exception.
 Thread mode can be set to either privileged or unprivileged, while Handler mode is always
privileged.
ARM CORTEX-M3 OPERATION MODES CONT..

Special Control Mechanisms:

1. Interrupt and Exception Handling:
o The Nested Vectored Interrupt Controller (NVIC) allows fast and efficient interrupt
processing.
o When an interrupt occurs, the processor switches to Handler mode and saves the current
Program Counter (PC), Link Register (LR), and other essential registers to the stack.
o After the interrupt is handled, the system returns to Thread mode.
2. Supervisor Call (SVC):
o The Cortex-M3 allows switching between privilege levels through software by using an
SVC instruction.
o For example, an application running in unprivileged Thread mode can request a service
from the OS or a higher-privilege task using SVC, switching temporarily to privileged
mode.
ARM CORTEX-M3 OPERATION MODES CONT..
Privilege Management:
 CONTROL[0] bit: Defines whether the system is in privileged or unprivileged state.
o 0: Privileged
o 1: Unprivileged
 Privilege level is important for embedded systems because it provides security and stability
by restricting access to critical system functions for general user tasks, thereby preventing
accidental or malicious system corruption.
Stack Pointers and Their Role in Modes:
 Main Stack Pointer (MSP): Used in Handler mode by default and can be used in privileged
Thread mode.
 Process Stack Pointer (PSP): Used in unprivileged Thread mode.
 This dual stack pointer system helps maintain clear separation between user-level tasks and
system-level tasks, ensuring robust operation during exception handling and task switching.
ARM CORTEX-M3 OPERATION MODES CONT..

Summary of Cortex-M3 Modes:

Mode Privilege Level Stack Pointer Typical Use Case

Privileged/ Application code

Thread MSP/PSP
Unprivileged execution

Interrupts/Exception
Handler Privileged MSP
handling
ADVANCED MICROCONTROLLER BUS
ARCHITECTURE
 Advanced Microcontroller Bus Architecture (AMBA) is a widely adopted on-chip bus
architecture used for ARM processors, allowing peripheral designers to easily reuse designs
across multiple projects and providing plug-and-play interface for hardware developers to
improve time to market.
 The Arm Advanced Microcontroller Bus Architecture (AMBA) is an open-standard, on-chip
interconnect specification for the connection and management of functional blocks in
system-on-a-chip (SoC) designs.
 It facilitates development of multi-processor designs with large numbers of controllers and
components with a bus architecture.
 Since its inception, the scope of AMBA has, despite its name, gone far beyond microcontroller
devices.
 Today, AMBA is widely used on a range of ASIC and SoC parts including applications
processors used in modern portable mobile devices like smartphones.
 AMBA is a registered trademark of Arm Ltd.[1]
 Advanced Microcontroller Bus Architecture (AMBA) is a set of open standard protocols created
by ARM Holdings, widely used in System-on-Chip (SoC) designs.
 The main goal of AMBA is to establish a scalable, flexible, and efficient communication
system for different components (like processors, memory, and peripherals) in an embedded
ADVANCED MICROCONTROLLER BUS ARCHITECTURE
CONT..

Why AMBA?

1. Modular Design: AMBA enables the integration of multiple IP blocks (like processors,
memory controllers, and peripherals) into a single chip.
2. Interoperability: Components designed using AMBA protocols by different vendors can
easily work together in SoC designs.
3. Scalability: AMBA protocols support various system complexities, ranging from simple
microcontroller-based designs to high-performance SoCs.
ADVANCED MICROCONTROLLER BUS ARCHITECTURE
CONT..
AMBA Architecture
 AMBA defines several bus protocols to
address different performance and power
requirements within a SoC. The main buses
used in AMBA are:
1. Advanced High-Performance Bus (AHB):
o AHB is designed for high-performance,
high-bandwidth components.
o It supports features like burst transfers,
split transactions, and pipelined
operations.
o Suitable for connecting the CPU, memory
controllers, and DMA (Direct Memory
Access) controllers.
2. Advanced Peripheral Bus (APB):
o APB is optimized for low-power, low-
bandwidth peripherals.
o It has a simple interface, which reduces
the complexity of the design.
o Used for peripherals like UART, timers,
and GPIOs that don't need high-speed
ADVANCED MICROCONTROLLER BUS ARCHITECTURE
CONT..
1. Advanced eXtensible Interface (AXI):
o AXI is a more recent and flexible protocol.
o Supports high-performance features such as multiple outstanding transactions, out-of-
order data completion, and burst transactions.
o Ideal for connecting high-speed peripherals, such as GPUs, and for memory interfaces.
o AXI is commonly used in modern SoCs that require high bandwidth, such as in mobile
devices or multimedia systems.
2. AXI Coherency Extensions (ACE):
o A specialized extension of AXI to maintain cache coherency in multi-core systems.
o Essential in systems where multiple processors share memory, enabling efficient data
access across cores without data duplication.
ADVANCED MICROCONTROLLER BUS ARCHITECTURE
CONT..
How the AMBA Buses Work Together

•The different bus types in AMBA are typically organized hierarchically in an SoC:

1. High-Performance Communication:

o Components like CPUs, DMA controllers, and high-speed memory devices are connected
through the AHB or AXI bus, providing fast data transfers.

2. Low-Speed Peripherals:

o Low-bandwidth devices, such as general-purpose I/O (GPIO), timers, and UARTs, are
connected through the APB bus, optimizing power consumption and design simplicity.
ADVANCED MICROCONTROLLER BUS ARCHITECTURE
CONT..
AMBA Protocol Details
1. Advanced High-Performance Bus (AHB):
o Features: Pipelined transfers, single and burst transfers, multiple bus masters, high
throughput.
o Example: Used in memory controllers for fast access to RAM in automotive systems,
where real-time processing is required.
2. Advanced Peripheral Bus (APB):
o Features: Simple interface, low power consumption, suitable for low-latency and low-
bandwidth peripherals.
o Example: Controlling sensors or actuators in automotive systems, which don't need high-
speed communication but should be energy-efficient.
3. Advanced eXtensible Interface (AXI):
o Features: High-performance protocol supporting data bursts, out-of-order transactions,
and multiple masters.
o Example: Connecting GPUs, video processing units, or memory in systems requiring high
data throughput, such as in modern infotainment systems.
INTRODUCTION TO STM32H7XXX
MICROCONTROLLER
What is STM full form?
 STM is an abbreviation which can have multiple full forms as
 Short-term memory,
 Software transactional memory
 Synchronous transport module
 Standard Time Management
 Standard Test Method.

What is STM32 microcontroller?

 STM32 microcontrollers are a family of 32-bit ARM Cortex M based microcontrollers
developed by STMicroelectronics.
 These microcontrollers are characterized by their high-performance computing capabilities
and low power consumption.
INTRODUCTION TO STM32H7XXX MICROCONTROLLER
CONT..
Understanding STM32H7xxx Microcontroller Series:

 The STM32H7xxx microcontroller refers to a specific series within STMicroelectronics' STM32

family of 32-bit microcontrollers.
 The "H7" Refers to the high-performance series within the STM32 family, powered by the
ARM Cortex-M7 core.
 The "xxx" part of STM32H7xxx indicates that the series includes multiple variants with
different feature sets (such as memory size, peripherals, or pin count) tailored to a wide
range of embedded applications.
INTRODUCTION TO STM32H7XXX MICROCONTROLLER
HISTORY
Brief History of STM32 Microcontrollers
 Early Beginnings (2007):
 The STM32 family was first introduced in 2007 by STMicroelectronics.
 The initial models were based on the ARM Cortex-M3 core, focusing on offering a 32-bit
architecture to developers who needed more performance and efficiency than traditional 8-
bit and 16-bit microcontrollers.
 Expansion to Multiple Core Architectures:
 Over time, STMicroelectronics expanded the STM32 family to cover a wide range of
performance and power levels, using different ARM Cortex cores.
 This gave rise to several series within the STM32 family:
o STM32F0 (Cortex-M0): Low-cost, low-power microcontrollers.
o STM32F1/F2/F3/F4 (Cortex-M3/M4): General-purpose and performance-focused
microcontrollers.
o STM32L0/L1/L4 (Cortex-M0+/M4): Ultra-low-power microcontrollers for battery-powered
applications.
o STM32G0/G4 (Cortex-M0+/M4): Bridging the gap between low-power and performance
applications.
INTRODUCTION TO STM32H7XXX MICROCONTROLLER
CONT..
STM32H7 Series:

o 2017: First STM32H7 microcontrollers introduced, featuring a single Cortex-M7 core, clocked at up to
400 MHz, which was the highest-performing Cortex-M microcontroller at the time.
o 2018: The first dual-core STM32H7 models were released, combining a Cortex-M7 (up to 480 MHz)
and a Cortex-M4 (up to 240 MHz) in the same package. This innovation enabled offloading lower-
priority tasks to the M4 core, making the H7 series a versatile solution for complex, multi-tasking
embedded applications.
o 2019-2021: The STM32H7 series continued to evolve with higher clock speeds (up to 550 MHz),
enhanced security features (TrustZone, Secure Boot), and expanded memory options (up to 2 MB of
Flash memory).

STM32H7 Series Evolution:

o Single-core STM32H7: These chips contain only the Cortex-M7 core, focusing on applications where
high-performance is the primary requirement.
o Dual-core STM32H7: By combining Cortex-M7 and Cortex-M4 cores, these chips allow developers to
STM32H7XXX MICROCONTROLLER FEATURES
Powerful Core
 Uses an ARM Cortex-M7 core running up to 550 MHz for high-speed processing.
 Some versions have dual cores (Cortex-M7 and Cortex-M4), allowing efficient handling of
complex tasks.
Lots of Memory
 Up to 2 MB of Flash memory (for storing programs) and 1 MB of RAM (for temporary data
storage).
 External Memory Support: Interfaces for external memory devices like SDRAM, NOR Flash,
NAND Flash, and SRAM, allowing for larger memory capacity in more complex systems.
Advanced Communication
 Ethernet, USB, CAN FD, SPI, UART, and I2C for connecting to networks and other devices.
 Supports fast data transfer and communication with external peripherals.
Graphics and Multimedia
 Has a built-in LCD display controller for graphical user interfaces (GUIs).
 Includes features to handle camera input and image processing.
STM32H7XXX MICROCONTROLLER FEATURES CONT..
Analog Functions
 Analog-to-digital converters (ADCs) to read sensor data.
 Digital-to-analog converters (DACs) for generating audio signals or controlling analog
devices.
Real-Time Control
 Includes timers for generating precise PWM signals (used in motor control, LED dimming,
etc.).
 Integrated Real-Time Clock (RTC) to keep time even when the system is powered off.
Security Features
 TrustZone technology for separating secure and non-secure code.
 Secure Boot to ensure only trusted software runs on the microcontroller.
 Built-in encryption for secure data handling.
Low Power Modes
 Several power-saving modes to reduce energy consumption, making it good for battery-
operated devices.
 Can maintain certain tasks (like timekeeping) while in low-power mode.
Easy Development
STM32XXX MICROCONTROLLER –ARCHITECTURE
 ICode Bus: Connects the
instruction bus of the
Cortex™-M3 core to the
Flash memory instruction
interface. Instruction
fetches are performed on
this bus.
 DCode Bus: Connects the
DCode bus (literal load
and debug access) of the
Cortex™-M3 core to the
Flash memory data
interface.
 System Bus: Connects
the system bus of the
Cortex™-M3 core
(peripherals bus) to a bus
matrix which manages
the arbitration between
the core and the DMA
STM32XXX MICROCONTROLLER –ARCHITECTURE
 DMA Bus: Connects the AHB
master interface of the DMA to
the bus matrix which manages
the access of CPU DCode and
DMA to the SRAM, Flash
memory and peripherals
 Bus Matrix: Manages the
access arbitration between the
core system bus and the DMA
master bus. The arbitration
uses a round robin algorithm
 AHB/APB Bridges (APB): The
two AHB/APB bridges provide
full synchronous connections
between the AHB and the two
APB buses
 APB buses operate at full
speed (up to 24 MHz)
STM32XXX MICROCONTROLLER –ARCHITECTURE
 Program memory, data
memory, registers and I/O
ports are organized within the
same linear 4-Gbyte address
space
 Bytes are coded in memory in
little endian format
 The lowest numbered byte
in a word is considered the
word’s least significant byte
and the highest numbered
byte, the most significant
 Addressable memory space is
divided into 8 main blocks,
each of 512 MB
 STM32XXX MICROCONTROLLER PIN DIAGRAM

• It has an operating voltage

of up to 3.3V.
• It consists of 10 analog
inputs.
• 37 digital I/O pins.
• It has flash memory up to
64/128kb.
• And SRAM up to 20kb.
• Maximum clock frequency
is up to 72MHz.
• It follows I2C, SPI, UART,
and CAN communication
protocols.
STM32XXX MICROCONTROLLER I/O
CONFIGURATION.
STM32H7XXX MICROCONTROLLER
THANK YOU