Hardware Description Languages

Increased traffic volumes resulting from urbanization, industrialization, and population growth have given rise to complex issues, including congestion, accidents, and traffic violations at intersections. In the absence of a functional smart traffic light system, traffic congestion occurs due to imbalanced traffic flow at intersections. Current traffic management lacks provisions for ensuring the unobstructed movement of emergency vehicles, even a small delay for which can have significant consequences. This paper presents a smart traffic light controller developed using Verilog hardware description language (HDL) in Quartus Prime 21.1 and Questa Intel field programmable gate array (FPGA) Starter Edition 2021.2, and implemented on an Altera DE2-115 FPGA. The controller is designed specifically to detect emergency vehicle at four-way intersections for inputs radio frequency identification (RFID) readers and infrared (IR) sensors. The RFID readers and IR sensors are managed through slide switches on the FPGA board. The smart traffic light controller contains three sub-modules: clock division, counter, and finite state machine (FSM) operation, enabling it to manage traffic in scenarios with emergency vehicles, high traffic density, and low traffic density. This proposed system can alleviate intersection congestion by controlling access and allocating time effectively. In conclusion, the project ensures the smooth passage of emergency vehicles by continuously monitoring their presence and giving them priority in traffic flow.

This paper presents the control of the DC-DC Buck converter using Digital Pulse Width Modulation (DPWM) methods in MATLAB-SIMULINK using XILINX TOOL. The conventional PWM is compared with the Digital Pulse Width Modulation. The DPWM generators like Counter based Digital Pulse Width Modulation (CDPWM); Delay-line based Digital Pulse Width Modulation (DDPWM) and Hybrid based Digital Pulse Width Modulation (HDPWM) are coded using VHDL. The DPWM generator is used for the control and analysis of the DC-DC Buck converter. The time transient analysis of the DPWM techniques are evaluated and compared.

System on Chip (SoC) designs inherit all the well known verification and validation difficulties associated with complex ASIC designs, besides adding their own set of newer problems. These arise because SoCs are primarily implemented by re-using Intellectual Property (IP) cores. It is well known that verification today constitutes about 70% to 80% of the total design effort, thereby, making it the most expensive component in terms of cost and time, in the entire design flow. It is expected to get even worse for SoC designs. In a complex SoC design flow functional verification is very important; any behavioral or functional bug escaping this phase will not be detected in the subsequent implementation phases and will surface only after the first silicon is integrated into the target system, resulting in costly design and silicon iterations. A number of academic and industrial research laboratories have been carrying out research on functional verification of SoCs based on different ap...

The aim of the hArtes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedded processor, digital signal processing and reconfigurable hardware. In this paper, we evaluate three tools from the hArtes toolchain supporting profiling, compilation, and HDL generation. These tools facilitate the HW/SW partitioning, co-design, co-verification, and co-execution of demanding embedded applications. The described tools are provided by the DelftWorkBench framework 1. Experimental results on MJPEG and G721 encoder application case studies suggest overall performance improvement of 228% and 36% respectively.

Reconfigurable Computing (RC) is one of the most intensively studied research areas nowadays due to its potential to dramatically increase application performance. RC combines a general purpose processor (GPP) and a Field Programmable Gate Array (FPGA), having the advantages of both hardware performance and software flexibility. Modern real-life applications (such as audio, video, image processing, etc) spend most of the execution time in loops, which represent or include the application kernels. These loops are an important source of performance improvement. In our work, we target loops that contain in their bodies code for the GPP (software functions) and also for the FPGA (hardware functions). We assume there are data dependencies between consecutive tasks in the loop body, but not between different loop iterations. Assuming the Molen machine organization as our framework, we focus on applying existing loop optimizations to such loops, with the purpose of parallelizing applications such that multiple kernel instances run in parallel on the reconfigurable hardware, while concurrently executing code on the GPP. In this paper, we focus on loop transformations that are suitable for loops containing an arbitrary number of software and hardware functions. The extended shifting consists of relocating the functions placed in the beginning and in the end of one loop iteration, in order to eliminate the data dependencies and allow certain software and hardware functions to be executed in parallel. The loop distribution consists of splitting the loop into small loops (e.g., with only one kernel) allowing in some cases a larger degree of parallelism when applying the loop unrolling and shifting techniques. We estimate the performance achieved by applying the extended shifting technique in conjunction with loop unrolling and compare it to the performance achieved when applying the loop unrolling and shifting techniques to smaller loops obtained by distributing the original loop. For the experimental results we used randomly generated tests, for loops containing a variable number of kernels (between 2 and 8 kernels).

This paper proposes a SystemC-based specification methodology of adaptive embedded systems to be implemented on a platform including one or more processors, thus supporting the execution of embedded software, and digital hardware with capabilities of partial dynamic reconfiguration (DRHW). For it, it proposes the collaboration of two specification methodologies: HetSC and OSSS+R. The main issues for the integration of these specification methodologies are addressed. This includes how to install and use them together, which is the structure of the specification, how adaptivity is specified for SW and DRHW implementation, and the syntactical and semanticual issues related to the MoC interface implicit in their connection. 1

The increasing complexity available in Application Specific Integrated Circuits (ASICs) and the requirement for reduced design time have increased the importance of hardware emulators for ASIC system verification prior to first silicon. This paper reviews current ASIC hardware emulators based on Field Programmable Gate Arrays (FPGAs), including their limitations and constraints. Based on these characteristics, FPGA kernel architectures and related technologies are identified that will significantly improve the performance and capabilities of ASIC hardware emulators.

This paper introduces SpecC language, a system level description language based on C, and its consortium, SpecC Technology Open Consortium (STOC). Currently SpecC language version 1.0 is publicly available. SpecC technology covers SpecC-based design "methodology" as well as SpecC language itself. In this paper not only SpecC language but also SpecC-based design methodology are briefly discussed. The SpecC language specification working group (LSWG) under STOC is discussing on SpecC version 2.0. We also give a summary of the discussions being made by LSWG targeting version 2.0. We plan to formally release version 2.0 in the beginning of 2002. The main goal is to precisely and exactly define the formal semantics of SpecC language especially on the semantics relating to parallel and concurrent statements and event control mechanisms. These are the issues on which SpecC version 1.0 does not give clear and concise semantics. With these clarifications given by SpecC version 2.0, varieties of supporting tools for SpecC can consistently and easily be developed.

En este trabajo se presenta una descripción utilizando el lenguaje de descripción de hardware VHDL (Very High Speed Integrated Circuit Hardware Description Language-VHSIC HDL) de un microcontrolador. Se define una estructura interconectada de componentes para describir la mayor parte los integrantes de una familia de microcontroladores comerciales. Cada componente y la estructura propuesta fueron simulados y sus resultados fueron los esperados. Dado que los elementos que constituyen el microcontrolador tienen las características de un sistema complejo (CPU, Memoria y puertos de E/S), la implementación física de un modelo completo nos llevaría a obtener un sistema en chip (System On a Chip-SOC). La descripción completa también permite definir un módulo IP utilizable en diseños con lógica programable.

Contemporary SoC design involves the proper selection of cores from a reference platform. Such selection implies the design exploration of alternative CPUs, which requires the generation of binary code for each possible target. However, the embedded computing market shows a broad spectrum of instruction-set architectures, ranging from micro-controllers to RISCs and ASIPs. As a consequence, binary utilities cannot always rely on pre-existent tools within standard packages. Besides, the task of manually retargeting every binary utility is not acceptable under time-to-market pressure. This paper describes a technique for the automatic generation of binary utilities from an abstract model of the target CPU, which can be synthesized from an arbitrary ADL. The technique is based upon two key mechanisms: model provision for tool generation (at the front-end) and automatic library modification (at the backend). To illustrate the technique's automation effectiveness, we describe the generation of assemblers, linkers and disassemblers. We have successfully compared the files produced by the generated tools to those produced by conventional tools. Moreover, to give proper evidence of retargetability, we present results for MIPS, SPARC, PowerPC and i8051.

The multilevel multiphase technology combines the benefits of multilevel converters and multiphase machines. Recently, a new multilevel multiphase space vector pulsewidth modulation algorithm that is valid for any number of levels and phases was developed. In this paper, a generic digital VHDL module for such an algorithm is presented. This module is parameterizable in relation to the number of levels, the number of phases, and the number of bits of fractional part of the reference vector. It is also technology independent, reusable, and modular. This circuit has been tested by implementation in a field-programmable gate array, with the goal of a balance of speed and area optimization. It was tested by using a five-level five-phase inverter feeding an induction motor.

| W e describe a system, developed as part of the Cameron project, which compiles programs written in a single-assignment subset of C called SA-C into data ow graphs, and then into VHDL. The primary application domain is image processing. The system consists of an optimizing compiler which produces data ow graphs, and a data ow graph to VHDL translator. The method used for the translation is described here, along with some results on an application. The objective is not to produce yet another design entry tool, but rather to shift the programming paradigm from HDLs to an algorithmic level, thereby extending the realm of hardware design to the application programmer. Keywords| Adaptive-computing, Con gurable, Imageprocessing, Recon gurable-components, Recon gurablecomputing, Recon gurable-systems

In this paper, we describe a novel top/down methodology for behavioral and structural modeling of multi domain microsystems. The study case is an integrated power harvesting circuit used for supplying power to nodes in wireless sensor networks. The system includes an analog circuit, a piezoelectric MEMS generator and a storage capacitor. The classical validation of such systems by separate simulation of each element: FEM analysis for mechanical part and traditional circuit-simulators for electrical part does not offer the possibility to predict the behavior of the complete system. To overcome such limitations, we propose to use a simulation environment based on VHDL-AMS and SPICE languages.

This paper starts with an overview of FPGA technology development, followed by a presentation of design methodologies, development tools and relevant CAD environments, including the use of portable hardware description languages and system level programming/design tools. In this paper, a new contribution for the FPGA-Based implementation of controls electrical. This approach is based on concept modularity and reusability. In this paper is presents a detailed description of the structure by Indirect Sliding Mode of Permanent Magnet Synchronous Machine PMSM. Experimental results carried from a prototyping platform are given to illustrate the efficiency and the benefits of the proposed approach and the various stages of implementation of this structure in FPGA.

Multilevel converters can meet the increasing demand of power ratings and power quality associated with reduced harmonic distortion and lower electromagnetic interference. When the number of levels increases, it is necessary to control more and more switches in parallel. Field programmable gate arrays (FPGAs), with their concurrent processing capability, are suitable for the implementation of multilevel modulation algorithms. Among them, space vector pulsewidth modulation algorithms offer great flexibility to optimize switching waveforms and are well suited for digital implementation. In this paper, two algorithms, 2-D and 3-D, are analyzed and implemented in an FPGA. In order to carry out the implementation, both algorithms have been described in very high speed integrated circuit hardware description language, partly hand coded, and partly automatically generated using the System Generator tool. Both implementations are compared in terms of implementation complexity and logic resources required. Finally, test results with a neutral-point-clamped inverter are presented. Index Terms-Field programmable gate array (FPGA), multilevel inverter, space vector pulsewidth modulation (SVPWM).

His research interests center around parallel algorithms and architectures. Facilitating a transition into ubiquitous parallel computing has been a strategic objective for computer science and engineering since its inception in the 1940s. A theory enthusiast, the overriding theme guiding his work was using theory to guide the rest of the field in addressing this strategic objective. Key components in his comprehensive plan include: (i) the very rich PRAM parallel algorithmic theory, and (ii) a PRAM-On-Chip vision comprising the explicit multi-threaded (XMT) computer system framework he invented. The latter provides a powerful approach to multi-core architectures, and, in particular, the exponential increase in the number of cores in the roadmap of most vendors into the late 2010s. Recently, he has focused on the feedback loop between algorithms, their programming and implementation, and architecture, as well as their performance modeling with an eye towards softer aspects, such as their ease-of-programming, teachability and learnability.

Skills in hardware-software co-design are quickly becoming critical to product development in hightechnology computer industries. Systems-on-silicon typically include a considerable amount of software as well as custom hardware and are increasingly difficult to develop using traditional techniques. To satisfy a growing demand in industry, students in electrical engineering, computer engineering, and computer science should be introduced to concepts of hardware-software co-design at the undergraduate level. This paper examines a new laboratory at the University of Missouri-Rolla in which students in Electrical and Computer Engineering are exposed to modern system design concepts through the use of hardware-software co-simulation. Key tools used in the course including a hardware prototype consisting of an 8051 microcontroller and a field programmable gate array, and a VHDL model of the prototype are discussed.

In this paper the hardware implementation of the direct torque control based on the fuzzy logic technique of induction motor on the Field-Programmable Gate Array (FPGA) is presented. Due to its complexity, the fuzzy logic technique implemented on a digital system like the DSP (Digital Signal Processor) and microcontroller is characterized by a calculating delay. This delay is due to the processing speed which depends on the system complexity. The limitation of these solutions is inevitable. To solve this problem, an alternative digital solution is used, based on the FPGA, which is characterized by a fast processing speed, to take the advantage of the performances of the fuzzy logic technique in spite of its complex computation. The Conventional Direct Torque Control (CDTC) of the induction machine faces problems, like the high stator flux, electromagnetic torque ripples, and stator current distortions. To overcome the CDTC problems many methods are used such as the space vector modulation which is sensitive to the parameters variations of the machine, the increase in the switches inverter number which increases the cost of the inverter, and the artificial intelligence. In this paper an intelligent technique based on the fuzzy logic is used because it is allows controlling the systems without knowing the mathematical model. Also, we use a new method based on the Xilinx system generator for the hardware implementation of Direct Torque Fuzzy Control (DTFC) on the FPGA. The simulation results of the DTFC are compared to those of the CDTC. The comparison results illustrate the reduction in the torque and stator flux ripples of the DTFC and show the Xilinx Virtex V FPGA performances in terms of execution time.

Abstract���We developed a compact modeling methodology as well as a niche SPICE design suite to enable integrated circuit design for extreme environment operation. This new design suite, CoolSPICETM, with its low temperature models is expected to significantly improve reliability, performance and lifetime of electronics that are used for space or low temperature niche applications. CoolSPICETM with its graphical user interface including schematics editor and plotter, as shown in Fig. 1, offer a convenient and accurate way to ...

This paper proposes design and
implementation of high throughput adaptive digital
filter. The Filter structure is based on Fast Block
LMS and Distributed Arithmetic (DA). With DA
we can able to calculate inner product by shifting
and accumulating of partial products and storing
in Look up table, also the desired filter will be
multiplier less. Thus DA based implementation of
adaptive filter is highly computational, power and
area efficient. DA based architecture map well to
the today’s Field Programmable Gate Arrays
(FPGA) architecture. FPGA results conforms that
proposed DA based filter requires 50% less area
and 50% less power than that of FBLMS.

A g-sensor based alarm system, available for use in many tilt sensor applications, was programmed and put in use in this work. The DE10-Lite FPGA was used, with its digital accelerometer sensor module ADXL345. The tilt sensor is programmed to present in seven segment display of the FPGA board, angle values from 0 to 90 degrees, using minus sign when the slope is to the right and the positive one when it tilts to the left, thus informing us about the sensor's tilt direction. Simultaneously the FPGA's right or left LEDs light up according to system tilt. It also uses key button for freezing its operation, hence presenting the latest angle value. The program controlling the sensor gives the ability of entering a critical angle value, depending on the application. As soon as this value is exceeded buzzer is activated, thus giving our system an alarm behavior.

Architecture Description Languages provide significant opportunity for the incorporation of formal methods and engineering models into the analysis of software and system architectures. A standard is being developed for embedded real-time safety critical systems which will support the use of various formal approaches to analyze the impact of the composition of systems from hardware and software and which will allow the generation of system glue code with the performance qualities predicted. The SAE AADL standard (International Society for Automotive Engineers (SAE) Architecture Analysis & Design Language) is based on the MetaH language developed under DARPA and US Army funding and on the model driven architectural based approach demonstrated with this technology over the last 12 years. The SAE AADL standard is aimed at supporting avionics, space, automotive, robotics and other real-time concurrent processing domains including safety critical applications.

Machine learning techniques, especially deep learning, are playing an increasingly important role in our lives. Deep learning uses different models to extract information from the data. They have already had a huge impact in areas such as health (i.e., cancer diagnosis), self-driving cars, speech recognition, and data encryption. Recently, deep learning models, including convolutional neural networks (CNN), have been proven to be more effective in the security field. Moreover, the National Institute of Standards and Technology (NIST) recommends the advanced encryption standard (AES) algorithm as the most often utilized encryption method in several security applications. In this paper, a crypt-intelligent system (CIS) capable of securing data is proposed. It is based on the combination of the performance of CNN with the AES, by substituting the key expansion unit of AES with a CNN architecture that performs the key generation. Our CIS is described using very high-speed integrated circuit (VHSIC) hardware description language (VHDL), simulated by ModelSim, synthesized, and implemented with Xilinx ISE 14.7. Finally, the Airtex-7 series XC7A100T device has achieved an encryption throughput of 965.88 Mbps. In addition, the CIS offers a high degree of flexibility and is supported by reconfigurability, based on the experimental results, if sufficient resources are available, the architecture can provide performance that can satisfy cryptographic applications.

Statecharts is a visual formalism suitable for high-level system specification, while Verilog is a hardware description language that can be used for both behavioural and structural specification of (hardware) systems. This paper implements a semantics-preserving mapping from Graphical Statecharts to Verilog programs, which, to the best of our knowledge, is the first algorithm to bridge the gap between Statecharts and Verilog, and can be embedded into the hardware/software co-specification process [19] as a front-end.

In brief, by operating the shifting and addition in parallel, an error-compensated addertree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-tonoise-ratio (PSNR) requirements. Thus, an areaefficient DCT core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements outlined in the

Elliptic Curve Cryptography (ECC) is one of the most interesting systems for protecting sensitive information nowadays. The latest versions of the Java Platform include classes and interfaces making ECC available to programmers, but due to the nature of Java it is still necessary to employ additional third party packages in order to use cryptographic operations and procedures related to ECC. In the present work, an extensive review of the most important ECC implementations in Java is presented.

Photodynamic therapy (PDT) is a method of treating cancer that combines light and light-sensitive drugs to selectively destroy cancerous tumours without harming the healthy tissue. The success of PDT depends on the accurate computation of light dose distribution. Monte Carlo (MC) simulations can provide an accurate solution for light dose distribution, but have high computation time that prevents them from being used in treatment planning. To alleviate this problem, a hardware design of an MC simulation based on the gold standard software in biophotonics was implemented on a large modern FPGA [1]. This implementation achieved a 28-fold speedup and 716-fold lower power-delay product compared to the gold standard software executed on a 3 GHz Intel Xeon 5160 processor. The accuracy of the hardware was compared to the gold standard using a realistic skin model. An experiment using 100 million photon packets yielded a light dose distribution that diverged by less than 0.1 mm. We also describe our development methodology, which employs an intermediate hardware description in SystemC [2] prior to Verilog coding that led to significant design effort efficiency.

Floating point multiplication is.a key.Significance to. many.modern.applications.such as image processing, signal processing etc.The performance of DSP systems usually decided with the performance.of.the.multiplier.because.the.multiplier is the slowest.constituent in the.system..As, the multiplication dominates the execution time of most of the DSP application, hence a high speed multiplier is much preferred. This paper proposes an effective scheme for floating point multiplication that offers a superior implementation in terms of delay and area. A group of Karatsuba and Urdhva-Tiryagbhyam algorithm is used to implement a binary multiplier for mantissa multiplication. The IEEE 754 format used for the representation of a floating point number. The algorithms are implemented with Verilog (HDL) and targeted on FPGA Vertex 5 board and for the simulation purpose Xilinx ISE simulator is used and a table of delay performance, device utilization is made.

O presente trabalho objetiva estudar as migrações internas, principalmente do campo para a cidade. Foram analisadas questões relativas às características sociais, econômicas e identitárias de produtores familiares, visando também a permanência no campo dos mesmos, e quais ações o Estado tem desenvolvido para que ocorra essa fixação nos dias atuais.

We present a method to estimate the power and energy consumption of an algorithm directly from the C program. Three models are involved: a model for the targeted processor (the power model), a model for the algorithm, and a model for the compiler (the prediction model). A functional-level power analysis is performed to obtain the power model. Five power models have been developed so far, for different architectures, from the simple RISC ARM7 to the very complex VLIW DSP TI C64. Important phenomena are taken into account, like cache misses, pipeline stalls, and internal/external memory accesses. The model for the algorithm expresses the algorithm’s influence over the processor’s activity. The prediction model represents the behavior of the compiler, and how it will allow the algorithm to use the processor’s resources. The data mapping is considered at that stage. We have developed a tool, SoftExplorer, which performs estimation both at the C-level and the assembly level. Estimations ...

This paper holds a brief methodology in the fundamentals of logic design simulation-based modelling with analytics that integrate block components. The simulation analysis and modelling techniques are considered together with the resulting output and advancement in modern logic design analytics. Two brief examples were illustrated as a base for the future design of 3D representation of logical design and demonstrate how we can dramatically develop efficient logical events simulation of the models. The problems highlighted started with an introduction to logic gates and a simple performance estimation that progressed to dynamic multiple logical stepwise processes for 2-4 bit logic design.

A new orientation for a multidisciplinary Industrial Engineering program course on Digital Electronics is proposed. Students are trained to describe complete systems in VHDL. These systems have been previously modeled with Matlab/Simulink ®, including both continuous and discrete components. Digital controllers based on concurrent hardware are designed for these systems in the same framework. After developing and simulating the behavioral model of the system or plant, the controller is re-described under the synthesis constraints and implemented in an FPGA evaluation board for verification along with the system under control. In this way, the course is not only intended for digital electronics specialists but also for students with diverse engineering backgrounds.

In this paper we present our results on verifying the implementation of a SCI-PHY (Saturn Compatible Interface for ATM-PHY devices) Level 2 protocol engine, commercialized by PMC-Sierra, Inc. Using the FormalCheck tool, we first established a proper verification environment, then defined a number of relevant liveness and safety properties, which we checked on an abstracted (8 PHY devices) as well as the original (32 PHY devices) hardware model. Throughout our verification efforts, we uncovered a number of mismatches between the hardware design in VHDL and the SCI-PHY protocol specification. Some of these are pertinent design bugs which were not caught during the simulation process.

h i g h l i g h t s • Multi-level design space exploration for Multiprocessor Systems-on-Chip (MPSoC). • Design exploration at the functional and transactional level. • Integration of runtime power optimization in the design flow. • A simulation time of less 1 s at the functional level and 160-190 s at the transactional level. • An average error of 1.59% of the transactional level results compared to physical implementations.

FPGA is a portable and very powerful device to efficiently implementation the logic. This paper presents a general idea to provide security when data is on channels there is a possibility that it can be affected by some malicious function. To avoid this condition some encoding schemes were used like Hamming code, block code, Turbo codes, CRC-cyclic redundancy check-based etc. This paper presents a review on number of scholars work and coding scheme introduced in those papers is binary Golay code (G23) and extended binary Golay (G24).These codes were used for the fulfillment of required high speed with low-latency, higher security and less complexity architecture. The main purpose of this paper is to introduce a new scheme in future that can be implemented on FPGA using both binary Golay code (G23) and extended binary Golay (G24).

Asynchronous circuits is an alternative to design digital systems that is becoming the interest of many researchers in the digital design area mainly due to it's low-power consumption and robustness. One of the most compelling design paradigms of asynchronous circuits is the NULL Convention Logic (NCL). The pipeline is a very common technique used in digital circuits to achieve high throughput. Although one can implement a pipeline using NCL gates, recent works have shown that register-less pipelines are possible using modified NCL gates. In this paper we propose two new Register-Less NCL (RL-NCL) pipeline architectures and two new methods to design NCL gates, which can be implemented even in Field Programmable Gate Arrays (FPGAs) or using the standard cells method. The new design of the proposed architecture was able to achieve an average area reduction of 27,32%, an average latency reduction of 14,1% and an average throughput increase of 5,54% comparing with the conventional NCL pipeline architecture.

The paper deals with the implementation of a high performances auto-tuning PID regulator by means of the Logic Cell Arrays (LCA) devices. The auto-tuning method is based on a preliminary use of Relay control to bring the output of the closedloop system to a permanent oscillating condition. The prototype is composed by two printed circuit boards: the first one, dedicated to the auto-tuning algorithm, is based on a 280 microprocessor, while the second one, equipped with 7 LCAs, is charged with the control tasks, i.e. the PID and Relay actions.

It is generally overlooked that designers use functional models more frequently than behavioral or gate-level models. In functional modeling, the functionality of one or more register-transfer level RTL) components are described language such as VHDL. In this paper, we present two algorithms that synthesize a netlist of RTL components from a functional description while minimizing hardware costs and delay. Experimental results show that the proposed algorithms produce designs that are comparable to those produced by human designers. as separate concurrent bloc i s using a hardware description 0738-100)(/92 33.00 Q 1992 IEEE

It is generally overlooked that designers use functional models more frequently than behavioral or gate-level models. In functional modeling, the functionality of one or more register-transfer level RTL) components are described language such as VHDL. In this paper, we present two algorithms that synthesize a netlist of RTL components from a functional description while minimizing hardware costs and delay. Experimental results show that the proposed algorithms produce designs that are comparable to those produced by human designers. as separate concurrent bloc i s using a hardware description 0738-100)(/92 33.00 Q 1992 IEEE