Hardware Description Languages

This paper provides insight into the development of System Verilog Assertions standardization efforts. Specifically it covers the evolution from Accellera 3.1a version to its current state of standardization (the upcoming SVA2012 release). Insight into the new features, changes and the reasons for the same exposes users of SVA to the direction the standard is evolving.

This paper presents a methodology for a unified cosimulation and co-synthesis of hardware-software systems. This approach addresses the modeling of communication between the hardware and software modules at different abstraction levels and for different design tools. The main contribution is the use of a multi-view library concept in order to hide specific hardware/software implementation details and communication schemes. A system is viewed as a set of communicating hardware(VHDL) and software(C) subsystems. The same C, VHDL descriptions can be used for both co-simulation and hardware-software co-synthesis. This approach is ilustrated by an example.

This paper presents a clock selection algorithm for control-flow intensive behaviors that are characterized by the presence of conditionals and deeply-nested loops. Unlike previous works, which are primarily geared towards data-dominated behaviors, this algorithm examines the effects of branch probabilities and their interaction with allocation constraints.

The introduction of HDLs (hardware description languages) have made a significant contribution to VLSI circuit design. While these languages are well suited to describe circuits in great detail, they are found wanting when attempting formal verification of circuits. One of the drawbacks lies in the lack of formal models of semantics. VHDL, with a wide variety of tools available to carry out circuit simulations, is the de facto standard used in VLSI design. On the other hand, the family of synchronous languages has been well studied for the design and synthesis of provably correct reactive systems. Thus, it behooves one to explore the possibility of interfacing languages such as VHDL with synchronous programming languages to handle higher levels of abstraction in circuit design with assured correctness. In this paper, we show how the paradigm of Multiclock ESTEREL provides a framework for the design of multi-clocked systems and asynchronous systems. Multiclock ESTEREL can be used for modeling in conjunction with VHDL to enable formal verification of circuit behavior. We shall also show that Multiclock ESTEREL captures the VHDL timing model succinctly. Multiclock ESTEREL can be used either in conjunction with VHDL or as a replacement depending on the requirements at hand. When used in conjunction, Multiclock ES-TEREL can be used to describe circuits at higher levels of abstraction while VHDL can be used to describe the signal propagation characteristics.

As técnicas de processamento digital de imagens tendem a ser extremamente custosas computacionalmente. Isso leva os cientistas da área a procurar soluções com desempenho otimizado. Sendo assim, neste trabalho foi implementado um hardware otimizado (comumente tem-se soluções baseadas em software) para os filtros Sharpen e Smooth de pré-processamento de imagens, os quais tem por objetivo melhorar a qualidade da imagem, cujo destino, nesse caso, é passar pelo filtro Prewitt de detecção de bordas.

This work shows a modular architecture based on FPGA's to solve the eigenvalue problem according to the Jacobi method. This method is able to solve the eigenvalues and eigenvectors concurrently. The main contribution of this work is the low execution time compared with other sequential algorithms, and minimal internal FPGA consumed resources, mainly due to the fact of using the CORDIC algorithm. Two CORDIC modules have been designed to solve the trigonometric operations involved. A parallel CORDIC architecture is proposed as it is the best option to compute the eigenvalues with this method. Both CORDIC modules can work in rotation and vector mode. The whole system has been done in VHDL language, attempting to optimize the design. * Project SILPAR (Ministerio de Ciencia y Tecnología ref: DPI2003-05067) and "Cátedra de control electrónico en transportes" founded by LOGYTEL and RENFE.

The VHDL Standard current allows concurrent access to variables shared between processes, but does not define any semantics for concurrency control. The IEEE 1076a Shared Variables Working Group has developed a form of monitors, called protected types, to provide mutually exclusive access to shared variables. This article identifies the problems that can arise from unprotected concurrent access to shared variables, and reviews the idea of monitors, which forms the basis of the proposed language change. It then describes protected types, gives some guidelines on using them for hardware modeling, and includes an example to illustrate their use.

The aim of the hArtes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedded processor, digital signal processing and reconfigurable hardware. In this paper, we evaluate three tools from the hArtes toolchain supporting profiling, compilation, and HDL generation. These tools facilitate the HW/SW partitioning, co-design, co-verification, and co-execution of demanding embedded applications. The described tools are provided by the DelftWorkBench framework 1. Experimental results on MJPEG and G721 encoder application case studies suggest overall performance improvement of 228% and 36% respectively.

The wavelet transform is an efficient technique for multi-resolution analysis of non-stationary and fast transient signals. For this reason, wavelet transform has been widely applied in signal analysis through processing, encoding, denoising and encrypting. The objective of this paper is to represent the development process of VHSIC (Very High Speed Integrated

The overall operation of a direct digital frequency synthesiser (DDFS) is based on a look-up table method, which performs functional mapping from phase to sine amplitude. The spectral purity of the conventional DDFS is determined by the resolution of the values stored in the sine table ROM. However, large ROM storage means higher power consumption, increased silicon area, lower reliability, lower speed and increased costs. A novel systematic design methodology for implementing a DDFS architecture with reduced memory size is introduced. Describing the proposed architecture using the hardware description language VHDL, it is possible to generate a plethora of alternative realisations in terms of the number of input and output bits, the memory size, the number of gates, the memory segmentation parameters and the spectral purity. In other words, the designer can perform extensive architecture exploration to reach an optimal solution. The experimental results prove that the new DDFS architecture can be realised with a smaller hardware complexity and total power consumption and improved performance compared to many existing approaches.

The objective of the work reported in this paper is to improve a 4-bit softcore processor previously designed in Verilog language, keeping its compact size. This processor was thought to be used as academic and didactic tool for teaching as computers architecture subject as digital circuits subject in the technology faculty of the Universidad Distrital. The new features include arithmetic instruction with input carry, BCD operations enabling, rotating instructions, implementation of input and output register banks, increase of the number of general purpose registers of the data memory, and the reduction of the execution clock cycles per instruction. Additionally, the assembler software was enabled to support macro-instructions to make easy the comprehension of some composed functions. As result, a very compact softcore processor was obtained, by means of a Verilog description done in a single file. This implementation occupies only the 2% of the medium-size FPGA used for the application, reaching a maximum possible working clock frequency of 929 Mhz.

Field programmable gate arrays (FPGAs) play many important roles, ranging from small glue logic replacement to System-on-Chip designs. Nevertheless, FPGA vendors can not accurately specify the energy consumption information of their products on the device data sheets because the energy consumption of FPGAs is strongly dependent on target circuit including resource utilization, logic partitioning, mapping, placement and route. While major CAD tools have started to report average power consumption under given transition activities, energy optimal FPGA design demands more detailed energy estimation.

The design of a reconfigurable capacitive sensor array interface comprised of a subsystem able to read an array of capacitive-type sensors and an embedded processor is described. Each sensor is connected to a ring oscillator, which translates capacitive changes into a variable-frequency pulse train. An indepth analysis of the oscillator behavior including all parasitic elements has been performed, and the use of a Schmitt trigger at the inverter chain is proposed to assure oscillation for capacitance values ranging from 1 to 1500 pF. The oscillation frequency is estimated by using a 16-b counter and the appropriate userdefined counting interval ranging from a few microseconds to several seconds in order to achieve maximum accuracy within the entire capacitance range. The 2-B word thus produced can be sent to a host computer through a serial or parallel interface for further processing. To demonstrate the concept, a 16-channel interface has been described in a hardware description language and implemented on a complex programmable logic device. Measurement of two different capacitive pressure sensors developed in-house reveals frequency sensitivity values of −252.1 and −9.54 Hz/fF, which are in good agreement with the expected values derived by the analytic relations.

. As a consequence, there is a growing interest in efficient implementations of the AES. For many applications, these implementations need to be resistant against side channel attacks, that is, it should not be too easy to extract secret information from physical measurements on the device. This article presents the first results on the feasibility of power analysis attack against an AES hardware implementation. Our attack is targeted against an ASIC implementation of the AES developed by the ETH Zurich. We show how to build a reliable measurement setup and how to improve the correlation coefficients, i.e., the signal to noise ratio for our measurements. Our approach is also the first step to link a behavior HDL simulator generated simulated power measurements to real power measurements.

Automation industry is experiencing a boom in the deployment of FPGA based controlling systems, which beat the run-time characteristics and behavior of microprocessors-based systems and which will bring new possibilities to the sector. Particularly, FPGAs are being progressively applied to develop PLCs. However, the end user, accustomed to traditional PLC programming environments, is reluctant to this new technology, which requires an additional effort for learning a new language and development environment. This paper presents a prototype tool that applies the relatively new Model-Driven Software Development approach to program these new devices using the classical ladder diagram notation. It also demonstrates its application in the classic star-delta starter for 3-phase motors.

This paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has been designed and implemented to write assembly programs in this teaching tool. In addition to the microoperation simulation, the complete configuration can be run on Xilinx Spartan-3 FPGA board. Such implementation offers good code density, easy customization, easily developed software, small area, and high performance at low cost.

In this paper, a VHDL model of a second-order all-digital phase-locked loop (ADPLL) based on bang-bang phase detectors is presented. The developed ADPLL is destined to be a part of a distributed clock generators based on networks of the ADPLL. The paper presents an original model and architecture of a digital multi-bit phase-frequency detector (PFD), and describes in details the VHDL modeling of metastability issues related with asynchronous operation of the digital PFD. This particular architecture of the digital PHD is required by the synchronised operation of the ADPLL network in the context of distributed clock generator. The whole ADPLL model have been validated by purely behavioral (VHDL) and mixed simulation, in which the digital PFD detector was represented by its transistor-level model.

This paper presents how one can effectively transfer electric power wirelessly using magnetic resonance coupling, this paper also shows the results obtained from effective wireless electric power transmission, these results are obtained by transmitting magnetic waves at specific resonance frequency between two coils. This paper also provides some ways to improve wireless power transmission efficiency. In the end this paper gives a lot of practical applications where results of this project can efficiently use.

Performance and power consumption are very important aspects of embedded systems design. Several studies have shown that cache memory consumes as much as 50% of the total power in such systems. Thus, the architecture of the cache governs both performance and power usage of the embedded system. In this paper a new Reconfigurable Embedded Data (RED) cache is proposed especially targeted towards embedded systems. This paper further explores the issues and considerations involved in designing such a reconfigurable cache. The novelty of the RED cache architecture lies in the fact that it can be configured as direct-mapped, two-way, or four-way set associative using a mode selector function. Thus, one cache design can be used for different applications. The module has been designed, simulated and synthesized in Xilinx ISE 9.1i and ModelSim SE 6.3e using the Verilog hardware description language.

An efficient piecewise linear approximation of a nonlinear function (PLAN) is proposed. This uses a simple digital gate design to perform a direct transformation from X to Y, where X is the input and Y is the approximated sigmoidal output. This PLAN is then used within the outputs of an artificial neural network to perform the nonlinear approximation. The comparison of this technique with two other sigmoidal approximation techniques for digital circuits is presented and the results show that the fast and compact digital circuit proposed produces the closest approximation to the sigmoid function. The hardware implementation of PLAN has been verified by a VHDL simulation with Mentor Graphics running under the UNIX operating system.

Verification of real time embedded systems is becoming more and more complex in terms of maintaining the code size and keeping equivalence between the specification. It requires the simulation of the system and the checking of its timing and functional properties as well as constraints. The paper presents a methodology which starts from UML sequence diagrams with MARTE timing constraints and generates a VHDL model with checkers. The simulation of the model allows to verify the specified sequence of exchanged information between components while checkers allow to verify that properties and timing constraints are met. The application of the methodology to the design of a wireless sensor node shows the validity of the approach and its simulation overhead.

The performance of any processor solely depends upon its power, area and delay. In order to get an effective processor, its power, area and delay should be less. Division is always considered to be bulky and one of the most difficult operations in arithmetic and hence all the implementations of division algorithms in VLSI architecture have higher orders of time and space complexities. Vedic Mathematics on the other hand offers a new holistic approach to mathematics. Its range extends from the most concrete values of numerical computation to the most abstract aspects of the dynamics of intelligence. In this work we have implemented an optimized binary division architecture using sutras of Vedic Mathematics which are Nikhilam Sutra and Parvartya Sutra. This work discusses about these two algorithms of division and their application for calculating deconvolution. Both the algorithms have been implemented with improved results of time delay and are with fewer complexities. The proposed division algorithm is coded in Verilog, synthesized and simulated using Xilinx ISE design suit 14.2. Simulated results for proposed Vedic divider circuit shows a reduction in delay of 19% than the conventional method.

We present a simple and rapid prototyping technique for Field Programmable Gate Array (FPGAs)-based digital controllers for power electronics and motor drives using MATLAB's Simulink and HDL Coder design software. The MATLAB/Simulink models are optimized and converted to

The contemporary design of sophisticated digital signal processing platforms involves the use of specifications at an increasingly raised abstraction level. This scheme is dictated by the ever growing divide between available circuit complexity and developer productivity. Algorithm developers tend to use very high-level programming languages such as MATLAB in order to rapidly and seamlessly generate low-level design facets such as ANSI C reference implementations and synthesizable HDL code. In this paper, a generic and parameterized implementation of fixed-point rounding operators in the VHDL hardware description language is introduced. Most hardware compilation frameworks either lack the support of these operators or provide specialized and non-portable implementations. Further, this is the first time that an implementation for these operators is being proposed, that can take advantage of features only present in the VHDL-2008 standard. Compared to existing fixed-point rounding, th...

In this paper we report our implealentation of Serpent algorithm 017 Virtex XCVlOOO FPGA using partial evaluation technique. Partial reconflgurafion is used in this implementation. The major eflect of using partial reconjguration is higher performance mid reduced required are0 compared with other iinplementations. The design is pipeliired in inner-outer of each round of the cpher and the results show thal this impleirientution has higher pepfomiatice in terms of encrypfion/decTpfion speed compared with other recent[v reported iniplenievtations. O w design was described with W D L . The JBits sofnvare was used to do partial recon$guration.

Recent work has shown the feasibility of integrating nonparametric frequency-domain system identification functionality into digital controllers for switched-mode pulse-width modulated (PWM) dc-dc power converters. The resulting discrete-time frequency response can be used for design, diagnostic, or self-tuning purposes. The success of these applications depends on the fidelity of the identified frequency responses and the degree to which the process is automated, as well as the costs, in terms of gate count, time duration of identification, and effect on output voltage, incurred to obtain these benefits. This paper demonstrates the feasibility of incorporating fully automated frequency response measurement capabilities in digital PWM controllers at relatively low additional cost. In particular, it is shown that relatively accurate and smooth frequency response data can be obtained using a Verilog-coded implementation with low tens of thousands of logic gates and about 10 kB of memory. The identification process can be accomplished in several hundred milliseconds and the output voltage can be kept within specified bounds during the entire process. Experimental results are provided for four different PWM dc-dc converters, including a synchronous buck with two different filter capacitors, a boost operating in continuous conduction mode (CCM), and a boost operating in discontinuous conduction mode (DCM).

This work proposes an VHDL generation software for optimized FIR filters. In this paper a near optimum algorithm for constant coefficient FIR filters was used. This algorithm uses general coefficient representation for the optimal sharing of partial products in Multiple Constants Multiplications (MCM). The developed tool was compared to Matlab FDA toolbox. Synthesis results show that our tool is able to produce significantly better hardware than FDA toolbox, doubling the speed and reducing the silicon area by 75%. The software produces a generic VHDL output, synthesizable to ASIC or FPGA.

To successfilly transmit data over any network, a protocol is required to manage the flow or pace at which the data is transmitted. This protocol is defined in Layer 2 of OS1 (Open Systems Interconnection) model. High-level Data Link Control (HDLC) is the most commonly used Layer 2 protocol and is suitable for bit oriented packet transmission mode. This paper discusses thc VHDL modeling of single-channel HDLC Layer 2 protocol Transmitter and its implementation using Xilinx Virtex FPGA as the target technology. The HDLC Transmitter is used to transmit the HDLC frame structure. Implementing the single-channel HDLC protocol Transmitter in FPGA gives you the flexibility] upgradability and customization benefits of programmable logic.

This paper describes the field programmable gate array (FPGA) implementation of Rijndael algorithm based on a novel design of S-box built using reduced residue of prime numbers. The objective is to present an efficient hardware implementation of Rijndael using very high speed integrated circuit hardware description language (VHDL). The novel S-box look up table (LUT) entries forms a set of reduced residue of prime number, which forms a mathematical field. The S-box with reduced residue of prime number adds more confusion to the entire process of Rijndael and makes it more complex and immune to algebraic attacks. The target hardware used in this paper is state-of-the-art Xilinx Virtex-5 XC5VLX50 FPGA. The proposed design achieves a throughput of 3.09 Gbps using only 1745 slices.

In this paper, a scalable scheme, configurable via register-transfer level parameters, for full register bypassing in a modern embedded processor architecture, termed ByoRISC, is presented. The register bypassing specification is parameterized regarding the number of homogeneous register file read and write ports and the number of pipeline stages of the processor. The performance characteristics (cycle time, chip area) of the proposed technique have been evaluated for FPGA target implementations of the synthesizable ByoRISC model. It is proved that, a full bypassing network is a viable solution for the elimination of data hazards when servicing instructions with multiple read and write operands. While the maximum clock frequency is reduced by 17.9% in average, when using partial versus full forwarding, the positive effect of custom computation eliminates this effect by providing cycle speedups of 3.9Â to 5.5Â and corresponding execution time speedups for a ByoRISC testbed processor of 3.6Â. Individual application speedups of up to 9.4Â have also been obtained.

We address a problem of reusing and customizing soft IP components by introducing a concept of design processa series of common, well-defined and well-proven domainspecific actions and methods performed to achieve a certain design aim. We especially examine system-level design processes that are aimed at designing a hardware system by integrating soft IPs at a high level of abstraction. We combine this concept with object-oriented hardware design using UML and metaprogramming paradigm for describing generation of domain code.

This work focuses on the realization of convolutional encoder and adaptive Viterbi decoder (AVD) with a constraint length, K of 3 and a code rate (k/n) of 1/2 using fieldprogrammable gate array (FPGA) technology. This paper presents a 4-state, radix-2, hard decision AVD which has the ability to decode adaptively through different traceback length (TL). The performance of the implemented AVD is analyzed by using ISE 9.2 and MATLAB simulations. The AVD is targeted to a Xilinx XCV300PQ240-4 FPGA device for hardware realization. The decoder parameter TL can be reconfigured via the implementation of AVD, in accordance with the changing channel noise characteristics of the threshold signal-to-noise ratio (SNR), which is 6 dB. The synthesis results show that the reconfiguration parameter TL of 4 and 15 of AVD implementation has significant difference (>20% improvement) in FPGA device utilization. The results also show that the use of reconfiguration leads to a 28% area occupancy of slice usage improvement over a TL of 15 model compared to a TL of 4 model with tolerable loss of decode accuracy, in accordance with the bit error rate (BER) for real-time voice and video.

High temperature has a direct impact on the behavior of an integrated circuit (IC). Instrumentation and measurement circuits and systems are one of the most sensitive ICs to such working condition. Modeling the temperature impact on these systems could be achieved by many approaches. In this paper, we present an attractive method to characterize the temperature effect on an elementary circuit: the operational amplifier (op amp). We develop a behavioral model for a commercial operational amplifier by using a set of temperature measurements of common performance parameters. As it presents several advantages, VHDL-AMS language was chosen to develop the model.

The inherent parallelism of Artificial Neural Networks (ANNs) introduces several difficulties for its software implementation because of the sequential nature of von Neumann architectures. In contrast, hardware implementations offer the possibility to explore the massive parallelism implicit in this model. Also, due to the dynamic nature of ANN's synapses, a flexible hardware platform is required for obtaining efficient solutions. Implementations of ANNs in FPGAs overcomes the lack of flexibility of ASICs, and are the most adequate technology for this task. One important question in this field is how to quickly and efficiently evaluate several alternative implementations taking into account the area and timing restrictions of the circuit. This paper presents a flexible high level description and synthesis tool called VANNGen, which allows the designer to explore different hardware implementations of ANNs. In addition, the user can generate synthesizable VHDL code for the Xilinx and Altera FPGA devices.

This paper presents a sensorless neural-networkbased induction motor control scheme, developed by following a holistic approach to electronic system modeling and controller design. The method uses Very-high-speed integrated circuits Hardware Description Language (VHDL), allowing the engineering system's functional description to be combined with a detailed digital controller design, which is then implemented into a fieldprogrammable gate array (FPGA). The VHDL description of the hardware-implemented neural networks is automatically generated by C++ programs, in an adaptable architecture, appropriate to low-dynamic systems such as fans and pumps. The complete system performance is investigated by simulation and validated experimentally. This approach provides advantages such as a unique modeling and evaluation environment for complete power electronic systems, the same environment is used for the digital controller design and compact FPGA rapid prototyping, fast design development, short time to market, a CAD platform independent model, and reusability of the model/design. Index Terms-Control systems, field-programmable gate arrays (FPGA), induction motor drives, modeling, neural networks. and Transilvania University of Brasov. He has published several technical books and about 95 peer-reviewed papers. His research focus is on digital circuit design, control systems for power electronics, holistic modeling of electronic systems, field-programmable gate arrays (FPGAs), and application-specific integrated circuit design. He has delivered five international courses/tutorials on very-high-speed integrated circuits hardware description language digital controller design applied to power electronic systems modeling and FPGA controller prototyping.

Math2Mat aims at automatically generating a VHDL description of a mathematical description written in Octave/Matlab. The generation creates a synthesizable RTL description using floating point operators (32 or 64 bits) combined in a fully pipelined way. Emphasis is put on the throughput attainable by the design, especially in the "for loop" implementation. The software also offers a graphical user interface, letting the developer manage the different parameters before generation. Verification can also be launched from the software, a SystemVerilog testbench being automatically generated.

Finite state machines (FSM) are a basic component in hardware design, they represent the transformation behveen inputs and outputs for sequential designs. FSMs can be rep-resented graphically, which would help the designer to visu-alize and design in R more efficient WRY, on the other ...

This paper presents a hardware-in-the-loop (HIL) simulation technique applied to a series-resonant multiple-output inverter for new multi-inductor domestic induction heating platforms. The control of the topology is based on a systemon-programmable chip (SoPC) solution, which combines the MicroBlaze embedded soft-core processor and a customized peripheral that generates the power converter control signals. The firmware is written in C, and the customized peripheral is described using a hardware description language. Simulating the whole system using digital or mixed-signal simulation tools is a very time-consuming task due to the embedded processor model complexity, and additionally, it does not support tracing C instructions. To overcome these limitations, this paper proposes a real-time simulation test bench. The embedded processor core, peripherals, and the power converter model are all implemented into the same field-programmable gate array (FPGA). Using the hardware and software debugging tools supplied by the FPGA vendor, currents and voltages of the power converter model are monitored, and firmware C instructions are traced while running on the embedded processor core. Then, it is presented a design flow that is proven to be an effective and low-cost solution to verify the functionality of the customized peripheral and to implement a platform to perform firmware verification.

Efficient simulation of wireless systems requires the development of antenna models compatible with microelectronic tools. This article describes a first behavioral antenna model using the VHDL-AMS language. Moreover, we present a complete behavioral RFID system model using this antenna model. Finally, several system simulation results demonstrate the interest of this approach.