RFIC Design

This paper presents the design and simulation of single stage low noise amplifier for wireless applications operating at the frequency of 2.45 GHz. In this paper the source degeneration topology is used and the inductor used at the source terminal is practically designed planar spiral inductor. The simulation is done using Advanced Design System (ADS). The proposed design provides a gain > 10 dB and noise figure < 2 dB at the operating frequency.

This paper presents low power CMOS RF front-end LNA architecture, employing voltage controlled capacitor in input matching with inductive source degeneration topology and current reused technique. This LNA is designed for Bluetooth application that provide circuit performance at 2.4 GHz. we are using TSMC 0.18 μm CMOS for this architecture. From the simulation results, the fully integrated LNA exhibits a gain of 13.39 dB and a noise figure of 1.44 dB at 2.4 GHz, operated at a supply voltage of 1.5 V. The design process is simulated using Advance Design System (ADS).

—This paper derives and analyzes the s-domain linear and time domain nonlinear models for a C-band wide locking range injection locked voltage controlled oscillator (ILVCO). Van der Pol equation is conducted to describe the behavior of ILVCO with different injection frequencies. Three phase plane plots, that are free-run, injection locked, and chaos states, are observed. The proposed ILVCO is fabricated in tsmc TM 0.18 μm 1P6M process. The measurements show that the locking range is from 3.6 GHz to 6.4 GHz at 0-dBm input power. The locking bandwidth is calculated as 56%.

— This paper presents the design of a CMOS low noise amplifier (LNA) with minimized group delay variations and optimized noise performance for ultra-wideband (UWB) applications. The proposed LNA employs a common source based current reuse topology. Through this configuration gain flatness of 12.25± 0.25 with noise figure (NF) less than 3.8 dB are achieved. This LNA achieves group delay variation of ±25 ps using the standard 0.18 µm CMOS technology. Weak Capacitive-Resistive shunt feedback technique is implemented across the input stage for wideband input matching. Series peaking with output resistive termination are adopted for group delay variations optimization. This UWB LNA has a measured 1dB compression point (P1dB) and an input third-order inter-modulation point (IIP3) of-7.0 dBm and 2.5 dBm respectively at 5.5 GHz. The implemented UWB LNA chip area is only 560 µm x 590 µm. Keywords — CMOS, group delay, low noise amplifier (LNA), ultra-wideband (UWB), current reuse, noise figure (NF), capacitive-resistive feedback, series peaking