Semiconductor Fabrication Processes and Devices

3-D printing shows great potential in laboratories for making customized labware and reaction vessels. In addition, affordable fused filament fabrication (FFF)-based 3-D printing has successfully produced high-quality and affordable scientific equipment, focusing on tools without strict chemical compatibility limitations. As the additives and colorants used in 3-D printing filaments are proprietary, their compatibility with common chemicals is unknown, which has prevented their widespread use in laboratory chemical processing. In this study, the compatibility of ten widely available FFF plastics with solvents, acids, bases and solutions used in the wet processing of semiconductor materials is explored. The results provide data on materials unavailable in the literature and the chemical properties of 3-D printable plastics that were, are in line with literature. Overall, many 3-D printable plastics are compatible with concentrated solutions. Polypropylene emerged as a promising 3-D printable material for semiconductor processing due to its tolerance of strongly oxidizing acids, such as nitric and sulfuric acids. In addition, 3-D printed custom tools were demonstrated for a range of wet processing applications. The results show that 3-D printed plastics are potential materials for bespoke chemically resistant labware at less than 10% of the cost of such purchased tools. However, further studies are required to ascertain if such materials are fully compatible with clean room processing.

Most digital designers will never be confronted with the details of the manufacturing process that lies at the core of the semiconductor revolution. Yet, some insight in the steps that lead to an operational silicon chip comes in quite handy in understanding the physical constraints that are imposed on a designer of an integrated circuit, as well as the impact of the fabrication process on issues such as cost. In this chapter, we briefly describe the steps and techniques used in a modern integrated circuit manufacturing process. It is not our aim to present a detailed description of the fabrication technology, which easily deserves a complete course [Plummer00]. Rather we aim at presenting the general outline of the flow and the interaction between the various steps. We learn that a set of optical masks forms the central interface between the intrinsics of the manufacturing process and the design that the user wants to see transferred to the silicon fabric. The masks define the patterns that, when transcribed onto the different layers of the semiconductor material, form the elements of the electronic devices and the interconnecting wires. As such, these patterns have to adhere to some constraints in terms of minimum width and separation if the resulting circuit is to be fully functional. This collection of constraints is called the design rule set, and acts as the contract between the circuit designer and the process engineer. If the designer adheres to these rules, he gets a guarantee that his circuit will be manufacturable. An overview of the common design rules, encountered in modern CMOS processes, will be given. Finally, an overview is given of the IC packaging options. The package forms the interface between the circuit implemented on the silicon die and the outside world, and as such has a major impact on the performance, reliability, longevity, and cost of the integrated circuit. 2.2 Manufacturing CMOS Integrated Circuits A simplified cross section of a typical CMOS inverter is shown in Figure 2.1. The CMOS process requires that both n-channel (NMOS) and p-channel (PMOS) transistors be built in the same silicon material. To accommodate both types of devices, special regions called wells must be created in which the semiconductor material is opposite to the type of the channel. A PMOS transistor has to be created in either an n-type substrate or an n-well, while an NMOS device resides in either a p-type substrate or a p-well.

Frog-leg robots have been widely used for handling silicon wafers inside the vacuum environment of semiconductor manufacturing machines. In order to enhance stiffness, frog-leg robots adopt a parallel structure. A main challenge of controlling wafer handling robot is avoiding vibration, which is the major cause of wafer sliding and particle contamination. This paper presents two control approaches to improve the performance of frog-leg robots. First, in addition to the basic tri-loop PID feedback controller, torque offset is injected to the input of the robot to compensate the robot’s nonlinear dynamics. This reduces the following error and major vibration. The torque offset is calculated based on identified robot dynamics. Second, a test based optimization method is developed to tune the gains of the feedback controller. Wafer vibration is measured and analyzed to score the system performance. Comparison results show that the proposed control scheme gives much improved performance.

__ This paper presents some of the techniques used to introduce simulation of semiconductor fabrication processes to undergraduate electrical engineering students at the American University of Sharjah. Students use Silvaco Athena process simulator and Atlas device simulator to perform experiments on semiconductor fabrication processes. Simulation results are compared with the theoretically expected results. As semiconductor process simulation tools respond to user initiated actions in real time, breaking the process at any point of time permits the visual inspection of the intermediate and final results. Therefore these tools are found to be effective in the learning process. A survey is conducted at the end of each semester to asses the ability of the students to perform semiconductor process simulation. Experience indicates that there is considerable increase in the confidence level of the students in terms of their understanding of semiconductor processes and devices.

__ This paper presents some of the techniques used to introduce simulation of semiconductor fabrication processes to undergraduate electrical engineering students at the American University of Sharjah. Students use Silvaco Athena process simulator and Atlas device simulator to perform experiments on semiconductor fabrication processes. Simulation results are compared with the theoretically expected results. As semiconductor process simulation tools respond to user initiated actions in real time, breaking the process at any point of time permits the visual inspection of the intermediate and final results. Therefore these tools are found to be effective in the learning process. A survey is conducted at the end of each semester to asses the ability of the students to perform semiconductor process simulation. Experience indicates that there is considerable increase in the confidence level of the students in terms of their understanding of semiconductor processes and devices.

This paper deals with the analysis of a novel micro-electro-mechanical (MEM) fluid density and viscosity sensor. The proposed sensor consists of a micro-beam and a sensing micro-plate immersed in a fluid. In order to actuate longitudinally the micro-beam and micro-plate, the sensor includes a pair of piezoelectric layers bonded to the upper and lower surfaces of the micro-beam and subjected to an AC voltage. The coupled governing partial differential equations of longitudinal vibration of the micro-beam and fluid field have been derived. The obtained governing differential equations with time varying boundary conditions have been transformed to an enhanced form with homogenous boundary conditions. The enhanced equations have been discretized over the beam and fluid domains using a Galerkin based reduced order model. The dynamic response of the sensing plate for different piezoelectric actuation voltages and different exciting frequencies has been investigated. The effects of viscosity and density of fluids and geometrical parameters of the sensor on the response of the sensing plate have been studied.

Currently, the semiconductor manufacturing industries over the world are upgrading from processing 300mm wafers to processing 450mm wafers.  In order to satisfy the requirements of producing and processing 450mm wafers, vibration control of wafer handling tools has to make new breakthroughs.  This paper introduces an active wide-band vibration rejection method with a vibrotactile actuator and applies it to a wafer transfer robot.  Compared to conventional methods based on motor control of the robot, active vibration cancellation with a separate actuator does not risk compromising the tracking accuracy of wafer transfer motions.  A three-step controller synthesis scheme is developed by analyzing and combining the strengths of several control strategies.  Experimental validation shows a vibration reduction of more than 40% in energy and 30% in amplitude.

The authors demonstrate high aspect ratio and large area metallic nanogrids as transparent electrodes with reduced series resistance on GaAs based optoelectronic devices. The fabrication process uses ultraviolet photolithography techniques, pulsed reactive ion etching, and two metallization steps: a vapor deposited contact seed layer and a thickening step by electrodeposition. As a result, a threefold reduction in resistive power losses is achieved with a contact grid transmission comparable to state-of-the-art devices.

We report the substrate transfer of InAs/GaSb/AlSb based type-II superlattice (T2SL) e-SWIR photodetector from native GaSb substrates to lowloss sapphire substrate in order to enhance the frequency response of the device. We have demonstrated the damage-free transfer of T2SL-based thin-films to sapphire substrate using top-down processing and a chemical epilayer release technique. After transfer the −3 dB cut-off frequency increased from 6.4 GHz to 17.2 GHz, for 8 μm diameter circular mesas under −15 V applied bias. We also investigated the cut-off frequency verses applied bias and lateral scaling to assess the limitations for even higher frequency performance.

This paper describes the optimisation of top-down fabrication process of the ZnO-based dual nanowire field effect transistors (NWFETs) based on the spacer method. The approach uses the top-down nanowire process with reduced sidewall roughness during pattern transfer to improve the electrical characteristics. The main feature of the process involves a reflow of the photoresist performed at a temperature of 130 °C and dry oxidation of the etched silicon sidewalls. The process optimisation leads to a significant reduction of the root-mean-square (rms) roughness of the photoresist from 23.2 nm to 3.6 nm and the ZnO nanowire rms surface roughness from 11.2 nm to 5.5 nm. The ZnO-based NWFET fabricated with the resist reflow process operates in depletion mode with a threshold voltage of −6 V, a subthreshold slope of 0.80 V/decade, an on–off current ratio of 10 6 , a transconductance of 5.9 nS and field effect mobility of 7.7 cm 2 /Vs.

Semiconducting boron doped single-crystal CVD diamond has been patterned using aluminum masks and an inductively coupled plasma (ICP) etch system. For comparison insulating HPHT diamond samples were also patterned using the same process. Diamond etch rates above 200 nm/min were obtained with an O 2 /Ar discharge for a gas pressure of 2.5 mTorr using 600 W RF power. We have accomplished the fabrication of structures with a minimum feature size of 1 lm with vertical sidewalls in both CVD and HPHT diamond. The ICP etching produced smooth surfaces with a typical root-mean-square surface roughness of 3 nm. The dependence of etch rate on bias voltage was somewhat different for the two types of diamond. However, for all samples both the etch rate and anisotropy were found to improve with increasing bias voltage.

In this paper, a miniature, multi-functional Si-based packaging technology which can reduce the size and cost and increase the performance of a wide range of millimeter wave systems is proposed. High density capacitors, low temperature coefficient resistors, high-Q inductors, low-loss transmission lines, filters and antennas can all be built within the Si package using standard semiconductor fabrication methods with very high manufacturing precision compared to conventional packaging technologies. Fine pitch metal bumps can be used to attach RF IC's and other components, while bonding can provide hermetic sealing where required. Vias through the Si package eliminates inductive bond wires and minimize parasitics at millimeter wave frequencies. By integrating both antenna and an RF IC in one single package, all high frequency signals are confined within the package and only baseband signals connected to the external package.

The atomic layer deposition ͑ALD͒ of Al 2 O 3 using trimethylaluminum ͑TMA͒ as a metal precursor on an InSb substrate with or without surface pretreatments was investigated. It was found that both in situ TMA/Ar purging ͑half-ALD cycle͒ and ex situ CP4A ͑HNO 3 :HF:CH 3 COOH:H 2 O = 2:1:1:10͒ chemical etching can remove the native oxides on InSb before ALD of Al 2 O 3 , and lead to a native-oxides-free Al 2 O 3 /InSb structure. Characteristics of current density-voltage and capacitance-voltage were also investigated to evaluate the insulative and interface quality in a Pt/Al 2 O 3 /InSb metal-oxide-semiconductor structure.

This investigation presents detailed characteristics of an im-
planted planar InSb p + n diode with a junction area scaled
down to 20 × 20 μm 2 . Low-temperature photo-chemical va-
por deposition oxide stacked with an optimized thin anodic
film, instead of a gate control structure, is used to control the
planar surface potential of the implanted p + n diode under the
weak inversion condition on the n-type surface and under
weak accumulation on the p-type surface. The zero-bias resist-
ance–area product is 7.6 × 10 4 Ω cm 2 at 77 K. To the best of
the authors’ knowledge, this result represents the best per-
formance of a small-area and implanted planar diode to date.
The dark current is controlled by an internal shunt conduction
mechanism, which seems to be related to the defects that are
produced by the implantation. Low leakage current and high
breakdown voltage have proven the feasibility of the compos-
ite anodic oxide/SiO x that is stacked as the passivation struc-
ture in small-pixel InSb p + n photodiodes for focal plane array
applications.

In this article, the authors report the development of a new low temperature plasma-assisted chemical vapor deposition (PACVD) process for the growth of low resistivity, cubic tantalum nitride (TaNx) for incorporation as a diffusion barrier/adhesion promoter in emerging ultralarge-scale integrated (ULSI) multilevel metallization (MLM) schemes. TaNx films were produced in a low density plasma using tantalum pentabromide, hydrogen, and nitrogen as coreactants. The films were grown at substrate temperatures of 350–450 °C, reactor working pressures of 0.9–1.6 Torr, hydrogen flow rates between 250 and 1500 sccm, nitrogen flow rates of 100–600 sccm, and plasma power ranging from 10 to 60 W, corresponding to a power density of 0.06–0.33 W/cm2. The films were subsequently characterized by Auger electron spectroscopy, Rutherford backscattering spectrometry, x-ray diffraction, atomic force microscopy, four-point resistivity probe, and cross-sectional scanning electron microscopy. These studies indicated that the TaNx films produced were stoichiometric and carbon and oxygen free, contained bromine concentrations below 3 at. %, and exhibited resistivities as low as 150 μΩ cm. The conformality was higher than 95% in the nominally 0.3 μm, 4.5:1 aspect ratio structures. These results indicate that in the case of halide-based Ta chemistries, PACVD in a (N2+H2) plasma might be more viable than thermal CVD in a NH3 atmosphere for the deposition of TaNx for ULSI MLM applications.

In this work, we demonstrate a wafer-level zinc oxide (ZnO) nanowire fabrication process using ion beam etching and a spacer etch technique. The proposed process can accurately define nanowires without an advanced photolithography and provide a high yield over a 6-inch wafer. The fabricated nanowires are 36 nm wide and 86 nm thick and present excellent transistor characteristics. The pH sensitivity using a liquid gate was found to be 46.5 mV/pH, while the pH sensitivity using a bottom gate showed a sensitivity of 366 mV/pH, which is attributed to the capacitance coupling between the top-and bottom-gates. The maximum process temperature used in the fabrication of the nanowire sensors is optimized to be 200 °C (after wet oxidation) which makes it applicable to low-cost substrates such as glass and plastic. The Ion Beam Etching (IBE) process in this work is shown to be highly transferable and can therefore be directly used to form nanowires of different materials, such as polysilicon and molybdenum disulfide, by only an adjustment of the etch time.

Shallow junctions are formed in crystalline Si by low-energy ion implantation of B+, P+, or As+ species accompanied by electrical activation of dopants by rapid thermal annealing and the special case of spike annealing. Diffusion depths were determined by secondary ion-mass spectroscopy (SIMS). Electrical activation was characterized by sheet resistance, Hall coefficient, and reverse-bias diode-leakage measurements. The B+ and P+ species exhibit transient-enhanced diffusion (TED) caused by transient excess populations of Si interstitials. The electrically activated fraction of implanted dopants depends mainly on the temperature for B+ species, while for P+ species, it depends on both temperature and P+ dose. The relatively small amount of diffusion associated with As+ implants is favorable for shallow-junction formation with spike annealing.