EE 5311 Digital IC Design Tutorial 3 - Sep 25, 2015: N Ox 2 P Ox 2 Min Min T T Dsat Dsat DD

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EE 5311 Digital IC Design Tutorial 3 Sep 25, 2015


n Cox = 160A/V 2
VDsatn = 0.35V


p Cox = 80A/V 2
|VDsat p | = 0.6V

Wmin = 4 = 0.36
VDD = 1.8V

Lmin = 2 = 0.18

VTn = |VTp | = 0.4V


Note: The SPICE simulations mentioned here are not evaluated for marks. They are meant for you to
get a clearer practical view of the issues involved.
1. For the RC tree structure shown, estimate the propagation delay from node 1 to node 5 using Elmores
delay formula. Use a SPICE simulation to check the result, and comment on the accuracy of the estimate. Do the SPICE simulation for both cases: (a) node 5 initially at 0 with Vi going from 0 to Vdd and
(b) node 5 initially at Vdd and Vi going from Vdd to 0.
3
R2

C2
1.0 fF

10

1
R1
10 k

R3
10
k

C1
1.0 fF

R4
10 k
C3
1.0 fF

C4
1.0 fF

Figure 1: Elmore delay tree


2. DCVSL:
(a) Draw the DCVSL transistor-level schematic for a 3-input XOR gate. Share as many transistors as
possible between the pull-down paths.
(b) Draw the schematic of a 3 input NAND gate in DCVSL. Specify the sizes of the transistors.
(c) SPICE: Measure the propagation delay from each of the inputs to the output assume all other
inputs are at the correct values required for transition.
3. Implement the function Y = AB + C.( D + EF ) (note: how many stages of logic are required here?)
using:
(a) Domino logic
(b) np or NORA logic: alternate stages use n type and p type evaluation blocks.
4. What function is implemented by the circuit in fig. 2. What considerations are necessary when sizing
the transistors?
5. For the circuit shown in fig 3, draw the waveforms at , W, X, Y and Z. Assuming 50ps as the delay
through any one stage (either the Domino pull down/precharge or the inverter), what is the minimum
value of time for the precharge and evaluate phases of the clock?
6. What function is the following circuit expected to implement? Will there be a problem with the functioning? How can you fix it? Assume C and Cn are clock and complement. Ignore skew.
7. In the discussion on energy-delay-product, we concluded that EDP could be expressed as EDP =
CV 2
2 .tdp since energy is product of power and time, and at highest possible operating frequency the
f and t terms cancel each other. Now assuming that tdp =

CL Vdd
Vdd Vte

where Vte = VT + Vdsat /2 (under

what operating conditions is this valid?), show that the EDP is minimum when Vdd = 23 .Vte .

EE 5311 Digital IC Design Tutorial 3 Sep 25, 2015

Vdd

Figure 2: Mystery circuit

Vdd

Y
X

A
B

Figure 3: Domino Logic circuit

Vdd

Vdd

Vdd

Cn

B
A

Cn
C

Vdd

Cn

Figure 4: Faulty Sequential circuit

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Cn

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