Analog Electronic and LIC

Simulation of Electronic Circuits using Multisim, PSpice and LabVIEW
Analog Electronic
Circuit (AEC) Lab
(21EC382)
Dept. of ECE 1
COURSE OBJECTIVES:
 To provide practical exposure to the students on designing, setting up, executing and
debugging various electronic circuits using simulation software.
 To give the knowledge and practical exposure on simple applications of analog electronic
circuits.
COURSE OUTCOMES (COURSE SKILL SET):

At the end of the course the student will be able to:
1. Understand the circuit schematic and its working.
2. Study the characteristics of different electronic devices.
3. Design and test simple electronic circuits as per the specifications using discrete electronic
components.
4. Compute the parameters from the characteristics of active devices.
5. Familiarize with EDA software which can be used for electronic circuit simulation.
Dept. of ECE 2
LIST OF EXPERIMENTS
Sl.No Experiments using Pspice/MultiSIM software

1 Experiments to realize diode clipping (single, double ended) circuits.
2 Experiments to realize diode clamping (positive, negative) circuits.
3 Experiments to realize Full wave rectifier without filter (and set-up to measure the
ripple factor, Vp-p, Vrms, etc.).
4 Design and conduct an experiment on Series Voltage Regulator using Zener diode to
determine line/load regulation characteristics.
5 Realize BJT Darlington Emitter follower without bootstrapping and determine the
gain, input and output impedances (other configurations of emitter follower can also
be considered).
6 Set-up and study the working of complementary symmetry class B push pull power
amplifier (other power amplifiers can also be suitably considered) and calculate the
efficiency)
7 Design and set-up the oscillator circuits (Hartley, Colpitts, etc. using BJT/FET) and
determine the frequency of oscillation.
8 Design and set-up the crystal oscillator and determine the frequency of oscillation.
9 Experiment to realize Input and Output characteristics of BJT Common emitter
configuration and evaluation of parameters.
10 Experiments to realize Transfer and drain characteristics of a MOSFET.
11 Experiments to realize UJT triggering circuit for Controlled Full wave Rectifier.
12 Design and simulation of Regulated power supply.
Dept. of ECE 3
EXPERIMENT 1:
AIM: - Conduct experiment to test diode clipping (single/double ended).
COMPONENTS REQUIRED: 1N4007G Diode, Resistors, Function generator,

Oscilloscope.
THEORY:-
Clippers are networks that employ diodes to clip away portions of an input signal without
distorting the remaining part of the applied waveform. Diode clipping circuits are used to
prevent a wave form from exceeding some particular limit either negative or positive or both.
This is achieved by connecting the diode in serial or in parallel circuit. Variable DC voltage
is connected in the circuit to achieve required level of clipping. By using different level DC
voltages, it is possible to get different level of clipping in positive and negative side. These
clipper circuits are also called as limiters.
Following are few types of clipper circuits
1. Single ended (positive or negative ) and double ended clipping
2. Series or parallel based on the construction. Peak detection is possible by connecting a

suitable capacitor across the output of single ended clipping circuit. The capacitor charging
time to be fast and discharging time to be slow so that capacitor holds the maximum value.
DESIGN:
Assume Forward Resistance of Diode, Rf =100 Ω;
Reverse Resistance of Diode, Rr =1MΩ
The series resistance is calculated such that R √ √ 10K

Note: If you are using 1N4001 Rf and Rr may be assumed to be 30 Ω and 300K Ω
respectively and R=3.3 K Ω .
The series resistor is used to limit the current through the diode.
Dept. of ECE 4
CIRCUIT DESIGN:
Fig. 1: Positive shunt clipper
If the output to be clipped above 2 V, Vo (max) = +2 V
From the Fig.1 observe that when the diode is ON Vo (max) = V + Vref
where V is Diode Cut-in Voltage which is equal to 0.6 V for IN4007 (Silicon diode) .Hence
Vref = Vo (max) – V = 2 – 0.6 = 1.4 V. Make sure that the amplitude of the input
sinusoidal signal is more than ±2Volts.
SIMULATED RESULT:
If the output to be clipped below  2 Volts.
Dept. of ECE 5
From the Fig.2 observe that when the diode is ON Vo (min) = VVref = 2 V = 0.6
Vref; Vref= 2  0.6 = 1.4 V Vref = 1.4 V Make sure that the amplitude of the input
sinusoidal signal is more than ±2Volts.
Fig. 2: Negative shunt Clipper
SIMULATED RESULT:
If the clipping the signal is required below 2 Volt and above 4 Volt then the design is as
follows.
1. Vo max = 4 V, Vo max = VR1 + V; VR1 = Vo max – V= 4 – 0.6; VR1 = 3.4 V
2. Vo min = 2 V Vo min = VR2 – V; VR2 = Vo min + V = 2 + 0.6; VR2 = 2.6 V
Dept. of ECE 6
Fig.3: Double ended clipper with independent voltage levels
SIMULATED RESULT:
If we need to generate a symmetrical clipping circuit with clipping voltage
V0 = ± 4 Volts, Vo max = VR1 + V = 4 V;
VR1 = 4 – 0.6 = 3.4 V
Vo min = V  VR2= - 4 V,
VR2 = 4  0.6 = 3.4 V
Dept. of ECE 7
Fig.4: Double ended clipper with symmetrical voltage levels
SIMULATED RESULT:
PROCEDURE:-
1. Select and place component from Sources Ground
2. Select and place component from SourcesPOWER_SOURCESAC_POWER
3. Select and place component from Allgroups DIODE 1N4001G
4. Select and place component from Basic RESISTOR
Dept. of ECE 8
5. Connections are made as shown in the circuit diagram.

6. Observe the waveforms by selecting the CRO.
RESULT: Diode Clipping circuits have been simulated by considering different cases.
VIVA QUESTIONS:
1. What is clipper circuit?
2. Which circuit parameter the clipper circuit consists of?
3. Explain the terms: Positive clipper, Negative clipper, Biased clipper and
Combination clipper.
4. Explain the terms: Biased positive, Biased negative clipper and combination clipper.
5. State the application of the clipper circuit.
Dept. of ECE 9
EXPERIMENT 2:
AIM: - Conduct experiment to test diode clamping circuits (positive/negative).
COMPONENTS REQUIRED: 1N4007G Diode, Resistors, capacitors, Function

generator, Oscilloscope.
THEORY:-
Clamper is a circuit that "clamps" a signal to a different dc level without changing the
appearance of the applied signal The different types of clampers are positive negative and
biased clampers A clamping network must have a capacitor, a diode and a resistive element.
The magnitude R and C must be chosen such that the time constant RC is large enough to
ensure that the voltage across the capacitor does not discharge significantly during the
interval the diode is non- conducting. By connecting suitable DC voltage in series with the
diode, the level of swing can be varied.
DESIGN:
Vo,max = Vdc + V ; V = 0.6V (Silicon diode), Vdc = Vo,max - V
To clamp the positive peak of a sine wave of 10 V (P – P) at +3V, we need Vdc = 3 – 0.6 =
2.4 V Note: Changing this voltage changes the clamping level. Let f = 1KHz.  T = 1msec.
Let R = 10K (design procedure is same as that of clipper) For the circuit to perform
satisfactorily RC = 10T Therefore C = 10T / R = 10 x 1ms / 10KΩ; C = 1.0 µF
CIRCUIT DESIGN:
Fig. 1: Positive clamper
Vo,max = Vdc – V; Assume we need to clamp the negative peak to -3V,
Dept. of ECE 10
ie., Vo,max= – 3V Vdc = Vo,max + V, Vdc = – 3 + 0.6 = – 2.4V
(Note: Changing this voltage changes the clamping level.) The design of R and C is as
mentioned in earlier circuit)
SIMULATED OUTPUT:
Fig. 2: Negative clamper
Dept. of ECE 11
SIMULATED OUTPUT:
PROCEDURE:
5. Select and place component from Basic CAPACITOR
RESULT: Diode clamping circuits have been simulated and output results have been
verified.
VIVA QUESTIONS:
1. What is operating principle of the Clamper circuit?
2. Describe the function of the Clamper circuit.
3. Whether the original signal change at the output of the Clamper circuit?
4. What is meaning of the Positive Clamper and Negative Clamper?
Dept. of ECE 12
EXPERIMENT 3:
AIM: To realize full wave rectifier without filter (and set-up to measure the
ripple factor, Vp-p Vrms, etc.,)
COMPONENTS REQUIRED: 1P2S, 1N4006G, Resistors, Oscilloscope
THEORY:
Full Wave Rectifier Working & Operation
The working & operation of a full wave bridge rectifier is pretty simple. The Full Wave Bridge
Rectifier, which uses four diodes, arranged as a bridge, to convert the input alternating current
(AC) in both half cycles to direct current (DC). In the case of center- tap full wave rectifier,
only two diodes are used, and are connected to the opposite ends of a center-tapped secondary
transformer as shown in the figure below. The center-tap is usually considered as the ground
point or the zero voltage reference point.
Working of Centre-Tap Full Wave Rectifier

As shown in the figure, an AC input is applied to the primary coils of the transformer. This
input makes the secondary ends P1 and P2 become positive and negative alternately. For the
positive half of the ac signal, the secondary point D1 is positive, GND point will have zero volt
and P2 will be negative. At this instant diode D1 will be forward biased and diode D2 will
be reverse biased. The diode D1 will conduct and D2 will not conduct during the positive
half cycle. Thus the current flow will be in the direction P1-D1-C-A- B-GND. Thus, the
positive half cycle appears across the load resistance RLOAD.
During the negative half cycle, the secondary ends P1 becomes negative and P2 becomes
positive. At this instant, the diode D1 will be negative and D2 will be positive with the zero
reference point being the ground, GND. Thus, the diode D2 will be forward biased and D1
will be reverse biased. The diode D2 will conduct and D1 will not conduct during the negative
half cycle. The current flow will be in the direction P2-D2-C-A-B-GND.
Dept. of ECE 13
CIRCUIT DESIGN
DESIGN:
For Centre tap full wave rectifier
= for FWR (both center tap and bridge rectifier)
For the given calculate and using the formula,
.
The value of the load resistance, &
calculate theoretical
Dept. of ECE 14
𝐼 2
𝜂 = 𝐼 2 + 𝐼 2 × 100
𝑎
Calculate the Efficiency
PROCEDURE:
3. Select and place component from Allgroups TRANSFORMER1P2S
7. Place probe across load resistor to measure Vp-p Vrms, Ip-p Irms
SIMULATED OUTPUT:
RESULT: Simulation of full wave rectifier without filter has been verified.
Dept. of ECE 15
VIVA QUESTIONS:
1. What is a rectifier?
2. What are PIV’s of the three different rectifiers?
3. What is efficiency of a rectifier?
4. What is the use of a centre tap in a full wave rectifier?
5. Explain the working of Full Wave Rectifier.
6. What are the advantages of bridge rectifiers over center-tapped FWR?
7. Define Transformer utilization factor (TUF). Calculate it for HWR
8. What is the TUF for full wave rectifier and bridge rectifier?
9. What are different types of filters used?
10. How does the performance of the capacitor input filter improve when RC time
constant is increased?
11. Why the capacitor input filter so called?
Dept. of ECE 16
EXPERIMENT 4
AIM: To design and conduct an experiment on series voltage regulator using zener diode to
determine line/load regulation characteristics.
COMPONENTS REQUIRED: BZB84-B10 zener diode, Potentiometer, dc power,

ground
THEORY:
Zener Diode is a general purpose diode, which behaves like a normal diode when forward
biased. But when it is reverse biased above a certain voltage known as zener breakdown
voltage or zener voltage or avalanche point or zener knee voltage the voltage remains
constant for a wide range of current.
Ordinary diodes will not have any significant current (only leakage current) when reverse
biased below its reverse breakdown voltage. When the reverse bias is increased beyond
reverse breakdown voltage its potential barrier breaks down. This may damage the diode due
to excess heat produced by the high current flow through the diode unless the current is limited.
Zener diode also exhibits similar properties except that it is designed to have lower breakdown
voltage. Ordinary diodes have breakdown voltages in the order of 100 or above.
Zener Diode as Voltage Regulator:

The function of a regulator is to provide a constant output voltage to a load connected in
parallel with it in spite of the ripples in the supply voltage or the variation in the load current
and the zener diode will continue to regulate the voltage until the diodes current falls below the
minimum IZ(min) value in the reverse breakdown region. The purpose of a voltage regulator is
to maintain a constant voltage across a load regardless of variations in the applied input voltage
and variations in the load current.
The resistor is selected so that when the input voltage is at VIN(min) and the load current is at
IL(max) that the current through the Zener diode is at least Iz(min). Then for all other
combinations of input voltage and load current the Zener diode conducts the excess current thus
maintaining a constant voltage across the load. The Zener conducts the least current when the
load current is the highest and it conducts the most current when the load current is the lowest.
Dept. of ECE 17
A Zener diode of break down voltage Vz is reverse connected to an input voltage source Vi
across a load resistance RL and a series resistor RS. The voltage across the zener will
remain steady at its break down voltage VZ for all the values of zener current IZ as long as the
current remains in the break down region. Hence a regulated DC output voltage V0 = VZ is
obtained across RL, whenever the input voltage remains within a minimum and maximum
voltage.
Basically, there are two type of regulations such as:
a. Line Regulation: In this type of regulation, series resistance and load resistance are
fixed, only input voltage is changing. Output voltage remains the same as long as the input
voltage is maintained above a minimum value.
b. Load Regulation: In this type of regulation, input voltage is fixed, and the load
resistance is varying. Output volt remains same if the load resistance is maintained above a
minimum value.
Transistor Series Voltage Regulator is simple series voltage regulator using a transistor and
Zener diode. The circuit is called a series voltage regulator because the load current passes
through the series transistor. The unregulated DC supply is fed to the input terminals and the
regulated output is obtained across the load. The Zener diode provides the reference voltage.
PROCEDURE:
2. Select and place component from SourcesPOWER_SOURCESDC_POWER
3. Select and place component from DIODES ZENER BZB84-B10
4. Select and place component from Basic Potientiometer
5. Select and place Multimeter to measure output voltage
7. Note the reading from multimeter by varying the source voltage and load resistor
values.
Dept. of ECE 18
CIRCUIT DESIGN:
RESULT:
Design of a series voltage regulator using zener diode to determine line/load regulation
characteristics has been simulated.
VIVA QUESTIONS:
1. What is the use of power transistor in the circuit
2. What are the ideal values of line and load regulation?
3. What is the difference between p-n Junction diode and zener diode?
4. What is break down voltage?
5. What are the applications of Zener diode?
6. What is cut-in-voltage?
7. What is voltage regulator?
8. What is line regulation?
9. What is load regulation?
10. Types of voltage regulators?
11. What is series voltage regulator?
12. What is shunt voltage regulator?
13. Applications of voltage regulators?
Dept. of ECE 19
EXPERIMENT 5
AIM: To realize BJT Darlington Emitter follower without bootstrapping and determine the
gain, input and output impedances (other configurations of emitter follower can also be
considered.
COPONENTS REQUIRED: 2N2222A, DC Power, AC Power, Potentiometer,

resistors.
THEORY:
A very popular connection of two BJTs for operation as one super beta transistor is the
Darlington connection. The main feature of Darlington connection is that the composite
transistor acts, as a single unit with a current gain is equal to product of individual current
gains. i.e. βD=β1xβ2 if β1= β2= β Then βD= β2 To make the two transistors Darlington pair,
the emitter terminal of the first transistor is connected to the base of the second transistor and
the collector terminals of the two transistors are connected together. The result is that
emitter current of the first transistor is the base current of the second transistor.
Bootstrapping: In the field of electronics, a bootstrap circuit is one where part of the
output of an amplifier stage is applied to the input, so as to alter the input impedance of the
amplifier. When applied deliberately, the intention is usually to increase rather than decrease
the impedance. Generally, any technique where part of the output of a system is used at startup
is described as bootstrapping. In analog circuit designs a bootstrap circuit is an arrangement of
components deliberately intended to alter the input impedance of a circuit. Usually it is
intended to increase the impedance, by using a small amount of positive feedback, usually over
two stages.
Dept. of ECE 20
CIRCUIT DESIGN
PROCEDURE:
2. Select and place component from SourcesPOWER_SOURCESDC_POWER
4. Select and place component from Transistors 2N2222A
6. Select and place component from Basic Resistor
7. Select and place component from Basic Capacitor
9. Simulate Run
10. Simulate  AC Analysis (and set different parameters)  Simulate
Dept. of ECE 21
SIMULATED OUTPUT
RESULT: Realization of BJT Darlington Emitter follower without bootstrapping to

determine the gain, input and output impedances has been simulated.
VIVA QUESTIONS:
1. Why common collector amplifier is known as emitter follower circuit?
2. What is the application of emitter follower ckt?
3. What is Darlington emitter follower circuit?
4. Can we increase the number of transistors in Darlington emitter follower circuit?
5. Name different types of Emitter follower circuits
6. Explain what are the advantages of using a Voltage Follower Amplifier?
7. Write an expression for the mid – band voltage gain for a single stage RC coupled
amplifier.
8. What is the approximate mid – band voltage gain of your amplifier? Does this tally with
practical value? Justify.
9. Write an expression for the voltage gain of the amplifier in the low frequency region in
terms of mid-band gain and lower cut – off frequency
10. What are the bias conditions for transistor to be in (a) Saturation region? (b) Cut –
off region? (c) Active region?
11. What are the merits and de-merits of the R – C Coupled amplifier?
Dept. of ECE 22
EXPERIMENT 6:
AIM: To set-up and study the working of complementary symmetry class B push pull
power amplifier (other power amplifiers can also be suitable considered) and calculate the
efficiency.
COMPONENTS REQUIRED: 2N2222A, DC Power, AC Power, Potentiometer,

resistors, Multimeter.
THEORY:
A push pull amplifier is an amplifier which has an output stage that can drive a current in
either direction through the load. The output stage of a typical push pull amplifier
consists of two identical BJTs or MOSFETs one sourcing current through the load while
the other one sinking the current from the load. Push pull amplifiers are superior over
single ended amplifiers (using a single transistor at the output for driving the load) in terms of
distortion and performance. A single ended amplifier, how well it may be designed will surely
introduce some distortion due to the non-linearity of its dynamic transfer characteristics. Push
pull amplifiers are commonly used in situations where low distortion, high efficiency and high
output power are required. The basic operation of a push pull amplifier is as follows: The signal
to be amplified is first split into two identical signals 180° out of phase. Generally this splitting
is done using an input coupling transformer. The input coupling transformer is so arranged that
one signal in applied to the input of one transistor and the other signal is applied to the input of
the other transistor. Advantages of push pull amplifier are low distortion, absence of magnetic
saturation in the coupling transformer core, and cancellation of power supply ripples which
results in the absence of hum while the disadvantages are the need of two identical transistors
and the requirement of bulky and costly coupling transformers.
CROSS OVER DISTORTION.
Cross over distortion is a type of distortion commonly seen in Class B amplifier configurations.
As we said earlier, the transistor are biased at cut off point in the Class B amplifier. We all
know a Silicon transistor requires 0.7V and a Germanium diode requires
0.2V of voltage across its base emitter junction before entering in to conducting mode and this
base emitter voltage is called cut in voltage. Germanium diodes are out of scope in amplifiers
and we can talk about a Class B push pull amplifier based on Silicon transistors. Since the
transistors are biased to cut off, the voltage across their base emitter junction
Dept. of ECE 23
remains zero during the zero input condition The only source for the transistors to get the
necessary cut in voltage is the input signal itself and the required cut in voltage will be looted
from the input signal itself. As a result portions of the input wave form that are below 0.7V (cut
in voltage) will be cancelled and so the corresponding portions will be absent in the output
wave form too. Have a look at the figure
PROCEDURE:
2. Select and place component from
SourcesPOWER_SOURCESDC_POWER
3. Select and place component from Transistors 2N2222A
5. Select and place function generator
6. Select and place Multimeter
8. Select and place CRO and Observe the output
CIRCUIT DESIGN
Dept. of ECE 24
SIMULATED OUTPUT
RESULT: Simulation of the working of complementary symmetry class B push pull power
amplifier and to calculate the efficiency has been verified.
VIVA QUESTIONS:
1. What is the efficiency of Class B push pull amplifier?
2. What is the drawback of Class B Push pull Amplifier? How it is eliminated.
3. What is the advantage of having complimentary symmetry push pull amplifier?
Dept. of ECE 25
EXPERIMENT 7:
AIM: Design and set-up the following tuned oscillator circuits using BJT, and determine the
frequency of oscillation (a) Colpitts Oscillator (b) Hartley Oscillator
COMPONENTS REQUIRED: BC547BP, Resistors, Capacitors
THEORY:
LC oscillators are generally used as RF oscillators since they generally used to create high
frequency oscillations. In Hartley and Colpitts oscillator an LC tank circuit is used for
selection of frequency of oscillation. A voltage divider biased common emitter amplifier is
used as amplifier. The amplifier and tank circuit together provides a phase shift of 360
degrees to satisfy Barkhausen criterion.
DESIGN:
BJT- Amplifier design is same as given in Common Emitter Amplifier. Tank Circuit Design:
Given Oscillation frequency f =1 MHz

-10
Assume C1=C2 = 470 pF  Ceq= 235 pF =2.35*10 F
Then,
Use L = 100 µH, For this value of L, f = 1.04 MHz
CIRCUIT DESIGN:
Fig 1: Colpitts Oscillator
Dept. of ECE 26
PROCEDURE:
2. Select and place component from Allgroups Transistor BC547BP
3. Select and place component from Basic RESISTOR , CAPACITORS
SIMULATED OUTPUT:
CIRCUIT DESIGN
Fig 2: Hartley Oscillator
Dept. of ECE 27
SIMULATED OUTPUT:
RESULT: Oscillator circuits have been simulated and results are verified.
VIVA QUESTIONS:
1. What is an oscillator?
2. Explain Barkhausen criterion for sustained oscillations.
3. What type of feedback is employed in the oscillator circuit?
4. Why amplifier is required in the oscillator circuits? 5) Mention the RF
range of frequencies.
Dept. of ECE 28
EXPERIMENT 8
AIM: Design and set-up the following tuned oscillator circuits using BJT, and determine the
frequency of oscillation (a) Crystal Oscillator
COMPONENTS REQUIRED: NPN transistor, resistors, Capacitors, HC-

49/U_1.5MHz crystal.
THEORY:
Crystal Oscillator: This oscillator uses a piezoelectric crystal as resonant circuit. The crystal
is made up of quartz material and it provides a high frequency stability and accuracy. A
crystal oscillator works on the principle of piezoelectric effect. According to this effect, when
an AC voltage is applied between the faces of a quartz crystal, it vibrates at the frequency of
the applied voltage and conversely, if the crystal is vibrated mechanically AC voltage is
generated. This oscillator is used to produce carrier frequencies in modulation techniques also
in microprocessor and microcontroller boards.
CIRCUIT DESIGN:
Dept. of ECE 29
SIMULATED OUTPUT:
RESULT: Crystal oscillator circuit has been simulated to get sustainable oscillations.
VIVA QUESTIONS:
1. Classify oscillators?
2. What are the various crystals?
3. Which oscillators are AF oscillators?
4. Why can't we use LC oscillator for low frequency oscillations
Dept. of ECE 30
EXPERIMENT 9:
AIM: To realize Input and Output characteristics of BJT Common emitter configuration and
evaluation of parameters.
COMPONENTS REQUIRED: Transistor 2N222A, DC power sources and Ground
THEORY:
In common emitter configuration, input voltage is applied between base and emitter terminals
and output is taken across the collector and emitter terminals. Therefore, the emitter terminal
is common to both input and output. The input characteristics resemble that of a forward
biased diode curve. This is expected since the Base-Emitter junction of the transistor is forward
biased. As compared to CB arrangement IB increases less rapidly with VBE. Therefore, input
resistance of CE circuit is higher than that of CB circuit. The output characteristics are drawn
between Ic and VCE at constant IB the collector current varies with VCE up to few volts only.
After this the collector current becomes almost constant, and independent of VCE. The value
of VCE up to which the collector current changes with V CE is known as Knee voltage. The
transistor always operated in the region above Knee voltage, IC is always constant and is
approximately equal to IB. The current amplification factor of CE configuration is given by
β = ΔIC/ΔIB
Input Resistance, ri = ∆VBE /∆IB (μA) at Constant VCE
Output Résistance, ro = ∆VCE /∆IC at Constant IB (μA)
CIRCUIT DESIGN:
Dept. of ECE 31
Fig.1 Input Characteristics
Dept. of ECE 32
Fig.2 Output characteristics
PROCEDURE:
1. Open MULTISIM software.
2. Design1 – Multisim file will be opened. Save it
3. Select NPN from the real components list and place it in the working area.
Dept. of ECE 33
4. Select DC power sources and ground from the same list and make connections as in the
circuit Fig.1.
5. As seen in the above characteristics, the range of voltage for VBE is to be set at 0 – 20
V in steps of 2V and range of voltage for VBE is to be set at 0 – 10 in steps of 2V.
6. For this, select Simulate => Analyses => DC sweep.
7. For Input Characteristics: In the DC Sweep Analysis, select Analysis Parameters. For
VBE, set the start value as 0, stop value as 1 and increment as 0.01V.
8. Select Use Source2. Select VCE as Source2. For VBE, set the start value as 2, stop
value as 20 and increment as 2V.
9. After that specify the output variables select Ib for input characteristics and Ic for
output characteristics and click Add. Click Ok.
10. To Simulate the circuit, select Simulate => Analyses => DC sweep and click
simulate.
11. The Input characteristics of NPN transistor is displayed. In the grapher view as below, to
change the labels of left axis and right axis, double click on it and change the labels as
required.
12. Select DC power sources, DC current and ground from the same list and make
connections as in the circuit Fig.2.
13. As seen in the above characteristics, the range of voltage for VCE is to be set at 0 –
20V in and range of voltage for VBE is to be set at 0 – 10.
15. In the DC Sweep Analysis, select Analysis Parameters. For VCE, set the start value as
0, stop value as 5 and increment as 0.01V.
16. Select Use Source2. Select Ib as Source2. For Ib, set the start value as 0, stop value as
0.0003A and increment as 0.00003A.
17. After that specify the output variables select Ic for output characteristics and click
Add. Click Ok.
simulate.
19. The output characteristics of NPN transistor is displayed. In the grapher view as
below, to change the labels of left axis and right axis, double click on it and change the
labels as required.
SIMULATION OUTPUT:
Dept. of ECE 34
RESULT: Simulation of Input and Output characteristics of BJT Common emitter

configuration and evaluation of parameters have been verified.
VIVA QUESTIONS:
1. Give the comparison of common emitter, common base and common collector
configurations?
2. Define cut-off, active and saturation regions in a transistor?
3. How you understand about input and output characteristics?
4. How you explain about the physical structure of a BJT?
5. How you understand about the emitter current increase with increase in reverse bias at the
collector junction?
Dept. of ECE 35
EXPERIMENT 10:
AIM: To realize drain and transfer characteristics of a MOSFET
COMPONENTS REQUIRED: MOSFET 2N700, DC power sources and Ground
THEORY:
MOSFET is a three terminal device which is a type of FET( Field effect transistor). It is
suitable for high power applications as it can withstand large amount of currents. The output
current is controlled by the input gate voltage. Hence, the field created by the input gate
voltage often termed as Vgs controls the drain current Id. There are two types of MOSFET N
Channel MOSFET and P Channel MOSFET. N Channel MOSFET’s are further classified
into Enhancement Type and Depletion type Mosfets. Here we will study N Channel
Enhancement type Mosfet characteristics.
In E Mosfet a positive gate voltage is required to be applied which creates a channel between
the source and the drain terminals. Therefore, this channel helps to induce drain current Id.
If there is no gate voltage, there is no channel created and hence there is no current flowing.
Hence, this MOSFET is also called as Noramally Off MOSFET.
N Channel MOSFET Characteristics
There are two types of characteristics
 Drain Characteristics
 Transfer Characteristics
Figure 1a shows the transfer characteristics (drain-to-source current IDS versus gate-to-
source voltage VGS) of n-channel Enhancement-type MOSFETs. From this, it is evident that
the current through the device will be zero until the VGS exceeds the value of threshold
voltage VT. This is because under this state, the device will be void of channel which will be
connecting the drain and the source terminals. Under this condition, even an increase in VDS
will result in no current flow as indicated by the corresponding output characteristics (IDS
versus VDS) shown by Figure 1b. As a result this state represents nothing but the cut-off
region of MOSFET’s operation. Next, once VGS crosses VT, the current through the device
increases with an increase in IDS initially (Ohmic region) and then saturates to a value as
determined by the VGS (saturation region of operation) i.e. as VGS increases, even the
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saturation current flowing through the device also increases. This is evident by Figure 1b
where IDSS2 is greater than IDSS1 as VGS2 > VGS1, IDSS3 is greater than IDSS2 as VGS3
> VGS2, so on and so forth. Further, Figure 1b also shows the locus of pinch-off voltage
(black discontinuous curve), from which VP is seen to increase with an increase in VGS.
CIRCUIT DESIGN:
Fig.2: MOSFET Circuit diagram
PROCEDURE:
3. Select MOSFET N CHANNEL from the real components list and place it in the
working area.
4. Select DC power sources and ground from the same list and make connections as in the
circuit Fig.1.
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5. As seen in the above characteristics, the range of voltage for VDS is to be set at 0 – 20
V in steps of 2V and range of voltage for VGS is to be set at 0 – 5V in steps of 2V.
7. For Drain characteristics: In the DC Sweep Analysis, select Analysis Parameters. For
VDS, set the start value as 0, stop value as 5 and increment as 0.5V.
8. Select Use Source2. Select VGS as Source2. For VGS, set the start value as 0, stop
value as 5 and increment as 0.5V.
9. After that specify the output variables select for Drain characteristics and -I(VDS) for
simulate.
11. For Output characteristics: In the DC Sweep Analysis, select Analysis Parameters.
For VDS, set the start value as 0, stop value as 5 and increment as 0.5V.
12. Deselect Use Source2.
13. After that specify the output variables select for Drain characteristics and -I(VDS) for
simulate.
15. The output characteristics of MOSFET is displayed. In the grapher view as below, to
change the labels of left axis and right axis, double click on it and change the labels as
required.
SIMULATION OUTPUT:
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RESULT: Simulation to realize drain and transfer characteristics of a MOSFET has been
verified.
VIVA QUESTIONS:
1. What does MOSFET stands for?
2. What type of a device is MOSFET?
3. What type of carriers are controlled in a MOSFET?
4. How many terminals does a MOSFET possess?
5. What type of MOSFETs preferred for Power electronics?
6. Which layer isolates terminal Gate from semiconductor?
7. Which substrate does a n-channel made device possess?
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EXPERIMENT 11:
AIM: To realize UJT triggering circuit for Controlled Full wave Rectifier.
COMPONENTS REQUIRED: SCR 2N6397, BRIDGE MDA920A4, UJT-

PUT2N6027, AC POWER, DC power sources, CRO and Ground
THEORY:
An UJT is made up of an n-type silicon base to which p-type emitter is embedded. The n-type
base is slightly doped whereas p-type is heavily doped.
The two ohmic contacts provided at each end are called base-one B1 and base-two B2.So an
UJT is a three terminal device emitter, base one and base two. The emitter terminal divides
the inter base resistance (VBB) into two parts (say, RB1 and RB2). If a dc biasing voltage
(VBB) is applied across the base terminals, the voltage in N-type material near emitter terminal
(k) is given by where η is called the intrinsic-standoff ratio of UJT and its value is less than
unity (typical value varies between 0.5 and 0.85).
The UJT is highly efficient switch; its switching time is in the range of nanoseconds. Since
UJT exhibit negative resistance characteristics, it can be used as a relaxation oscillator.
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The external resistance R1 and R2 are small in comparison with the internal resistances RB1
and RB2. The charging resistance R should be such that its load line intersect the device
characteristics only in the –ve resistance region. When source voltage VBB is applied,
capacitor C begins to charge through R exponentially towards VBB. The time constant of the
charge circuit is When this emitter voltage reaches peak-point voltage Vp,
theuni-junction between E-B1 breaks down, as a result, UJT turns on and capacitor C rapidly
discharges through low resistance R1 with a time constant . When emitter voltage
decays to the valley-point voltage Vv, emitter current falls below Iv and UJT turns off. The
time T required for the capacitor C to charge from initial voltage Vv to peak-point voltage Vp
through large resistance R can be obtained as
CIRCUIT DESIGN:
Fig.1
PROCEDURE:
3. Select the real components list and place it in the working area.
4. Make connections as in the circuit Fig.1.
5. Double click on CRO to check the Generated waveform.
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SIMULATION OUTPUT
RESULT: Simulation to realize UJT triggering circuit for Controlled Full wave Rectifier
has been verified.
VIVA QUESTIONS:
1. What are unijunction transistors used for?
2. What is the generalized value for the voltage across resistor RB1 in a unijunction
transistor?
3. Which type of material is the channel of a unijunction transistor made up of?
4. What are the terminals of a unijunction transistor?
5. What are the working regions of a unijunction transistor?
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EXPERIMENT 12
AIM: To Design and simulation of Regulated power supply.
COMPONENTS REQUIRED: Voltage Regulator LM7805CT, BRIDGE 3N246,

Multimeter, AC POWER, DC power sources and Ground
THEORY:
The IC Regulated power supply (RPS) is one kind of electronic circuit, designed to provide the
stable DC voltage of fixed value across load terminals irrespective of load variations. The main
function of the regulated power supply is to convert an unregulated alternating current (AC) to
a steady direct current (DC). The RPS is used to confirm that if the input changes then the
output will be stable. This power supply is also called a linear power supply, and this will
allow an AC input as well as provides steady DC output.
A power supply can be used for providing the necessary amount of power at the precise
voltage from the main source like a battery. A transformer alters the AC mains voltage
toward a necessary value and the main function of this is to step up and step down the
voltage. For instance, a step-down transformer is used in a transistor radio, and a step-up
transformer is used in a CRT. Transformer gives separation from the power-line, and must be
used even as any modify within voltage is not required. A rectifier is an electrical device used
to convert alternating current into direct current. It can be a full wave rectifier as well as half
wave rectifier with the help of a transformer by a bridge rectifier otherwise center tapped
secondary winding. However, the rectifier’s o/p can be variable. A filter in the regulated
power supply is mainly used for levelling the ac differences from the corrected voltage.
Rectifiers are classified into four types namely capacitor filter, Inductor filter, LC filter & RC
filter. A voltage regulator in the regulated power supply is essential for keeping a steady DC
output voltage by supplying load regulation as well as line regulation.
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CIRCUIT DESIGN:
Fig.1Regulated Power supply.
PROCEDURE:
3. Select the real components list and place it in the working area.
4. Make connections as in the circuit Fig.1.
5. Double click on CRO to check the Generated waveform and verify the DC voltage in
multimeter.
SIMULATION OUTPUT
RESULT: Design and simulation of Regulated power supply has been verified.
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VIVA QUESTIONS:
1. Why Zener diodes are provided in dc supply?
2. Stability of output voltage is entirely depended on
3. The unregulated power supply is used in
4. The features of IC723 linear regulator are
5. The blocks that regulated DC power supply consists of
6. Which circuit is used for rectification?
7. What are the commonly used filter circuits?
8. The maximum output power of the push-pull converter topology of SMPS is
9. How many terminals do fixed voltage regulators have?
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“Simulation of Electronic circuits using Multisim, PSpice and Labview”
Linear integrated
Circuits (LIC) Lab
MANUAL (21EC383)
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COURSE OBJECTIVES:
1. To apply operational amplifiers in linear and nonlinear application.

2. To acquire the basic special function IC’s.
3. To use Multisim/Pspice software for circuit design and simulation.
COURSE OUTCOMES (COURSE SKILL SET):
After studying this course, the student will be able to:
1. Sketch/draw circuit schematics, construct circuits, analyse and troubleshoot circuits containing op-amps,
resistors, diodes, capacitors the independent sources.
2. Relate to the manufacturer’s data sheets of IC 555 timer and IC 741 OP-AMP.
3. Realize and verify the operation of analog integrated circuits like Amplifiers, Precision Rectifiers,
Comparators and Waveform generators.
4. Design and implement analog integrated circuits like Oscillators, Active filters, Timer circuits, Data
converters and compare the experimental results with theoretical values.
ASSESSMENT DETAILS (BOTH CIE AND SEE):
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks). A student shall be deemed to
have satisfied the academic requirements and earned the credits allotted to each course. The student has to
secure not less than 35% (18 Marks out of 50) in the semester-end examination (SEE).
CONTINUOUS INTERNAL EVALUATION (CIE):
1. CIE marks for the practical course is 50 Marks. The split-up of CIE marks for record/ journal and test are
in the ratio 60:40.
2. Each experiment to be evaluated for conduction with observation sheet and record write-up. Rubrics for the
evaluation of the journal/write-up for hardware/software experiments designed by the faculty who is handling
the laboratory session and is made known to students at the beginning of the practical session.
3. Record should contain all the specified experiments in the syllabus and each experiment write-up will be
evaluated for 10 marks.
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4. Total marks scored by the students are scaled downed to 30 marks (60% of maximum marks).
5. Weightage to be given for neatness and submission of record/write-up on time.
6. Department shall conduct 02 tests for 100 marks, the first test shall be conducted after the 8th week of the
semester and the second test shall be conducted after the 14th week of the semester.
7. In each test, test write-up, conduction of experiment, acceptable result, and procedural knowledge will
carry a weightage of 60% and the rest 40% for viva-voce.
8. The suitable rubrics can be designed to evaluate each student’s performance and learning ability. Rubrics
suggested in Annexure-II of Regulation book.
9. The average of 02 tests is scaled down to 20 marks (40% of the maximum marks). The Sum of scaled-
down marks scored in the report write-up/journal and average marks of two tests is the total CIE marks scored
by the student.
SEMESTER END EVALUATION (SEE):
SEE marks for the practical course is 50 Marks. SEE shall be conducted jointly by the two examiners of the
same institute, examiners are appointed by the University.
1. All laboratory experiments are to be included for practical examination.

2. (Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be
strictly adhered to by the examiners. OR based on the course requirement evaluation rubrics shall be decided
jointly by examiners.
3. Students can pick one question (experiment) from the questions lot prepared by the internal /external
examiners jointly.
4. Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by examiners.
5. General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction procedure and result in -
60%, Viva-voce 20% of maximum marks. SEE for practical shall be evaluated for 100 marks and scored marks
shall be scaled down to 50 marks (however, based on course type, rubrics shall be decided by the examiners).
Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be made zero. The
duration of SEE is 03 hours. Rubrics suggested in Annexure-II of Regulation book.
SUGGESTED LEARNING RESOURCES:
Op-Amps and Linear Integrated Circuits, Ramakant A Gayakwad, 4th Edition, Pearson Education, 2018.
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LIST OF EXPERIMENTS
1 TO REALIZE USING OP-AMP AN INVERTING AND
NON-INVERTING AMPLIFIER.
2 TO REALIZE USING OP-AMP SUMMING AMPLIFIER
AND DIFFERENCE AMPLIFIER.
3 TO REALIZE USING OP-AMP AN
INSTRUMENTATIONAL AMPLIFIER.
4 TO REALIZE USING OP-AMP DIFFERENTIATOR AND
INTEGRATOR.
5 TO REALIZE USING OP-AMP A FULL WAVE
PRECISION RECTIFIER.
6 TO REALIZE USING OP-AMP ZERO CROSSING
DETECTORS, POSITIVE AND NEGATIVE
VOLTAGE LEVEL DETECTORS.
7 TO REALIZE USING OP-AMP AN INVERTING SCHMITT
TRIGGER.
8 TO REALIZE USING OP-AMP AN ASTABLE
MULTIVIBRATOR.
9 TO DESIGN AND IMPLEMENT USING OP-OMPS LOW
PASS, HIHG PASS FILTER AND BUTTERWORTH
SECOND ORDER LOW PASS, HIGH PASS FILTER.
10 TO DESIGN AND IMPLEMENT USING OP-OMPS A RC

PHASE SHIFT OSCILLATOR.
11 TO DESIGN AND IMPLEMENT MONO-STABLE
MULTIVIBRATOR USING 555 TIMER.
12 TO DESIGN AND IMPLEMENT 4BIT R-2R DIGITAL TO
ANALOG CONVERTER.
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EXPERIMENT 1
INVERTING AND NON-INVERTING AMPLIFIER AIM: To design
and study the voltage gain from Inverting and non-inverting Amplifier circuit. LEARNING
OBJECTIVES:
i) To understand the working of Inverting and non-inverting Amplifier.

ii) To understand the open loop Amplifier gain, amplitude and phase shift.
COMPONENTS REQUIRED: Function generator, CRO, Regulated Power supply, resistor,

op amp 741 IC, connecting wires.
THEORY: An inverting-amplifier circuit is shown in figure 1.1 built by grounding the positive input of the
operational amplifier and connecting resistors R1 and R2, called the feedback networks, between the inverting
input and the signal source and amplifier output node, respectively. With assumption that reverse-transfer
parameter is negligibly small, circuit voltage gain Av, input resistance Zin and output resistance Zo can be
calculated.
CIRCUIT DIAGRAM:
Figure 1.1: Inverting Amplifier
DESIGN:
Av = Vo/Vin
Vin = I1*R1 and Vo = - If*R2

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Where Vrf = Iin*R2
Av= - - If*Rf / I1*R1
Av= - Rf/ R1
Gain is set by resister ratio. With this circuit hard to achieve both high gain and high Zin with this
circuit.
Where R1 = 5kΩ and R2 = 10kΩ
Vo = Vin * Av
Av = - 10/5 = -2
Vo = 2V * (-2) = -4V(inverted).
CIRCUIT DIAGRAM USING MULTISIM:
Figure 1.2: Inverting Amplifier configuration of an op-amp using Multisim
PROCEDURE:
1. Make the connections in the MULTISIM schematic editor as per the circuit diagram shown in
Figure 1.2.
2. Set the input sine signal voltage to 2 V peak to peak at a frequency of 1 kHz.
3. Observe the input and output waveforms and expected waveform shown in below Figure 1.3.
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EXPECTED WAVEFORM:
Figure 1.3: Inverting Amplifier input and output waveforms
SIMULATED RESULT:
Figure 1.4: Inverting Amplifier input and output waveforms using Multisim
The inverted output is ±4 Volts.
OBSERVATION:
i) Observe the output waveform from CRO shown in Figure 1.4. An inverted and amplified waveform will
be observed.
i) Measure the input and output voltage from the input and output waveform in the CRO.
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ii) Calculate Av gain and Vo.
NON-INVERTING AMPLIFIER:
The operational amplifier can also be used to construct a non-inverting amplifier with the circuit
indicated below in the figure 1.5 and figure 1.6 shows non-inverting amplifier circuit diagram
using Multisim . The input signal is applied to the positive or non-inverting input terminal of the
operational amplifier, and a portion of the output signal is fed back to the negative input terminal.
Analysis of the circuit is performed by relating the voltage at V2 to both the input voltage Vin and
the output voltage Vo.
The output is applied back to the inverting (-) input through the feedback circuit (closed loop)
formed by the input resistor R1 and the feedback resistor R2. This creates ve feedback as follows.
Resistors R1 and R2 form a voltage-divider circuit, which reduces Vo and connects the reduced
voltage V2 to the inverting input.
CIRCUIT DIAGRAM:
Figure 1.5: Non-Inverting Amplifier.
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Figure 1.6: Non-Inverting Amplifier configuration of an op-amp using Multisim
DESIGN:
Av = Vo/Vin
Vo = 1+(R2/R1) * Vin
Theoretically voltage gain is given by: Av = 1 +
( R2/R1) = (1+(10K/3.3K)) = 4
Vo = Av * Vin = 4 * 1V = 4V = 4V
PROCEDURE:
1. Make the connections in the MULTISIM schematic editor as per the circuit diagram.
2. In a toolbar click on place then click on component Then Go to all groups.

3. Set the input signal voltage to 1 V peak to peak at a frequency of 1 kHz from the function generator.
4. Observe the input and output waveforms from the CRO shown in below Figure 1.7.
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OBSERVATION:
1. Observe the output waveform from CRO shown in Figure 1.4. An inverted and amplified waveform
will be observed.
2. Measure the input and output voltage from the input and output waveform in the CRO.
3. Calculate Av gain and Vo.
EXPECTED WAVEFORM:
Figure 1.7: Inverting Amplifier input and output waveforms
SIMULATED RESULT:
Figure 1.8: Non - Inverting Amplifier input and output waveforms using Multisim.
Input voltage is given as 1V and non-inverted output voltage is 4V.

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RESULT: Inverting and non-inverting amplifier circuits are observed from the simulated input and output
waveforms.
VIVA QUESTIONS
1. What is an operational amplifier?

2. What is gain of inverting and non-inverting amplifiers?
3. What are the characteristics of op amp?
4. Define CMRR?
5. Define offset with respect to op- amp?
6. List out difference between open loop and feedback amplifier.
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EXPERIMENT 2
SUMMING AMPLIFIER AND DIFFERENCE AMPLIFIER
AIM: To realise using Op-amp
i) Summing Amplifier
ii) Difference Amplifier
LEARNING OBJECTIVES:
i) To design the Adder and difference amplifier.

ii) To know that the signals coming from different channels can be effectively mixed.
COMPONENTS REQUIRED: OP-AMP IC741, Resistors: 1 kΩ, Function generator, and oscilloscope
THEORY: Summing amplifier or an adder is used to sum one or more signal voltages. It has wide variety of
applications in electronic circuits. For example, on a precision amplifier, you may need to add a small voltage to
cancel the offset error of the op amp itself. An audio mixer is another good example of adding waveforms
(sounds) together from different channels (vocals, instruments) before sending the combined signal to a
recorder. The advantage is that the gain for the signals from different channels can be individually controlled.
In the Figure 2.1, the non-inverting input terminal of the op-amp is connected to ground. That means zero volts
is applied at its non-inverting input terminal. According to the virtual short concept, the voltage at the
inverting input terminal of an op-amp is same as that of the voltage at its non-inverting input terminal. So, the
voltage at the inverting input terminal of the op-amp will be zero volts. The output waveform is shown in Figure
2.2. Difference amplifier shown in Figure 2.3, amplifies the difference between the two input voltages Va and
Vb. The output waveform is shown in Figure 2.4.
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CIRCUIT DIAGRAM:
1. SUMMING AMPLIFIER
XSC1
XFG1 Rf
GT
A B C D
10kΩ VEE
-12V
4 U1
R1
2
2kΩ
6
XFG2 R2
3
3.3kΩ 7 1 5 741
VCC
12V
Figure 2.1 Summing Amplifier circuit
DESIGN:
The nodal equation at the inverting input terminal’s node is
V1/R1 + V2/R2 = 0-Vo/RF
Vo = -[(Rf/R1)v1 + (Rf/R2)v2]
gain for signal v1 be 5 and for v2 be 3. Choose RF = 10 k , then R1 = 2

kΩ (Use 1 kΩ + 1 kΩ) and R2 = 3.3 kΩ
𝑣𝑜 = −(5𝑣1 + 3𝑣2)
Let v1 = 0.5Vpp and v2 = 0.1Vpp (AC, freq = 1kHz)
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EXPECTED WAVEFORM:
Figure 2.2 output wave
PROCEDURE:
1. Rig up the circuit as shown in figure

2. Apply V1 = 0.5 Vpp and v2 = 0.1Vpp
3. Observe the output waveform
2. DIFFERENCE AMPLIFIER
Rf2
10kΩ XSC1
VEE
XFG1 GT
-12V
A B C D
4 U1
R1
2
2kΩ
6
R2 3
XFG2
2kΩ 7 1 5 741
Rf1
10kΩ VCC
12V
Figure 2.3 Difference Amplifer circuit
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PROCEDURE:
1. Rig up the circuit as shown in figure

2. Apply Va = 2 Vpp and Vb = 1.5Vpp
3. Observe the output waveform
DESIGN:
Vo = Rf/R1[ Va-Vb]
Let Rf1=Rf2 =Rf ; R1=R2=R
Let Av = Rf/R = 5 ; Let Rf= 10kΩ ,R =2KΩ
Choose Va = 2 Vpp and Vb = 1.5Vpp
EXPECTED WAVEFORM:
Figure 2.4 Output waveform
RESULT:
Circuit Input signal Expected Output signal

Adder v1=2 Vpp v2=1Vpp (AC, sine, f =1kHz)
Difference v1=2 Vpp v2=1Vpp (AC, sine, f =1kHz)
amplifier
VIVA QUESTION
1) Mention the applications of Adder and subtractor.
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2) How do you solve a summing amplifier?

3) What are the applications of summing amplifier?
4) Is summing amplifier a DAC?
5) What is adder or summing amplifier?
6) What is the purpose of a difference amplifier?
7) What is the purpose of a difference amplifier?
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EXPERIMENT 3
INSTRUMENTATIONAL AMPLIFIER
AIM: To realise using op-Amp an Instrumentation Amplifier.
LEARNING OBJECTIVES: To understand the working of Instrumentation Amplifier and to calculate

Ad,Ac, CMRR.
COMPONENTS REQUIRED: Op-amp, Resistor, AC and DC supply, function generator.
THEORY: An instrumentation amplifier is used to amplify very low-level signals, rejecting noise and
interference signals. Examples can be heartbeats, blood pressure, temperature, earthquakes and so on
The instrumentation amplifier using op-amp circuit is shown Figure 3.1. The op-amps 1 & 2 are non-
inverting amplifiers and op-amp 3 is a difference amplifier. These three op-amps together, form an
instrumentation amplifier. Instrumentation amplifier’s final output Vout is the amplified difference of the input
signals applied to the input terminals of op-amp 3 as shown in Figure 3.2. Let the outputs of op-amp 1 and op-
amp 2 be Vo1 and Vo2 respectively.
Vout = (R3/R2)(Vo1-Vo2)
CIRCUIT DIAGRAM:
To measure Ac:
Figure 3.1: Instrumentation Amplifier To measure Ac

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To measure Ad:
VCC
XMM3
XMM1
12V
7 1 5
U1
3
VDD
2 R7
R1
15kΩ 100kΩ
R4 U3
V1 VDD 2
10kΩ
-12V VDD R5 6
20mVpk R2 3
1kHz 1kΩ 10kΩ 741
0° 7 1 5
-12V
VCC
4 U2 R3 R6 100kΩ 12V
15kΩ
2 XMM2
6
7 1 5 741
VCC
12V
Figure 3.2: Instrumentation Amplifier To measure Ad
DESIGN:
Let Ad=Av1.Av2=300
Let Av1 is gain of differential amplifier
Av1= 1+(2R1/R2) = 30; Here R1=R3
Let R1=15KΩ, R2 =1KΩ
Av2= R7/R4 = R6/R5 = 10
Let R6 = 100 KΩ; R5 = 10 KΩ; R4=R5= 10 KΩ; R6=R7=100 KΩ
PROCEDURE:
1.Set up Vd=Vin=20mvVp-p for measuring Ad = Vod/Vd
2. Set Vc= 5Vp-p for measuring common mode gain, Ac=Voc/Vc
3. Calculate CMRR from the relation CMRR = 20log(Ad/Ac).
RESULT:
Differential mode gain Ad =
Common mode gain Ac =
CMRR =
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VIVA QUESTIONS:
1. What is the important feature of instrumentation amplifier?

2. What are the applications of instrumentation amplifier?
3. Why instrumentation amplifier is used in measurement system?
4. What is advantage of instrumentation amplifier?
5. Is instrumentation amplifier a differential amplifier?
6. How do you test an instrumentation amplifier?
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EXPERIMENT 4
DIFFERENTIATOR AND INTEGRATOR
AIM: To design and conduct experiments on Differentiator and Integrator Circuits using Op-amps
i) To design and simulate Integrators and Differentiators using Op-amps.
ii) To see that the shape of the input and output waveforms of Differentiator and
Integrators.
COMPONENTS REQUIRED: OP-AMP IC741, capacitor: 0.047µF, Resistors: 1 kΩ, 3.3 kΩ, 33 kΩ, 10
kΩ, Function generator, DC dual power supply and CRO.
THEORY: Operational amplifiers can be used for mathematical applications such as Integration and
Differentiation by implementing specific op-amp configurations.
DIFFERENTIATOR: A differentiator (Figure 4.1) is a circuit that is designed such that the output of the
circuit is directly proportional to the rate of change of the input or differentiation of the input voltage applied to
the op-amp with respect to time. An operational amplifier differentiator basically works as a high pass filter.
When the input resistance in the inverting terminal is replaced by a capacitor, an RC Network has been
established across the operational amplifiers’ negative feedback path which helps in obtaining differentiation of
the input voltage. Therefore the op-amp differentiator works in an inverting amplifier configuration, which
causes the output to be 180 degrees out of phase with the input. An active differentiator includes some form of
amplifier such as op-amps. A passive differentiator circuit is made of only resistors and capacitors. A
differentiator circuit consists of an operational amplifier, resistor is used at feedback side and capacitor is used
at the input side. Differentiating op-amp configuration is generally considered for triangular or rectangular input
waveforms.
The input capacitor C1 is initially uncharged and hence operates as an open-circuit. The non-inverting terminal
of the amplifier is connected to the ground, whereas the inverting input terminal is through the negative
feedback resistor Rf and connected to output terminal. Due to the ideal op-amp characteristics (the input
impedance of the
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op-amp is infinite), the input current, I to the input of an op-amp is ideally zero. Therefore the current flowing
through the input capacitor due to the applied input voltage Vin flows along the feedback path through the
feedback resistor Rf.
Figure 4.1: Basic Opamp Differentiator
As observed from the figure, point X is virtually grounded (according to the virtual ground concept) because the
non-inverting input terminal is grounded and is at 0V. With respect to the input side capacitor, the current
carrying through the capacitor can be written as:
With respect to the output side feedback resistor, the current flowing through it can be represented as:
From the above equations when we equate the currents in both the results we get,
Note: The differentiating amplifier circuit requires a very small time constant for its application
(differentiation), and hence it is one of its main advantages.
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In practical differentiators (Figure 4.2), we use a resistor in series with the capacitor. This ensures that the high
frequency noise does not push the op-amp output to saturation. The series resistor connected will have
negligible effect on the response at frequencies of interest (where differentiation is considered).
Figure 4.2: Practical Opamp Differentiator
When we apply a constant voltage with one step change at t=0 like a step signal in the input terminal of the
differentiator, the output should be ideally zero as the differentiation of constant is zero. But in practice, the
output is not exactly zero because the constant input wave takes some amount of time to step from 0 volts to
some Vmax volts. Therefore the output waveform appears to have a spike at time t=0.(Figure 4.3)
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Figure 4.3: Waveforms of Basic Op-amp Differentiator
DESIGN OF DIFFERENTIATOR:
1
Given 𝑑𝑖𝑓𝑓 =
2𝜋𝑅 𝐶
1 1
Let fdiff = 1 kHz, C1=0.047F. Therefore, R1 = 3.18 kΩ (select R1= 3.3 kΩ)
Let the gain be limited to 10 at high frequencies:
=>RF/R1=10
=> RF=33K.
Let vin = 1Vpp, square wave of frequency, f=100 Hz (<< fdiff ). The output will be a spike waveform of
around 20Vpp.
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The input and output waveforms are as shown in Figure 4.4 below :
Figure 4.4: Expanded View of Input and output waveforms of Differentiator
PRACTICAL DIFFERENTIATOR USING SIMULINK:
A practical differentiator realized using multisim is shown in Figure 4.5 and the corresponding waveform is
shown in Figure 4.6
Figure 4.5: Differentiator Circuit using Simulink
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Figure 4.6: Input and output waveforms of Differentiator using Simulink
INTEGRATOR: Integrator circuits (Figure 4.7) are basically inverting operational amplifiers (they work in
inverting op-amp configuration, with suitable capacitors and resistors), which generally produce a triangular
wave output from a square wave input. Hence, they are also used for creating triangular pulses. The current in
the feedback path is involved in the charging and discharging of the capacitor; therefore, the magnitude of the
output signal is dependent on the amount of time a voltage is present (applied) at the input terminal of the
circuit. For the capacitor present between the terminals, one end is at zero potential and other is at potential V 0.
When a constant voltage is applied at the input, it results in a linearly increasing voltage (positive or negative as
per the sign of the input signal) at the output whose rate of change is proportional to the value of the applied
input voltage.
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CIRCUIT DIAGRAM:
Figure 4.7: Basic Op-amp Integrator
From the above circuitry it is observed, V- = V+= 0.

The input current is:
Due to the op-amp characteristics (the input impedance of the op-amp is infinite), the input current to the input
of an op-amp is ideally zero. Therefore the current passing from the input resistor by applied input voltage
Vi will flow along the feedback path into the capacitor C1.
Therefore, the current from the output side can also be expressed as:
Equating the above equations we get,
Therefore, the op-amp output of this integrator circuit is:
For a step input, the output changes linearly as shown in Figure 4.8 below. Hence a square wave input results
in a triangular output.
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EXPECTED WAVEFORM:
Figure 4.8: Waveforms of Basic Op-amp Integrator
Note: If we apply a sine wave input signal to the integrator, the integrator allows low-frequency signals to
pass while it attenuates the high frequencies parts of the signal. Hence, it behaves like a low-pass filter rather
than an integrator.
Unlike ideal op-amps, practical op-amps have a finite open-loop gain, finite input impedance, an input offset
voltage, and an input bias current. This deviation from an ideal op-amp can affect working in several ways. For
example, if Vin = 0, current passes through the capacitor due to the presence of both output offset voltage and
input bias current. This causes the drifting of the output voltage over time till the op-amp saturates. If the input
voltage current is zero in case of the ideal op-amp, then no drift should be present, but it is not true for the
practical case. To nullify the effect caused due to the input bias current, we have to modify the circuit as shown
in Figure 4.9.
Figure 4.9: Practical Op-amp Integrator
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Op-amps allow us to make nearly perfect integrators such as the practical integrator. The circuit incorporates a
large resistor in parallel with the feedback capacitor. If this resistor is not used, then the op-amp operates in
open-loop under bias conditions, and as a result, the output goes to saturation. After this, the circuit does not
respond to the signal applied to it. The feedback resistor gives a path for the bias current to flow. The effect of
this resistor on the response is negligible at frequencies of interest (where integration is considered) except at
bias conditions and low-frequencies (outside the band of interest).
DESIGN OF INTEGRATOR:
1
𝑖𝑛𝑡 =
2𝜋𝑅𝐹 𝐶𝐹
Let fint=100 Hz
CF=0.047F
RF = 1/ (2x 0.047x10-6x 100) = 31.8K (Select 33K)
Let the gain under DC condition be 10;
=>RF/R1=10
=> R1=3.3K
The circuit operates as an integrator well beyond fint. Therefore, select f=1 kHz, operational frequency.
We apply square wave of 1Vp-p , the output will be triangular wave of slightly greater than 1V.
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The input and output waveforms are as shown below in Figure 4.11.
Figure 4.11: Input and output waveforms of Integrator
PRACTICAL INTEGRATOR CIRCUIT USING SIMULINK:
A practical integrator realized using multisim is shown in Figure 4.12 and the corresponding waveform is shown
in Figure 4.13
Figure 4.12: Practical Integrator Circuit using Multisim
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SIMULATED WAVEFORM:
Figure 4.13: Output and input waveforms of Integrator using Simulink
COMMON PROCEDURE FOR IMPLEMENTING DIFFERENTIATOR AND

INTEGRATOR:
1. Rig up the circuits as shown in the respective diagrams.
2. Apply input signal as specified. Make sure that operational frequency, f >> fint, in the case of Integrator, and
f << fdiff, in the case of Differentiator.
3. Observe the output waveforms and make sure they are as expected.
RESULT:
Circuit Input signal Expected Output signal
Differentiator vin = 1 Vpp, square, f = 100 Hz vo ≈20 Vpp, spike, f = 100 Hz
Integrator vin = 1 Vpp, square, f = 1kHz vo ≈1.6 Vpp, triangular, f = 100 Hz
VIVA QUESTIONS:
1) Why the operational frequency of the practical integrator much greater than fint?
2) Why the operational frequency of the practical differentiator much lesser than fdiff?
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3) Mention the applications of Adder, Integrator and differentiator.

4) Why feedback resistor is needed in practical integrator and a series resistance in practical differentiator?
5) What shape will the output waveform take, when a triangular waveform is applied as the input to a
differentiator?
6) What is the phase difference between input and output waveforms when a sinusoidal signal is applied as
input to an integrator?
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EXPERIMENT 5
FULL WAVE PRECISION RECTIFIER
AIM: To realize using op amp a Full-wave Precision rectifier.
i) Signal waveforms having amplitudes lesser than cut-in voltage ofthe diode can be rectified. ii)
Full-wave precision rectifier can operate as absolute value circuit.
COMPONENTS REQUIRED: OP-AMP IC741, Resistors: 1 kΩ, Diodes 1N4001. Function generator,
DC dual power supply and CRO
THEORY: These are the circuits which are able to rectify signal waveforms which have amplitudes lesser
than cut-in voltage of the diode. Along with rectification, these can induce amplification of the signals,
eliminate the diode voltage drop between input and output(that exists in an ordinary diode rectifier), and
possess low output resistance.
The circuit of figure 5.1 operates as half-wave rectifier. During positive half-cycle of vin, the OP-AMP output
vo’ is negative, and therefore, diode D1 is forward biased and D2 is reverse biased.The OP-AMP output is
held at -0.7 V. The circuit output voltage is zero as it is now connectedonly to virtual ground. During the
negative half-cycle of vin, the vo’ is positive, forward biasingD2 and reverse biasing D1. The OP-AMP is now
connected to operate as inverting amplifier. Therefore, the circuit output is, vo = -RF/R1 vin. We select
RF=R1 = 1 kΩ, and so, vo = -vin, a positive value. The input and output waveforms, are as shown in figure
5.2. The circuit providesthe unity gain. A gain more than unity can be induced by suitably setting RF > R1.
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CIRCUIT DIAGRAM:
Figure-5.1: Precision HWR with unity gain
The circuit of figure 5.3 shows the full-wave precision rectifier and Figure 5.4 shows Precision FWR with unity
gain using Multisim
During the positive half-cycle of vin, vo’ is negative, D2 is F.B and D1 is R.B. OP-AMP A1 operates as
inverting amplifier, giving v1 = -RF/R1 vin = -2 vin, as we set RF = 2 R1. The overall output of the circuit,
Vo is given by:
Vo = - (V1*(R4 / R2) + (R4/R3)* Vin
We select R4 =R3 =R2=R1, therefore vo =vin. During the negative half-cycle, vo’ is positive, D1 is F.
B. and D2 is R.B., and as a result, V1 = 0.
EXPECTED WAVEFORM:
Figure 5.2 Input (top) and output waveforms of circuit HWR

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CIRCUIT DIAGRAM:
Figure 5.3: Precision FWR with unity gain
Figure 5.4: Precision FWR with unity gain using Multisim
The output voltage Vo = (- R4 1/R2+R4/R3(Vin)) = 0 - Vin = -Vin (a positive value).
The input and Output waveforms are as shown in below figures 5.5 and 5.6. Set the value of R4 greater than
other resistors to induce the gain more than unity. Both the circuits are fed with input voltage of 1 Vpp (let the
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frequency be 500 Hz), having a peak value of 0.5 V, which is lesser than cut-in voltage of the diode, to
appreciate the ability of Precision rectifier.
PROCEDURE:
1. Make the connections in the MULTISIM schematic editor as per the circuit diagram.
2. Set the input signal voltage to 1 V peak to peak at a frequency of 500 Hz.
3. Observe the input and output waveforms.
Precision rectifiers can be used in envelope detector circuits in communication receivers,

wherein the signal voltage received will be much smaller than cut-in voltage of the diode.
EXPECTED WAVEFORM:
Figure 5.5: Precision FWR with unity gain
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SIMULATION WAVEFORM:
Figure 5.6: Input and output waveforms of Precision FWR using Multisim.
RESULT: The Precision rectifiers operation is practically seen and recorded.
VIVA QUESTIONS:
1) Mention the advantages of Precision Rectifiers.
2) Write the precision rectifier circuit which gives negative DC voltage.
3) Can a precision HWR be realized using an OP-AMP and a single diode? If yes, why it is not
considered practically?
4) Why the full-wave precision rectifier circuit is called as absolute value circuit? Can the
ordinary diode full-wave rectifier circuit be called so?
5) What modification must be made in order to ensure bias compensation in the precision
rectifiers?
6) Draw the transfer characteristics of precision HWR, when RF = 10 R1.
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EXPERIMENT 6
ZERO CROSSING DETECTORS, POSITIVE AND NEGATIVE
VOLTAGE LEVEL DETECTORS.
AIM: To realize using op- amps
 Inverting and non- Inverting zero crossing detectors.

 Positive and negative voltage level detectors.
LEARNING OBJECTIVES: To understand the difference between two input signal and amplitude level
detector in output waveforms with reference voltage.
COMPONENTS REQUIRED: Function generator, CRO, Regulated Power supply, resistor,

op amp 741 IC, connecting wires.
THEORY: An op-amp detector that has the ability to detect the change from positive to negative or negative
to a positive level of a sinusoidal waveform is known as a zero crossing detector. The circuit diagrams of
Inverting and non-inverting Amplifier configuration of zero crossing detectors using Multisim are shown in
below figure 6.1 and 6.3. More specifically, we can say that it detects the zero crossing of the applied ac
signal.
It is basically a voltage comparator whose output changes when the input signal crosses the zero of the
reference voltage level. Thus it is named so. It is also known to be a square wave generator as the applied
input signal is converted into a square wave by the zero crossing detector.
The reference level is set at 0 and applied at the non-inverting terminal of the op-amp. The sine wave applied
at the inverting terminal of the op-amp is compared with the reference level each time the phase of the wave
changes either from positive to negative or negative to positive. When positive half of the sinusoidal signal
appears at the input. Then the op-amp comparator compares the reference voltage level with the peak level of
the applied signal. And in case of the negative half of the sinusoidal signal, the op-amp comparator again
compares the reference voltage level with the peak of the applied signal. As this time the circuit is dealing with
negative half of the signal, thus the peak will have a negative polarity.
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CIRCUIT DIAGRAM:
Figure 6.1: Inverting Amplifier configuration of zero crossing detectors using Multisim
DESIGN:
𝑉𝑜 = 𝑉 − 𝑉𝑖
And we know the reference level is 0, thus
𝑉𝑜 = 0 − (+ 𝑉 𝑎 )
𝑉𝑜 = − 𝑉𝑎
𝑉𝑜 = 𝑉 − 𝑉𝑖 Again
𝑉𝑜 = 0 − ( − 𝑉 𝑎 )
𝑉𝑜 = + 𝑉𝑎
In this way, the zero crossing detector detects the change in the level of the applied signal and input output
waves are shown in figure 6.2.
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Figure 6.2: zero crossing Inverting Amplifier input and output waveforms using Multisim.
NON-INVERTING ZERO CROSSING DETECTORS:
Figure 6.3: non - Inverting Amplifier of zero crossing detectors using Multisim.
𝑉𝑜 = 0 − (− 𝑉 𝑎 )
𝑉𝑜 = + 𝑉𝑎
𝑉𝑜 = 𝑉 − 𝑉𝑖 Again
𝑉𝑜 = 0 − ( + 𝑉 𝑎 )
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𝑉𝑜 = − 𝑉𝑎
SIMULATED WAVEFORM: simulated input output waves are shown in figure 6.4.
Figure 6.4: zero crossing n
on-Inverting Amplifier input and output waveforms using Multisim.
INVERTING POSITIVE VOLTAGE LEVEL DETECTOR:
An op-amp detector that has the ability to detect the change from positive to negative or negative to a positive
level. The reference level is set at 1.6 and applied to the non-inverting terminal of the op-amp that can observe
in figure 6.5. The triangular wave applied to the inverting terminal of the op-amp is compared with the
reference level each time the phase of the wave changes either from positive to negative or negative to
positive.
When positive half of the triangular signal appears at the input. Then the op-amp comparator compares the
reference voltage level with the peak level of the applied signal. And in case of the negative half of the
triangular signal, the op-amp comparator again compares the reference voltage level with the peak of the
applied signal. As this time the circuit is dealing with negative half of the signal, thus the peak will have a
negative polarity.
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CIRCUIT DIAGRAM:
Figure 6.5: The inverting Positive voltage level detector amplifier circuit using Multisim.
DESIGN:
An op amp is an open loop amplifier hence it has high gain. The Vd is the potential difference between two
input voltages ie
Vin and Vref(Vin = Vn & Vref = Vp).
Where Vd = Vp – Vn = +Vref – Vin
Vo = A * Vd
When Vin > Vref , Vd = -Ve , Vo= - Vsat
Vin < Vref , Vd = +Ve , Vo= +Vsat
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SIMULATED WAVEFORM: simulated input output waves are shown in figure 6.6.
Figure 6.6: The inverting Positive voltage level detector waveform.
NON-INVERTING POSITIVE VOLTAGE LEVEL DETECTOR:
Figure 6.7: The non - inverting Positive voltage level detector amplifier circuit using multisim.
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DESIGN:
Above Figure 6.7 shows the non - inverting Positive voltage level detector amplifier circuit using multisim An
op amp is an open loop amplifier hence it has high gain 105 . The Vd is the potential difference between two
input voltages ie Vin and Vref(Vin = Vn & Vref = Vp).
Where Vd = Vp – Vn = Vin – (-Vref)
Vo = A * Vd
When Vin > Vref , Vd = +Ve , Vo= +Vsat
Vin < Vref , Vd = -Ve , Vo= - Vsat
SMULATED WAVWFORM: simulated input output waves are shown in figure 6.8.
Figure 6.8: The non - inverting Positive voltage level detector waveform using multisim.
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INVERTING NEGATIVE VOLTAGE LEVEL DETECTOR:
Figure 6.9: The Inverting negative voltage level detector circuit diagram using multisim.
DESIGN:
In above Figure 6.9 The Inverting negative voltage level detector circuit diagram has high gain and The Vd is
the potential difference between two input voltages ie Vin and Vref(Vin = Vn & Vref = Vp).
Where Vd = Vp – Vn = - Vref – Vin
Vo = A * Vd
When Vin > Vref , Vd = -Ve , Vo= - Vsat
Vin < Vref , Vd = - Vref – (-Vin) , Vo= +Vsat
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SIMULATED WAVEFORM: The input output waveform of inverting negative voltage level detector
are shown in Figure 6.10.
Figure 6.10: The inverting negative voltage level detector waveform using multisim.
NON-INVERTING NEGATIVE VOLTAGE LEVEL DETECTOR:
Figure 6.11: The non-inverting negative voltage level detector circuit diagram using multisim.
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DESIGN: Figure 6.11 shows The non-inverting negative voltage level detector circuit diagram using
multisim. The Vd is the potential difference between two input voltages ie Vin and Vref (Vin = Vn & Vref =
Vp).
Vo = A * Vd
Where Vd = Vin – (-Vref) = Vin + Vref
When Vin > Vref , Vd = +Ve , Vo= A * (+Ve) = +Vsat
Vin < Vref , Vd = -Ve , Vo= A * (-Ve) = - Vsat
SIMULATED WAVEFORM: The input output waveform of non-inverting negative voltage level
detector are shown in Figure 6.12.
Figure6.12: The non-inverting negative voltage level detector waveform using multisim.
RESULT: The inverting and non-inverting of positive and negative voltage level detector amplifier circuits
are observed from the simulated input/output waveforms.
VIVA QUESTIONS:
1. What is a zero-crossing detector used for?

2. What is difference between positive and negative voltage detector?
3. What are the limitations of zero-crossing detector?
4. What is the significance of an inverting zero-crossing detector?
5. When does op-amp have infinite gain?
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EXPERIMENT 7
SCHMITT TRIGGER
AIM: To realize using op amp an Inverting Schmitt Trigger.
 To design the OP-AMP Schmitt Trigger

 To find the values of UTP and LTP practically.
 To know that by using reference voltage source, the UTP andLTP values can have same
signs.
COMPONENTS REQUIRED: OP-AMP IC741, Resistors: 1 kΩ, 22 kΩ. Function generator, DC dual
power supply and CRO.
THEORY: Schmitt trigger is a comparator with positive feedback (employing regenerative feedback). This
circuit shown in figure 7.1 has two threshold levels, UTP (Upper Threshold Point) and LTP (Lower Threshold
Point). In the inverting Schmitt trigger, when the input voltage just exceeds the UTP (by the order of μV), the
output swings from +Vsat to -Vsat. And, when the input voltage just goes below LTP (by the order of μV), the
output swings from -Vsat to +Vsat. Schmitt trigger devices are typically used in signal conditioning applications
to remove noise from signals used in digital circuits. Theyare also used in closed loop negative feedback
configurations to implement relaxation oscillators, used in function generators and switching power supplies.
They can also be used as two-level detectors, which find their applications in automatic water level monitoring
system in tanks. The difference between UTP and LTP voltages is referred to as Hysteresis voltage orNoise
margin, which indicates that the circuit is immune to noise voltages having peak to peakvalues up to UTP-LTP
(Hysteresis voltage).
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CIRCUIT DIAGRAM:
Figure 7.1: Schmitt trigger
DESIGN:
Given UTP = 2 V & LTP = 1 V
R R1
UTP = 2 ×V + ×V
R1+ R2 ref R1+ R2 sat
R2 R1
LTP = ×V + × (−V )
R1+ R2 ref R1+ R2 sat
2R2
UTP + LTP = × Vref
R1+ R2
---------------- (1)
2R2
3= ×V
R1+ R2 ref
UTP - LTP= 2R
1
× VSat
R1+ R2
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sat
2R1 ---- (2)
1= × Vsat
R1 + R2
2R1 = 1 (subs. Vsat = 11V)

From 2: × V Sat = 22R1
R1+ R2 R1+ R2
Hence R1 + R2 = 22 R1 => R2 =21 R1
select, R1 =1 kΩ and therefore, R2 = 21 kΩ, select R2 = 22 kΩ (standard value)
3(R1+ R2) 69 set V ref = 1.6 V

From 1: Vref = = = 1.56 V,
2R2 44
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CIRCUIT DIAGRAM:
Figure 7.2: Inverting Schmitt Trigger using multisim.
PROCEDURE:
1. Make the connections in the MULTISIM schematic editor as per the circuit diagram shown in figure 7.2.
2. Set the input in the signal generator, a sine wave of amplitude > max ( |UTP|, |LTP| ) with frequency
around 500 Hz.
3. Observe the input and output waveforms shows in figure 7.3.
4. Measure UTP and LTP. UTP is the valueof the input when o/p changes from +Vsat to –Vsat. and
LTP is the value of the input when o/p changes from -Vsat to +Vsat
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EXPECTED WAVWFORM:
Figure 7.3: input and output waveforms of Inverting Schmitt Trigger.
HYSTERESIS CURVE OR TRANSFER CHARACTERISTICS:
Figure 7.4 Hysteresis curve of Schmitt trigger.
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SIMULATED WAVEFORM: simulated input and output waveforms are shown in below figure 7.5.
Figure 7.5: Input and output waveforms Schmitt trigger using multisim.
TABULATION:
Threshold point Theoretical Practical
UTP 2V
LTP 1V
RESULT: The Schmitt trigger operation is observed and recorded UTP, LTP values.
VIVA QUESTIONS:
1) What are the differences between an ordinary comparator and Schmitt trigger?
2) If in the above circuit, Vref = -2 V, R1= 10 kΩ and R2 =100 kΩ, mention the values of UTP
and LTP?
3) What is the advantage of considering reference DC voltage source in the Schmitt trigger
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circuit?
4) In the Schmitt trigger circuit with Vref =0, UTP =25mV. Up to what value of noise voltage peak to
peak, the circuit is immune to it?
5) Why the Schmitt trigger is referred to as regenerative comparator?
6) Mention applications of Schmitt trigger circuit.
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EXPERIMENT 8
ASTABLE MULTIVIBRATOR USING OP-AMP
AIM: To generate a rectangular/square wave signal using Op-amp based Astable Multivibrator
i) To observe that the frequency which is obtained is dependent on RC components. ii)
To calculate the frequency using CRO in Simulation tool.
COMPONENTS REQUIRED: OP-AMP IC741, Capacitor 0.01 µF, Resistors 50 kΩ, 35 kΩ, 30kΩ,
Potentiometer 500 Ω, DC power supply, CRO.
THEORY: The Op-amp Multivibrator is a non-inverting op-amp circuit that produces its own input signal
with the aid of an RC feedback network. Multivibrator circuits can be constructed using transistors, logic gates
or dedicated chips such as the NE555 timer. Also, the astable multivibrator switches continuously between its
two unstable (or quasi stable) states without the need for any external triggering. Unlike a 555 timer that may
not always give us a symmetrical output without additional biasing components, the Op-amp
Multivibrator circuit however, can provide us with a good rectangular wave signal with the use of just four
components, three resistors and a timing capacitor. It generates a rectangular output waveform using an RC
timing network connected to the inverting input of the operational amplifier and a voltage divider network
connected to the other non-inverting input as shown in Figure 8.1.
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CIRCUIT DIAGRAM:
Figure 8.1: Circuit diagram of Astable Multivibrator using Opamp
The astable multivibrator has two states, neither of which are stable as it is constantly switching between these
two states with the time spent in each state controlled by the charging or discharging of the capacitor through a
resistor. In the op-amp multivibrator circuit the op-amp works as an analog comparator that compares the
voltages on its two inputs and gives a positive or negative output depending on whether the input is greater or
less than some reference value, VREF. However, because the open-loop op-amp comparator is very sensitive to
the voltage changes on its inputs, the output can switch uncontrollably between its positive, +V(sat) and
negative, -V(sat) supply rails whenever the input voltage being measured is near to the reference voltage, VREF.
Working: Firstly let’s assume that the capacitor is fully discharged and the output of the op-amp is saturated at
the positive supply rail. The capacitor, C starts to charge up from the output voltage, Vout through resistor R, at a
rate determined by their RC time constant. In RC circuits the capacitor usually will try to charge up fully to the
value of Vout (which is +V(sat)) within five time constants. However, as soon as the capacitors charging
voltage at the op-amps inverting (-) terminal is equal to or greater than the voltage at the non-inverting terminal
(the op-amps output voltage fraction divided between resistors R1 and R2), the output will change state and be
driven to the opposing negative supply rail. But the capacitor, which has been charging towards the positive
supply rail (+V(sat)), now sees a negative voltage, -V(sat) across its plates. This sudden reversal of the output
voltage causes the capacitor to discharge toward the new value of Vout at a rate dictated again by their RC time
constant. The output and capacitor waveforms are as shown in Figure 8.2.
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Figure 8.2: Waveform across Capacitor and the Output of Opamp
Once the op-amps inverting terminal reaches the new negative reference voltage, -Vref at the non-inverting
terminal, the op-amp once again changes state and the output is driven to the opposing supply rail
voltage, +V(sat). The capacitor now sees a positive voltage across its plates and the charging cycle begins again.
Thus, the capacitor is constantly charging and discharging creating an astable op-amp multivibrator output.
The period of the output waveform is determined by the RC time constant of the two timing components and
the feedback ratio established by the R1, R2 voltage divider network which sets the reference voltage level. If
the positive and negative values of the amplifiers saturation voltage have the same magnitude, then T1 = T2 and
the expression to give the period of oscillation becomes:
Then we can see from the above equation that the frequency of oscillation for an Op-amp Multivibrator circuit
not only depends upon the RC time constant but also upon the feedback fraction. However, if we used resistor
values that gave a feedback fraction of 0.462, (β = 0.462), then the frequency of oscillation of the circuit would
be equal to just 1/2RC as shown because the linear log term becomes equal to one.
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DESIGN: To obtain a square wave of frequency 10KHz

𝑹
Let
𝑹+𝑹
β=0.5 =
Let R1=R2 = 10KΩ
Let C=0.01 µF, so R=?
T= 1/f =1/10KHz =0.1ms
+𝜷 +.𝟓
Therefore T=2RC ln[ ] = 2RC ln[ ] = 2RC (1.098)=2.197 (0.01µF) R =0.1ms
−𝜷 −.𝟓
R=4.55KΩ ~4.7KΩ
Example Design 2: An op-amp multivibrator circuit is constructed using the following

components. R1 = 35kΩ, R2 = 30kΩ, R = 50kΩ and C = 0.01uF. Calculate the circuit’s frequency of oscillation.
The Astable MV in example is as shown in Figure 8.3.
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Figure 8.3: Astable Multivibrator as in example design
Then the frequency of oscillation is calculated as 1kHz. When β = 0.462, this frequency can be calculated
directly as: ƒ = 1/2RC. Also when the two feedback resistors are the same, that is R1 = R2, the feedback fraction
is equal to 3 and the frequency of oscillation becomes: ƒ = 1/2.2RC.
This op-amp multivibrator circuit can be taken one step further by replacing one of the feedback resistors with
a potentiometer to produce a variable frequency op-amp multivibrator as shown in Figure 8.4.
Figure 8.4: Astable Multivibrator for varying output frequencies
Dept. of ECE 58
By adjusting the central potentiometer between β1 and β2 the output frequency will change by the following
amounts as shown in Figure 8.4.
Potentiometer wiper at β1
Potentiometer wiper at β2
Then in this simple example we can implement an operational amplifier multivibrator circuit that can produce
a variable output rectangular waveform from 100Hz to 1.2kHz, or any frequency range we require just by
changing the RC component values.
We have seen above that an Op-amp Multivibrator circuit can be constructed using a standard operational
amplifier, such as the 741, and a few additional components. These voltage controlled non-sinusoidal relaxation
Dept. of ECE 59
oscillators are generally limited to a few hundred kilo-hertz (kHz) because the op-amp does not have the
required bandwidth, but nevertheless they still make excellent oscillators.
The astable multivibrator realized in MultiSIM is as shown in Figure 8.5 and the corresponding output
waveforms are as shown in Figure 8.6
Figure 8.5: Astable Multivibrator Circuit using MultiSIM
Dept. of ECE 60
Figure 8.6: Waveforms of Astable Multivibrator Circuit using MultiSIM
PROCEDURE:
1. Connect the circuit as shown in the figure.
2. Obtain the output for different duty cycle and verify the waveforms.
RESULT: It is a rectangular waveform of the frequency for which the circuit is designed.
VIVA QUESTIONS:
1. What are the other names of Astable multivibrator?
2. Define quasi stable state?
3. Is it possible to change time period of the waveform with out changing R & C?
4. Explain charging and discharging of capacitors in an Astable Multivibrator?
5. How many stable states are there in Astable MV circuit?
Dept. of ECE 61
6. The frequency of oscillation of a symmetric Astable MV with R=10KΩ and C=10nF is

7. Multivibrators are also referred to as
8. Which feedback does a multivibrator have?
9. What are the types of Multivibrators?
10. How do Multivibrators differ from Oscillators?
Dept. of ECE 62
EXPERIMENT 9
LOW PASS, HIHG PASS FILTER AND BUTTERWORTH SECOND

ORDER LOW PASS, HIGH PASS FILTER
AIM : To design and implement using Op-amps
i) Butterworth first order low pass and high pass filter

ii) Butterworth second order low pass and high pass filter
i) To observe that filters are frequency selective circuits.

ii) To observe that the roll-off rate is 20dB/dec for a first order filter and 40 dB/dec for a second order
filter.
iii) To calculate the cut-off frequency without plotting the frequency response.
COMPONENTS REQUIRED: OP-AMP IC741, Resistor, capacitor, Function generator, oscilloscope,

multimeter.
THEORY: Filter is a frequency-selective circuit that is used to pass a specific band of

frequencies. A low pass filter (LPF) shown in Figure 9.1 is one that suppresses frequencies that are
beyond a specified frequency called as cut-off frequency, whose frequency response and frequency
response using multisim is shown in Figure 9.2 and 9.3. first order HPF circuit, frequency
response and frequency response using multisim is shown in Figure 9.4, 9.5and 9.6.
A pass band (gain significant) and a stop band (gain insignificant) characterize frequency response. In
the second order low pass filter as in Figure 9.7, the roll-off rate in the stop band is 40 dB/dec
shown Figure 9.8. frequency response of second order LPF using multisim is shown in Figure 9.9.
Here, we use an OP-AMP, an active device, which induces the gain and at the same time, solves the
problem of source loading (provides impedance matching). The OP-AMP here is configured to
operate as non-inverting amplifier, with the gain, AF = 1 + RF /R1 = 1.586. With this gain, the overall
filter is referred to as Butterworth filter, since it leads to damping coefficient of 0.707 in this second
Dept. of ECE 63
order system. Thus, resulting maximally flat frequency response. Butterworth filters mainly find their
applications in audio, since we expect flat frequency response there. Circuit for the LPF uses two
stage passive RC filters connect to the input of non-inverting amplifier. A high pass filter (HPF) is
one that suppresses frequencies that are below a specified frequency called as cut-off frequency.
CIRCUIT DIAGRAM:
Figure 9.1 First Order Active low-pass Butterworth filter
DESIGN:
fc = 1/2πRC
fc =10 kHz, C = 0.01µF
Then R = 1/2πfc =1.59kΩ; R= R1=1.59k
A = 1+R2/R3 = 2
R2=R3= 1 kΩ
Dept. of ECE 64
EXPECTED FREQUENCY RESPONSE:
Figure 9.2 Frequency response of the first order LPF circuit
SIMULATION RESULT:
Figure 9.3 Frequency response of the first order LPF circuit using Multisim
Dept. of ECE 65
CIRCUIT DIAGRAM:
R1 XBP1
VEE R2
1kΩ
-12V 1kΩ
IN OUT
4 U1
XFG1 2
C1 6 XMM1
3
0.01uF 7 1 5 741
R3
3.18kΩ VCC
12V
Figure 9.4 First Order Active High-pass Butterworth filter
DESIGN:
fc = 1/2πRC
fc =5 kHz, C = 0.01µF
Then R = 1/2πfc =3.18kΩ; R= R3 =3.18K
A = 1+R2/R1 = 2 :R2=R1= 1 kΩ
Figure 9.5 Frequency response of the first order HPF circuit
Dept. of ECE 66
SIMULATION RESULT:
Figure 9.6 Frequency response of the first order LPF circuit using Multisim
OBSERVATION: Low pass and high pass filter Vin= 1vp-p
1 Frequency(Hz) Vout (volts) Gain in dB

100
. . .
. . .
. . .
10k
Dept. of ECE 67
CIRCUIT DIAGRAM:
VEE
-12V XSC1
R3 R4
Ext Trig
+
10kΩ 5.86kΩ _
A B
_ _
4 U1 + +
2
XMM1
6
R2 R1
3
XFG1 1.59kΩ 1.59kΩ 7 1 5 741
C1 VCC
C3 0.01uF
12V XBP1
0.01uF
IN OUT
Figure 9.7 Second Order Active Low-pass Butterworth filter
At frequencies much lowe r than cut-off, the reactance offered by capacitances will be very high, and
hence can be treated as open. Then, the circuit is just non-inverting amplifier, with vin appearing at
non-inverting input terminal. Therefore, the gain at low frequencies, is given by AF = 1 + RF /R1, or
20 log AF. At cut-off frequency, the gain is 3-dB lesser than maximum gain which happens at low
frequencies. At frequencies, beyond cut-off frequency, the gain falls off at a rate 40 dB/dec (for 10
times increase in frequency, gain falling by 40 dB).
DESIGN:
fc = 1/2πRC
fc =10 kHz, C = 0.01µF
Then R = 1/2πfc =1.59kΩ;
R=R1=R2= 1.59kΩ
A = 1+R4/R3 = 1.586
R4=0.586R2
R3 = 10kΩ; R4 = 5.86kΩ
Dept. of ECE 68
Figure 9.8 Frequency response of the second order LPF circuit
SIMULATION RESULT:
Figure 9.9 Frequency response of the second order LPF circuit using Multisim
Dept. of ECE 69
CIRCUIT DIAGRAM:
-12V
VCC
R3 R4
Ext Trig
10kΩ 5.86kΩ _
A B
4 U1 _ _
+ +
2
C1 C2
6
R1
XFG1 0.01uF 0.01uF 3
3.18kΩ 7 1 5 741
XBP1
R2
3.18kΩ
VDD IN OUT
12V
XMM1
Figure 9.10 Second Order Active High-pass Butterworth filter
Second Order Active High-pass Butterworth filter shown in Figure 9.10, at frequencies much higher
than cut-off, the reactance offered by capacitances will be very low, and hence can be treated as short.
Then, the circuit is just non-inverting amplifier, with vin appearing at non-inverting input terminal.
Therefore, the gain at high frequencies, is given by, AF = 1 + RF /R1, or 20 log AF. At
𝐴
cut-off frequency, the gain is 3-dB lesser than the maximum gain which happens at high
frequencies. At frequencies, below cut-off frequency, the gain falls off at a rate 40 dB/dec, as we
decrease the frequency as shown in Figure 9.11.frequency response of the second order HPF circuit
using Multisim shown in Figure 9.12.
DESIGN:
fc = 1/2πRC
fc =5kHz, C = 0.01µF Then
R = 1/2πfc =3.18KΩ
R=R1=R2=3.18KΩ
A = 1+R4/R3 = 1.586
R4=0.586R3
R3 = 10kΩ; R4 = 5.86kΩ
Dept. of ECE 70
Figure 9.11 Frequency response of the second order HPF circuit

SIMULATION RESULT:
Figure 9.12 Frequency response of the second order HPF circuit using Multisim
PROCEDURE:
1. Rig up the circuits as shown.

2. Input taken from function generator. Vary the frequency of the signal keeping the amplitude constant.
3. At each step, note down the output using multimeter.
4. We also use bode plotter to observe the output
5. Calculate the gain.
6. Plot the graph of gain versus frequency.
7. To determine fc practically.
Dept. of ECE 71
OBSERVATION: Sencond order Low pass and high pass filter Vin= 1vp-p
1 Frequency(Hz) Vout (volts) Gain in dB

100
. . .
. . .
. . .
RESULT:
LOW PASS FILTER
Theoretical Practical
Cut off Frequency
Roll off Rate
Pass band Gain
HIGH PASS FILTER
Theoretical Practical
Cut off Frequency
Roll off Rate
Pass band Gain
Dept. of ECE 72
VIVA QUESTIONS:
1) What is a filter?
2) What are the different classifications of filters?
3) Prove that a single RC network can operate as low-pass filter with the roll-off rate 20 dB/
dec.
4) Prove that a single RC network can operate as high-pass filter with the roll-off rate 20 dB/
dec.
5) Mention the applications of filters.
6) In the second order active LPF above, what is the value of the voltage at the non-inverting input
terminal, at frequencies, much below fc and at much beyond fc?
7) In the second order active HPF above, what is the value of the voltage at the non-inverting
input terminal, at frequencies, much below fc and at much beyond fc?
Dept. of ECE 73
EXPERIMENT 10
RC PHASE SHIFT OSCILLATOR
AIM: To generate an audio frequency sinusoidal signal using RC Phase-shift oscillator.
i) To observe that the audio frequency which is obtained is dependent on RC components.

ii) To calculate the frequency of the waveform and the phase shifts using CRO in Simulation tool.
COMPONENTS REQUIRED: OP-AMP IC741, Capacitors 0.047 µF(3), Resistors 1.5 kΩ(3), 56 kΩ,
DC power supply, CRO.
THEORY: RC-Phase Shift Oscillator: Tuned LC oscillators operate well at high frequencies. At low
frequencies, as the inductors and capacitors required for the corresponding time period would be very bulky,
RC oscillators are found to be more suitable. A Phase Shift Oscillator (Figure 10.1) is an electronic
oscillator circuit which produces sine wave output. It can either be designed by using transistor or by using
an Op-amp as inverting amplifier. Generally, these phase shift oscillators are used as audio oscillators. In RC
phase shift oscillator, 180 degree phase shift is generated by the RC network and another 180 degree is
generated by the Op-amp, so the resulting oscillation is obtained since barkhausen’s criteria of phase shift
around the loop which should be zero or 360 degrees is satisfied.
CIRCUIT DIAGRAM:
Figure 10.1: RC Phase Shift Oscillator Circuit using Op-amp
Dept. of ECE 74
Apart from generating the sine wave output they are also used to provide significant control over the phase
shifting process. Other usages of phase shift oscillators are: In audio oscillators, Sine Wave Inverter, Voice
Synthesis, GPS units and Musical Instruments.
The maximum phase shift of the output wave of a single RC circuit is 90 degree, and in practice we generate 60
degrees in each RC section. The formula for calculating the phase angle of the RC network is mentioned below:
φ = tan-1(Xc / R)
Where, Xc is the reactance of the capacitor and R is the resistor connected in the RC network.
If we cascade three RC networks, we will get 180-degree phase shift.
In the RC-Phase shift oscillator, the required phase shift of 180º in the feedback loop from output to input is
obtained by using R and C components instead of tank circuit.
Why use Op-amp for RC Phase Shift Oscillator instead of Transistor?

There are some limitations in using Transistor for Building RC Phase Shift Oscillator:
1. It is stable for low frequencies only.

2. RC phase shift oscillator requires additional circuitry to stabilize the amplitude of the waveform.
3. Frequency accuracy is not perfect and it is not immune to noisy interference.
4. Adverse Loading effect. Due to cascade formation the second pole’s input impedance change the
resistors resistance properties of the first pole filter. More the filters cascaded more the situation worsen up as it
will affect the accuracy of calculated phase shift oscillator frequency.
Due to the attenuation across resistor and capacitor, the loss across each stage is increased and the total loss
is approximately 1/29th of the input signal.
The practical circuit uses an Opamp Inverting amplifier which is followed by 3-sections of RC phase shift
network, the output of the last section being returned to the input. The phase angle of each section of RC
network will be 60º. In the last section of RC, the input impedance of the amplifier comes as a part of R and
therefore, only a resistance (R – Rin) is connected after the last C. Once the circuit is switched on, the output
starts to build up and finally, will be a sinusoid of required frequency.
Dept. of ECE 75
In this circuit, the amplifier produces the 180º phase shift and one more 180 º phase shift is given by the RC-
network. We know that the phase angle shift even depends on the frequency and this RC-network is designed
in such a way that it gives 180 º phase shift for the required frequency.
The RC phase shift oscillator is suitable for audio frequencies only. Its main drawbacks are that the three
capacitors or resistors should be changed simultaneously to change the frequency of oscillation.
DESIGN:
If the given frequency for RC-phase shift Oscillator is, say, 1 kHz. Then,
for a phase lead network
Let C=0.047 µF, then fo =1 / (2лRC√2𝑁) = 1 kHz, f0 =1/2л*R*0.01µ*√6 =1KHz
Therefore R=~1.5Kohms
In the above equation, N refers to the number of RC legs in the circuit (N = 3 above), so the output can be scaled
by carefully adding or removing RC legs in the feedback loop. We consider C= 0.047µF. The third stage R =
Rin of opamp which is 1.5kΩ and therefore, RF >= 44kΩ; Since the gain of the amplifier, Av should be ≥ 29.
The Circuit used for simulation is shown in Figure 10.2 and the obtained waveforms are shown in Figures 10.3
and 10.4.
Dept. of ECE 76
CIRCUIT DIAGRAM USING MULTISIM:
Figure 10.2: Multisim Circuit Simulation of RC phase shift oscillator
SIMULATED WAVEFORM:
Figure 10.3: Waveform of Multisim Circuit Simulation of RC phase shift oscillator
Dept. of ECE 77
PROCEDURE:
1) Connect the circuit as shown in the circuit diagram.
2) Observe the sinusoidal waveform output and calculate the frequency using CRO.
3) Measure the phase-difference between the output and at points y1(after rightmost RC sections), y2(after
2 rightmost RC sections), y3(after all 3 RC sections).
4) For this, connect the main output to first channel and connect the output at y1 or y2 or y3 to second channel.
Go to x-y mode and observe the lissajous figures to measure the phase-difference between output and at y1 or
y2 or y3.
5) Determination of phase-difference from waveforms will generate the following ellipses and graphs as shown
in Figures 10.4 and 10.5
Figure 10.4a Phase difference Figure 10.4b Phase Figure 10.4c Phase
between output and point y1 difference between output difference between output
and point y2 and point y3
Dept. of ECE 78
Figure 10.5: Phase Shift between Output and various RC sections of RC phase shift oscillator
RESULT: It is a sinusoidal waveform of the frequency for which the circuit is designed and phase shifts
between various points in the waveforms (Figure 10.5).
VIVA QUESTIONS:
1) Where does the RC oscillator find its application?
2) Why RC oscillators are used for generating audio frequencies?
3) What should be the value of current gain of the transistor in RC-phase-shift oscillator?
4) Can RC-phase-shift oscillator be used for generating RF range of frequencies?
5) What is an oscillator?
6) Explain Barkhausen criterion for sustained oscillations.
7) What type of feedback is employed in the oscillator circuits.
8) Why amplifier is required in the oscillator circuits?
9) Mention the AF range of frequencies.
Dept. of ECE 79
EXPERIMENT 11
MONOSATBLE MULTIVIBRATOR USING IC 555 TIMER
AIM: To generate time-interval and rectangular waveforms using monostable multivibrator of 555 timer.
i) To design the Monostable MV circuit to generate accurate time-intervals.
ii) To find that the ON-time of the timer output is controlled by capacitor charging and discharging,
connected at pin 6 of the timer.
COMPONENTS REQUIRED: IC 555, diode 1N4001, capacitors 0.01µF, 0.1 µF Resistors 6.8 kΩ, 3.3
kΩ, 10 kΩ, Signal generator, DC power supply and CRO
THEORY: The Monostable Multivibrator (Figure 11.1) has one stable state and one quasi-stable state. The
output remains at stable state (logic ‘0’ in 555 timer) and when the trigger signal is applied, the output swings to
quasi-stable state (logic ‘1’ in 555 timer), remains in that state for the duration determined by RC components
and comes back to stable state . Again, if the output has to switch to quasi-stable state, once again the trigger
signal has to be applied. It has applications like, missing pulse detector, ramp generator, pulse-width modulation
etc.
CIRCUIT DIAGRAM:
Figure 11.1: Monostable multivibrator using 555 Timer
Dept. of ECE 80
′
In the circuit of Figure 11.2, when the trigger signal at pin 2 (v tri
) goes below Vcc/3, the output of the timer is
set to ‘high’, and the capacitor starts charging towards Vcc through RA. As the capacitor voltage (pin 6, threshold
pin voltage) increases due to charging and just exceeds 2/3 Vcc, the output of the timer goes ‘low’ and the
capacitor discharges through pin 7 (as discharge transistor will be ON by then) to ground. Therefore, the output
remains high till the capacitor charges from 0 to 2/3 Vcc, which is determined by product of RAC. A pulse-width
of a specific duration is generated. In the circuit above, the trigger’s negative period must be smaller than the
designed pulse-width to avoid invalid state in RS flipflop in timer. To ensure this, the differentiator along with
diode is connected as shown in the circuit diagram. With this configuration, the signal from trigger source (vtri )
having a negative duration larger than pulse-width, will be converted to negative spike (extremely small
duration) at pin 2 (v ′ tri
). A differentiator RT-CT along with a diode D is included to differentiate the input pulses
and eliminate the positive edges so as to prevent false triggering of the multivibrator at the positive edges.
DESIGN: Given T =1 ms. T= 1.1 RA C = 1 ms. If C= 0.1 μF, then RA =9.09 kΩ.
Select RA = (8.2k +820) Ω.
RTCT << T, say RTCT =0.1 T = 0.1ms. If CT = 0.01 μF, then RT = 10 kΩ
EXPECTED WAVEFORM:
Dept. of ECE 81
“Simulation of Electronic
The circuit diagram circuits using
and waveforms Multisim,
for the PSpice
simulation and Labview”
of monostable multivibrator without RC diffrentiator
are as shown in Figure 11.3 and 11.4. The same with RC differentiator are shown in Figure 11.5 and 11.6.
Figure 11.3: Monostable MV Circuit using MultiSim
SIMULATED WAVEFORM:
Figure 11.4: Waveforms of Monostable multivibrator shown in Circuit of Figure 11.3
Dept. of ECE 82
CIRCUIT DIAGRAM OF MONOSTABLE MV:
Figure 11.5: Monostable MV Circuit using MultiSim with RC differentiator and diode
SIMULATED WAVEFORM:
Figure 11.6: Waveforms of Monostable MV Circuit using MultiSim with RC differentiator and diode
Dept. of ECE 83
OUTPUT: It is a pulse waveform with pulse width (or ON time) as designed.
PROCEDURE: MONOSTABLE MULTIVIBRATOR

1. Connect the circuit as shown in the figure.
2. Apply vtri, a square waveform, with 5Vpp and freq = 400 Hz (observe 400 Hz has a negative duration
= 1.25 ms > T).
3. Observe the negative going spikes (extremely small duration) at pin no 2, resulting by the action
of waveform shaping circuit.
4. Measure Time period (T) of the output waveform at pin no. 3. Observe the capacitor voltage
waveform.
TABULATION OF MONOSTABLE MULTIVIBRATOR:
Amplitude (V)
Input 5 Vpp, sqr w/f,

f=400Hz
Output
RESULTS: The operation of Monostable multivibrator is realized using 555 Timer.
VIVA QUESTIONS:
1) What is a 555 IC?
2) What is called frequency and duty cycle?
3) Why the Reset pin of IC 555 is normally connected to Vcc?
4) Why the control voltage pin (pin 5) of 555 timers is connected to ground through a 0.01µf capacitor?
5) How can a missing heart beat be detected using Monostable MV?
6) How can we implement speed control using Monostable MV?
7) How can the pulse width be varied in a monostable MV without varying R and C?
8) What is the minimum and maximum pulse width possible with a 555 timer?
9) What is the min and max values of Vcc that can be used with 555?
Dept. of ECE 84
EXPERIMENT 12
4BIT R-2R DIGITAL TO ANALOG CONVERTOR
AIM: To design and implement 4bit R-2R digital to Analog convertor.
COMPONENTS REQUIRED: OP-AMP IC741, Resistors: 1 kΩ, Function generator, and oscilloscope.
LEARNING OBJECTIVES: To understand the working of DAC.
THEORY: DAC: The DAC generates an equivalent analog output for the digital data (binary codeword)
input. Here, we consider R-2R ladder network connected to OP-AMP to realize the DAC . The advantage of
this circuit is that only two sets of precision resistors are required, unlike weighted-resistors DAC. The output
of the circuit which we consider is given by:
Vo = Vref / 16 [8b3 + 4b2 + 2b1 + b0 ] . Here, b3 b2 b1 b0 form the binary data input.
Vref (5 V) is the voltage representing logic’1’. DACs are predominantly used when the processed or stored
digital data (from computer or any dedicated digital hardware) is to be represented in equivalent analog form.
For ex, in music system, the audio signal which is stored in digital form in the memory, has to be converted to
equivalent analog form during playback. They are also used in video display systems, converting digital data
from video processor to equivalent video signals which will enable display of different colour images. In the
circuit shown in Figure 12.1, the binary inputs are given through switches which change their positions
between Vref (logic’1’) and ground (logic’0’). Expected graph and staircase waveform shown in Figure 12.2
and 12.3.
PROCEDURE:
1. Make the connections as shown in circuit diagram.
2. Set 4-bit binary input from SPDT(single port double throw) switches.
3. For different digital inputs note the output voltage which is displayed in multi-meter.
4.Verify whether the theoretical value is matching with practical values and observes the outputs.
Dept. of ECE 85
DESIGN:
Let R=1 kΩ ; 2R = 2 kΩ
choose 2.2 kΩ
CIRCUIT DIAGRAM:
Figure 12.1: R-2R DAC
TABULATION:
b3 b2 b1 b0 Vo(Th.) in V Vo(Prac.) in V
0 0 0 0 0
0 0 0 1 0.3125
0 0 1 0 0.625
0 0 1 1 0.9375
0 1 0 0 1.25
0 1 0 1 1.5625
Dept. of ECE 86
0 1 1 0 1.875
0 1 1 1 2.1875
1 0 0 0 2.5
1 0 0 1 2.8125
1 0 1 0 3.125
1 0 1 1 3.4375
1 1 0 0 3.75
1 1 0 1 4.0625
1 1 1 0 4.375
1 1 1 1 4.6875
EXPECTED GRAPH:
Figure 12.2: Analog Output v/s binary input
Dept. of ECE 87
Figure 12.3 Staircase output
RESULT:
(i) Analog output values for corresponding binary inputs are tabulated, and the value of
Linearity error =…………...
VIVA QUESTIONS:
1) Mention the applications of DAC.
2) Mention the differences between weighted-resistor DAC and R-2R DAC.
3) Mention the specifications of DAC.
4) In the above circuit, if the OP-AMP operates in a non-inverting configuration, with
feedback resistor = the resistor between inverting terminal and ground = R, then what is the
output of the circuit, if the digital input is “0010”?
5) In the above circuit, if the OP-AMP operates in an inverting configuration with feedback
resistor =R, then what is the output of the circuit, if the digital input is “0011”?
6) In the above circuit, if we include a feedback resistor = 2R, then what is the output of the
circuit, if the digital input is “0011”?
Dept. of ECE 88
Simulation of electronic circuits using Multisim,Pspice and LabVIEW.
LabVIEW
PROGRAMMING
BASICS
21EC384
Dept Of ECE 1
COURSE OBJECTIVES:
• Aware of various front panel controls and indicators.
• Connect and manipulate nodes and wires in the block diagram.
• Locate various toolbars and pull down menus for the purpose of implementing
specific functions.
• Locate and utilize the context help window.
• Familiar with LabVIEW and different applications using it.
• Run a virtual instrument(VI).
COURSE OUTCOMES:
At the end of the course the student will be able to :
1.Use LabVIEW to create data acquisition , analysis and display oerations.
2. Create user interfaces with charts ,graphs and buttons.
3.Use the programming structures and data types that exist in Lab VIEW.
4.Use various editing and debugging techniques.
Dept Of ECE 2
LIST OF EXPERIMENTS
Sl.No VI programs(Using LabVIEW software )to realize the following:
1 Basic arithmetic operations:addition,subtraction,multiplication and division
2 Boolean operations:AND,OR,NOT,XOR and NAND
3 Sum of ‘n’ numbers using ‘for’ loop
4 Factorial of a given number using ‘for’ loop
5 Determine square of a given number
6 Factorial of a given number using ‘while’ loop
7 Sorting even numbers using while loop in an array
8 Finding the array maximum and array minimum
Demonstration experiments
9 Build a Virtual instrument that simulates a heating and cooling system .The system must
be able to be controlled manually or automatically.
10 Build a Virtual instrument that simulates a basic calculator.
11 Build a virtual instrument that simulates a water level indicator.
12 Demonstrate how to create basic VI which calculates area and perimeter of a circle.
Dept Of ECE 3
Introduction to LabVIEW
Virtual Instrumentation:
Virtual instrumentation is the use of customizable software and modular measurement
hardware to create user-defined measurement systems, called virtual instruments. Traditional
hardware instrumentation systems are made up of pre-defined hardware components, such as
digital multimeters and oscilloscopes that are completely specific to their stimulus, analysis,
or measurement function. Because of their hard-coded function, these systems are more
limited in their versatility than virtual instrumentation systems. The primary difference
between hardware instrumentation and virtual instrumentation is that software is used to
replace a large amount of hardware. The software enables complex and expensive hardware
to be replaced by already purchased computer hardware; e. g. analog-to-digital converter can
act as a hardware complement of a virtual oscilloscope, a potentiostat enables frequency
response acquisition and analysis in electrochemical impedance spectroscopy with virtual
instrumentation.
Layers of Virtual Instrumentation

• Application Software: Most people think immediately of the application software layer. This
is the primary development environment for building an application.
• Test and Data Management Software: Above the application software layer the test
executive and data management software layer. This layer of software incorporates all of the
functionality developed by the application layer and provides system-wide data management.
• Measurement and Control Services Software: The last layer is often overlooked, yet critical
to maintaining software development productivity.
LabVIEW
Laboratory Virtual Instrumentation Engineering Workbench (LabVIEW) is a graphical
programming language that uses icons instead of lines of text to create applications. In
contrast to text-based programming languages, where instructions determine program
execution, LabVIEW uses dataflow programming, where the flow of data determines
execution. In LabVIEW, a user interface can be build by using a set of tools and objects. The
user interface is known as the front panel. Then code can be added using graphical
representations of functions to control the front panel objects. The block diagram contains
this code. In some ways, the block diagram resembles a flowchart.
LabVIEW programs are one of the suitable for virtual instruments, or VIs, because their
appearance and operation imitate physical instruments, such as oscilloscopes and
multimeters. Every VI uses functions that manipulate input from the user interface or other
sources and display that information or move it to other files or other computers.
A VI contains the following three components:
Front panel - Serves as the user interface. Fig 1 shows front panel example.
Block diagram - Contains the graphical source code that defines the functionality of the VI.
Icon and connector panel - Identifies the VI so that the VI can be used in another VI. A VI
within another VI is called a subVI. A subVI corresponds to a subroutine in text-based
programming languages. Fig 2 shows Block diagram of VI programming.
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Fig 1. Front Panel of Virtual Instrumentation.vi
Fig 2. Block Diagram of Virtual Instrumentation.vi
The front panel is the user interface of the VI. The front panel is build with controls and
indicators, which are the interactive input and output terminals of the VI, respectively.
Controls are knobs, pushbuttons, dials, and other input devices. Indicators are graphs, LEDs,
and other displays. Controls simulate instrument input devices and supply data to the block
diagram of the VI. Indicators simulate instrument output devices and display data the block
diagram acquires or generates. After the front panel is build, add code using graphical
representations of functions to control the front panel objects. The block diagram contains this
graphical source code. Front panel objects appear as terminals on the block diagram.
Additionally, the block diagram contains functions and structures from built-in LabVIEW VI
libraries. Wires connect each of the nodes on the block diagram, including control and
indicator terminals, functions, and structures.
LabVIEW Palettes
LabVIEW palettes give provide the options needed to create and edit the front panel and
block diagram. The Tools palette is available on the front panel and the block diagram. A
tool is a
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special operating mode of the mouse cursor. By selecting a tool, the cursor icon changes to
the tool icon. Use the tools to operate and modify front panel and block diagram objects.
Select Window » Show Tools Palette to display the Tools palette.
The Tools palette can be placed anywhere on the screen. If automatic tool selection is enabled
and as the cursor is moved over objects on the front panel or block diagram, LabVIEW
automatically selects the corresponding tool from the Tools palette.
The Controls palette
The Controls palette is available only on the front panel. The Controls palette contains the
controls and indicators used to create the front panel. to display the Controls palette, Select
Window » Show Controls Palette or right-click the front panel workspace. The Controls
palette can be placed anywhere on the screen. Fig 3 shows control pallete.
Fig 3: Controls Palette
The Functions palette

The Functions palette is available only on the block diagram. The Functions palette contains
the VIs and functions used to build the block diagram. To display the Functions palette, select
Window » Show Functions Palette or right-click the block diagram workspace. The Functions
palette can be placed anywhere on the screen. Fig 4 shows Function pallette of LabVIEW.
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Fig 4: Functions Palette

Tips for Working in LabVIEW
• Keystroke Shortcuts
– <ctrl-H> – Activate/Deactivate Context Help Window
– <ctrl-B> – Remove Broken Wires From Block Diagram
– <ctrl-E> – Toggle Between Front Panel and Block Diagram
– <ctrl-z> – Undo (Also in Edit Menu)
• Tab Key – Toggle Through Tools on Toolbar
• Tools » Options… – Set Preferences in LabVIEW
• VI Properties – Configure VI Appearance, Documentation, etc.
Advantages of LabVIEW
– Graphical User Interface
– Drag-and-Drop built-in functions
– Modular design and hierarchical design
– Multiple high level development tools
– Professional Development Tools
– Multi platforms
– Reduces cost and preserves investment
– Flexibility and scalability
– Connectivity and instrument control
Creating a VI
Launch Labview: Fig 5 shows front and block diagram panel of LabVIEW files.
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Fig 5: LabVIEW Windows
Front Panel Controls and Indicators

Controls and Indicators
– Controls are knobs, push buttons, dials and other input devices.
– Indicators are graphs, LEDs and other displays.
– Controls simulate instrument input devices and supply data to the block diagram of
the VI.
– Indicators simulate instrument output devices and display data the block diagram
acquires or generates.
– Every control or indicator has a data type associated with it. They are numeric data
type, boolean data type, string data type
Block Diagram
Terminals
– Front panel object appear as terminals on the block diagram.
– Terminals are entry and exit ports that exchange information between the front panel
and block diagram.
– Terminals are analogous to parameters and constants in text-based programming
languages. Types of terminals include control or indicator terminals and node
terminals.
– Control and indicator terminals belong to front panel controls and indicators.
– Data you enter into the front panel controls enter the block diagram through the control
terminals.
– The terminals represent the data type of the control or indicator.
– You can configure front panel controls or indicators to appear as icon or data type
terminals on the block diagram.
– By default, front panel objects appear as icon terminals.
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– To display a terminal as a data type on the block diagram, right-click the terminal and
select View As Icon from the shortcut menu
Wires
– You can transfer data among block diagram objects through wires.
– Each wire has a single data source, but you can wire it to many VIs and functions that
read the data.
– Wires are different colors, styles and thicknesses, depending on their data types.
– A broken wire appears as a dashed black line with a red X in the middle.
– Broken wires occur for a variety of reasons, such as when you try to wire two objects
with incompatible data types.
– You must connect the wires to inputs and outputs that are compatible with the data
that is transferred with the wire.
– You cannot wire an array output to a numeric input.
– In addition, the direction of the wires must be correct. You must connect the wires to
only one input and at least one output.
– You cannot wire two indicators together
– <Ctrl+B> to delete all broken wires or right click and select Clean Up Wire to reroute
the wire.
Data Flow Program

– LabVIEW follows a dataflow model for running VIs.
– A block diagram node executes when all its inputs are available.
– When a node completes execution, it supplies data to its output terminals and passes
the output data to the next node in the dataflow path.
– Visual Basic, C++, JAVA, and most other text-based programming languages follow a
control flow model of program execution.
Review Questions.
What is virtual instrumentation?
What are the different palettes in VI?
What is sub VI?
What are the advantages of VI?
Compare hardware instrumentation and VI
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EXPERIMENT 1
ARITHMETIC OPERATIONS
AIM:
To perform basic arithmetic operations using LabVIEW.
Addition, Subtraction, Multiplication and division.
THEORY:
To give the 2 inputs numeric controls are selected in Front panel .And all arithmetic operators
can be selected from Functions palette. Addition, subtraction, multiplication and division are
the basic arithmetic operations.
PROCEDURE:
Step 1: Start the LabVIEW and select the blank VI.
Step 2: Create front and block diagram panel.
Step 3: Numeric controls are given as inputs and numeric indicators are given as output they
are selected by right clicking on the front panel.
Step 4: Different arithmetic operators such as addition, subtraction, multiplication
and division are generated in block diagram panel.
Step 5: Using wiring operation inputs and outputs are connected to the respective
operators in the block diagram panel.
Step 6: Input values are given in the front panel and the program is executed.
Hence the output is generated.
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BLOCK DIAGRAM:
The block diagram for basic arithmetic operations using LabVIEW is shown below in Fig.1.1.
Fig:1.1:Block diagram of basic arithmetic operations
OUTPUT/FRONT PANEL:
Output of basic arithmetic operations is shown in below fig 1.2.
Fig:1.2:output of basic arithmetic operations
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RESULT:
The arithmetic operations were performed and the result is verified using LabVIEW.
Viva questions:
1.What are the advantages of LabVIEW?
2.What are the two panels used in LabVIEW programming?
3.What is the difference between local variable and global variable in LabVIEW?
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EXPERIMENT 2
BOOLEAN OPERATIONS
AIM:
To perform Boolean operations using LabVIEW.
AND,OR,NOT,XOR , NAND
THEORY:
The truth table of Boolean operations like AND, OR,NOT,XOR ,and NAND is shown below
in Fig 2.1.The Boolean inputs are given by push buttons in the control palette .All the
Boolean operators can be taken from the functions palette.
Fig2.1:Truth table of all the logic gates
PROCEDURE:
Step 1: Start the LabVIEW and select the blank VI.
Step 2: Create front and block diagram panel.
Step 3: To perform Boolean operation push buttons are taken as inputs and round LED as
output.
Step 4: Different Boolean operations such as AND, OR, XOR, NOT, NAND are selected
from the block diagram panel.
Step 5: Boolean inputs and outputs are wired in the block diagram panel.
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Step 6: Logic values 0 & 1 are given in the front panel and the program is executed.
BLOCK DIAGRAM:
The block diagram of Boolean operations is shown below in Fig.2.2.
Fig 2.2:Block diagram of Boolean operations
OUTPUT/FRONT PANEL:
The output of Boolean operations is shown below in Fig.2.3.
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Fig.2.3: output of Boolean operations
RESULT:
The Boolean operation using LabVIEW is performed.
VIVA QUESTIONS:
1.Is LabVIEW a compiled programming language?
2. Can LabVIEW be integrated into existing software engineering practices?
3.What is LabVIEW?
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EXPERIMENT 3
SUM OF N NUMBERS USING FOR LOOP
AIM:
To find the sum of ‘n’ numbers using FOR loop.
THEORY:
Usually sum of n numbers, we take for natural numbers.The equation to calculate sum of n
numbers is n(n+1)/2.So we want to take sum of first 3 numbers, n=3.Then as per the equation
it becomes 3(4)/2=6.i.e 3+2+1=6.
FOR loop in LabVIEW is shown below in Fig 3.1.
Fig 3.1:Structure of FOR loop

In FOR loop, shift registers are used if we make use of previous results.N is the count and I is
the iteration terminal and initial value is zero.
PROEDURE:
Step 1: Create blank VI.
Step 2: First of all move to the front panel and press right then control palette and choose
numeric option place in the front panel and its correspondent will shown block diagram.
Step 3:Right click on the block diagram panel, select program , go to structures and select a
FOR loop.
Step 4: Right click on the border of the FOR loop and select add shift register, borders are
converted into shift register.
Step 5: In block diagrams select the numeric button and choose constant and connect it to
register.
Step 6: Select the add button from the numeric tab. Then select the increment option from the
numeric tab .Connect the output of this increment block to the remaining input of the add
block.
Step 7: At the right shift register click right and from the drop down select create and then
select indicator .
Step 8:Inputs are given in the front panel and the program is executed.
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BLOCK DIAGRAM:
The block diagram of sum of n numbers using FOR loop is shown in Fig 3.2 below.
Fig 3.2: Block diagram of sum of n numbers using FOR loop
OUTPUT/FRONT PANEL:
The output or the front panel view of sum of n numbers using FOR loop is shown below in Fig
3.3.
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Fig 3.3: result of sum of n numbers using FOR loop
RESULT:
Thus the sum of ‘n’ natural numbers using FOR loop is performed in LabVIEW.
VIVA QUESTIONS:
1.What is shift register?How is it implemented in Lab VIEW?
2.Can LabVIEW Vis be merged?
3.What is LabVIEW signal express?
4.What is Formula node in LabVIEW?
5.In which palette,FOR loop is available?
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EXPERIMENT 4
FACTORIAL OF A NUMBER
AIM:
To perform the factorial of a given number using FOR loop.
THEORY:
Factorial is an important function, which is used to find how many ways things can be
arranged or the ordered set of numbers. The factorial concept is used in many mathematical
concepts such as probability, permutations and combinations, sequences and series, etc. In
short, a factorial is a function that multiplies a number by every number below it till 1. For
example, the factorial of 3 represents the multiplication of numbers 3, 2, 1, i.e. 3! = 3 × 2 × 1
and is equal to 6.
A For Loop is a structure you use to execute a block of code a set number of times. When the
VI runs, the iteration count is evaluated, and then the code is executed.A For Loop can be
configured to conditionally stop code execution in addition to its iteration-based exit. In these
cases, the code will execute until the count terminal setting is reached or the condition is met
– whichever happens first.The structure of FOR loop in LabVIEW is shown below in Fig.4.1.
Fig:4.1 Structure of FOR loop
In FOR loop structure , N is the count and I is the iteration value. Initial value of I is zero.
PROCEDURE
Step 2: Click right on the front panel from the control palette selects numeric and then
selects control .
Step 3: Right click on the block diagram panel , select program , go to structures and select a
FOR loop.
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Step 4: Connect the numeric control in which the user input will be stored to the N. Right
click on the border of the FOR loop and select add shift register, borders are converted into
shift register.
Step 5: To initialize the shift register, from the function palette select numeric and then select
constant. Place this numeric with the shift register and set its value to 1.
Step 6: For the multiplication task place a multiply block, from the function
palette select numeric and then select multiply. At one of the two inputs of the multiply
block connect the right shift register, and the output of this block connect the right shift
register.
Step 7: On the other input of the multiply block we have to connect the incremented iteration
because the number of iterations start from 0 but we want the factorial from 1 onwards,
because the factorial will turn out to be zero otherwise. From the function palette select
numeric and then select increment.
Step 8: At the input of this increment block connect the iterative index of the for loop, and
connect the output of this increment block to the remaining input of the multiply block.
Step 9: At the right shift register click right and from the drop down select create and then
select indicator.
Step 10:Inputs are given in the front panel and the program is executed.
BLOCK DIAGRAM:
Block diagram of factorial of a number using FOR loop is given below in Fig.4.2.
Fig.4.2: Block diagram of Factorial of a number using FOR loop
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OUTPUT/FRONT PANEL:
The output of factorial of a number using FOR loop is shown below in Fig.4.3.
Fig:4.3: Output of factorial of a number using FOR loop
RESULT:
The factorial of a given number is using FOR loop is performed in LabVIEW.
VIVA QUESTIONS:
1. How mixed data types are combined and passed from one file or place to the other in
LabVIEW?
2. What is the initial value of iteration count?
3. What is subVI?
4. What is block diagram panel?
5. What is front panel?
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EXPERIMENT 5
DETERMINE SQUARE OF A GIVEN NUMBER
AIM:
To determine Square of a given number using LabVIEW.
THEORY:
The Square root VI computes the square root of the input value. If x is negative, the square root is
NaN unless x is complex. If x is a matrix, this function takes the matrix square root of x. The
connector pane displays the default data types for this polymorphic function. x can be a scalar
number, array or cluster of numbers and array of clusters of numbers. sqrt(x) is a double-precision,
floating-point number if x is an integer. If x is less than 0, sqrt(x) is not a number (NaN).
PROCEDURE:
Step 2: Right click on the block diagram window, select numeric, add numeric constant to
represent the input.
Step 3: Right click on the block diagram window, select numeric, add numeric constant to
represent the output. Change the control to indicator.
Step 3: Right Click on the block diagram window, select numeric, add the square root block.
Step 4: Using wiring operations required connections are given in the block diagram.
Step 5: Inputs are given in the front panel and the program is executed.
BLOCK DIAGRAM:
Block diagram to calculate square and square root of a number is shown below in fig 5.1.
Fig.5.1: To find square root of a number (additionally factorial and square of number is also
shown)
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OUTPUT/FRONT PANEL:
The output or the front panel window is shown below in fig 5.2.
Fig.5.2:Output of square of a given number
RESULT:
Square of a given number is determined using LabVIEW.
VIVA QUESTIONS:
1. What is the output of square root block if input is negative number?
2. What is the default data type for input for square root block?
3. Can square root block help in finding roots of a complex number?
4. What is the datatype for integer or floating-point number?
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EXPERIMENT 6
FACTORIAL OF A NUMBER USING WHILE LOOP
AIM :
To find factorial of a number using while Loop in LabVIEW.
THEORY:
Use shift registers when you want to pass values from previous iterations through a loop to
the next iteration. A shift register appears as a pair of terminals, shown as follows, directly
opposite each other on the vertical sides of the loop border. The terminal on the right side of
the loop contains an up arrow and stores data on the completion of an iteration. LabVIEW
transfers the data stored in the right terminal of the shift register to the left terminal. The loop
then uses the data from the left terminal as the initial values for the next iteration. This
process continues until all iterations of the loop execute. After the loop executes, the terminal
on the right side of the loop returns the last value stored in the shift register. A shift register
transfers any data type and automatically changes to the data type of the first object wired to
the shift register. The data you wire to the terminals of each shift register must be the same
type. If you have multiple operations that use previous iteration values within a loop, use
multiple shift registers to store the data values from those different processes in the structure,
as shown in the following block diagram in Fig 6.1 and 6.2.
PROCEDURE:
Step 2: Right click on the block diagram panel , select program , go to structures
and select a WHILE loop.
Step 3: Right click on the border of the WHILE loop and select add shift register,borders are
converted into shift register.
Step 4: Using wiring operations required connections are given in the block
diagram.
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BLOCK DIAGRAM :
Fig.6.1 Block diagram using For loop
Fig 6.2.Block diagram using while loop
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OUTPUT/FRONT PANEL:
The output or the front panel window view is shown below in fig 6.3.
Fig.6.3 output
RESULT:
Factorial of a number is determined using while loop in LabVIEW.
VIVA QUESTIONS:
1. What is the role of shift register in the while loop?
2. What is the default data type for factorial block?
3. How to find factorial of integer numbers?
4. Differentiate for loop and while loop.
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EXPERIMENT 7
SORTING EVEN NUMBERS USING WHILE LOOP IN AN
ARRAY
AIM:
To sort even numbers using WHILE loop in an array.
THEORY:
Loops are used for controlling the iteration and execution flow of programs. Charts display
the recent data and update periodically by maintaining a history of the past data.
While Loop
While Loop executes a subdiagram until a condition is met. The While Loop executes the
subdiagram until the conditional terminal, an input terminal, receives a specific Boolean
value. The default behavior and appearance of the conditional terminal is Continue If True.
When a conditional terminal is Continue If True, the While Loop executes its subdiagram
until the conditional terminal receives a FALSE value. To change the behavior and
appearance of the conditional terminal, right-click on the terminal and select Stop If True.
When a conditional terminal is Stop If True, the While Loop executes its subdiagram until the
conditional terminal receives a TRUE value. Because the VI checks the conditional terminal
at the end of each iteration, the While Loop always executes at least one time. The VI is
broken if the conditional terminal is not wired. Fig 7.1 shows example of while loop structure
Basic error handling can be performed using the conditional terminal of a While Loop. When
an error cluster s wired to the conditional terminal, only the TRUE or FALSE value of the
status parameter of the error cluster passes to the terminal. Also, the Stop If True and
Continue If True shortcut menu items change to Stop If Error and Continue while Error. The
iteration terminal (an output terminal) contains the number of completed iterations. The
iteration count always starts at zero. During the first iteration, the iteration terminal returns 0.
Fig.7.1. While Loop structure

• A While Loop executes a subdiagram until a condition is met.
• The While Loop is like a Do Loop or a Repeat-Until Loop in text-based
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programming languages.
• The While Loop always executes at least once.
• The For Loop differs from the While Loop in that the For Loop executes a set
number of times.
• A While Loop stops executing the subdiagram, only if the expected value at the
conditional terminal exists.
• In LabVIEW, the WHILE Loop is located on the Functions » Programming »
Structures palette.
• You also can place a For Loop on the block diagram, right-click the border of the
For Loop, and select Replace with While Loop from the shortcut menu to change a
For Loop to a While Loop.
• The While Loop contains two terminals, namely Conditional Terminal and Iteration
Terminal.
• The Conditional Terminal is used to control the execution of the loop, whereas the
Iteration Terminal is used to know the number of completed iterations.
PROCEDURE:
Step 2: Right click on the Block diagram panel →structures→ while loop
Step 3: Right click on the Block diagram panel (inside while loop) → array→ index array
Step 4: Right click on the index array (input side) →create →control
Step 5: Right click on the Block diagram panel →array →array size
Step 6: Right click on the Block diagram panel →numeric→ Quotient & Remainder
Step 7: Right click on the Block diagram panel → Comparison→ Equal to 0?
Step 8: Right click on the Block diagram panel →numeric→ numeric constant
Step 9: Right click on the Block diagram panel →numeric→ decrement
Step 10: Right click on the Block diagram panel →numeric→ numeric constant
Step 11: Right click on the Block diagram panel → Comparison→ Equal ?
Step 12: Using wiring operations required connections are made as given in the block
diagram inside loop.
Step 13: Make a connection to while loop from index array
Step 14: Right click step 13 connection (on loop) →Tunnel mode→ Indexing
Step 15: Right click step 14 connection (on loop) →Tunnel mode→Conditional
Step 16: Right click on the Block diagram panel →array→ sort 1D array
Step 17: Right click on the sort 1D array (input side) →create→ control [Even array]
Step 18: Right click on the sort 1D array (output side) →create→ control [Sorted array]
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diagram outside loop.
BLOCK DIAGRAM:
Fig 7.2 shows the block diagram of sorting even numbers using while loop. The array takes
the input values. Using indexing values are accessed, and checked for even or not. To check
for even number the element value is divided by two and resulting remainder if zero
considered as even. This data is stored in output array. Using sort function, array is sorted.
Fig7.2.Block diagram Sorting even Number in LabVIEW
OUTPUT/ FRONT PANEL :
Input
Output
Fig.7.3.Input and output of sorted even numbers
RESULT:
Fig 7.3 shows the input array and sorted array. Even numbers are sorted using while loop in
an array.
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VIVA QUESTIONS:
1. What are the different loops available in LabVIEW?
2. Distinguish between for and while loop.
3. What is loop iteration control?
4. What is Multitracing?
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EXPERIMENT 8
FINDING ARRAY MAXIMUM AND ARRAY MINIMUM
AIM:
To find the maximum and minimum variable from an array.
THEORY:
Arrays
• A group of homogeneous elements of a specific data type is known as an array.
• Arrays hold a sequence of data elements,usually of the same size and same data
type placed in contiguous memory locations.
• Individual elements are accessed by their position in the array.
• The position is given by an index, which is also called as subscript
• Some arrays are multi-dimensional, generally one -and two- dimensional arrays
are the most common.
• You can build arrays of numeric, boolean, path, string and cluster data types.
• You cannot create arrays of arrays
1D Array Controls, Indicators and Constants

• The index ranges from 0 to 3. The first element in the array is at index 0, the
second element is at index 1, etc..
• In an array the element selected in the index display always refer to the element
shown in the upper left corner of the element display.
• The element (9) at index 0 is not shown in the array, because index 1 is selected in
the index display.
• Steps for creating an array constant
• Select an array constant from Functions » Programming » Arrays. Array shell
appears with an index display on the left, an empty element display on the right.
• Place a constant in the array shell.
• The array shell automatically resizes to accommodate the object place in the array
shell.
• Alternative method is to copy an existing array on the front panel to the block
diagram to create a constant of same data type.
Initializing Arrays
• When an array is initialized, define the number of elements in each dimension and
contents of each element.
• An uninitialized array has a dimension but no elements.
• An uninitialized array control with all the elements are dimmed indicating that the
array is uninitialized.
Inserting Elements within Arrays

– One can insert an element into a 1D array and a row or column into a 2D array.
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• To add an element 1D, right click the array on the front panel and select Data
Operation
» Insert Element Before.
• To add a row or column to a 2D array, right click the array on the front panel and select
Data Operations » Insert Row Before or Insert Column Before.
• One can insert elements, rows, column into arrays using the Insert Into Array function.
• Place an Insert Into Array function on the block diagram.
• The index input specifies the element, row, column where to insert the element or
array with 0 being the first.
• Elements are added before the value wire to index.
2D Arrays
• A 2D arrays stores elements in a grid.
• It requires a column index and a row index to locate an element both of which are
zero- based.
• To create a 2D array on the front panel, right click the index display of the array and
select Add Dimension from the shortcut menu.
Deleting Elements within Arrays

• One can delete an element within a 1D array and a row or column within a 2D.
• To delete an element in a 1D array, right-click the array element on the front panel
and select Data Operations » Delete Element.
• To delete a row or column in a 2D array, right-click the array row or column on the
front panel and select Data Operations » Delete Row or Delete Column
• Can delete elements, rows, columns and pages within array using the Delete From
Array function.
Replacing Elements within Arrays

• Place the Replace Array Subset function on the block diagram
• Wire an array of any dimension to the n-dimension array input of the Replace
• Array Subset function.
• The function automatically resizes based on the dimensions of the array.
• The index input specifies which element, row, column to replace.
• The new element/subarray input specifies the value you want to replace an element.
• Resize the Replace Array Subset function to replace another element, row, column
within an array
• Run the VI
Deleting Elements within Arrays

• One can delete an element within a 1D array and a row or column within a 2D.
• To delete an element in a 1D array, right-click the array element on the front panel and
select Data Operations » Delete Element.
• To delete a row or column in a 2D array, right-click the array row or column on the front
panel and select Data Operations » Delete Row or Delete Column
• Can delete elements, rows, columns and pages within array using the Delete From Array
function.
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PROCEDURE:
Step 2: Right click on the Block diagram panel →array→ max & min.
Step 3: Right click on the max & min (input side) →create →control.
Step 4: Create four numeric indicators in the front panel for maximum variable, index,
minimum variable, and index by right clicking on output side of max & min.
Step 5: Using wiring operations required connections are made as given in the block diagram.
BLOCK DIAGRAM:
Fig 8.1 shows the block diagram of array maximum and minimum in LabVIEW. Array input
is taken and using the array max and min function values are indicated using the indicators.
Fig 8.1: Block diagram of array maximum and minimum in LabVIEW
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OUTPUT /FRONT PANEL :
Input
Output
Fig 8.2: Input and output of array maximum and minimum
RESULT:
Fig 8.2 shows the maximum and minimum of given input array. The array maximum and
minimum is determined using LabVIEW and also its index.
VIVA QUESTIONS:
1. What is array? How it can be assigned?
2. Distinguish Array and Clusters.
3. How do graphs are made in VI?
4. Mention the difference between graph and charts.
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DEMONSTRATION EXPERIMENTS
EXPERIMENT 9
BUILD A VI THAT SIMULATES A HEATING AND COOLING
SYSTEM.THE SYSTEM MUST BE ABLE TO BE
CONTROLLED MANUALLY OR AUTOMATICALLY.
AIM:
To build a vi that simulates a heating and cooling system.The system must be able to be
controlled manually or automatically.
The VI’s specifications are listed below.
• Must be able to be controlled automatically or manually

• In manual mode, the heater and air conditioning (AC) can be switched on/off by the
user
• In automatic mode, the heater and AC turn on/off based on the following conditions:
o The air conditioner is turned on when the temperature is above 80°F
o The heater is turned on when the temperature is below 60°F
o The heater and the air conditioner are turned off when the temperature is between
60°F and 80°F.
THEORY:
Structures are process control elements, such as while loops and for loops. The structure to
be used in this experiment is the case structure which is essentially multiple if-statements. A
case structure contains multiple subdiagrams (or cases), and a case will be executed
depending on the input to the case structure
PROCEDURE:
1. In the front panel, drag and drop three Round LEDs and three Slide Switches by going to
the Controls palette > Modern tab > Boolean. Each round LED and each slide switch will
represent the AC, heater, and manual mode. The round LEDs will indicate if the item is
on, and the slide switches will toggle the items on/off.
2. Rename the LEDs and their corresponding switches "Manual," "AC," and "Heater" to
make building the system clearer. This can be done by using the editing text tool in the
Tools palette.
3. Drag and drop a thermometer into the front panel (Controls palette > Modern tab >
Numeric
> Thermometer).
4. In the back panel, right click the thermometer terminal and select Change to Control, and
observe how the arrow switches from the left side to the right side. This makes the
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thermometer a control that will give an input to the program, which in this case is
temperature.
5. In the back panel, insert a case structure to control the manual and automatic operation of
the heating and cooling system (Functions palette > Structures > Case Structure). To place
the case structure, click once to place one corner of the case structure, and once more to
place the other corner of the case structure.
6. Wire the slide switch designated as Manual to the case selector on the case structure. This
should automatically change the selector label values to True and False, if they were not
already, because the slide switch is a Boolean data type. The true value corresponds to
manual mode being on (where the user can directly toggle the heater and AC), while the
false value corresponds to manual mode being off (where the heater and AC are
automatically toggled by the system).
7. Because the temperature of the room is input into the system only when the system is not
in manual mode (the false case), the thermometer terminal should be moved into the false
subdiagram.
8. In the true sub-diagram, wire the AC and heater switches directly to their corresponding
LEDs. This allows the switches to directly toggle their corresponding LEDs.
9. Staying in the true sub diagram, insert a True Constant (Functions palette > Programming
tab > Boolean > True Constant). Wire the true constant to the manual LED to turn the
manual LED on and indicate that the system is in manual mode.
10. In the false sub diagram, insert two Numeric Constants (Functions palette >
Programming > Numeric > Numeric Constant), one Greater? function and one Less?
function (Functions palette > Programming > Comparison). These will be used to build the
program for the heating and cooling system in automatic mode.
11. The less and greater functions compare what is wired to the upper input terminal to
what is wired to the lower input terminal. Wire the thermometer to the upper input
terminals of the less and greater functions. Set a numeric constant to 60 and the other to
80. Wire the
60 numeric constant to the lower input terminal of the less function and the 80 numeric
constant to the lower input terminal of the greater function. Wire the output terminal of the
greater function to the AC LED and wire the output of the less function to the heater LED.
12. In the false sub diagram, Insert a False Constant (Functions palette > Programming >
Boolean > False Constant) and wire it to the manual LED. This is to turn off the manual
LED and indicate that the system is in automatic mode.
13. The system is now complete. Click the continuously run button to control and test the
VI. If the continuously run button is faded out, that means the system is wired completely.
When successfully running the system, the gridlines in the background of the front panel
should disappear. Click the switches and thermometer on the front panel to test the system.
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BLOCK DIAGRAM:
Fig 9.1 and 9.2 shows the block diagram for true case and false case respectively.
Fig .9.1 Block Diagram – For True Case
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Fig 9.2. Block Diagram – For False Case
OUTPUT/FRONT PANEL:
The output for VI simulating a heating and cooling system is shown in Fig 9.3.
Fig 9.3.output
RESULT:
A virtual instrument that simulates a heating and cooling system is built.
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VIVA QUESTIONS:
1. Design a temperature-controlled kettle for heating water and freezing water.
2. What are the temperature indicators in LabView?
3. What are True and False constant in LabView?
4. What is a if Block in LabView ?
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EXPERIMENT 10
BUILD A VIRTUAL INSTRUMENT THAT SIMULATES
BASIC CALCULATOR USING FORMULA MODE
AIM :
To build a Virtual Instrument that simulates basic Calculator Using Formula Mode.
THEORY:
The Formula Node in LabVIEW software is a convenient, text-based node you can use to
perform complicated mathematical operations on a block diagram using the C- syntax
structure. It is most useful for equations that have many variables or are otherwise
complicated. The text- based code simplifies the block diagram and increases its readability.
Furthermore, you can copy and paste existing code directly into the Formula Node rather than
recreating it graphically. The Formula Node is available in all development versions of
LabVIEW and does not require an additional toolkit or add-on.
PROCEDURE:
The Formula Node in LabVIEW software is a convenient, text-based node you can use to
perform complicated mathematical operations on a block diagram using the C- syntax
structure. It is most useful for equations that have many variables or are otherwise
complicated.
The text-based code simplifies the block diagram and increases its readability. Furthermore,
you can copy and paste existing code directly into the Formula Node rather than recreating it
graphically. The Formula Node is available in all development versions of LabVIEW and
does not require an additional toolkit or
add-on.
This tutorial is useful for familiarizing yourself with the Formula Node. Follow the steps to
create a simple structure to compute different formulas depending on input values. Then,
compare the simplicity of your block diagram using a formula node to its counterpart using
graphical programming. The Formula Node is a tool that allows the benefits of text-based
code within the easy-to-use graphical LabVIEW architecture.
1. Selecting File»New VI to open a blank VI.

2. Place a Formula Node on the block diagram.
1. Right-click on the diagram and navigate
to Programming»Structures»Formula Node.
2. Left-click to select the Formula Node.
3. Place the Formula Node on the block diagram by left-clicking, dragging, and
releasing the mouse.
3. Right-click the border of the Formula Node and select Add Input from the shortcut
menu.
4. Label the input variable x.
5. Repeat steps 3 and 4 to add another input and label it y as in fig 10.1.
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Fig.10.1 add input
5. Right-click the border of the Formula Node and select Add Output from the shortcut
menu as in fig 10.2.
Fig.10.2. add output
6. Label the output z1.

7. Repeat step 5 to create another output, and label this output z2 as in Fig 10.3.
Fig.10.3 create output and label

Note: It is considered good programming practice to keep the inputs on the left border and
the outputs on the right border of the Formula Node. This helps you follow the data flow in
your VI and keep your code organized.
8. Enter the expressions below in the Formula Node.

▪ Make sure that you complete each command with a semicolon. Notice,
however, that the if-statement does not require a semicolon on the first line.
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if (x*y>0)
z1 = 3*x**2 - 2*y**3;
else z1 = 0;
z2 = sinh(z1);
9. Create controls and indicators for the inputs and outputs.

1. Right-click on each input and select Create»Control from the shortcut menu.
2. Right-click on each output and select Create»Indicator from the shortcut
menu.
Note that you can change the control and indicator names to their respective variable by
editing their labels as in Fig 10.4.
Fig.10.4 .Creating indicators and control
10. Place a While Loop around the Formula Node and the controls.
1. Right-click on the diagram and navigate to Programming»Structures»While
Loop.
2. Left-click to select the While Loop.
3. Place the While Loop on the block diagram by left-clicking, dragging, and
releasing the mouse.
4. Right-click the Stop icon and Create Control. Label it as Stop.
11. Add a Wait (ms) function inside of the While Loop to conserve memory usage, and
wire in 100 milliseconds as a wait time. Your block diagram should appear as follows
in Fig 10.5.
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Fig.10.5 while loop
11. Click the Run button to run the VI. Change the values of the input controls to
12. see how the outputs change.
In this case, the Formula Node helps minimize the space required on the block diagram.
Accomplishing the same task without the use of a Formula Node requires the following code
as in Fig 10.6.
Fig.10.6 Block diagram without formula node

BLOCK DIAGRAM :
The block diagram with formula node is shown in Fig 10.7.
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Fig 10.6 Block diagram
OUTPUT/FRONT PANEL:
The front panel view is shown in following fig 10.7.
Fig 10.7 output
RESULT:
A virtual instrument that simulates a basic calculator is built.
VIVA QUESTIONS:
1. What is the formula node?
2. Use formula node for finding area of circle, circumference of circle and arc of a circle
3. What is the advantage of using formula node?
4. Is formula node text based or block (graphical) based?
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EXPERIMENT 11
WATER LEVEL INDICATOR
AIM:
To create and demonstrate water level indicator.
Description:
If No water is in tank then motor must be ON.
If water level crosses 8 then Motor must be OFF.
THEORY:
The water level indicator circuits are used in factories, chemical plants, and electrical substations and
in other liquid storage systems. There are many possible uses for this simple system, examples include
monitoring a sump pit (to control pump activation), rainfall detection, and leakage detection.
Electronic water level circuits have the capability of alerting if there is a water leak somewhere in the
factory. When the water level is too high or too low or exceeds the higher limit, it can detect the water
level easily by hearing an alarm sound or from different colors of a light bulb. We can also measure
the fuel level in motor vehicles and the liquid level containers which are huge in the companies.
The circuit is designed to indicate three levels of water stored in the tank: empty, half and full but not
overflowing. When there is no water in the tank, all the LEDs are off as an indication that the tank is
completely empty. Then, manually control the knob to turn ON LED. When water level increases and
touches the maximum limit, the OFF LED will glow indicating that there is water within the tank. As
the water level continues to rise and reaches half the tank, ON LED will still glow indicating tank is
filling.
The important LabVIEW components or tools, required to design a water level detector, list
of these components below:
• Tank
• Round Knob
• Upper Level Indicator
• Lower Level Indicator
• Numerical Indicator
• Graph to observe the results
Vertical pointer is used to control the level of the water in the tank. Upper level indicator shows
when the tank is about to completely fill. Lower level indicator shows indication by turning
"ON" the LED when the level of the water in the tank is too low and we need to fill it. Graphs
shows the graphical visualization as the vertical pointer moves up ow down.
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PROCEDURE:
Step 2: Right click on the front panel →numeric→ knob.
Step 3: Right click on the knob →Properties→ scale→ Set maximum 10 and minimum 0
Step 4: Right click on the front panel →Boolean→ Round LED (Name it ON).
Step 5: Right click on the front panel →Boolean→ Round LED (Name it OFF).
Step 6: Right click on the front panel →numeric→ Numeric control
Step 7: Right click on the front panel →numeric→ Tank
Step 8: Right click on the Block diagram panel →comparison→ greater or equal?
Step 9: Right click on the Block diagram panel →comparison→ less?
Step 10: Right click on the Block diagram panel → numeric→ Numeric constant (set 8)
[twice]
diagram. Step 5: Execute- give inputs in the front panel by rotating knob and observe tank
filling and
switches ON & OFF.
BLOCK DIAGRAM:
Fig 11.1 shows the block diagram water level indicator in LabVIEW. A round control knob is
used to switch on the motor and off. Numeric indicator display water level in tank.
Fig.11.1 block diagram
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Fig 11.2 (a): Motor is on- (no water) Fig 11.2 (b): Motor is on- (water in tank)
Fig 11.2(c). Motor is off- (more than threshold)
RESULT:
Fig 11.2 (a), (b) and (c) shows Motor on with no water and filling and reached upper limit
and off. A VI that indicates water level is built.
VIVA QUESTIONS:
1. How to create vertical indicators?
2. Is it possible to change the settings of LED?
3. Is it possible to implement this using While loop?
4. Comparator functions are present in which palette?
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EXPERIMENT 12
CALCULATION OF AREA AND PERIMETER OF CIRCLE
AIM:
To calculate area and perimeter of a circle.
Description: Area of circle = 𝜋𝑟2
Perimeter/circumference of circle = 2𝜋𝑟
r- radius of circle
if r>10 then indicate to reduce radius.
THEORY:
The area shows the space inside an object having two dimensions. Where as, circumference is
the parameter which shows the boundary of the object. Area is usually measured in m² and
circumference is measured in m according to their System International (SI) units. In this area
and area and circumference calculation of circle is achieved. In this LabVIEW program,
which will take radius as an input and calculates the area and circumference of circle, You
can also select the maximum limit of the radius. When the radius approaches its maximum
limit an LED will glow showing the notification reduce the radius.
PROCEDURE:
Step 2: Right click on the front panel → numeric→ Numeric control
Step 3: Right click on the front panel → numeric→ Numeric indicator [Name Area]
Step 4: Right click on the front panel → numeric→ Numeric indicator [Name Circumference]
Step 5: Right click on the front panel → Boolean→ Square LED
Step 6: Right click on the Block diagram panel →Numeric→ multiply (thrice)
Step 7: Right click on the Block diagram panel →structures→ while loop
Step 8: Right click on the Block diagram panel →numeric→ numeric constant [set value 10]
Step 9: Right click on the Block diagram panel →numeric→ numeric constant [set value 2]
Step 10: Right click on the Block diagram panel →numeric→ math constants→pi
Step 11: Using wiring operations required connections are made as given in the block diagram
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BLOCK DIAGRAM:
Fig 12.1 shows the block diagram of area and circumference of circle in LabVIEW. Area
and circumference is calculated using formulas. An upper limit to radius is also kept here.
Fig.12.1 block diargram
Fig 12.2 (a): Radius is < 10- (Reduce radius is OFF) Fig 12.2 (b): Radius is > 10- (Reduce
radius is ON)
RESULT:
Fig 12.2 (a) shows area and circumference of circle and indication of Radius is < 10-
(Reduce radius is OFF). Fig 12.2 (b) shows Radius is > 10- (Reduce radius is ON). A VI
which calculates area and perimeter of a circle is created and demonstrated.
VIVA QUESTIONS:
1. What are the units of area and perimeter?
2. Where to select pi function?
3. What is the difference between continuous run and run?
4.How to indicate broken wire in LabVIEW?
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Dept Of ECE 50
Simulation
Experiments using
PSpice
Simulation of Electronic Circuits using Multisim, Pspice and LabVIEW
LIST OF EXPERIMENTS COVERED:

1. Voltage Regulator using Zener diode
2. Darlington Emitter follower without

bootstrapping
3. Darlington Emitter follower with bootstrapping
4. Hartley Oscillator
5. Colpitts Oscillator
6. Astable Multivibrator
7. Monostable Multivibrator
8. Low Pass Filter
9. Digital to Analog Converter (DAC)

10. Basic Logic Gates (AND & OR)
11. Mod – 8 Counter

12. Square wave to Sine wave generator
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Demo Expt. #1 – Voltage Regulator using Zener diode
Fig.1a
Output:
Fig 1b
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Demo Expt. #2 – Darlington Emitter follower without

bootstrapping
Fig 2.a
Output
Fig 2.b
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Demo Expt. #3 – Darlington Emitter follower with bootstrapping
Fig 3.a
Output
Fig 3.b
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Demo Expt. #4 – Hartley Oscillator
Fig 4.a
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Output
Fig 4.b
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Demo Expt. #5 – Colpitts Oscillator
Fig 5.a
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Output
Fig5.b
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Demo Expt. #6 – Astable Multivibrator
Fig 6.a
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Output
Fig 6.b
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Demo Expt. #7 – Monostable Multivibrator
Fig 7.a
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Output
Fig 7.b
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Demo Expt. #8 – Low Pass Filter
Fig 8.a
Output
Fig 8.b
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Demo Expt. #9 – Digital to Analog Converter (DAC)
Fig 9.a
Output
Fig 9.b
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Demo Expt. #10 – Basic Gates (AND & OR)
Fig 10a
Output
Fig 10.b
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Demo Expt. #11 – Mod 8 Counter
Fig 11.a
Output
Fig 11.b
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Demo Expt. #12 – Square Wave to Sine Wave Generator
Fig 12.a
Output
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Fig
12.b
Dept of ECE 19

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Simulation of Electronic Circuits using Multisim, PSpice and LabVIEW

COURSE OUTCOMES (COURSE SKILL SET):

1. Understand the circuit schematic and its working.

2. Study the characteristics of different electronic devices.

4. Compute the parameters from the characteristics of active devices.

Sl.No Experiments using Pspice/MultiSIM software

COMPONENTS REQUIRED: 1N4007G Diode, Resistors, Function generator,

Following are few types of clipper circuits

1. Single ended (positive or negative ) and double ended clipping

2. Series or parallel based on the construction. Peak detection is possible by connecting a

The series resistance is calculated such that R √ √ 10K

Fig. 1: Positive shunt clipper

If the output to be clipped above 2 V, Vo (max) = +2 V

If the output to be clipped below  2 Volts.

Fig. 2: Negative shunt Clipper

2. Vo min = 2 V Vo min = VR2 – V; VR2 = Vo min + V = 2 + 0.6; VR2 = 2.6 V

Fig.3: Double ended clipper with independent voltage levels

If we need to generate a symmetrical clipping circuit with clipping voltage

V0 = ± 4 Volts, Vo max = VR1 + V = 4 V;

VR1 = 4 – 0.6 = 3.4 V

Vo min = V  VR2= - 4 V,

VR2 = 4  0.6 = 3.4 V

Fig.4: Double ended clipper with symmetrical voltage levels

5. Connections are made as shown in the circuit diagram.

COMPONENTS REQUIRED: 1N4007G Diode, Resistors, capacitors, Function

Fig. 1: Positive clamper

ie., Vo,max= – 3V Vdc = Vo,max + V, Vdc = – 3 + 0.6 = – 2.4V

Fig. 2: Negative clamper

Working of Centre-Tap Full Wave Rectifier

COMPONENTS REQUIRED: BZB84-B10 zener diode, Potentiometer, dc power,

Zener Diode as Voltage Regulator:

Basically, there are two type of regulations such as:

COPONENTS REQUIRED: 2N2222A, DC Power, AC Power, Potentiometer,

RESULT: Realization of BJT Darlington Emitter follower without bootstrapping to

COMPONENTS REQUIRED: 2N2222A, DC Power, AC Power, Potentiometer,

CROSS OVER DISTORTION.

COMPONENTS REQUIRED: BC547BP, Resistors, Capacitors

Given Oscillation frequency f =1 MHz

Use L = 100 µH, For this value of L, f = 1.04 MHz

Fig 1: Colpitts Oscillator

Fig 2: Hartley Oscillator

COMPONENTS REQUIRED: NPN transistor, resistors, Capacitors, HC-

COMPONENTS REQUIRED: Transistor 2N222A, DC power sources and Ground

Input Resistance, ri = ∆VBE /∆IB (μA) at Constant VCE

Output Résistance, ro = ∆VCE /∆IC at Constant IB (μA)

Fig.1 Input Characteristics

Fig.2 Output characteristics

RESULT: Simulation of Input and Output characteristics of BJT Common emitter

COMPONENTS REQUIRED: MOSFET 2N700, DC power sources and Ground

N Channel MOSFET Characteristics

There are two types of characteristics

Fig.2: MOSFET Circuit diagram

COMPONENTS REQUIRED: SCR 2N6397, BRIDGE MDA920A4, UJT-

COMPONENTS REQUIRED: Voltage Regulator LM7805CT, BRIDGE 3N246,

Fig.1Regulated Power supply.

1. To apply operational amplifiers in linear and nonlinear application.

COURSE OUTCOMES (COURSE SKILL SET):

After studying this course, the student will be able to:

ASSESSMENT DETAILS (BOTH CIE AND SEE):

Vin = I1R1 and Vo = - IfR2

Av= - - IfRf / I1R1