ECE 1371 ANALOG ELECTRONICS II

Recent Trends in CMOS Low Noise Ampliers

Abstract - This paper presents an overview and comparison of CMOS low noise amplier (LNA) architectures. A brief review of noise gure and linearity is presented to give the reader some background into typical performance measures of LNAs. A traditional radio frequency (RF) receiver architecture is presented and LNA performance is related to overall receiver performance. Recent CMOS LNA performance comparisons are made and a representative LNA architecture is reviewed. The two highest performance CMOS LNAs to date (introduced at ISSCC 2001) in terms of noise gure and linearity are reviewed. Finally, a predicted low-voltage CMOS architecture based on an innovative bipolar architecture is presented.

I. INTRODUCTION

Low Noise Ampliers (LNA) are the backbone of radio frequency (RF) communications receivers. Their specications dene the overall noise performance and can have deleterious effects on the linearity of the RF receiver. However, consumer demands to increase the frequencies at which RF systems operate are straining the capabilities of existing architectures. CMOS LNAs are recently drawing intense attention because users want a cheaper, fully integrated solution. Bipolar solutions generally offer higher performance, but cannot be fully integrated with the receivers baseband digital signal processing which is inherently realized in CMOS technology. This paper gives an introduction to the fundamental concepts of LNAs and their relevance to modern wireless communications receivers. Section II introduces two fundamental concepts in LNA performance measure, noise gure and linearity. Section III will show how these two performance measures affect the overall specications of a RF receiver. From there, some traditional CMOS architectures are described in Section IV. The two highest performance CMOS LNAs to date (reported at ISSCC 2001) are described in Section V. Finally, a prediction of a future CMOS LNA design is presented in Section VI.

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II. TWO FUNDAMENTAL PERFORMANCE MEASURES OF LOW NOISE AMPLIFIERS

Noise Factor and Noise Figure The noise factor (F) of a two port stage is simply dened as:
SN R IN F = -----------------------SN R OUT (1)

where SNRIN and SNROUT are dened as the signal-to-noise ratios at the input and the output of the stage, respectively. Thus the noise gure is a measure of the degradation of the SNR through a stage. A stage with better noise performance has a lower noise factor (the minimum being 1).
F1 G1 FCAS G1G2 F2 G2

Figure 1: Noise factor of a cascaded system

For a cascaded system of two stages as shown in Fig. 1,

where G1 is the gain of the rst stage and F1, F2, FCAS are the noise factors of the rst stage, second stage and the cascade of the two stages, respectively. Hence, the noise factor of the entire cascaded system depends only on the noise gure of the rst stage, given that the gain G1 of the rst stage is large enough to make the second term of equation (2) negligible. Because LNAs are the rst gain stage in a RF receiver, they are required to have moderate gains and low noise factors. Finally, the noise gure (NF) of a system is simply the noise factor (F) measured in Decibels:
NF = 10 log ( F ) in dB
(3)

Noise gure is used instead of noise factor to characterize LNAs in literature and will be used through the remainder of this paper.

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Linearity - Third-order intercept point (IP3) The IP3 of stage is a measure of its linearity. While many analog and RF circuits are approximated with a linear model to obtain their response to small signals, non-linearities often lead to harmful phenomena. For this discussion, we assume that an input of x(t) to a system leads to the linear and nonlinear output:
2 3 y ( t ) = 1 x ( t ) + 2 x ( t ) + 3 x ( t ) (4)

We nd that if x(t) consists of sinusoids of two frequencies 1 and 2, then output contains terms at the frequencies n1 +/- m2. These terms are called intermodulation (IM) products are present due to the nonlinearity of the system described in (4). The order of an intermodulation product is (n+m). Of particular interest are the third-order IM products at 21-2 and 22-1, illustrated in Fig. 2. If the difference between 1 and 2 is small, the components at 21-2 and 22-1 will appear very close to the original signals. These unwanted signals may cause errors in the detection of the wanted signals.

1 2

1 2 21-2 22-1

Figure 2 Third-order intermodulation in a nonlinear system

A measure the relative strength of the unwanted signals at 21-2 and 22-1 is the thirdorder intercept point (IP3). Two equal power tones at frequencies 1 and 2 are applied to a system and the power of the third-order IM products are measured. A typical plot of output vs. input power in dBm [= 10log(x/0.001)] is shown in Fig. 3.

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Pout (dBm) OIP3 Third-Order Intercept Point

3 IIP3 Pin (dBm)

Figure 3 Growth of Output Components in an intermodulation test

The top line is a plot of the power of the linear term of equation (4) and the bottom line is a plot of the power of the third-order IM products. It can be shown that the power of the third order IM products increases with a slope of three relative to the slope of the linear gain line. The IP3 is the point at which the two lines intersect. A standard measure in RF circuits is the IP3 referred to the input power called the input-referred IIP3 (or IIP3). As inferred from Fig. 3, higher values of IIP3 mean lower third-order IM products for a given input power. Thus, the higher the IIP3 of LNA, the better its linearity.

III. A MODERN COMMUNICATION RECEIVER

In this section, a typical communication receiver architecture is presented. The performance measure of the entire receiver is also related to the performance of the LNA. Fig. 4 shows the basic architecture used in many RF receivers. The RF signal is detected by the antenna and put through a band pre-select lter with unity nominal gain in the band of interest. The band pre-select lter usually has low selectivity (wide passband) because its passband is centered at such high frequencies. The LNA is the rst gain stage of the receiver, and may or may not be tuned to a specic passband. Image reject ltering may be in the signal path before a mixer brings down the RF signal to the intermediate frequency (IF) for further signal processing.
Antenna Band pre-select lter

LNA

Image reject lter

Mixer

RF

LO

IF

Figure 4 A Typical Wireless Receiver

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From equation (2), it is seen that the LNA is responsible for providing the rst gain in the receiver while itself contributing as little noise as possible. Although the mixer tends to dene the linearity of a given receiver, an exceptional IIP3 in the LNA allows the linearity of the mixer to be relaxed considerably. This can be greatly advantageous in some architectures. The LNA impedances should be matched closely to 50 at both its input and output for maximum power transfer at radio frequencies. LNA input and output matching is also essential because RF lter responses are heavily dependent on matching conditions. Finally, the LNA must have good reverse isolation (signal path from its output to input) so that the LO signal at the output is not permitted to traverse backwards through the LNA into the antenna (a phenomenon known as LO leakage).

IV. TRADITIONAL CMOS LNAS

The term traditional is a misnomer when it comes to CMOS LNAs. As late as 1996, only four published papers on CMOS LNAs existed in literature [4]. In fact, CMOS LNA architectures have not changed drastically since the rst published CMOS LNA because most advancements were accomplished during the bipolar age of RF circuits. However, some interesting design styles that optimized noise gure and/or linearity at moderate power consumptions have dominated over the last ve years. A plot of recent trends in CMOS LNA achievements is shown in Fig. 5. The solid line in each graph shows the IIP3/power and NF/power trade-off. In general, power can be exchanged for lower NF and higher IIP3.

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20

(3)
15

(6)
10

LNA IIP3 (dBm)

(2)
5

IIP3 vs. Power in Traditional CMOS LNA (10)

(8) (11) (4)

(12)

(7) (1)

(9)

(5)

(1) Leroux 2001, CMOS @ 1.23GHz [1] (2) Ding 2001, 0.35um CMOS @ 900MHz [2] (3) Ding 2001, 0.35um CMOS @ 900MHz [2] (4) Janssens 1998, 0.5um CMOS @ 900MHz [3] (5) Shaeffer 1997, 0.6um CMOS @ 1.5GHz [4] (6) Rodgers 1999, UTSi CMOS @ 2.0GHz [5] (7) Shahani 1997, 0.35um CMOS @ 1.6GHz [6] (8) Floyd 1999, 0.8um CMOS @ 900MHz [7] (9) Zhou 1998, 0.6um CMOS @ 900MHz [8] (10) Kim 1998, 0.8um CMOS @ 1.9GHz [9] (11) Karanicolas 1996, 0.5um CMOS @ 900MHz [10] (12) Huang 1999, 0.25um CMOS @ 900MHz [11]

10

15

10

15

20 25 30 35 40 45 LNA Power Consumption (referred to singleended) (mW)

50

55

(7) (5)
3.5

(4) (9) (3) (2)

3 LNA Noise Figure (dB)

NF vs. Power in Traditional (10) CMOS LNA

2.5

(11) (12)
2

(6)

1.5

(8) (1)

0.5

10

15

20 25 30 35 40 45 LNA Power Consumption (referred to singleended) (mW)

50

55

Figure 5 Trends in Noise gure and IIP3 in recent CMOS LNAs

Designs 1 and 3 are state-of-the-art representatives of optimum noise gure and linearity, respectively. These designs will be discussed in the next section. Design 11 (Karanicolas [10]) is a representative high performance design, reporting the lowest noise gure and highest IIP3 per unit power until this year. Other designs (12, 8, 6) give better performance but with at least 50% more power consumption. The basic problem with using CMOS for LNAs is its inherently low transconductance and hence small gain. A typical CMOS LNA suffers from not providing enough single stage gain to make the second term in equation (2) negligible. Thus, CMOS LNAs usually trade power for noise gure by increasing bias currents. Karanicolas, however, uses an intelligent current-reuse technique to effectively double the

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transconductance of a single stage without increasing the bias current. Fig. 6 shows a simplied schematic of design 11. Transistors M1 and M2 are essentially a digital inverter biased for large gain by the negative feedback loop. The key to this design is that given the same bias current, the effective transconductance of this LNA is gm1 + gm2 versus simply gm1 in the case that transistor M2 were omitted.

M2 Vin M1 M3 Vout

+ -

Vref

Figure 6 Simplied current-reuse LNA schematic [10]

The design was optimized for linearity (maximum IIP3) by choosing Vref so that the output obtains the maximum swing without clipping. The actual design uses two of these identical stages in cascade for better reverse isolation (to block signals from the output from leaking back to the input). A major drawback of this design is its inherently high input and output impedances, requiring it to have external matching networks. This obstacle precludes the use of this design in fully integrated applications.

V. STATE-OF-THE-ART CMOS LNAS

Lowest noise gure to date Design 1 in Fig. 5 has the lowest reported noise gure to date. Lerouxs design has achieved this while also consuming a fraction of the power compared with other designs. It achieves input and output matching on-chip and includes the effects of ESD protection diodes, making it fully integratable.

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Fig. 7 shows the simplied schematic of the design [1]. To maximize gain and reverse isolation while conserving power, a cascode topology is used. Furthermore, degradation of linearity is prevented because only a single stage is employed. The cascode conguration minimizes the Miller effect, signicantly lowering the input capacitance seen at the gate of M1 and enhancing stability. The use of a load inductor L2 permits large gains with no DC voltage drop, a necessity for low-voltage design (1.5V). The input of LNA is protected from ESD by two reverse-biased diodes D1 and D2.

Rs L2 Vcasc D1 Vin D2

M2

C1 Vout

Lg

M1 C2 Ls

Figure 7 Simplied LNA schematic with ESD protection

The input and output impedances are matched to 50 by using on-chip impedence transformations [12]. The input matching (to 50 ) is accomplished with on-chip inductors Lg, Ls and transistor M1. The input impedence at high frequencies is:
g m1 1 Z in = s ( L s + L g ) + -------------- + ----------- L s sC gs 1 C gs 1
(5)

which can be set to a real impedance of 50 at resonance (@1.23 GHz for this application) with proper component selection. The output impedence match is achieved by the capacitive divider of C1 and C2 and the load inductor L2. At resonance, the impedence seen at Vout is 50 , while the impedence seen at the drain of M2 is 500 . Thus, a high gain is attained even under matched conditions. The noise gure of this design is minimized by careful device sizing and layout. The large gain of the single stage minimizes the last term in equation (2). As shown in [1],[13], intricate

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second order noise effects which are beyond the scope of this paper are taken into account to minimize the noise gure. This design is highly attractive because it is fully integrated and is the rst published design (to the authors knowledge) to incorporate ESD protection making it immediately viable for commercial use.

Highest IIP3 to date Design 3 reports the highest linearity in a LNA to date. Ding [2] achieves IIP3 maximization by introducing an architectural innovation. The placement of two LNAs in parallel allows the third-order IM products to be effectively cancelled. The drawback of this design is a doubling of power consumption due to the dual-LNA architecture. The basic innovation in this LNA is the cancellation of the third-order harmonics. Omitting the second term (because the second-order harmonics usually fall out band) of equation (4) gives:
2 y ( x ) = Ax 1 + 2 x
(6)

If an auxiliary signal path with times the signal gain is also passed through an identical system, then the third harmonic is cancelled by subtracting 1/3 times the auxiliary output from the primary output [2]. The procedure is shown below:
2 y main ( x ) = Ax 1 + 2 x 2 2 y aux ( x ) = Ax 1 + 2 x 1 y ( x ) = y main ( x ) ----- y aux ( x ) 3 1 = A 1 ----- x 2
(7)

The third harmonic caused by the third-order term is completely cancelled theoretically. However, nonlinearity cancellation is limited in practice by device mismatches which are on the order

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of 1%. The auxiliary LNA consumes additional power and decreases the gain of the main LNA by 1/2 as shown by equation (7).

L2

L2

Vout Vcasc Vcasc Vcasc Vcasc

Vin (main)
-

Lg Ls Ls

Lg

Lg Ls Ls

Lg

Vin (auxiliary)

Figure 8 Simplied high linearity LNA schematic

Fig. 8 shows a simplied schematic of the design [2]. Each LNA is implemented differentially with a telescopic cascode inductor-degenerated architecture. This type of CMOS LNA has become the most popular design choice in recent years ([1], [6], [7], [11]) because it achieves high-gain and low noise in a single low-power stage with internal input and output matching. Input matching is achieved with inductors Lg and Ls. A of 2 (see equation 7) is chosen for this implementation which means that the auxiliary LNA requires 1/8th of the gain of the main LNA. To achieve better matching, the sizes and drain currents through the two LNAs are identical, but only 1/8th of the auxiliary output current is subtracted from the main LNA output. Thus, this implementation consumes twice the power. Since the auxiliary LNA contributes only 1/8th more output noise, its addition increases the overall noise gure of the circuit by less than 0.2dB. One major drawback of the given implementation is that the reported power gain (<5dB) of the full LNA is much less than its voltage gain (23.8dB), implying that the output impedance is extremely large and not matched to 50 . This obstacle prevents this LNA from interfacing with external lters (see Fig. 4) at its output and results in extremely poor power transfer.

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VI. PREDICTED LNA RESEARCH

As shown in Fig. 5, CMOS LNAs are already capable of achieving high performance with moderate power consumption. However, due to increasing demand for low-power portable devices, future LNA research will be directed at sustaining performance while decreasing power. As evidenced by the highest performance designs of late ([1], [2], [6], [7], [11]), cascoding of MOS devices has become almost a standard in CMOS LNAs. However, as supply voltages decrease, new architectures for CMOS LNAs must be dened. An extremely innovative low-power bipolar design (Long, [14]) has yet to be reported in CMOS technology. Fig. 9 shows the simplied schematic. This design can operate at supplies well under 1V because the only required DC voltage drop is across M1 (about Veff). The input matching is achieved with network Lg and C1.
L2 Vin C1 Lg Q1 T1 Vout

Figure 9 Bipolar LNA incorporating transformer feedback

The integrated transformer T1 has two purposes. The negative feedback it employs improves the linearity of the circuit. More importantly, the transformer feedback tunes out the Miller capacitor Cgd, which is the main reason non-cascoded common-source MOS stages are so unattractive. The normally present feedback path through this capacitor causes poor isolation from the output to the input. This lack of reverse isolation causes instability in the LNA and makes input and output matching extremely difcult (because they are then inter-dependent). Other forms of feedback which attempt to accomplish this either largely increase the noise gure (feedback resistor from gate to drain) or must be accomplished off-chip with high quality components (inductor and capacitor from gate to drain). This interesting method of transformer feedback permits the design of fully-integratable, stable and extremely low-voltage CMOS LNAs.

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VII. CONCLUSION

This paper presented a comparison of recent CMOS LNA architectures in terms of noise gure and linearity. A brief overview of noise gure and linearity (IP3) was presented to give the reader some background into typical LNA perfomance measures. A typical RF receiver architecture was presented and LNA specications were related to overall receiver specications. Recent CMOS LNA performance comparisons were made and a traditional LNA architecture was reviewed. Two of the highest performance CMOS LNAs to date in terms of noise gure and linearity were reviewed. Finally, a predicted CMOS architecture based on an extremely low-voltage bipolar architecture was presented.

REFERENCES
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] P. Leroux, J. Janssens, M. Steyaert, A 0.8dB NF ESD-protected 9mW CMOS LNA, ISSCC Dig. Tech. Papers, vol. 26, pp. 410-411, 2001 Y. Ding, R Harjani, A +18dBm IIP3 LNA in 0.35um CMOS, ISSCC Dig. Tech. Papers, vol. 10, pp. 162163, 2001 J. Janssens, J. Crols, M. Steyaert, A 10mW Inductorless, Broadband CMOS Low Noise Amplier for 900MHz Wireless Communications, IEEE Custom Int. Circ. Conf., 1998, pp. 75-78 D. Shaeffer, T. H. Lee, A 1.5V, 1.5-GHz CMOS Low Noise Amplier,, IEEE Journal of Solid-State Cir cuits, Vol. 32, No. 5, pp. 745-759, May 1995 P. Rodgers, M. Megahed, C. Page, J. Wu, D. Staab, Silicon UTSi CMOS RFIC for CDMA wireless com munication systems, IEEE Raio Frequency Int. Circ. Symp., pp.181-184, 1999 A. Shahani, D. Shaeffer, T. H. Lee, A 12mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver, IEEE Journal of Solid State Circuits, vol. 32, no. 12, pp. 2061-2070, Dec. 1997 B. Floyd, J. Mehta, C. Gamero, K. K. O, A 900-MHz, 0.8um CMOS Low Noise Amplier with 1.2dB Noise Figure, IEEE Cust. Int. Circ. Conf., pp. 661-662, 1999 J. Zhou, D. Allstot, A Fully Integrated CMOS 900MHz LNA Utilizing Monolithic Transformers, ISSCC Dig. Tech. Papers, vol. 8, pp. 132-133, 1998 C. S. Kim et al, A Fully Integrated 1.9-GHz CMOS Low Noise Amplier, IEEE Microwave and Guided Wave Letters, Vol. 8, No. 8, Aug. 1998 A. Karanicolas, A 2.7-V 900MHz CMOS LNA and Mixer, IEEE Journal of Solid State Circuits, Vol. 31, No. 12, Dec. 1996 Q. Huang, P. Orsatti, F. Piazza, GSM Transceiver Front-End Circuits in 0.25-um CMOS, IEEE Journal of Solid State Circuits, Vol. 24, No. 3, March 1999 B. Razavi, RF Microelectronics, Prentice Hall, pp. 50-52, 1998 A. Rofougaran et al., A 1 GHz CMOS RF Front-End IC for Direct Conversion Wireless Receiver, IEEE Journal of Solid State Circuits, Vol. 31, No. 7, pp 880-889, July 1996 J.R. Long, M. A. Copeland, A 1.9GHz Low-Voltage Silicon Bipolar Receiver Front-End for Wireless Per sonal Communications Systems, IEEE Journal of Solid State Circuits, Vol. 30, No. 12, Dec. 1995