Lecture 3 VHDL Data Types and Operators
Translation of VHDL code to circuit !! Code structure
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Translation of VHDL code to circuit Code structure
!! What main example did we use? !! What are 3 important sections of VHDL code structure? !! In the section that you implement the behavior, is the default flow sequential or concurrent?
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Translation of VHDL code to circuit Code structure
!! What main example did we use? D flip-flop !! What are 3 important sections of VHDL code structure? !! Library, Entity, and Architecture !! In the section that you implement the behavior, is the default flow sequential or concurrent? Concurrent
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VHDL Data types !! Operators and Attributes !! Generic
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VHDL Data types !! Operators and Attributes !! Generic
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Pre-defined !! User-defined !! Subtypes
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Data types BIT, BIT_VECTOR STD_LOGIC, STD_LOGIC_VECTOR BOOLEAN INTEGER SIGNED UNSIGNED User-dened integer type User-dened enumerated type SUBTYPE
Synthesizable values 0, 1 X, 0, 1, Z (resolved) True, False From -2,147,483,647 to +2,147,483,647 From -2,147,483,647 to -2,147,483,647 (binary rep). From 0 to +2,147,483,647 (binary rep). Subset of INTEGER Collection enumerated by user Subset of any type ( pre- or userdened)
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Data types BIT, BIT_VECTOR STD_LOGIC, STD_LOGIC_VECTOR BOOLEAN INTEGER SIGNED UNSIGNED User-dened integer type User-dened enumerated type SUBTYPE
Synthesizable values 0, 1 X, 0, 1, Z (resolved) True, False From -2,147,483,647 to +2,147,483,647 From -2,147,483,647 to -2,147,483,647 (binary rep). From 0 to +2,147,483,647 (binary rep). Subset of INTEGER Collection enumerated by user Subset of any type ( pre- or userdened) Predefined
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They are parts of packages/libraries !! Package standard of library std: Defines BIT, BOOLEAN, and INTEGER data types !! Do you remember how you would include this in your VHDL code?
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They are parts of packages/libraries !! Package standard of library std: Defines BIT, BOOLEAN, and INTEGER data types. !! Do you remember how you would include this in your VHDL code? !! LIBRARY STD; !! USE STD.STANDARD.ALL;
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They are parts of packages/libraries !! Package standard of library std: Defines BIT, BOOLEAN, and INTEGER data types. !! Do you remember how you would include this in your VHDL code? !! LIBRARY STD; !! USE STD.STANDARD.ALL;
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BIT, BIT_VECTOR values: 0, 1
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BIT, BIT_VECTOR values: 0, 1
SIGNAL x: BIT; -- x is declared as a one-digit signal of type BIT. SIGNAL y: BIT_VECTOR (3 DOWNTO 0); -- y is a 4-bit vector, w/ the leftmost bit as MSB. SIGNAL w: BIT_VECTOR (0 TO 7); -- w is an 8-bit vector, w/ the rightmost bit as MSB. IMPORTANT: To assign a value to these signals you use <= operator
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BIT, BIT_VECTOR values: 0, 1
SIGNAL x: BIT; -- x is declared as a one-digit signal of type BIT. SIGNAL y: BIT_VECTOR (3 DOWNTO 0); -- y is a 4-bit vector, w/ the leftmost bit as MSB. SIGNAL w: BIT_VECTOR (0 TO 7); -- w is an 8-bit vector, w/ the rightmost bit as MSB. x <= '1'; -- x is assigned value 1. Single quotes (' ') -- are used for a single bit.
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BIT, BIT_VECTOR values: 0, 1
SIGNAL x: BIT; -- x is declared as a one-digit signal of type BIT.
SIGNAL y: BIT_VECTOR (3 DOWNTO 0); -- y is a 4-bit vector, w/ the leftmost bit as MSB. SIGNAL w: BIT_VECTOR (0 TO 7); -- w is an 8-bit vector, w/ the rightmost bit as MSB. x <= '1'; -- x is assigned value 1. Single quotes (' ') -- are used for a single bit. y <= "0111"; -- y is assigned "0111 (MSB='0'). Double -- quotes (" ") are used for vectors.
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BIT, BIT_VECTOR values: 0, 1
SIGNAL x: BIT; -- x is declared as a one-digit signal of type BIT. SIGNAL y: BIT_VECTOR (3 DOWNTO 0); -- y is a 4-bit vector, w/ the leftmost bit as MSB.
SIGNAL w: BIT_VECTOR (0 TO 7); -- w is an 8-bit vector, w/ the rightmost bit as MSB. x <= '1'; -- x is assigned value 1. Single quotes (' ') -- are used for a single bit. y <= "0111"; -- y is assigned "0111 (MSB='0'). Double -- quotes (" ") are used for vectors. w <= "01110001"; -- w is assigned "01110001 (MSB='1').
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BIT, BIT_VECTOR values: 0, 1
SIGNAL x: BIT; -- x is declared as a one-digit signal of type BIT. SIGNAL y: BIT_VECTOR (3 DOWNTO 0); -- y is a 4-bit vector, w/ the leftmost bit as MSB. SIGNAL w: BIT_VECTOR (0 TO 7); -- w is an 8-bit vector, w/ the rightmost bit as MSB.
Remember: [declaration] section of ARCHITECTURE
x <= '1'; -- x is assigned value 1. Single quotes (' ') -- are used for a single bit. y <= "0111"; -- y is assigned "0111 (MSB='0'). Double -- quotes (" ") are used for vectors. w <= "01110001"; -- w is assigned "01110001 (MSB='1').
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(code) section of ARCHITECTURE
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BOOLEAN: TRUE, FALSE !! INTEGER: From -2,147,483,647 to +2,147,483,647
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BOOLEAN: TRUE, FALSE !! INTEGER: From -2,147,483,647 to +2,147,483,647
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!! IF ready THEN... -- Boolean, executed if ready=TRUE !! n <= 1200; -- integer
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Package STD_LOGIC_1164 of library IEEE: Defines STD_LOGIC !! STD_LOGIC similar to BIT and what you will be using most in course
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Value X 0 1 Z W L H Definition Forcing Unknown (synthesizable unknown) Forcing Low Forcing High High impedance Weak unknown Weak low Weak high Dont care
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(synthesizable logic 1) (synthesizable logic 0) (synthesizable tri-state buffer)
Synthesizable
Package STD_LOGIC_1164 of library IEEE: Defines STD_LOGIC !! STD_LOGIC similar to BIT and what you will be using most in course
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Value X 0 1 Z W L H Definition Forcing Unknown (synthesizable unknown) Forcing Low Forcing High High impedance Weak unknown Weak low Weak high Dont care
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(synthesizable logic 1) (synthesizable logic 0) (synthesizable tri-state buffer)
Synthesizable
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Resolved Logic System
X X 0 1 Z W L H X X X X X X X X 0 X 0 X 0 0 0 0 X 1 X X 1 1 1 1 1 X Z X 0 1 Z W L H X W X 0 1 W W W W X L X 0 1 L W L W X H X 0 1 H W W H X X X X X X X X X
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Resolved Logic System
X X 0 1 Z W L H X X X X X X X X 0 X 0 X 0 0 0 0 X 1 X X 1 1 1 1 1 X Z X 0 1 Z W L H X W X 0 1 W W W W X L X 0 1 L W L W X H X 0 1 H W W H X X X X X X X X X
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SIGNAL a: BIT; SIGNAL b: BIT_VECTOR(7 DOWNTO 0); SIGNAL c: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL e: INTEGER RANGE 0 TO 255; -- Assignments across data types are illegal. a <= b(5); -b(0) <= a; -c <= d(5); -d(0) <= c; -a <= c; -b <= d; -e <= b; e <= d; -- 2009 O. Adekunle 25
SIGNAL a: BIT; SIGNAL b: BIT_VECTOR(7 DOWNTO 0); SIGNAL c: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL e: INTEGER RANGE 0 TO 255; -- Assignments across data types are illegal a <= b(5); -- legal (same scalar type: BIT) b(0) <= a; -- legal (same scalar type: BIT) c <= d(5); -- legal (same scalar type: STD_LOGIC) d(0) <= c; -- legal (same scalar type: STD_LOGIC) a <= c; -- illegal (type mismatch: BIT x STD_LOGIC) b <= d; -- illegal (type mismatch: BIT_VECTOR x -- STD_LOGIC_VECTOR) e <= b; -- illegal (type mismatch: INTEGER x BIT_VECTOR) e <= d; -- illegal (type mismatch: INTEGER x -- STD_LOGIC_VECTOR)
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Pre-defined !! User-defined !! Subtypes
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Integers declare name and range
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Enumerated declare name and values
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Integers Ex:
!! !! !! !!
TYPE my_integer IS RANGE -32 TO 32; -- A user-defined subset of integers. TYPE student_grade IS RANGE 0 TO 100; -- A user-defined subset of integers or naturals.
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Enumerated EX:
!! TYPE state IS (idle, forward, backward, stop); !! -- An enumerated data type, typical of finite state machines. !! TYPE color IS (red, green, blue, white); !! -- Another enumerated data type.
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Pre-defined !! User-defined !! Subtypes
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Any type with the addition of a constraint !! Main reason for subtypes
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Examples:
!! Operations between different types arent allowed !! Operations between type and subtype are allowed
SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO '1'; SIGNAL a: BIT; SIGNAL b: STD_LOGIC; SIGNAL c: my_logic; ... b <= a; -b <= c; - 2009 O. Adekunle 31
Any type with the addition of a constraint !! Main reason for subtypes
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Examples:
!! Operations between different types arent allowed !! Operations between type and subtype are allowed
SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO '1'; SIGNAL a: BIT; SIGNAL b: STD_LOGIC; SIGNAL c: my_logic; ... b <= a; -- illegal (type mismatch: BIT versus STD_LOGIC) b <= c; -- legal (same "base" type: STD_LOGIC)
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VHDL Data types !! Operators and Attributes !! Generic
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Some operators do different things in different contexts EX: <= is used as less than or equal too
!! IF (a <= b) THEN
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Ex: <= is used as assignment
!! a <= b;
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We will show you how to differentiate
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Assignment !! Logical operators !! Arithmetic operators !! Comparison operators !! Attributes
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Are used to assign values to signals, variables, and constants !! Three assignment operators:
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!! <= Used to assign a value to a SIGNAL !! := Used to assign a value to a VARIABLE, CONSTANT, or GENERIC. Used also for establishing initial values. !! => Used to assign values to individual vector elements or with OTHERS
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Lets look at examples
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Given signal/variable declarations:
!! SIGNAL x : STD_LOGIC; !! VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0); -Leftmost bit is MSB !! SIGNAL w: STD_LOGIC_VECTOR(0 TO 7); -- Rightmost bit is -- MSB !! !! !! !! !! !! !! x <= '1'; -y := "0000"; -w <= "10000000"; w <= (0 =>'1', OTHERS =>'0'); - 2009 O. Adekunle 37
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Given signal/variable declarations:
!! SIGNAL x : STD_LOGIC; !! VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0); -Leftmost bit is MSB !! SIGNAL w: STD_LOGIC_VECTOR(0 TO 7); -- Rightmost bit is -- MSB !! !! !! !! !! !! !! x <= '1'; -- '1' is assigned to SIGNAL x using "<=" y := "0000"; -- "0000" is assigned to VARIABLE y using ":=" w <= "10000000"; w <= (0 =>'1', OTHERS =>'0'); -- LSB is '1', the others are '0'
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Assignment !! Logical operators !! Arithmetic operators !! Comparison operators !! Attributes
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!!
Same as boolean logic operators you may be familiar with
!! NOT, AND, OR,NAND, NOR, XOR, XNOR
Main thing to keep in mind is that the NOT operator has precedence over all other operators !! Examples:
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!! y <= NOT a AND b; -- (a'.b) !! y <= NOT (a AND b); -- (a.b) !! y <= a NAND b; -- (a.b)'
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Assignment !! Logical operators !! Arithmetic operators !! Comparison operators !! Attributes
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Arithmetic can be performed on INTEGER, SIGNED, and UNSIGNED !! Also, if the std_logic_signed or the std_logic_unsigned package of the ieee library is used, then STD_LOGIC_VECTOR can also be employed directly in addition and subtraction operations
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Again the operators are similar to what you are used too
!! + Addition !! - Subtraction !! * Multiplication !! / Division !! ** Exponentiation !! MOD Modulus !! REM Remainder !! ABS Absolute value
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Assignment !! Logical operators !! Arithmetic operators !! Comparison operators !! Attributes
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Used for making comparisons !! Similar to what you are used to !! Can be only used within IF and WAIT statements !! = Equal, !! /= Not equal to, !! < Less than, !! > Greater than, !! <= Less than or equal to, !! >= Greater than or equal to
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Code example
SIGNAL counter : INTEGER; SIGNAL clock: INTEGER; PROCESS (counter) BEGIN IF (counter <= 10) THEN clock <= 0; ELSIF (clock <= 20) THEN clock <= 1; END IF; END PROCESS;
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Code example
-- Signals entity port definitions SIGNAL counter : INTEGER; -- counts from 1 to 20 then resets SIGNAL clock: INTEGER; -- Excerpt of code PROCESS (counter) BEGIN IF (counter <= 10) THEN clock <= 0; ELSIF (counter > 10) THEN clock <= 1; END IF; END PROCESS;
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Code example
-- Signals entity port definitions SIGNAL counter : INTEGER; -- counts from 1 to 20 then resets SIGNAL clock: INTEGER; -- Excerpt of code PROCESS (counter) BEGIN IF (counter <= 10) THEN equal to clock <= 0; ELSIF (counter > 10) THEN clock <= 1; END IF; END PROCESS;
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-- less than or -- assignment -- assignment
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Assignment !! Logical operators !! Arithmetic operators !! Comparison operators !! Attributes
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Ways to specify certain parts of data: !! Synthesizable types:
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!! dLOW: Returns lower array index !! dHIGH: Returns upper array index !! dLEFT: Returns leftmost array index !! dRIGHT: Returns rightmost array index !! dLENGTH: Returns vector size !! dRANGE: Returns vector range !! dREVERSE_RANGE: Returns vector range in reverse order
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If given: Then:
!! SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0);
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!! d'LOW= !! d'HIGH= !! d'LEFT= !! d'RIGHT= !! d'LENGTH= !! d'RANGE= !! d'REVERSE_RANGE=(0 to 7)
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!!
If given: Then:
!! SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0);
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!! d'LOW=0 !! d'HIGH=7 !! d'LEFT=7 !! d'RIGHT=0 !! d'LENGTH=8 !! d'RANGE=(7 downto 0) !! d'REVERSE_RANGE=(0 to 7)
--lower array index --high array index --leftmost array index --rightmost array index --size
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!!
Or if given:
!! SIGNAL x: STD_LOGIC_VECTOR (0 TO 7);
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Then the LOOP statements below are equivalent:
!! FOR !! FOR !! FOR !! FOR i i i i IN IN IN IN
RANGE (0 TO 7) LOOP ... x'RANGE LOOP ... RANGE (x'LOW TO x'HIGH) LOOP ... RANGE (0 TO x'LENGTH-1) LOOP ...
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All signals also have attributes too !! For a SIGNAL s:
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!! sEVENT: Returns true when an event occurs on s !! sSTABLE: Returns true if no event has occurred on s !! sACTIVE: Returns true if s = 1 !! sQUIET <time>: Returns true if no event has occurred during the time specied !! sLAST_EVENT: Returns the time elapsed since last event !! sLAST_ACTIVE: Returns the time elapsed since last s = 1 !! sLAST_VALUE: Returns the value of s before the last event.
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VHDL Data types !! Operators and Attributes !! Generic
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What if you want a parity detector? !! Parity detector: a circuit that provide
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!! output = 0 when the number of 1s in the input vector is even !! output 1 otherwise
input (1 downto 0)
output
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!!
3 input parity detector
input (2 downto 0)
output
ENTITY parity_det IS PORT ( input: IN STD_LOGIC_VECTOR (2 DOWNTO 0); output: OUT BIT); END parity_det;
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!!
3 input parity detector
input (2 downto 0)
output
!!
4 input parity detector
ENTITY parity_det IS PORT ( input: IN STD_LOGIC_VECTOR (2 DOWNTO 0); output: OUT BIT); END parity_det;
input (3 downto 0)
output
ENTITY parity_det IS PORT ( input: IN STD_LOGIC_VECTOR (3 DOWNTO 0); output: OUT BIT); END parity_det;
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!!
3 input parity detector
input (2 downto 0)
output
!!
4 input parity detector
ENTITY parity_det IS PORT ( input: IN STD_LOGIC_VECTOR (2 DOWNTO 0); output: OUT BIT); END parity_det;
input (3 downto 0)
output
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Redundant much?
ENTITY parity_det IS PORT ( input: IN STD_LOGIC_VECTOR (3 DOWNTO 0); output: OUT BIT); END parity_det;
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A way of specifying a generic parameter !! Different for different applications !! Example syntax:
!! !!
Generic parity detector
!! GENERIC (parameter_name : parameter_type := parameter_value);
ENTITY parity_det IS GENERIC (n : INTEGER := 8); -- 8 input PORT ( input: IN STD_LOGIC_VECTOR (n DOWNTO 0); output: OUT BIT); END parity_det;
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VHDL Data types !! Operators and Attributes !! Generic
!! !!
Next class
!! Concurrent programming !! Sequential programming !! Signals and variables
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