UNIT -2

Introduction / 2
Features • Open standard
– VHDL – VHSIC Hardware • Human readable
• Evolution
Description Language
• Portability
– DOD, USA 1970’s &
1980’s • Documentation, Simulation,
– IEEE 1076.3 Synthesis
• Schematic • Hierarchical design (top-
– Connectivity Information (Net list) down or bottom-up)
– Hierarchy, but bottom-up • Higher Level constructs
– Portability (Schematic database, • Supports library based
Libraries)
design
– Controller (FSM) Design
external • Strict Type checking
– Design Description

1
Schemati 3
c

VHDL Features 4
• Entity – Interface Specifications • Function
• Architecture – Functionality
e.g. 4 bit comparator
a(3)
b(3)

a
a(2)

b = equals b(2) equals

2
Equality 5
Comparator bit - ‘0’, ‘1’
library
-- 4 bit ieee;
equality comparator std_logic – ‘0’, ‘1’, ‘Z’, …
use
ieee.std_logic_1164.all;
in out
entity eqcomp is
port (a, b: in std_logic_vector(3 downto
0); equals: out std_logic);
end eqcomp; buffer inout

architecture arch_eqcomp of eqcomp

is begin
equals <= ‘1’ when (a = b) else ‘0’; buffer – has restrictions, we use
end arch_eqcomp;
signals (wires) for local feedback

Equality 6
• Comments start with -- anywhere on
Comparator
the line
• Identifiers
– Alphabetic, Numeric or
underscore characters
• Library  Packages  – Not case sensitive
Components, Functions, Procedures, – The first character must be an
Data Objects alphabet
– The last character cannot be
• Mode an underscore
– in, out, inout, buffer – Two underscores in
succession are not allowed
• Range: downto, to (MSbit,
LSbit)
– Bit order, Byte order (Little
Endian, Big Endian)

3
Syntax, Operators 7
• Architecture Body • Logical Operators
– Architecture declaration – and, nand, or, nor, xor, xnor,
• Component declarations
not
• Type declarations
• Constant declarations These are defined for data type
• Signal declarations “bit” and “boolean”
• Function, Procedure For “std_logic” data type these
definitions operators are overloaded in
“ieee.std_logic_1164” package
– Architecture
statement

Operators 8
• Arithmetic Operators • These operators are
– +, -, *, / defined for “integer” and
–** (exponentiation) “real” data types
– mod (modulo division) • For “std_logic” data type,
– rem (modulo remainder) these operators are
–abs (absolute value) overloaded in
A mod B = A – B * N “ieee.std_logic_unsigned”
package
A rem B = A  A /

B  B

4
Operators 9
• Relational Operators • Shift Operators
=, >, <, <=, >=,
/= sll (shift left logical), srl
These operators are defined for sla (shift left arithmetic), sra
“integer” and “real” data types rol (rotate left), ror
For “std_logic” data type, these
operators are overloaded in These operators are defined for
“ieee.std_logic_arith” package “bit” and “boolean” data types
For “std_logic” data type, these
operators are overloaded in
“ieee.std_logic_arith” package

Operators 10
• Aggregate operator • Concatenation operator
Applied to elements Concatenate different size
of same type and size arrays of the same element
type.
signal a, b, c: std_logic;
signal tmp: type byte is array (7 downto
std_logic_vector(2 0) of bit;
downto 0); signal count: byte;
tmp <= (a, b, c); count <= “010” & “00110”;

5
Operators - 11
precedence
1. Logical operators Increasing precedence from 1 to 6
Operators of same category same
2. Relational operators
precedence.
3. Shift operators Left to right evaluations.
4. Adding operators “not” operator has precedence 6
5. Multiplying operators
6. Miscellaneous operators

7
Data 38
•Objects
Classes • Constants
Constants, Signals, Variables, Files – For readability and easy modification
of code
• Syntax constant width: integer := 8;

class object_name: data type;

• Variables
– Declared in sequential bodies
• Signals (process, functions, procedures).
Signals declared in architecture – Used in simulation extensively.
declarative region and used anywhere Indexing, temporary storage etc..
(architecture, processes, functions, Synthesis is not well defined in non-
procedures) trivial cases.
signal carry: std_logic_vector(7 variable count: integer range 0 to
downto 0); 255;

8
Data Objects, Types 39
• Files • Data Types
Used in test benches to store input – Scalar: enumerated, integer,
vectors and to write output vectors. float
Screen output – Composite: array, record
type logic_data is file of character;
file logical_name: logic_data;
file logical_name: logic_data is
• Enumerated
“inpvec.dat”;
type state_type (init, sample, wait,
file logical_name: logic_data
interrupt, out);
open read_mode is
“inpvec.dat”;
– Normally takes the values
0,1,2,3,4, ..
– Could be changed using
attributes

Data Types - Scalar 40

• Enumerated subtype std_logic is resolved
std_ulogic;
type boolean is (FALSE, TRUE);
type bit is (‘0’, ‘1’); – Synthesis: ‘0’, ‘1’, ‘L’, ‘H’, ‘Z’, ‘-’
– Simulation: All except ‘-’
type std_ulogic is
( 'U', -- Un-initialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
‘W’, -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care );

Kuruvilla Varghese

9
Data Types, Scalar Predefined 41
• Integer Physical Types
type time is range -2147483647 to
•
2147483647
type integer is range -2147483647 to units
2147483647;
fs;
ps = 1000 fs;
Range ns = 1000 ps;
variable count: integer range 0 to us = 1000 ns;
255; ms = 1000 us;
constant width: integer := 16; sec = 1000 ms;
min = 60 sec;
• Floating types hr = 60 min;
end units;
type real is range –1.0E38 to
+1.0E38

Subtype 42
s • What is the difference between
the above two?
• Subtype
– subtype my_int is integer range
48 to 56; – In the first one, all the operators
– subtype “UX01” is resolved defined for integer works. In the
std_ulogic range ‘U’ to ‘1’; second case various operators
need to be overloaded for the
• Type and subtype new my_int type.

– subtype my_int is integer range

48 to 56;
– type my_int is range 48 to 56;

10
User defined Data 43
Types • Array Types
• User defined type word is array (15 downto 0) of bit;
signal address: word;
– type MVL is (‘U’, ‘O’, ‘1’, ‘Z’);
– type index is range 0 to 15; • Unconstrained Array (constrained
– type word_length is range 31 at the time of object declaration)
downto 0;
– type volt_range is 3.3 downto type bit_vector is array (natural range
1.1; <>) of bit;
– type current is range 0 to type std_logic_vector is array (natural
1E9 units range <>) of std_logic;
nA; signal a: std_logic_vector(3 downto
uA = 1000 nA; 0);
mA = 1000 uA;
amp = 1000 mA;
end units;
– subtype filter_current is current
range 10 uA to 5 mA;

Data Types - 44
Composite • Record Types

type iocell is record

type table8x4 is array (0 to 7, 0 to 3) of buffer_inp: std_logic_vector(7
std_logic; downto 0);
constant ex_or: table8x4 := enable: std_logic; buffer_out:
(“000_0”, “001_1”, std_logic_vector(7
“010_1”, “011_0”, downto 0);
“100_1”, “101_0”, end record;
“110_0”, “111_1”);
signal busa, busb, busc: iocell;
signal vec: std_logic_vector(7
downto 0);

11
Data Types - 45
Composite • Array assignments
signal row: std_logic_vector(7 downto
busa.buffer_inp <= vec; 0);
busb.buffer_inp <= busa.buffer_inp row <= (‘1’, ‘0’,’1’,’1’, ‘1’, ‘1’,’1’,’1’);
busb.enable <= ‘1’; row <= (7 =>’1’, 6 => ’0’, others =>
busa.buffer_out
busc <= busb; <= busa.buffer_inp ’1’);
when (busa.enable = ‘1’) else
(others => ‘Z’); row <= “10111111”
row <= (‘1’, ‘0’, others => ‘1’);
row <= X”BF”
• Alias row <= (others => ‘0’);
signal address: std_logic_vector(31 row <= (others => ‘Z’);
downto 0); Base: Hexadecimal – X,
Octal – O,
alias top_ad: std_logic_vector(3 Binary - B
downto 0) is address(31 downto 28);

12
Behavioral Model 17
library ieee; architecture arch_eqcomp of
eqcomp is
use ieee.std_logic_1164.all;
begin
entity eqcomp is eqproc: process (a, b)
port (a, b: in std_logic_vector(3 begin
downto 0); if (a = b) then
equals: out std_logic); equals <= ‘1’;
end eqcomp; else
equals <= ‘0’;
end if;
end process;
end
arch_eqcomp;

Process 18
• Sequential body • Higher level constructs
– The way simulator computes – if … then,
– Synthesis is based on the – case … when
statements – for … loop
• Process Body – while … loop
– Process declarative part
• Variable, Constant
declarations
• Type declaration
• Function, Procedure
definitions
– Process statement
part

13
Proces 19
s • Sensitivity list
eqproc: process (a) – Compatibility between
begin simulation model and
synthesis model (sensitivity
if (a = b) then list – RHS of assignments,
equals <= ‘1’; and Conditions)
else – Focus of synthesis tool is
equals <= ‘0’; the structure of the circuit,
end if; not the real time behavior
end process of the circuit. Simulation
eqproc; tool focuses on latter

Using 20
Process
process (a,b,c)
begin
a y 0.
b
y <= f1 (a,b,c)
c z
0
z <= f2 (a,b,c)

end process;

* Note: Little more detail is required

14
Sequential 57
Statements
• if-then-else a, b, signals of cond1: inputs
• case-when y: output

• Equation
• if-then-else – syntax 1
y = a and cond1 or b and not(cond1)

if cond1
then y <= Note: cond1 here means the
a; Boolean equation of the
else condition.
y <= b; Note: Sequential statements
end if; are used in process,
functions and procedures
only

if-then- 58
else
• General conditions • Equations
• Priority
y = a and cond1 or
• Syntax 2
b and cond2 and not(cond1) or
c and cond3 and not(cond2) and
if cond1 then
not(cond1) or
y <= a; d and not(cond3) and
elsif cond2 then not(cond2)
y <= b; and not(cond1)
elsif cond3
then y <= c;
else
y <= d;
end if;

15
if-then- 59
•else
Equivalent to when-
else, but if cond1 then
• Multiple outputs y <= a; z <= a and b;
• Nesting elsif cond2 then
y <= b; z <= c;
elsif cond3 then
y <= c; z <= a;
a Y else
b z y <= d; z <= b;
c
end if;

if-then-else 60
• More complex behaviour/structure can be • Equations
specified by nesting. E.g. if there are
y = a and cond1 and cond2 or …
multiple outputs and we may not be able
to specify all outputs for same conditions

if cond1 then
if cond2
then
y <=
a;
elsif
00.
end if;
elsif
0
0.
end if;

16
if-then- 61
else if cond1
if cond1 then y <=
then y <= a;
a;
else
end if; cond
1
y <= y;
end if;
a y

• Implied Memory / Inferred

latch

Implied Memory / Inferred latch 62

• Concurrent equivalents • Implied Memory / Inferred latch is
useful in specifying the behaviour of
with en select latches and flip-flops or registers
y <= a when ‘1’; • But, unintentional implied latches
with en select can happen
y <= a when e.g. when multiple outputs are specified
‘1’, for each conditions, a missing output
unaffected when others; can result in implied latch on that
output. This is all the more possible
y <= a when en = ‘1’; when nested loops are not balanced,
y <= a when en = ‘1’ else as it is difficult to detect
unaffected; • This is one of the common errors
that inexperienced designer commit
• Concurrent: in VHDL coding
unaffected
• Sequential: null

17
Implied Memory / Inferred 63
latch
• It is difficult to expose this error in
simulation, as just verifying all
conditions would not be sufficient.
• Suppose, one output was missing
in condition 3, and the previous
condition simulated has the same
value expected of this output in
condition 3, then output will be
correct.
• If the designer has inadvertently
missed specifying an output, then
working out the condition for
exposing such an error would be
remote.

Case-when 64
• Syntax • All mutually exclusive values
of sel_signal need to be
case sel_signal is specified
when value1 • No priority, Truth table
=> • Equivalent to with-select, but
(statements)
when value2 • Multiple Outputs
=> (statements) • Nesting
000..
when valuex
=> (statements)
when others =>
(statements)

18
Case- 65
when
case sel is
• Equations
x = a and (decode of sel = val1) or
when val1 =>
c and (decode of sel = val2) or …
x <= a;
y = b and (decode of sel = val1) or
y <= b;
when val2 =>
d and (decode of sel = val2)
or …
x <=
c; y <= • Implied memory, if any output is
d; not specified in all choices of
when val3 => selection signal.
0 0 0
end case;

Case-when Nesting 66
• “case … when …’’ can be nested • Equation
with “if .. then ..’’ to specify
complex structure / behavior.
y = a and decode of (sel =
val1)
case sel is and cond2 or 0
when val1 =>
if cond2 then
y <= a;
elsif
00.
end if;
when val2 =>
0
end case;

Kuruvilla
Varghese

19
Case- 67
when library ieee;
use ieee.std_logic_1164.all;

entity dmux1t4 is
port (y: in std_logic_vector(3 downto 0);
a
0

s: in std_logic_vector(1 downto 0);

b
1

y a, b, c, d: out std_logic_vector(3
c
2

downto 0));
d
3

end dmux1t4;

architecture arch_dmux1t4 of dmux1t4 is

begin

Kuruvilla Varghese

Demultiplexer 68
process (s, y) when others =>
begin a <= “0000”; b <= “0000”; c <=
case s is “0000”;
when “00” d <= “0000”;
=> end case;
a <= y; b <= “0000”; c <= “0000”; end process;
d <= “0000”; end
when “01” => arch_dmux1t
b <= y; a <= “0000”; c <= “0000”; 4;
d <= “0000”;
when “10” =>
c <= y; a <= “0000”; b <= “0000”;
d <= “0000”;
when “11” =>
d <= y; a <= “0000”; b <= “0000”;
c <= “0000”;

20
Demultiplexer 69
process (s, y)
begin when others =>
a <= “0000”; b <= “0000”;
a <= “0000”;
c <= “0000”; d <= “0000”;
b <= “0000”; end case;
c <= “0000”; end process;
d <= “0000”; end
case s is arch_dmux1t
when “00” => 4;
a <= y;
when “01” =>
b <= y;
when “10” =>
c <= y;
when “11” =>
d <= y;

Loop 70
s• Concurrent: generate
• Sequential: loop

• Generate
– Equations
– Component Instantiations

21
Generate - 71
Example carry(0)
a(0) sum(0)
a b(0)
sum carry(1)
b
cin
a a(1) sum(1)
b b(1)
carry(2)
b
cout
cin
a
cin
carry(7) sum(7)
a(7)
b(7) carry(8)

Generat 72
e carry(0) • Equations
a(0) sum(0) for i in 0 to 7 generate
b(0) sum(i) <= a(i) xor b(i) xor carry(i);
carry(1)
carry(i+1) <= (a(i) and b(i)) or ((a(i) or
b(i)) and carry(i));
a(1) sum(1) end generate;
b(1)
carry(2) • Component Instantiations
for i in 0 to 7 generate

carry(7)
u1: fulladd port map (carry(i), a(i), b(i),
a(7) sum(7) sum(i),
b(7)
carry(i+1));
carry(8)
end generate;

22
Conditional Loops 73
• if ... Generate (Concurrent • If the condition is true, then the
statement, no else /elsif) generate is done
• Useful to generate irregular
loop_label: if (condition / expression) structures, i.e. Conditional on
generate loop index (e.g. i = 2) different
000.. structures can be generated
000..
end generate;

Sequential: For … 74
Loop • Syntax

if (rst = ‘1’) then loop_label: while expression loop

for i in 0 to 7 loop 0 0 . ..
fifo(i) <= (others => ‘0’); 0 0 0
end loop; end loop;

else
• Exampl
……. e
• The code decides whether the tbloop: while not endfile(vector_file)
loop is synthesizable. Above loop
loop is easily synthesizable. 0 0 0
0 0 0

23
Loop Control 75
• Exit • Next
exit; next;
exit [loop_label]; next [loop_label];
exit [loop_label] when condition; next [loop_label] when condition;

if condition then
if condition then
exit;
next;
end if;
end if;

Sequential Circuits: D Flip Flop 76

• Flip Flops behavior is modeled in
d q VHDL, not their equivalent circuit.
clk • Behavior: Up on the active edge of
the clock the input is transferred to
the output and is held (Memory)
until the next active clock edge.

clk

24
Flip Flop - Simulator 77

process (clk) • ‘clk’ in the sensitivity list computes

begin the process on both the edges of
clocks.
if (clk = ‘1’) then
• The clause (clk = ‘1’) selects the
q <= d; positive edge of the clock.
end if; • The Implied memory / Inferred latch
end process; takes care of memory

Flip Flop - Simulator 78

• But synthesis tools ignore d q
sensitivity list, hence the above
clk
code would mean a (transparent)
latch, as the events on ‘clk’ is not
considered. Whenever ‘clk’ is
high ‘q’ gets ‘d’ and on the d
negative edge the last value of
‘q’ is held. (Memory) clk

25
FF – Synthesis, 79

Simulation • clk’event is a predefined attribute

which is true whenever there is an
process (clk) event on the signal ‘clk’. The
begin statement clk’event and clk = ‘1’,
if (clk’event would mean the positive edge of
and clk =
clock. Statement clk’event would be
redundant for simulation.
‘1’) then
q <= d; • The statement clk’event and clk =
end if; ‘1’, would also be true when clk
end process;
transits from ‘U’ to ‘1’ (std_logic),
this could occur at the beginning of
simulation.

FF – Synthesis, 80
Simulation
• To avoid this, functions
‘rising_edge(clk)’ and
‘falling_edge(clk)’ in
ieee.std_logic_1164 package
could be used
• Equivalent concurrent statement

q <= d when clk’event and clk = ‘1’;

26
D 81
Latch
clkd
process (clk, d)
begin
q if (clk = ‘1’)
then q <= d;
end if;
Synthesis Tool end process;

process (clk)
begin
if (clk = ‘1’) then
q <= d;
end if;
end process;
Kuruvilla
Varghese

D 82
Latch
• ‘clk’ in the sensitivity list invokes
process for computation only on clock
• wait
edges, hence ‘d’ is added to sensitivity
list to respond to changes in the input ‘d’ process
• The statement clk = ‘1’ takes care of the
begin
transparent latch behavior. if (clk
• Implied memory takes care of the latch =
operation ‘1’)
the
nq
• Equivalent concurrent statement <=
d;
q <= d when clk = ‘1’;
end if;
wait on clk, d;
end process;

27
Wai 83
•t wait on sensitivity-list;
•wait until boolean-expression;
• wait for time-expression;

• Examples
wait on clk, d;
wait until count = 10;
wait for 10 ns;
wait on clk for 17 ns;
wait until sum > 100
for 50 ns;

Asynchronous 84
Reset process (clk, reset)
begin
d q
if (reset = ‘1’) then
clk q <= ‘0’;
AR elsif (clk’event and
clk = ‘1’) then q
<= d;
process (clk) end if;
begin end process;
if (clk’event
and clk =
• Concurrent statements
‘1’) then
q <= d; q <= ‘0’ when (reset = ‘1’) else
end if; d when (clk’event and clk = ‘1’);
end process;

28
Registers with comb circuit 85

process (clk)
a
begin d q
if b
clk
(clk’even
t and clk
= ‘1’)
then q • This means a single process can
<= a xor code registers preceded by any
b; combinational circuit
end if;
end process;

Registers with comb 86

circuit
process (clk)
begin
comb
if
(clk’event a
d q
b
and clk =
** code for combinational
‘1’) then
circuit ** clk

end if;
end process; • Note: Any assignment you do
here will have flip-flop/register

29
Registers with comb circuit 87
• Combinational circuit at the
input ‘d’ can be coded within the
clk’event and clk = ‘1’ statement
• This code being in process
should be using if … then, case
… when, for … etc.
• Any signal connected to ‘d’ is
synchronous with clock, hence
such code always represent
synchronous behavior

FF Synchronous 88
Reset • Asynchronous Reset
d q
process (clk, reset)
clk begin
if (reset = ‘1’) then
SR
q <= ‘0’;
elsif (clk’event and
clk = ‘1’) then q
<= d;
end if;
end process;

30
FF Synchronous 89
Reset process (clk)
d q begin
if (clk’event
clk
and clk =
SR ‘1’) then if
(reset =
‘1’) then
• if … then allows nesting and
q <= ‘0’;
synchronous circuit can be coded
else
• Nesting isn’t possible with q <= d;
concurrent statement, hence end if;
doesn’t make sense to code end if;
synchronous circuit.

Sync Reset, 90
Synthesis
0
d D Q
q
1
‘0’
reset
CK
clk

31
Synchronous circuit - 91
synthesis
d q r

process (clk) ck ck

begin clk
if (clk’event
and clk =
r <=then
‘1’) q; q
• Above process executes sequentially, but
end<=if; d;
both the assignments happens after ‘t +
end process; delta’ time. This along with implied
memory makes cascaded flip-flops.

Shift 92
Register
d(0) q(0) q(1) q(2) q(7)

ck ck ck ck

clk

32
Shift 93
Register
process (clk)
begin process (clk)
if (clk’event begin
and clk
= ‘1’) if (clk’event
then and clk
q(0) <= = ‘1’)
d(0); then q
for i in 0 to 6 loop <= q(6
q(i+1) <= q(i);
downto
end loop;
end if; 0) &
end d(0);
process; end if;
end process;

Counter 94

library ieee; count <= q;

use ieee.std_logic_1164.all; use
ieee.std_logic_unsigned.all; process (clk, reset)
begin
entity count8 is if (reset = '1')
port (clk, reset: in std_logic; then
count: out std_logic_vector(7 downto 0)); q <= (others =>
end count8; '0‘);
elsif (clk'event
architecture arch_count8 of count8 is and clk = '1')
signal q: std_logic_vector(7 downto 0); then q <= q +
begin 1;
end if;
end process;

end
arch_count8;

33
Counte 95
r library ieee;
d q count use ieee.std_logic_1164.all; use
+1
q ieee.std_logic_unsigned.all;
clk clk
AR
entity count8 is port
reset (clk, reset, load: in std_logic;
din: in std_logic_vector(7 downto 0);
count: out std_logic_vector(7 downto 0));
end count8;

architecture arch_count8 of count8 is

signal q: std_logic_vector(7 downto 0);
begin

Counte 96
r
count <= q;
process (clk, reset) + 0
d q count
begin din 1 1 q
if (reset = '1') then load
clk clk
q <= (others => A
R
'0‘);
rese
elsif (clk'event and t
clk = '1') then if
(load = '1') then • Synthesis Tools might optimize
q <= din; else q further to get efficient target specific
<= q + 1;
circuits
end if;
end if;
end process;
end arch_count8;

34
Unit 4
Structural Code 23
library ieee; architecture arch_eqcomp of eqcomp is
use ieee.std_logic_1164.all;
component xnor2
entity eqcomp is port (i1, i2: in std_logic, o1: out
port (a, b: in std_logic_vector(3 downto 0); std_logic);
equals: out std_logic); end component;
end eqcomp; component and4
port (i1, i2, i3,
i4: in std_logic,
o1: out
std_logic);
end component;
signal int1, int2, int3, int4: std_logic;
begin

Kuruvilla Varghese

Structural 24
Code
c1: xnor2 port map (a(3), b(3), int1);
a(3) int1
c2: xnor2 port map (a(2), b(2), int2); b(3
)
c3: xnor2 port map (a(1), b(1), int3); a(2) int2
c4: xnor2 port map (a(0), b(0), int4); b(2
equals
)
c5: and4 port map (int1, int2, int3, int4,
a(1)
equals); b(1 int3
)a(0)
end arch_eqcomp; b(0
) int4

i1
i1 o1 i2 o1
i2 i3
i4

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36
Components 25
-- Components library ieee;
library ieee; use ieee.std_logic_1164.all;
use
ieee.std_logic entity and4 is
_1164.all;
entity xnor2 is port (i1, i2, i3, i4: in std_logic, o1:
port (i1, i2: in std_logic, o1: out out std_logic);
std_logic); end and4;
end xnor2;
architecture arch_and4 of and4 is
architecture arch_xnor2 of xnor2 is begin
begin o1 <= i1 and i2 and i3
and i4;
o1 <= i1 xnor i2; end arch_and4; end arch_xnor2;

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Component instantiation 26
• Port map
– Formal to actual mapping
• Positional association
xnor2 port map (a(3), b(3), int1);

• Named Association

xnor2 port map (o1 => int1, i2

=> b(3), i1 => a(3));

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37
Naming signals, 27
ports
signal int1, int2, int3, int4: std_logic;
for i in 0 to 3 generate
signal int: std_logic_vector(3 downto 0);
c: xnor2 port map (a(i), b(i), int(i));
c1: xnor2 port map (a(3), b(3), int1);
end generate;
c2: xnor2 port map (a(2), b(2), int2);
c3: xnor2 port map (a(1), b(1), int3); c4: and4 port map (int(0), int(1), int(2),
c4: xnor2 port map (a(0), b(0), int4); int(3), equals);
c5: and4 port map (int1, int2, int3, int4,
equals);
• open
c1: xnor2 port map (a(3), b(3), int(3));
when a component is instantiated if any of
c2: xnor2 port map (a(2), b(2), int(2)); its output is unused, those can be mapped
c3: xnor2 port map (a(1), b(1), int(1)); to ‘open’
c4: xnor2 port map (a(0), b(0), int(0));
c5: and4 port map (int(3), int(2), int(1), int(0), unused inputs must be tied to appropriate
equals); logic levels

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38
Unit 5
Coding Scenario 97
Topmost Level
Structural code
Components

Structural
code

Bottom most level

Single Component
Behavioral /
Dataflow
Descriptions
Processes

Concurrent
statements

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Library, Packages 98
library ieee; use ieee.std_logic_1164.all;
d

q entity dataff is port

ck (d, clk: in std_logic; q: out std_logic);
clk int so end dataff;
in 1 p
p
c c
scl
k k architecture behave of dataff is
k begin
process (clk)
begin
• Component: D Flip-flop
if (clk'event
• Tope Level entity: Double and clk =
Synchronizer '1') then q
<= d; end
if;
end process;
end behave;
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40
Library, 99
Packages
library ieee; architecture struct of dsync is
use ieee.std_logic_1164.all; component dataff
port (d, clk: in std_logic;
entity dsync is q: out std_logic);
port (inp, sclk: in std_logic; end component; signal
sop: out std_logic); int1: std_logic;
end dsync; begin
c1: dataff port map
(inp, sclk, int1); c2:
dataff port map (int1,
sclk, sop);
end struct;

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Library, Packages 100

• Library  Packages  • Implicitly
Components, Functions,
Procedures, Data types declared library
std, work; use
• Predefined libraries – STD, std.standard.all;
• Implicitly not declared
WORK use std.textio.all;

• Predefined packages in STD –

standard, textio

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41
Writing component in Package 101
library ieee; entity dff is
use ieee.std_logic_1164.all; port (d, clk: in std_logic; q: out
std_logic); end dff;
package xy_pkg is architecture behave of dff
component dff is begin
port (d, clk: in std_logic; process
q: out std_logic);
(clk) begin
end component;
if (clk'event and clk = '1') then
end xy_pkg;
q <= d;
library ieee; end if;
use end process;
ieee.std_logic_11 end behave;
64.all;
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Using Component from a package 102

architecture struct of dsync is
library xylib, ieee;
signal int1: std_logic;
use ieee.std_logic_1164.all;
begin
use xylib.xy_pkg.all;
c1: dff port map
entity dsync is (inp, sclk, int1); c2:
port (inp, sclk: in std_logic; dff port map (int1,
sop: out std_logic); sclk, sop);
end dsync; end
in struct;
int so
1 p
p
c c
k k
scl
k

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42
Instantiation 103
• Positional association
c1: dff port map (inp, sclk, int1);

• Named association
c1: dff port map (clk => sclk,
d => inp, q => int1);

– Formal to Actual association

– Signal order doesn’t matter
– Need to know only the port
names of the components, not
the order

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Generi 104
c• Generic components library ieee;
use ieee.std_logic_1164.all;
• Components that suite
package xy_pkg is
various data size, storage component count
sizes etc. generic (size: integer := 4);
• e.g. Counter with port (clk, rst: in std_logic;
count: out
configurable output width std_logic_vector(size-
• e.g. FIFO with 1 downto 0); end
component;
configurable width, end xy_pkg;
configurable depth

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43
Generic 105
Counter
library ieee; count <= q;
use ieee.std_logic_1164.all; use
ieee.std_logic_unsigned.all;
process (clk, rst)
entity count is begin
generic ( size: integer := 4); if (rst = ‘1’)
port (clk, rst: in std_logic;
then q <=
count: out
std_logic_vector(size- (others => ‘0’);
1 downto 0); end count; elsif (clk’event
and clk = ‘1’)
architecture behave of count is then
signal q: std_logic_vector(size-1 downto 0); q <= q + 1;
end arch_count;
end if;
begin
end process;
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Instantiatio 106
n• Default value – 4 entity nand2 is
• Default Usage generic (tplh: time := 3 ns; tphl: time := 2
c1: count port map (clock, rst, co); ns);
port (i1, i2: in std_logic; o1: out
std_logic); end nand2;
• Generic
c1: count generic map (8) port 0000.
map (clock, rst, co);
o1 <= i1 nand i2 after (tplh + tphl) /2;
0000.
• Any number of parameters,
any type
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44
Generic in Hierarchy 107
Generics of components can be
mapped to the generics of the
architectures that instantiate those
components.

c1: count generic map (twidth) port map

(clock, co);

Here ‘twidth’ is the generic of the

timer which instantiate a counter
with generic ‘size’. When the timer
instantiates counter it uses ‘twidth’
for ‘size’.
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Configuration 108
• Configuration Specification • Configuration Declaration
– Binds the components – Binds a top level entity to one of
instantiated in the architecture to the many architectures it has.
entity-architecture pair in any – Bind the components used at
design library. any level of hierarchy to an
– Specified in the architecture entity- architecture pair in any
declaration region design library.
– Separate design unit.
– Hierarchical
– Specified at the end
Library & Packages, Entity,
Architecture 1,
Architecture 2, …,
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45
Configuration Specifications 109
library ieee, hs_lib, cm_lib;
use ieee.std_logic_1164.all;
a s1
sum
b
cin entity full_adder is
a s2 port (a, b, cin: in std_logic;
b s5 sum, cout: out std_logic);
b s3
cout end full_adder;
cin
a s4
cin
architecture fa_str of full_adder is
component xor2
port (d1, d2: in std_logic;
dz: out std_logic);
end component;

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Configuration Specifications 11
0
component and2 -- Configuration specifications
port (z: out std_logic; a0, for x1, x2: xor2 use entity
a1: in std_logic); work.xor2(xorbeh);
end component; for a3: and2 use entity
component or2 hs_lib.and2hs(and2str) port map
port (n1, n2: in std_logic; (hs_b=>a1; hs_z=> z; hs_a=> a0);
z: out std_logic); for all: or2 use entity
end component; cmlib.or2cm(or2str); for others: and2
signal s1, s2, s3, s4, s5: use entity
std_logic; work.agate2(agate_df) port map (a0, a1,
z);

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46
Configuration Specifications 111

begin
x1: xor2 port map (a, b, s1); a s1
sum
x2: xor2 port map (s1, cin, sum); b
cin
a1: and2 port map (s2, a, b); s2
a
a2: and2 port map (s3, b, cin); b s5
a3: and2 port map (s4, a , cin); b s3
cout
cin
o1: or2 port map (s2, s3, s5); s4
a
o2: or2 port map (s4, s5, cout); cin
end fa_str;

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Configuration 11
2
Declaration
-- binding entity to architecture library cm_lib;
configuration fa_con of full_adder is
and for fa_str
-- binding components to use work.all;
architecture for a1, a2, a3: and2
use entity
cm_lib.and2(and2df); end for;
-- binding entity to for others:
architecture configuration or2 end for;
fa_con of full_adder is for for all: xor2
fa_str use configuration work.xor2con;
end for; end for;
end for;
end fa_con;
end fa_con;
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47
Packages: Operators, Functions 113
ieee.std_logic_1164 (ieee) subtype std_logic is resolved std_ulogic;

type std_ulogic is type std_ulogic_vector is array ( natural

( 'U', -- Un-initialized range <> ) of std_ulogic;
'X', -- Forcing Unknown
'0', -- Forcing 0 type std_logic_vector is array ( natural
'1', -- Forcing 1 range <> ) of std_logic;
'Z', -- High Impedance
‘W’, -- Weak Unknown
ieee.std_logic_1164 (ieee)
'L', -- Weak 0
'H', -- Weak 1 • Logical operators
'-' -- Don't and, nand, or, nor, xor, xnor, not
care );

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Packages: Operators, Functions 11

4
ieee.std_logic_unsigned (ieee) • Shift Operators
std_logic, std_logic_vector
SHR, SHL
Overloaded operators • Functions
• Arithmetic Operators conv_integer
+, -, *, /
• Relational Operators
<, >, =, /=, <=, >=

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48
Packages: Operators, Functions 11
5
ieee.std_logic_arith (synopsys) Overloaded operators
• Arithmetic Operators
type unsigned is array ( natural +, -, *, /
range <> ) of std_logic;
• Relational Operators
type signed is array ( natural
range <, >, =, /=, <=, >=
<> ) of std_logic; • Shift Operators
SHR, SHL
(unsigned – logical
signed –
arithmetic)

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Packages: Operators, Functions 11

6
ieee.std_logic_arith (synopsys) • Usage
Conversion Functions library ieee ;
use ieee.std_logic_1164.all ; use
from: std_logic_vector, ieee.std_logic_arith.all ; use
unsigned, signed, integer ieee.std_logic_unsigned.all;
• Recommendations
– Use std_logic_arith for numeric
conv_integer
operations
conv_unsigned
– Use std_logic_unsigned only
conv_signed for counters and testbenches
conv_std_logic_vector – Don't use the package
std_logic_signed
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49
Packages: Operators, Functions 11
7
ieee.numeric_std (ieee) Overloaded operators
• Arithmetic Operators
type unsigned is array ( natural range <> +, -, *, /, abs, rem, mod
) of std_logic;
type signed is array ( natural range <> )
• Relational Operators
of std_logic; <, >, =, /=, <=, >=
• Logical operators
and, nand, or, nor, xor, xnor, not

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Packages: Operators, Functions 11

8
ieee.numeric_std (ieee) • Usage

• Shift operators (signed, library ieee ;

use ieee.std_logic_1164.all ;
unsigned)
use ieee.numeric_std.all ;
shift_left, shift_right
rotate_left, rotate_right
sll, srl, rol, ror
• Conversion Functions
to_integer
to_unsigned
to_signed
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50
Type 119
Conversions
Automatic sl_vect <= std_logic_vector(usg_vect)
sl_vect <= std_logic_vector(sg_vect)
• – Between base types and
usg_vect <= unsigned(sl_vect)
subtypes sg_vect <= signed(sl_vect)
• Using Conversion
Functions signed(“1101”)

– e.g. to_integer,
conv_integer
• Type Casting
between signed, unsigned,
and std_logic_vector

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Type Conversion and synthesis 120

• Type conversion is required when • But, in a code, where a
you connect a signal of one data type std_logic_vector address is
(e.g. integer) to another (e.g. converted to integer, as an index into
std_logic_vector), as VHDL is a a memory array, type conversion
strict type checking language implies an address decoder
• Type conversion implies no
hardware, Hence directives (user
defined attributes) are given to
synthesis tool, not to synthesize the
code.

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51
Arithmetic 121
signal a, b, s: unsigned(7 downto 0) signal a, b, s: unsigned(7 downto 0);
; signal s9: unsigned(8 downto 0) ;
signal s9: unsigned(8 downto 0) ; signal cin: std_logic ;
signal s7: unsigned(6 downto 0) ; -- Carry in
s9 <= (a & '1') + (b & cin);
-- Simple Addition, no carry out s <= s9(8 downto 1) ;
s <= a + b ;
-- Carry Out in result
s9 <= ('0' & a) + ('0' & b) ;
-- For smaller result, slice input
arrays
s7 <= a(6 downto 0) + b(6
;
downto 0) Kuruvilla
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Arithmetic with time 122

• Suppose you want to do some
computation with ‘time’ data type
• Then it is better to remove time
unit and cast it to real and do the
arithmetic operations like
multiplication, division etc.

variable period: real;

period := real(time_data / 1 ns)

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52
Example - Demultiplexer

129
process (s, y) when others =>
begin a <= “0000”; b <= “0000”; c <=
“0000”;
case s is d <= “0000”;
when “00” => end case;
a <= y; b <= “0000”; c <= “0000”; end process;
d <= “0000”; end arch_dmux1t4; when “01” =>
b <= y; a <= “0000”; c <= “0000”;
d <= “0000”;
when “10” =>
c <= y; a <= “0000”; b <= “0000”;
d <= “0000”;
when “11” =>
d <= y; a <= “0000”; b <= “0000”;
c <= “0000”;

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Example - 130
a(0) <= y(0) and not(s(1)) and not(s(0));
Demultiplexer
library ieee;
use ieee.std_logic_1164.all; a(1) <= y(1) and not(s(1)) and not(s(0));
a(2) <= y(2) and not(s(1)) and not(s(0));
entity dmux1t4 is a(3) <= y(3) and not(s(1)) and not(s(0));
port (y: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0); b(0) <= y(0) and not(s(1)) and s(0);
a, b, c, d: out std_logic_vector(3 b(1) <= y(1) and not(s(1)) and s(0);
downto 0)); b(2) <= y(2) and not(s(1)) and s(0);
end dmux1t4; b(3) <= y(3) and not(s(1)) and s(0);

architecture arch_dmux1t4 of dmux1t4 is c(0) <= y(0) and s(1) and not(s(0));
begin c(1) <= y(1) and s(1) and not(s(0));
c(2) <= y(2) and s(1) and not(s(0));
c(3) <= y(3) and s(1) and not(s(0));
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53
Example - Demultiplexer 131
architecture arch_dmux1t4 of dmux1t4 is
d(0) <= y(0) and s(1) and s(0);

begin d(1) <= y(1) and s(1) and s(0);

glp: for i in 0 to 3 generate
d(2) <= y(2) and s(1) and s(0);
a(i) <= y(i) and not(s(1)) and not(s(0));
d(3) <= y(3) and s(1) and s(0);
b(i) <= y(i) and not(s(1)) and s(0);
end arch_dmux1t4; c(i) <= y(i) and s(1) and not(s(0));
d(i) <= y(i) and s(1) and s(0);
end generate;

end arch_dmux1t4;

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With … select 132

architecture arch_dmux1t4 of dmux1t4 is with s select
begin d <= y when "11",
"0000" when others;
with s select
a <= y when "00", end arch_dmux1t4; "0000" when others;
with s select
b <= y when "01",
"0000" when others;
with s select
c <= y when "10",
"0000" when others;

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54
When … else / Case 133
architecture arch_dmux1t4 of dmux1t4 is
architecture arch_dmux1t4 of dmux1t4 is begin
begin process (s, y)
begin
a <= y when (s = "00") else "0000"; a <= "0000";
b <= "0000";
b <= y when (s = "01") else "0000"; c
c <= "0000";
<= y when (s = "10") else "0000"; d
d <= "0000";
<= y when (s = "11") else "0000";
case s is
when "00" => a <= y;
end arch_dmux1t4;
when "01" => b <= y;
when "10" => c <= y;
when "11" => d <= y;
when others => null;
end case;
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end process;

If … then 134
architecture arch_dmux1t4 of dmux1t4 is elsif (s = "10") then
begin c <= y; a <= "0000"; b <= "0000";
d <= "0000";
process (s, y) else
begin d <= y; a <= "0000"; b <= "0000";
c <= "0000";
if (s = "00") then end if;
a <= y; b <= "0000"; c <= "0000"; end process;
d <= "0000"; end arch_dmux1t4;
elsif (s = "01") then
b <= y; a <= "0000"; c <=
"0000"; d <= "0000";

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55
If … 135
then
process (s, y)
begin
a <= "0000";
b <= "0000";
c <= "0000";
d <= "0000";
if (s = "00") then a <= y;
elsif (s = "01") then b <= y;
elsif (s = "10") then c <= y;
else d <= y;
end if;
end process;

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If … then 136
process (s, y) process (s, y)
begin begin
if (s = "00") then a <= y; else a <= a <= "0000";
"0000"; end if; b <= "0000";
if (s = "01") then b <= y; else b <= c <= "0000";
"0000"; end if; d <= "0000";
if (s = "10") then c <= y; else c <= if (s = "00") then a <= y; end if;
"0000"; end if; if (s = "01") then b <= y; end if;
if (s = "11") then d <= y; else d <= if (s = "10") then c <= y; end if;
"0000"; end if; if (s = "11") then d <= y; end if;
end process; end process;

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56
Ripple 137
Adder architecture arch_add8 of add8 is
signal carry: std_logic_vector (8 downto
0); begin

carry(0) <= cin; cout <= carry(8);

library ieee;
use ieee.std_logic_1164.all; glp: for i in 0 to 7 generate
sum(i) <= a(i) xor b(i) xor carry(i);
entity add8 is carry(i+1) <= (a(i) and b(i)) or (( a(i) or b(i))
port(a, b: in std_logic_vector(7 downto 0); and carry(i));
sum: out std_logic_vector(7 downto 0); end generate;
cin: in std_logic; cout: out std_logic);
end add8; end arch_add8;

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Carry Look Ahead Adder

138

s(i) = a(i) xor b(i) xor c(i)

c(i+1) = a(i) b(i) or
(a(i) or b(i)) c(i)

g(i) = a(i) b(i)

p(i) = a(i) or b(i))

Image Source: htsvn.getgoo.net

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57
Carry Look Ahead Adder 139
architecture arch_add8 of add8 is carry(1) <= g(0) or (p(0) and carry(0));
signal carry: std_logic_vector(8 downto 0);
signal g, p: std_logic_vector(7 downto 0); carry(2) <= g(1) or (p(1) and g(0)) or
begin (p(1) and p(0) and carry(0));

carry(0) <= cin; cout <= carry(8); carry(3) <= g(2) or (p(2) and g(1)) or
(p(2) and p(1) and g(0)) or
glp: for i in 0 to 7 generate (p(2) and p(1) and p(0) and carry(0));
g(i) <= a(i) and b(i);
p(i) <= a(i) or b(i); 00000..
sum(i) <= a(i) xor b(i) xor carry(i);
end generate; end arch_add8;

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Adder: Operator 140

library ieee; • Depends on how operator is
use ieee.std_logic_1164.all; use implemented
ieee.std_logic_unsigned.all; • Mostly ripple adder
entity add8 is • In FPGA’s it will result in
port(a, b: in std_logic_vector(7 downto 0); using in-built adder
sum: out std_logic_vector(7 downto 0)); resource
end add8;

architecture arch_add8 of add8 is

begin
sum <= a + b;
end arch_add8;

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58
Shift Register 141
d7 d0
Source Reg

Shift

Dest Reg
d’7 d’1 ‘0’

• Fixed Shift – wiring Shift

• Destination could be a Src/Dest Reg

different register or same
register
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Shift 142
d0
Register
d7

• Variable Shift – Multiplexer

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59
 Universal Shift 143
Register library ieee;
use ieee.std_logic_1164.all;

pi6 entity shift8 is port

q7 (clk, reset, lin, rin: in std_logic;
q6 q5 sel: in std_logic_vector(1 downto 0);
pin: in std_logic_vector(7 downto 0);
d0 y: out std_logic_vector(7 downto 0));
rin lin
end shift8;
architecture arch_shift8 of shift8 is
signal q: out std_logic_vector(7 downto
q6 q0 0)); begin
y <= q;

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Universal Shift 144

Register -- shift right
process (reset, clk) when "10" =>
begin q(7) <=
if (reset = '1') then q <= (others => '0'); rin;
elsif (clk'event and clk = '1') then for i in 6
case sel is downto 0
-- parallel load loop q(i)
when "00" => q <= pin; <= q(i+1);
-- shift left end loop;
when "01" => q(0) <= lin; -- hold
for i in 0 to 6 loop q(i+1) when others => q <= q;
<= q(i); end case;
end loop; end arch_shift8;
end if;
end process;
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60
Universal Shift 145
Register
process (reset, clk)
-- shift right
when "10" =>
begin
q(7 downto 0) <= rin & q(7 downto 1);
if (reset = '1') then
-- hold

q <= (others => '0');

when others => q <= q;

elsif (clk'event and clk = '1') then

end case;

case sel is
end if;

-- parallel load
end process;

when "00" => q <= pin;

end arch_shift8;
-- shift left
when "01" =>
Kuruvilla
q(7 downto Varghese
0) <= q(6
downto 0) &
lin;

VHDL 146
Code
+ +
1

a z
1

b(7:0)
0

(7:0) D Q (7:0)
0

a (7:0) b(7:0
loc CK )
clk lo CK
A z (7:0) c A
rst R cl R
krst

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61
VHDL Code 147

library ieee;
use ieee.std_logic_1164.all; use process (rst, clk)
ieee.std_logic_unsigned.all begin
entity dt1q2 is if (rst = '1') then q <= (others => '0');
elsif (clk'event and clk = '1') then
port (clk, rst, loc: in std_logic; if (loc = '1') then
a, b: in std_logic_vector(7 downto 0); q <= q + a;
z: out std_logic_vector(7 downto 0)); else
end entity; q <= b;
end if;
architecture arch_dt1q2 of dt1q2 is end if;
signal q: std_logic_vector(7 downto 0); end process;
begin end arch_dt1q2;
z <= q;

Kuruvilla
Varghese

Draw the block 148

diagram process (a, b)
begin
library ieee; use ieee.std_logic_1164.all; if (a = '1')
use ieee.std_logic_unsigned.all; then y <=
use ieee.std_logic_arith.all; (others =>
entity dt1q3 is
'0'); elsif
port (a, b, d: in std_logic;
(b'event and
c: in std_logic_vector(7 downto 0); z: b = '1') then
out std_logic_vector(7 downto 0)); if (y = c)
end entity; then
for i in 0 to 6 loop
architecture arch_dt1q3 of dt1q3 is y(i+1) <= y(i);
signal y: std_logic_vector(7 downto 0); end loop;
begin y(0) <= d;
z <= y; end if;
end if;
end
Kuruvilla
proces
Varghese
s;
end
arch_dt
1q3;

62
Block 149
Diagram
c (7:0) =
z
0

D Q (7:0)
y
1

y(6:0) &
(7:0)
d
b CK
AR
a

Kuruvilla
Varghese

VHDL to 150
Circuit
library ieee; architecture arch_dsft1a of dsft1a is
use ieee.std_logic_1164.all; use
ieee.std_logic_unsigned.all; type dtype1 is array (3 downto 0) of
std_logic_vector(3 downto 0);
entity dsft1a is signal y: dtype1;
port (u, v: in std_logic_vector(3 downto 0);
w: out std_logic_vector(7 downto 0)); type dtype2 is array (3 downto
end dsft1a; 0) of
std_logic_vector(7 downto 0);

signal x: dtype2;

constant temp:
std_logic_vector(3 downto 0)
:= "0000";
Kuruvilla
Varghese
begin

63
VHDL to Circuit 151

V3
U3 U2 U1 U0
gnlp1: for i in 0 to 3 generate V2
V1
y(i) <= u and (v(i), v(i), v(i), v(i)); V0
end generate;

Y0(3) Y0(2) Y0(1) Y0(0)

Y1(3) Y1(2) Y1(1) Y1(0)
Y2(3) Y2(2) Y2(1) Y2(0)
Y3(3) Y3(2) Y3(1) Y3(0)

Kuruvilla
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VHDL to Circuit 152

x(0) <= temp(3 downto 0) & y(0);

0 0 0 0 Y0(3) Y0(2) Y0(1) Y0(0)
X(0)
gnlp2: for i in 1 to 3 generate 0 0 0 Y1(3) Y1(2) Y1(1) Y1(0) 0 +
X(1)
x(i) <= temp (3 downto i) & y(i) & 0 0 Y2 (3) Y2 (2) Y2 (1) Y2 (0) 0 0 +
X(2)
temp(i-1 downto 0) + 0 Y3 (3) Y3 (2) Y3 (1) Y3 (0) 0 0 0 +
X(3)
x(i-1);
end generate; W

w <= x(3); • 4 bit Array Multiplier

• Adders are ripple Adders (+)
end arch_dsft1a;

Kuruvilla
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64
Desig 153
n• Synchronous 4 bit up/down
counter with parallel load +

1
feature

0
1 coun

0
dir -1 d t
q q
• Block schematic

1
din
loa
• Behavioral VHDL Code d
clk
AR
cl
rst
k

Kuruvilla
Varghese

Design: Counter 154

library ieee;
use ieee.std_logic_1164.all; use process (clk, rst)
ieee.std_logic_unsigned.all; begin

entity dsft1a is if (rst = '1') then q <= (others => '0');

port (clk, rst, load, dir: in std_logic; din: elsif (clk'event and clk = '1') then
in std_logic_vector(3 downto 0); if (load = '1') then q <= din; elsif
count: out std_logic_vector(3 downto 0)); (dir = '1') then q <= q + 1; else
end dsft1a; q <= q - 1;
end if;
architecture arch_dsft1a of dsft1a is end if;
signal q: std_logic_vector(3 downto 0); end
begin process
;end arch_dsft1a;
count <= q;

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65
 FSM 155
Coding
• Inputs, clock, outputs: ports /
input NS output signals
s
s
NSL FF PS OL • Present State, Next State:
signals
• Choose the FSM Coding style specified
cloc by the Synthesis Tool, as the tool can
k
extract the FSM and optimize it.
reset

Kuruvilla
Varghese

FSM Coding 156

• 1 Process for NSL, 1 process for FF,
1 process for outputs
• 1 Process for NSL, 1 process for FF,
NS outputs
inputs Concurrent statements for outputs
NSL FF PS OL
(When number of outputs are less)
• 1 Process for NSL + FF, 1 process
for Outputs
• 1 Process for NSL + FF, Concurrent
clock
reset
statements for outputs (When
number of outputs are less)
• Asynchronous reset in FF process
• Synchronous reset in NSL process

Kuruvilla
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66
 FSM 157
Coding
• NSL: Process, • OL: Concurrent statements
“case … when” (on present state) with (present state) … select
with nested “if (on inputs)
…then” for next state • NSL+FF: Process
• Flip Flops: Process, if (rst) ... then
“if (rst) ... then” elsif (clk’event and clk = ‘1’) then
elsif (clk’event and clk = ‘1’) case … when” (on present state)
then
• OL: Process
“case … when” (present state)
for outputs.

Kuruvilla
Varghese

FSM 158
Coding • Logic: Process,
outputs
inputs “case … when” (present state)
NS
Logic PS outputs.
Flip
Flops “if (on inputs) …then” for
next state
clock
reset • Flip Flops: Process,
“if (rst) ... then”
“elsif (clk’event and clk = ‘1’)
• 1 process for Logic (NSL + OL)
then”
• 1 process for FF’s
• Implied Latch on outputs
when synchronous reset is
Kuruvilla
used
Varghese

67
Sequence Detector 159
• A simple sequence Detector. Sequence
101. Data shift clock used as FSM clock.
Overlapping detector. Moore Machine din’
reset
a detect = 0
din
clk din
detect din’ b detect = 0
Tx din Det din’
din
c detect = 0
din’ din
d detect = 1

Kuruvilla
Varghese

Sequence Detector: VHDL 160

Code
-- NSL process; FF process; OL nsl: process (pr_state, din) concurrent
begin

library ieee; case pr_state is

use ieee.std_logic_1164.all; when a =>
if din = '1' then nx_state
<= b;
entity sqdet1 is else nx_state <= a;
port (din, clk, reset: in std_logic; end if;

detect: out std_logic); when b =>

end sqdet1; if din = '0' then

nx_state <= c; else
nx_state <= b;
architecture sqd1 of sqdet1 is end if;

type statetype is (a, b, c, d); when c =>

signal pr_state, nx_state: statetype; if din = '1' then nx_state <= d;

begin else nx_state <= a;
end if; 68
Kuruvilla Varghese
 Sequence Detector: VHDL 161
Code
when d =>
if din = '0' then nx_state <= c;
flfl: process (clk, reset)
begin
else nx_state <= b; if (reset = '1') then pr_state <= a;
end if; elsif (clk'event and clk = '1') then
when others => pr_state <= nx_state; nx_state <= a; end
if;
end case; end process flfl;
end process nsl;

detect <= '1' when

(pr_state = d) else '0';
end sqd1;

Kuruvilla
Varghese

FSM 162
Coding • Logic: Process,
outputs
inputs “case … when” (present state)
NS
Logic PS outputs.
Flip
Flops “if (on inputs) …then” for
next state
clock
reset • Flip Flops: Process,
“if (rst) ... then”
“elsif (clk’event and clk = ‘1’)
• 1 process for Logic (NSL + OL)
then”
• 1 process for FF’s
• Implied Latch on outputs
when synchronous reset is
Kuruvilla
used
Varghese

69
Sequence Detector: VHDL 163
•Code
-- NSL + OL process; FF process; comb: process (pr_state, din)
begin
library ieee;
case pr_state is
use ieee.std_logic_1164.all;
when a => detect
<= ‘0’;
entity sqdet1 is if din = '1' then
port (din, clk, reset: in std_logic; nx_state <= b;
detect: out std_logic); else nx_state <=
end sqdet1; a;
end if;
architecture sqd1 of sqdet1 is when b => detect
<= ‘0’;
type statetype is (a, b, c, d);
if din = '0' then
signal pr_state, nx_state: statetype;
nx_state <= c;
begin
else nx_state <=
b;
end if;
when c => detect
<= ‘0’;
if din = '1' then nx_state <= d;
else nx_state <= a;
end if;
Kuruvilla Varghese

Sequence Detector: VHDL 164

Code
when d => detect <= ‘1’;
if din = '0' then nx_state <= c;
flfl: process (clk, reset)
begin
else nx_state <= b; if (reset = '1') then
end if; pr_state <= a; elsif
when others => detect <= ‘0’; (clk'event and clk =
nx_state <= a; '1') then
end case; pr_state <= nx_state;
end process comb; end if;
end process flfl;

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70
Sequence Detector - 165
Mealy
• A simple sequence Detector. Sequence
101. Data shift clock used as FSM clock.
comb: process (pr_state, din)
begin
Overlapping detector. Mealy machine case pr_state is
when a => detect <= ‘0’;
reset din’
if din = '1' then nx_state <= b;
else nx_state <= a; end if;
a detect = 0 when b => detect <= ‘0’;
din
din if din = '0' then nx_state <= c;
din’ b detect = 0 else nx_state <= b; end if;
din’ din when c => detect <= din;
c detect = din if din = '1' then nx_state <= b;
else nx_state <= a; end if;
when others => detect <= ‘0’;
-- NSL + OL single process nx_state <= a;
end case;
end process comb;
Kuruvilla
Varghese

Synchronous Reset 166

-- OL Concurrent statement -- Synchronous reset when NSL + OL is
-- coded in single process
detect <= '1' when ((pr_state = c) and -- Avoid implied latches on outputs
(din = ‘1’)) else '0'; comb: process (reset, pr_state, din)
begin
if (reset = ‘1’) then
detect <= ‘-’; nx_state <= a;
else
case pr_state is
------
end case;
end if;
end
process
comb;
Kuruvilla
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71
Synchronous Reset 167
-- Synchronous reset when NSL + OL is • State encoding
-- coded in single process sequential, gray, one-hot-one,
-- Avoid implied latches on outputs
one-hot-zero
comb: process (reset, pr_state, din)
begin
case pr_state is
------
end
case;
if (reset = ‘1’) then nx_state <= a;
end if;
end process comb;

Kuruvilla
Varghese

State encoding 168

• User defined attributes • Explicit declaration of states
– attribute state-encoding of signal pr_state, nx_state:
std_logic_vector(3 downto 0);
type-name: type is value;
constant a: std_logic_vector(3
(sequential, gray, one-hot- downto 0)
one, := “0001”;
one-hot-zero) constant b: std_logic_vector(3
attribute state_encoding of downto 0)
statetype: type is gray; := “0010”;
– attribute enum_encoding of constant c: std_logic_vector(3
downto 0)
type-name: type is “string”;
:= “0100”;
attribute enum_encoding of constant d: std_logic_vector(3
statetype: type is “00 01 11 •downto
FSM0)Editors
10”; := “1000”;
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72
Test 169
Bench
• Interactive simulation • Test bench
• Design steps verification – Input test vectors could be stored
in a file
• Design Iterations
– Output test vectors observed as
waveform or could be stored in a
file.
– Output could be checked against
the expected response stored.
– Automation, Documentation
– Same test bench could be used
in different design steps and in
design iterations.

Kuruvilla
Varghese

Test 170
Bench
– Compile the design in to library
• Component
(normally work library).
• Process –
– Create test bench code with empty
entity. Comparator
– Declare the top level component of
design.
– Declare the signals of type of the top a>b
level component. a
– Instantiate the component in the test a=b
bench code. b
– Apply the stimulus to the input a<b
ports.
– Compile the test bench and run
simulation.
– Observe the waveform and
verify.

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73
Test bench Signal Assignment 171
library ieee; use ieee.std_logic_1164.all; a <= “0000”, -- a = b
entity comp_tb is “1111” after 100 ns, -- a > b
end comp_tb; “1110” after 200 ns, -- a < b
“1110” after 300 ns, -- a > b
architecture arch_comp_tb of comp_tb is “1010” after 400 ns, -- a < b
component comp4 “1111” after 500 ns; -- a = b
port (a, b: in std_logic_vector(3 downto 0); b <= “0000”, -- a = b
agtb, aeqb, altb: out std_logic); “1110” after 100 ns, -- a > b
end component; “1111” after 200 ns, -- a < b
signal a, b: std_logic_vector(3 downto 0); “1100” after 300 ns, -- a > b
signal agtb, aeqb, altb: std_logic; “1100” after 400 ns, -- a < b
begin “1111” after 500 ns; -- a = b
a1: comp4 port map (a, b, agtb, aeqb, end arch_comp_tb;
altb);
Kuruvilla
Varghese

Test bench Signal Assignment 172

-- another way • Features
– Stimulus is part of the test bench
code
a <= “0000”; b <= “0000”;
– Stimulus is distributed in the test
wait for 100 ns; bench code
a <= “1111”; b <= “1110”; – Manual verification
wait for 100 ns;
a <= “1110”; b <= “1111”;
• Can we store input test vectors
wait for 100 ns;
and expected outputs together?
end arch_comp_tb;
• What data type is best for this?
– Record

Kuruvilla
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74
Test bench TV’s in Array 173
• Compile the design in to library – Check Process:
(normally work library).
• Declare a variable of type record
• Create test bench code with empty
entity. Loop
• Declare the top level component • Read the array element to the
of the design. record variable
• Declare the signals of type of the top • Apply the stimulus to the
level component. input ports,
• Declare a record with port signals of • Verify the actual outputs
top-level component. match the expected output.
• Declare an array of this record. • Compile the test bench and run
• Initialize the array with the input test simulation.
vectors and expected outputs • Check the Messages for error; up on error
observe debug messages and/or the
• Instantiate the component in the test
waveform
bench code.
Kuruvilla
Varghese

Test bench - Component 174

library ieee; q <= count;

use ieee.std_logic_1164.all; use
ieee.std_logic_unsigned.all; process (clk, rst)
begin
entity count4 is if (rst = '1') then
port (clk, rst: in std_logic; count <= (others
q: out std_logic_vector(3 downto 0)); => '0'); elsif
end count4; (clk'event and
clk = '1') then
architecture arch_count4 of count4 is count <= count + 1;
signal count: std_logic_vector(3 downto 0); end if;
arch_count4;
begin end process;

Kuruvilla
Varghese

75
Test bench TV’s in Array 175
library ieee; type tblk is record
use ieee.std_logic_1164.all; rst: std_logic; clk: std_logic;
q: std_logic_vector(3 downto 0);
end record;
entity countf_tb is
type testv is array (natural range
end countf_tb;
<>) of tblk;
constant tv: testv :=
architecture arch_countf_tb of countf_tb is (('1', '0', "0000"), ('1', '0', "0000"),
component count4 ('0', '0', "0000"), ('0', '1', "0001"),
port (rst, clk: in std_logic; ('0', '0', "0001"), ('0', '1', "0010"),
q: out std_logic_vector(3 downto 0)); ('0', '0', "0010"), ('0', '1', "0011"),
end component; ('0', '0', "0011"), ('0', '1', "0100"),
signal clk, rst: std_logic; ('0', '0', "0100"), ('0', '1', "0101"),
signal q: std_logic_vector(3 downto ('0', '0', "0101"), ('0', '1', "0110"),
0); ('0', '0', "0110"), ('0', '1', "0111"));
begin

Kuruvilla
Varghese

Test bench TV’s in Array 176

uut: count4 port map (rst => rst, assert q = vtv.q report “Counter output is not
clk => clk, q => q); what expected” severity note;
test: process end loop;
variable vtv: tblk; assert false report “Test over” severity note;
begin wait;
for i in tv'range loop end process;
vtv := tv(i); end arch_countf_tb;
rst <= vtv.rst;
clk <= vtv.clk;
wait for 20 ns;

Kuruvilla
Varghese

76
Test bench: Timing 177
Simulation
D Q
ts: Setup time: Minimum time input
must be valid before the active clock
CL
K edge

th: Hold time: Minimum time input

CL must be valid after the active clock
K
edge
D
ts
th tco: Propagation delay for input to
Q
appear at the output from active clock
edge
tco

Kuruvilla
Varghese

Test bench: Timing Simulation 178

• Setting up input
• Verifying the output
tclk

Input tclk
ts

CL tco
K
Outpu
t

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Varghese

77
Test bench: Timing Simulation 179
• Clock Generation • Checking outputs
– Period, Initial offset, Duty cycle – Give a delay for the full run after
• Asynchronous Reset applying inputs and add ts + tco
– Remove tRR time before clock edge – Or if there is a data valid signal
detect it
– Example uses ts instead of
t
RR Note: Period, setup time, and tco should
• –Applying Inputs
Apply ts time before active clock be noted from the Static Timing Analysis
edge for test bench, and is with respect to
– Detect the clock edge explicitly corresponding input/output pin/pad.
or implicitly (e.g. add clock
period – setup)

Kuruvilla
Varghese

Test bench: Timing Simulation 180

• Clock Generation • Checking outputs
– Period, Initial offset, Duty cycle – Give a delay for the full run after
• Asynchronous Reset applying inputs and add ts + tco
– Remove tRR time before clock edge – Or if there is a data valid signal
detect it
– Example uses ts instead of
t
RR Note: Period, setup time, and tco should
• –Applying Inputs
Apply ts time before active clock be noted from the Static Timing Analysis
edge for test bench
– Detect the clock edge explicitly
or implicitly (e.g. add clock
period – setup)

Kuruvilla
Varghese

78
Test bench: Timing Simulation 181
library ieee; use ieee.std_logic_1164.all;
Divider use ieee.std_logic_unsigned.all;

entity lex9_tb is
end lex9_tb;
clk
dv architecture arch_lex9_tb of lex9_tb is
rst
component nrdiv8
start
Divider port (
divdi(7:0) quoto(7:0) clk, rst, start: in std_logic;
dv: out std_logic;
divsi(7:0) remdo(8:0) divdi, divsi: in
std_logic_vector (7
downto 0); remdo: out
std_logic_vector (8
downto 0);
quoto: out std_logic_vector (7 downto 0));
Kuruvilla
end component;
Varghese

Test bench: Timing Simulation 182

signal clk: std_logic := '0'; type tblk is record
signal rst: std_logic := '1'; divdi: std_logic_vector(7 downto 0);
signal start: std_logic := '0'; divsi: std_logic_vector(7 downto 0);
signal dv: std_logic; quoto: std_logic_vector(7 downto 0);
signal divdi: remdo: std_logic_vector(8 downto 0);
std_logic_vector(7 downto end record;
0)
type testv is array (natural range <>) of
:= "11000000";
signal divsi: tblk; constant tv: testv :=
std_logic_vector(7 downto (("11000000", "00101101",
0)
"00000100", "000001100"),
:= "00101101";
signal quoto: ("00101101", "00000111",
std_logic_vector(7 downto "00000110", "000000011"),
0); signal remdo: ("11111111", "00000001",
std_logic_vector(8 downto "11111111", "000000000“));
0);
constant period: time := 200 ns; begin
constant duty_cycle: real := 0.5; Kuruvilla
Varghese
constant offset: time := 0 ns;
constant setup: time := 15 ns;
constant tco: time := 15 ns;
constant onerun: time := 2200 ns;

79
Test bench: Timing Simulation 183
uut: nrdiv8 port map test: process
(clk => clk, rst => rst, start => start, dv variable vtv: tblk;
begin
=> dv, divsi => divsi, divdi => divdi,
wait for (period -
remdo => remdo, quoto => quoto); (period *
clock: process -- clock process for clk duty_cycle) -
setup);
begin rst <= '0';
wait for offset; wait for period;
for i in tv'range loop
clock_loop : loop vtv := tv(i);
clk <= '0'; start <= '1';
wait for divdi <= vtv.divdi;
(period - divsi <= vtv.divsi;
wait for period;
(period *
start <= '0';
duty_cycle)); wait for (onerun +
clk <= '1'; setup + tco);
wait for Kuruvilla
Varghese
(period *
duty_cycle);
end loop clock_loop;
end process;

Test bench: Timing Simulation 184

assert quoto = vtv.quoto
report "Quotient is not what expected“ • Instead of adding (period - tco + ts) at the
severity note; end of the loop to setup the data correctly
assert remdo = vtv.remdo at the next iteration, code could wait for
report "Remainder is not what active clock edge at the beginning of
expected“ severity note; each iteration
wait for (period - (setup + tco));
end loop; wait for (clk’event and clk = ‘1’);
assert false report "Test over" severity wait for (period - (period * duty_cycle) -
note; setup);
wait;
end process; end
arch_lex9_tb;

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80
Test bench: Timing Simulation 185
• You may do this at the end of
iteration to check the output

wait for (clk’event and clk = ‘1’);

wait for (tco);

OR

wait for (dv’event and dv = ‘1’);

Kuruvilla
Varghese

Test bench: Algorithmic 186

-- Test Bench for 4 bit adder

• Instead of explicitly storing test library ieee;

vectors, it could be generated use ieee.std_logic_1164.all; use
ieee.std_logic_unsigned.all; use
algorithmically in some cases.
ieee.std_logic_arith.all;
• If the input test vectors follow a
regular pattern or functions, test entity addtb1 is
vectors could be generated end addtb1;
using test bench code architecture arch_addtb1 of addtb1 is
component adder4
port (a, b: in std_logic_vector(3
downto 0); s: out
std_logic_vector(4 downto 0));
end component;

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Varghese

81
Test bench: Algorithmic 187
test: process
signal a, b: std_logic_vector(3 downto 0); begin
signal s: std_logic_vector(4 downto 0); for i in 0 to width-1 loop
constant width: integer := 16; a <= conv_std_logic_vector(i, 4);
constant delay: time := 12 ns; for j in 0 to width-1 loop
begin b <= conv_std_logic_vector(j, 4);
wait for delay;
-- component Instantiation assert s = conv_std_logic_vector(i+j, 5) uut:
adder4 port map (a => a, b => b, report "Sum is not what is expected" s =>
s); severity note;
end loop;
end loop;
assert false report "Test Over"
severity note;
wait;
end process; end
arch_addtb1;
Kuruvilla Varghese

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