Lecture 4:

VHDL Basics
TIE-50206 Logic Synthesis
Arto Perttula
Tampere University of Technology
Fall 2017
Contents
• VHDL basics
– Packages
– Libraries
– Attributes

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Acknowledgements
• Prof. Pong P. Chu provided ”official” slides for
the book which is gratefully acknowledged
– See also: http://academic.csuohio.edu/chu_p/
• Most slides were originally made by Ari Kulmala
– and other previous lecturers (Teemu Pitkänen, Konsta
Punkka, Mikko Alho, Erno Salminen…)

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Packages

VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
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Packages
• Meant for encapsulating data which can be shared globally among several design units
• Consists of declaration part and optionally body part design_0.
• Package declaration can contain: vhd
– type and subtype declarations
– subprograms
– constants, alias declarations System_ design_1.
– file declarations pkg.vhd vhd
– global signal declarations
– component declarations

…
• Package body consists of
– type and subtype declarations
– subprogram declarations and bodies
design_n.
– deferred constants (avoids some re-compilation, rare concept)
vhd
– file declarations

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Package Example
PACKAGE example_pkg IS
CONSTANT example_c : STD_LOGIC := ’1’;
FUNCTION integer_to_vector
(size : INTEGER; number : INTEGER)
RETURN STD_LOGIC_VECTOR;
END example_pkg;

PACKAGE BODY example_pkg IS

FUNCTION integer_to_vector
(size : INTEGER; number : INTEGER)
RETURN STD_LOGIC_VECTOR IS
... --insert the implementation here
END integer_to_vector;
END example_pkg;
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Package Example (2)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_NUMERIC.all;

PACKAGE io_pkg IS
CONSTANT addr_width_c : NATURAL := 16;
CONSTANT data_width_c : NATURAL := 16;
CONSTANT stat_c : NATURAL := 1;
CONSTANT total_out_c : NATURAL := 10;
TYPE o_bits_arr IS ARRAY (0 to total_out-1)
OF NATURAL;
FUNCTION inmux(
data : STD_LOGIC_VECTOR(data_width_c-1 downto 0);
sel : NATURAL)
RETURN STD_LOGIC_VECTOR;
END io_pkg;

-- Function inmux will be defined in package body

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Libraries
• Collection of compiled VHDL design units (database)
1. Packages (declaration + body)
2. Entities (entity declaration)
3. Architectures (architecture body)
4. Configurations (defines comp-arch pairs)
• Some pre-defined, e.g., STD and IEEE
• One can also create own libraries
– At least a library called work
• To use, e.g., package, it must be compiled to some library first
(typically to work)
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Libraries (2)
• All entity names etc. must be unique within a library
• If you make two different entities with the same name,
e.g., fifo, you must compile them into separate
libraries
• You must define which fifo to use for each component
instance
– Either during instantiation or with separate configuration

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Using Packages And Components
1. Packages and entities are first compiled into some library (subdirectory on hard
disk)
– Compilation command in ModelSim is vcom
2. Command vlib tells the path to ModelSim
– VHDL file can refer to that library with symbolic name like ieee or work
3. In VHDL file, introduce first what libraries are used
– work is the default name, no need to introduce
4. Then, tell what packages are used
5. Then, tell what stuff is used from the package
– Function name, types etc., usually ”all”
library <libname>;
use <libname>.<pkg_name>.<stuff>;
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Using Packages And Components (2)

• Standard IEEE packages are the most common

– Compiled automatically during the ModelSim installation
– Referred using symbolic name ieee
– Most common package is std_logic_1164
• Sometimes, you need others
– E.g., special simulation models for FPGA-related primitive
components

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Browsing the Package Contents
a) Read the files directly from installation directory
– Something like: C:\Apps\MODELTECH_10.2C\vhdl_src\ieee
b) Start simulation of a design with ModelSim, open either tab ”sim” or ”Files”, and double-click some package

A package used in
this design

Double-clicking opens the

source code for the
package

12
Standard Packages

VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
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Data Types of Standard VHDL
• integer:
– Minimal range: -(231-1) to 231-1
– Two subtypes: natural, positive
• boolean: (false, true)
• bit: (‘0’, ‘1’)
– Not capable enough, but we’ll return to that…
• bit_vector: a one-dimensional array of bit

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Operators in Standard VHDL

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Operators (2)

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Concatenation
• Concatenation operator (&)
• Attaches multiple signals together into array
y <= "00" & a(7 DOWNTO 2);
y <= a(7) & a(7) & a(7 DOWNTO 2);
y <= a(1 DOWNTO 0) & a(7 DOWNTO 2);
7 2 0 7 2 0 7 0

a a a

... ... ...

y ”00” y y
7 6 5 0 7 6 5 0 7 6 5 0
Array Aggregate
• Aggregate is a VHDL construct to assign a value to an array-typed object
• Different types supported, e.g.,
a <= "10100000"; --direct
a <= (7=>'1', 6=>'0', 0=>'0', 1=>'0',
5=>'1', 4=>'0', 3=>'0', 2=>'1');
a <= (7|5=>'1', 6|4|3|2|1|0=>'0');
a <= (7|5=>'1', others=>'0');
• E.g., setting all elements at the same time
a <= "00000000" -- Size of a has to be known
a <= (others=>'0'); -- Size not needed, Flexible, Good
-- for reset. Superb!

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IEEE std_logic_1164 Package
• ’Bit’ is too limited having only 2 possible values
• Introduce extended data types
– std_logic
– std_logic_vector
• std_logic: 9 values: (’U’, ’X’, ’0’, ’1’, ’Z’, ’W’, ’L’, ’H’, ’-’)
– ’0’, ’1’; forcing logic 0 and forcing logic 1
– ’Z’: high-impedance, as in tri-state buffer
– ’L’, ’H’: weak logic 0 and weak logic 1
• As in wired-OR and wired-AND logic (pull-down/pull-up resistors)
– ’X’, ’W’: ”unknown” and ”weak unknown”
– ’U’: for uninitialized
– ’-’: don’t care

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IEEE std_logic_1164 Package (2)
• std_logic_vector
– An array of elements with std_logic data type
– Implies a bus (=set of signals)
• Recommended form is descending range
signal a : std_logic_vector(7 downto 0);
• Another form (less desired, do not use)
signal b : std_logic_vector(0 to 7);
– Always be consistent within a design
– Assigning a<=b or b<=a will be confusing
• Need to invoke package to use the data type:
library ieee;
use ieee.std_logic_1164.all;
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Overloaded Operator
IEEE std_logic_1164 Package
• Which standard VHDL operators can be applied to std_logic and std_logic_vector?
• Overloading: same operator of different data types
• Overloaded operators in std_logic_1164 package

Note: that shift is not defined

for std_logic_vector. Use
slicing and concatenation. Arto Perttula 2.11.2017 21
Type Conversion
• Type conversion is crucial in strongly typed language, such as VHDL
• Type conversion function in std_logic_1164 package:

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Examples of Type Conversions
• E.g.,

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IEEE numeric_std Package
• How to infer arithmetic operators?
• In standard VHDL:
signal a, b, sum: integer;
. . .
sum <= a + b;
• What’s wrong with integer data type?
– Negative or positive representation of the number
– Integer is typically 32-bit
• Default range is also 32-bit, synthesis tools may not optimize
• Note the range -(231-1) to 231-1
• I.e., 0 to 232-1 not supported!
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IEEE numeric_std Package (2)
• IEEE numeric_std package: define integer as an array of elements of
std_logic
• Two new data types: unsigned, signed
• The array interpreted as an unsigned or signed binary number, respectively
– Unsigned are represented as standard binary
– Signed vectors are represented using two’s complement
• E.g.,
signal x, y: signed(15 downto 0);
• Need to invoke package to use the data type
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
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Overloaded Operators in
IEEE numeric_std Package

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New Functions in IEEE
numeric_std Package

Note: that these

are functions, not
operators.

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Operator Overloading Example
-- this internal function computes the addition
• Operator overloading is a declaration of a function whose
-- of two UNSIGNED with input CARRY
designator is an operator symbol -- * the two arguments are of the same length
– Note the double quotes around the symbol
package body NUMERIC_STD is function ADD_UNSIGNED (L, R: UNSIGNED;
. . . C: STD_LOGIC) return UNSIGNED is
-- Result subtype: UNSIGNED(MAX(L'LENGTH, -- constant L_LEFT: INTEGER := L'LENGTH-1;
-- R'LENGTH)-1 downto 0). alias XL: UNSIGNED(L_LEFT downto 0) is L;
-- Result: Adds two UNSIGNED vectors that may be of alias XR: UNSIGNED(L_LEFT downto 0) is R;
-- different lengths. variable RESULT: UNSIGNED(L_LEFT downto 0);
function "+" (L, R: UNSIGNED) return UNSIGNED is variable CBIT: STD_LOGIC := C;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); begin
variable L01 : UNSIGNED(SIZE-1 downto 0); for I in 0 to L_LEFT loop
variable R01 : UNSIGNED(SIZE-1 downto 0); RESULT(I) := CBIT xor XL(I) xor XR(I);
begin CBIT := (CBIT and XL(I))
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then or (CBIT and XR(I))
return NAU; end if; or (XL(I) and XR(I));
end loop;
L01 := TO_01(RESIZE(L, SIZE), 'X'); return RESULT;
if (L01(L01'LEFT)='X') then return L01; end ADD_UNSIGNED;
end if;

R01 := TO_01(RESIZE(R, SIZE), 'X');

if (R01(R01'LEFT)='X') then return R01;
end if;

return ADD_UNSIGNED(L01, R01, '0');

end "+";
. . .

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Operators Over an Array Data Type
• Relational operators for array
– Operands must have same element type
– But their lengths may differ! Be careful!
• Two arrays are compared element by element, starting from the left
– If an array has less bits, it is considered smaller if compared bits are equal
(std_logic_vector)
• All the following return true
• “011“ = “011“
• “011“ > “010“
• “011“ > “00010“
• “0110“ > “011“

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Operators Over an Array Data Type
• a = 2 bits wide, b = 3 or 4 bits wide:
a b a > b, std_logic_vector a > b, unsigned
11 000 1 1
11 011 1 0
11 0111 1 0
11 110 0 0
00 001 0 0
00 000 0 0

• Problems: consider std_logic_vector ’if a = b then’

– If a and b have different length, the expression is always false!
– Syntactically correct so no warning/error
– => Use always unsigned/signed data type for values (that need to be compared)
– std_logic_vector only for ”general” control and ports

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Type Conversion
• std_logic_vector, unsigned and signed are defined as an array of
elements of std_logic
• They are considered as three different data types in VHDL
• Type conversion between data types:
a) Type conversion function
b) Type casting (for ”closely related” data types)
• Sometimes operands must be resized to same size, e.g., both to 16
bits

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Example
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
. . .
signal s1, s2, s3, s4, s5, s6:
std_logic_vector(3 downto 0);

signal u1, u2, u3, u4, u5, u6, u7:

unsigned(3 downto 0);

signal sg: signed(3 downto 0);

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Example (continued)
-- Ok
u3 <= u2 + u1; -- ok, both operands unsigned

u4 <= u2 + 1; -- ok, unsigned and natural operands

-- Wrong
u5 <= sg; -- type mismatch
u6 <= 5; -- type mismatch, 5 is integer/natural

-- Fixed
u5 <= unsigned(sg); -- type casting
u6 <= to_unsigned(5,4); -- use conversion function,
-- use 4 bits to represent
-- the value 5
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Example (continued 2)
-- Wrong
u7 <= sg + u1; -- + undefined over these types

-- Fixed
u7 <= unsigned(sg) + u1; -- ok, but be careful

-- Wrong
s3 <= u3; -- type mismatch
s4 <= 5; -- type mismatch
-- Fixed
s3 <= std_logic_vector(u3); -- type casting
s4 <= std_logic_vector(to_unsigned(5,4));

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Example (continued 3)
-- Wrong
s5 <= s2 + s1; -- + undefined for
-- std_logic_vector

s6 <= s2 + 1; -- + undefined for

-- std_logic_vector

-- Fixed
s5 <= std_logic_vector(unsigned(s2)
+ unsigned(s1));

s6 <= std_logic_vector(unsigned(s2) + 1);

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Conversion Example HW
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
r=
entity addsub is r=
port (
a,b: in std_logic_vector(7 downto 0);
ctrl: in std_logic;
r: out std_logic_vector(7 downto 0)
);
end addsub;

architecture direct_arch of addsub is

signal src0, src1, res:
signed(7 downto 0);
begin • Only a single line implements all the HW!
src0 <= signed(a); • No logic from the conversions!
src1 <= signed(b); • Exact HW for ”+” and ”-” operations do not
res <= src0 + src1 when ctrl='0' else have to be specified, tool will select
src0 - src1;
appropriate
r <= std_logic_vector(res);
• It is possible to code own
end direct_arch;
implementation, also

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resize() in numeric_std.vhdl
--===========================================================================
-- RESIZE Functions
--===========================================================================

-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.

-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.

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Resize in Action
• Original data width 4b (u_counter_r, sg_counter_r) is resized to 2b and 8b

Radix=
unsigned
hex signed
hex
Note: showing values in hex format is bit misleading with negative numbers 2.11.2017 38
resize() in numeric_std.vhdl (2)
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT)); -- sign extension
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;

-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;

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Conversion and Resize Summary
From type To type Conversion function

std_logic_vector unsigned unsigned( arg )

std_logic_vector signed signed( arg )

unsigned std_logic_vector std_logic_vector( arg )

signed std_logic_vector std_logic_vector( arg )

integer unsigned to_unsigned( arg, size )

integer signed to_signed( arg, size )

unsigned integer to_integer( arg )

signed integer to_integer( arg )

integer std_logic_vector integer -> unsigned/signed -> std_logic_vector

std_logic_vector integer std_logic_vector -> unsigned/signed -> integer

unsigned + unsigned std_logic_vector std_logic_vector( arg1 + arg2 )

signed + signed std_logic_vector std_logic_vector( arg1 + arg2 )

Type Resize function

unsigned resize( arg, size )

signed resize( arg, size )

http://www.tkt.cs.tut.fi/kurssit/50200/S17/Harjoitukset/conversion.html

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Non-IEEE Package
• Several supported non-IEEE packages exists
• Packages by Synopsys
• std_logic_arith:
– Similarities with numeric_std
• Cannot be used at the same time
– New data types: unsigned, signed
– Details are different
• std_logic_unsigned / std_logic_signed
– Treat std_logic_vector as unsigned and signed numbers
– i.e., overload std_logic_vector with arith operations
• USE NUMERIC_STD
– It is the standard and implementation is known and portable

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Attributes

VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
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Attributes
• A special identifier used to return or specify information about a
named object
• Denote values, functions, types, signals, or ranges associated with
various kinds of elements
• Predefined (a part of the VHDL’87) and user defined
• Predefined attributes are always applied to a prefix
• Used instead of fixed values or constants (unless the value is known
and very unlikely to be modified)
 Code is easier to maintain and reuse

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Attributes (2)
• Predefined attributes
• Notation in the examples:
– t = scalar type or subtype, e.g., integer
– a = array type, e.g., std_logic_vector(3 downto 0)
– s = signal, e.g., std_logic

• There are 5 kinds of attributes

1. Value kind attributes, return a constant value
– Return an explicit value and are applied to a type or subtype
– t’high, t’low
– t’left, t’right
– a’length[(n)]
2. Type, return a type: (t’base)
3. Range, return a range: (a’range, a’reverse_range)
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Attributes (3)
4. Function, call a function that returns a value:
– Attributes that return information about a given type, signal, or array value
– s’event, s’active, s’last_event, s’last_active, s’last_value
– t’pos(x), t’val(x), t’succ(x), t’pred(x), t’leftof(x), t’rightof(x)
– a’left[(n)], a’right[(n)], a’high[(n)], a’low[(n)]
5. Signal, create a new implicit signal:
– s’delayed [(t)], s’stable[(t)], s’quiet[(t)], s’transaction
• User defined
– Only constants possible
• Only a few are commonly needed

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Attributes: event
• Returns value true if an event occured (signal has changed its value) during the current delta, and
otherwise returns value false
• General form:
S’EVENT
• Example:
PROCESS(clk)
BEGIN
IF clk’EVENT AND clk=’1’ THEN
q <= d;
END IF;
END PROCESS;
• NOTE:
Typical way to model flip-flop behavior
– Use only for clock signal
– Can be used in synthesis
– Cannot be nested!
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Attributes: low
• Returns the lower bound of array object or type
• General form:
T’LOW and A’LOW [(N)]
• Example:
...
VARIABLE c,b: BIT_VECTOR(5 DOWNTO 0);
...
FOR i IN c’LOW TO 5 LOOP
c(i) := b(i); -- i goes from 0 to 5
END LOOP;

• T’LOW is value kind of attribute and A’LOW is function kind of attribute

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Attributes: left
• Returns the left-most element index of a given type or subtype
• General form:
T’LEFT

• Example:
...
TYPE bit_array IS ARRAY (5 DOWNTO 1) OF BIT;
...
SIGNAL tmp_r : INTEGER;
...
tmp_r <= bit_array’LEFT;
-- tmp_r is assigned with a value of 5

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Array Attributes
TYPE v41 IS (’X’, ’0’, ’1’, ’Z’);
TYPE v4l_4by8 is ARRAY (3 downto 0, 0 to 7) of v41;
Signal s_4by8 : v41_4by8;

More info about

attributes in the
extra section

Source: Zainalabedin Navabi, VHDL: Modular Design and Synthesis of Cores and Systems
2.11.2017 49
VHDL Summary
Language Purpose Other notes C++ counterpart
constructs in VHDL
ENTITY Defines interface. Includes generics and ports ”Public interface”, the actual implementation is Class definition
(their names, widths, and directions). hidden into architecture.

GENERIC Instance-specific constant value Excellent idea in HDL! Constant parameters, templates

PORT I/O pin of an entity. Defines direction and type. See also signal. Method of a class, inter-process
message

ARCHITECTURE Contains functionality. One entity may have many architectures in the Class implementation
library

SIGNAL, Communication channel between They are not the same! Variables only inside Variable
(VARIABLE) components/processes. processes

COMPONENT For instantiating a sub-block Needed for hierarchy. Class instance, object

PROCESS These capture most of the functionality. Processes are executed in parallel. Both seq. Thread
and comb.

IF,FOR,CASE, Control statements Bounds must be known for loops at compile- The same
ASSIGNMENT time

PACKAGE Contains shared definitions. Constants, functions, procedures, types Header file (file.h)

LIBRARY Holds analyzed (’compiled’) codes Standard ieee library is practically always used Compiled object codes (file.o)

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Capabilities Verilog-95,
VHDL, SystemVerilog
• Verilog is another, but primitive HDL
– For some reason, more popular in US and Asia than in Europe
• SystemVerilog is rather new language which adds many handy features for verification

SystemVerilog

( )
VHDL

Verilog-95

51
EXTRA SLIDES ON VHDL

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Shift…
• For bit_vectors: operators: sla, sra, sll, srl…
• For (un)signed: functions shift_left() and shift_right()
• For std_logic_vector: no operators nor built-in functions, you should use slicing
• variable A: bit_vector :=”101101”;
– A sll 2 -- “110100”, filled with zeros
– A sla 2 -- “110111”, filled with LSB!
• sla is rather strange operator in VHDL

– A srl 2 -- “001011”, filled with zeros

– A sra 2 -- “111011”, filled with MSB

grey color denotes

– A rol 2 -- “110110”
– A ror 2 -- “011011”
inserted bits
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Configurations
• Links entity declaration and architecture body together
– Apply to structural description (one that instantiates components)
• Concept of default configuration is a bit messy in VHDL ’87
– Last architecture analyzed links to entity?
• Can be used to change simulation behaviour without re-analyzing the VHDL
source
• Complex configuration declaration are ignored in synthesis
• Some entities can have, e.g., gate level architecture and behavioral
architecture
• Are always optional

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Configuration Example
ARCHITECTURE configurable OF multiplexer IS
COMPONENT n2
PORT (
a: IN std_logic; CONFIGURATION
b: IN std_logic;
y: std_logic is in its own section
); in VHDL file, not
END COMPONENT;
SIGNAL sbar, asel, bsel : std_logic; within entities or
BEGIN architectures.
U1: n2 PORT MAP (a => s, b => s, y => sbar);
U2: n2 PORT MAP (a => x, b => sbar, y => asel);
END ARCHITECTURE configurable; Component
Mapping of ”n2” used
component n2
Use entity
nand2_t with
CONFIGURATION example_cfg OF multiplexer IS architecture
FOR configurable arch_2
FOR ALL : n2
USE ENTITY WORK.nand2_t (arch_2)
GENERIC MAP (cc_delay_g => 3);
END FOR;
END FOR;
END CONFIGURATION example_cfg; Generic for
the nand2_t
2.11.2017 55
Resolution Function
• Describes the resulting value when two or more different values are
driven onto a signal (more than one driver exists)
• Enables resolved data types
• Multi-value logic, implementation of three-state drivers

56
Type Conversion Between
Number-Related Data Types

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Attributes: high
• Returns the upper bound of array object or type
• General form:
T’HIGH and A’HIGH [(N)]
• Example:
...
VARIABLE c,b: BIT_VECTOR(5 DOWNTO 0);
...
FOR i IN c’HIGH DOWNTO C’LOW LOOP
c(i) := b(i); -- i goes from 5 to 0
END LOOP;
• T’HIGH is value kind of attribute and A’HIGH is function kind of attribute

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Attributes: right
• Returns the right-most bound of a given type or subtype
• General form:
T’RIGHT
• Example:
...
TYPE bit_array IS ARRAY (5 DOWNTO 1) OF BIT;
...
SIGNAL tmp_r : INTEGER;
...
tmp_r <= bit_array’RIGHT;
-- r is assigned with a value of 1

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Attributes: length
• Returns the length (number of elements) of an array
• General form:
A’LENGTH[(n)]
• Example:
...
TYPE bit_array IS ARRAY (31 TO 0) OF BIT;
...
SIGNAL len : INTEGER;
...
len <= bit_array’LENGTH;
-- LEN is assigned with a value of 32

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Attributes: range
• Returns the range of array object or array subtype
• General form:
A’RANGE and A’REVERSE_RANGE [(N)]
• Example:
...
SIGNAL c,b: std_logic_vector(5 DOWNTO 0);
...
FOR i IN c’RANGE LOOP
c(i) <= b(i); -- i goes from 5 to 0
END LOOP;
• NOTE:
– T’RANGE doesn’t exists

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Attribute Examples
• Signal d: std_logic_vector(7 downto 0)
– d’LOW = 0
– d’HIGH = 7
– d’LEFT = 7
– d’RIGHT = 0
– d’LENGTH = 8
– d’RANGE =(7 downto 0)
– d’REVERSE_RANGE=(0 to 7)
• Unfortunately, these cannot be applied to, e.g., a specific integer
– Only infromation type integer is obtainable, not about it’s instantiation
– integer’high, integer’low
– Not:
signal d : integer range 0 to 3;
d’high, d’low; -- does not work

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Attributes: active
• Returns value true if any transaction occured during the current delta, and otherwise
returns value false
• General form:
S’ACTIVE
• Example:
PROCESS(clk)
BEGIN
IF clk’ACTIVE AND clk=’1’ THEN
q <= d; AVOID
END IF;
END PROCESS; !
• NOTE:
Synthesis tools may not work correctly, use ’EVENT instead
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Attributes: stable
• Creates a boolean signal that is true whenever the reference signal has had no
events for the time specified by the optional time expression
• General form:
S’STABLE [(time)]
• Example:
PROCESS(clk)
BEGIN
IF NOT(clk’STABLE) AND clk= ’1’ THEN
q <= d;
END IF; AVOID
END PROCESS;
!
• NOTE:
Used to model flip-flop behaviour. Not so efficient as event.
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Type Attributes
TYPE v41 IS (‘X’, ’0’, ‘1' ,’Z' );
SUBTYPE v31 IS v41 RANGE ‘0' TO ‘Z’;
SUBTYPE v21 IS v41 RANGE ‘0‘ TO ‘1';
TYPE opcode IS (sta, lda, add, sub,
and, nop, jmp, jsr);

Source: Zainalabedin Navabi, VHDL: Modular

Design and Synthesis of Cores and Systems
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Block Statement
• Partitioning mechanism that allows design to group logically areas of design

ARCHITECTURE behav OF cpu IS

BEGIN
alu : BLOCK
BEGIN
statements
END BLOCK alu;

regs : BLOCK
BEGIN
statements
END BLOCK regs;
END behav;

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Guarded Block
• A block containing boolean expression which can enable and disable driver inside a block

ARCHITECTURE behav OF guarded_latch IS

BEGIN
latch : BLOCK(clk = ‘1’)
BEGIN
q <= GUARDED d AFTER 3ns;
qn <= GUARDED NOT(d) AFTER 5;
END BLOCK latch;
END guarded_latch Not
synthesizable
• Not synthesizable !

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Guarded Signal Assignment
• Like sequential signal assignment except guarded expression
• General form:
target <= [quarded] [transport] expr [after t_expr{,
expr after t_expr} ];
• Example, guarded signal assignment:
BLOCK (enable = ‘1’) AVOID
q <= GUARDED d AFTER 10 ns; !
END BLOCK
• When enable = ‘1’, d is asssigned to q after 10 ns, otherwise q and d
are disconnected
– I.e., changes in d are not reflected in q

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