UNITED INSTITUTE OF TECHNOLOGY

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INTERNAL ASSESSMENT EXAMINATION-III
SIXTH SEMESTER (2015-2016)
Electronics and Communication Engineering
CS6303 - COMPUTER ARCHITECTURE
Time: Three hours
Maximum: 100 marks
Answer ALL questions.
PART A (10 2 = 20 marks)
1. Define Processor clock and clock rate.
2. What are the ways to truncate guard bits?
3. How overflow occur in subtraction?
4. What do you meant by sub word parallelism?
5. What are the overflow/underflow conditions for addition and subtraction?
6. What is the advantage of non restoring over restoring division method?
7. Define the terms hit, miss ratio with respect to cache.
8. Where is a TLB located and what does it contain?
9. What is DMA? Mention its advantages.
10. What is cycle stealing in DMA?
PART B (16 5 = 80 marks)
11. a) Explain in detail the various components of computer system with neat diagram.
(16)
(or)
b) State the CPU performance evaluation and discuss the factors that affect the performance.(16)
12. a) Explain in detail about the multiplication algorithm with suitable example and diagram.
(16)
(or)
b) With flowchart and numerical example, explain 32-bit Boolean number representation of
division Hardware.
(16)
13. a) With relevant diagram and expressions, explain the operation of carry look ahead adder.
(16)
(or)
b) Explain booths algorithm with an example.
(16)
14. a) Draw the typical block diagram of a DMA controller and explain how it is used for direct data
transfer between memory and peripherals?
(16)
(or)
b) What is the need for an I/O interface? Describe the functions of SCSI interface with a neat
diagram.
(16)
15. a) What is virtual memory? Explain the steps involved in virtual memory address translation.
.
(16)
(or)
b) Explain the structure of the cache memory with its characteristics and mapping techniques.
.
(16)

QUESTION PAPER SETTER

HOD

PRINCIPAL

INTERNAL ASSESSMENT EXAMINATION-III

SIXTH SEMESTER (2015-2016)
Electronics and Communication Engineering
CS6303 - COMPUTER ARCHITECTURE
ANSWER KEY
Time: Three hours
Maximum: 100 marks
Answer ALL questions.
PART A (10 2 = 20 marks)
1. Define Processor clock and clock rate.
Processor clock is defined as the time periods in which all operations and data transfers
within the processor take place.
The clock rate typically refers to the frequency at which a chip like a central processing
unit (CPU), one core of a multi-core processor, is running and is used as an indicator of
the processor's speed. It is measured in clock cycles per second or its equivalent, the SI unit
hertz (Hz).
2. What are the ways to truncate guard bits?
1.Chopping
2.Von Neumann rounding
3.Rounding procedure
3. How overflow occur in subtraction?
When operand 1 is subtracted from operand 2 ,if operand 2 is greater than operand 1 (i.e)borrow
will occur.This condition is called as overflow in subtraction.
4. What do you meant by sub word parallelism?
Subword Parallelism is a technique that enables the full use of word-oriented datapaths
when dealing with lower-precision data. It is a form of low-cost, small-scale SIMD parallelism
5. What are the overflow/underflow conditions for addition and subtraction?
The term arithmetic underflow (or "floating point underflow", or just "underflow") is a
condition in a computer program where the result of a calculation is a smaller number than the
computer can actually store in memory.
Arithmetic underflow can occur when the true result of a floating point operation is smaller
in magnitude (that is, closer to zero) than the smallest value representable as a normalfloating
point number in the target datatype. Underflow can in part be regarded as negative overflow of
the exponent of the floating point value. For example, if the exponent part can represent values
from 127 to 127, then a result with a value less than 127 may cause underflow.
6. What is the advantage of non restoring over restoring division method?
In restoring division algorithm,when a subtraction step involving the divisor yields a
negative result,the register containing the remainder is restored,but in non restoring
divisionalgm,the remainder does not have to be restored at any stage of the calculation.

7. Define the terms hit, miss ratio with respect to cache.

HIT:
The number of hits stated as a fraction of all attempted access .

MISS RATIO:
The miss ratio is the fraction of accesses which are a miss. It holds that. miss rate=1hit
rate. miss rate = 1 hit rate . The (hit/miss) latency (AKA access time) is the time it takes to
fetch the data in case of a hit/miss.
8. Where is a TLB located and what does it contain?
A translation lookaside buffer (TLB) is a cache that memory management
hardware uses to improve virtual address translation speed.[1] The majority of desktop, laptop,
and server processors includes one or more TLBs in the memory management hardware, and it is
nearly always present in any hardware that utilizes paged or segmented virtual memory.
9. What is DMA? Mention its advantages.
Transfer of a block of data directly between an external device and main memory, with
out continuous intervention by the processor is called DMA.DMA allows a peripheral device to
read from/write to memory without going through the CPU. DMA allows for faster processing
since the processor can be working on something else while the peripheral can be populating
memory.
10. What is cycle stealing in DMA?
The processor originates most memory access cycles and the DMA controller can be
said to stael memory cyckles from the processor.This technique is known as cycle stealing.
Where is a TLB located and what does it contain?
PART B (16 5 = 80 marks)
11.a) Explain in detail the various components of computer system with neat diagram.
(16)

A computer can process data, pictures, sound and graphics. They can solve highly complicated problems quickly
and accurately. A computer as shown in Fig. performs basically five major computer operations or functions
irrespective of their size and make. These are
1) it accepts data or instructions by way of input,
2) it stores data,
3) it can process data as required by the user,
4) it gives results in the form of output, and
5) it controls all operations inside a computer.
FUNCTIONAL UNITS
In order to carry out the operations mentioned in the previous section the computer allocates the task between its
various functional units. The computer system is divided into three separate units for its operation. They are
1) arithmetic logical unit
2) control unit.
3) central processing unit.

(or)
b) State the CPU performance evaluation and discuss the factors that affect the performance.(16)
Computer performance is characterized by the amount of useful work accomplished by a
computer system or computer network compared to the time and resources used. Depending on the
context, high computerperformance may involve one or more of the following: Short response time for
a given piece of work.
CPU Performance Decomposed into Three Components:
Clock Frequency ()
Determined by technology and influenced by organization.
Clocks per Instruction (CPI) Determined by ISA, microarchitecture, compiler, and program.
Instruction Count (IC) Determined by program, compiler, and ISA.
These combined to form CPU Performance Equation tT = 1/ CPI IC , where tT denotes the
execution time.

Given a program there are two ways instructions could be tallied:

Static Instruction Count: The number of instructions making up the program.
Dynamic Instruction Count (IC): The number of instructions executed in a run of the program.
For estimating performance, dynamic instruction count is used.
Cycles (clocks) per Instruction (CPI) Oversimplified definition: CPI: Average number of cycles needed
to execute an instruction.
12.a) Explain in detail about the multiplication algorithm with suitable example and diagram.
(16)

(or)
b) With flowchart and numerical example, explain 32-bit Boolean number representation of
division Hardware.
(16)

13.a) With relevant diagram and expressions, explain the operation of carry look ahead adder.
(16)

(or)

b) Explain booths algorithm with an example.

(16)

14.a) Draw the typical block diagram of a DMA controller and explain how it is used for direct data
transfer between memory and peripherals?

(16)

DMA Transfer Types

Memory To Memory Transfer
In this mode block of data from one memory address is moved to another memory address. In
this mode current addressregister of channel 0 is used to point the source address and the
current address register of channel is used to point the destination address in the first transfer
cycle, data byte from the source address is loaded in the temporary register of the DMA
controller and in the next transfer cycle the data from the temporary register is stored in the
memory pointed by destination address. After each data transfer current address registers are
decremented or incremented according to current settings. The channel 1 current word count
register is also decremented by 1 after each data transfer. When the word count of channel 1
goes to FFFFH, a TC is generated which activates EOP output terminating the DMA service.
Auto initialize
In this mode, during the initialization the base address and word count registers are loaded
simultaneously with the current address and word count registers by the microprocessor. The
address and the count in the base registers remain unchanged throughout the DMA service.
After the first block transfer i.e. after the activation of the EOP signal, the original values of the
current address and current word count registers are automatically restored from the base
address and base word count register of that channel. After auto initialization the channel is
ready to perform another DMA service, without CPU intervention.
(or)

b) What is the need for an I/O interface? Describe the functions of SCSI interface with a neat diagram.
(16)
In computing, input/output or I/O (or, informally, io or IO) is the communication between
an information processing system, such as a computer, and the outside world, possibly a human or
another information processing system. Inputs are the signals or data received by the system and
outputs are the signals or data sent from it. The term can also be used as part of an action; to "perform
I/O" is to perform an input or output operation. I/O devices are used by a human (or other system) to
communicate with a computer.

15.a) What is virtual memory? Explain the steps involved in virtual memory address translation.
.
(16)
Virtual memory is a feature of an operating system (OS) that allows a computer to
compensate for shortages of physical memory by temporarily transferring pages of data from
random access memory(RAM) to disk Storage

In a virtual memory system, the program memory is divided into fixed sized pages and allocated
in fixed sized physical memory frames. The pages do not have to be contiguous in memory. A page
table keeps track of where each page is located in physical memory. This allows the operating system to
load a program of any size into any available frames. Only the currently used pages need to be loaded.
Unused pages can remain on disk until they are referenced. This allows many large programs to be
executed on a relatively small memory system. A resident flag in the page table indicates whether or not
the page is in memory. The page table also includes several other flags to keep track of memory usage.
A use flag is set whenever the page is referenced. A dirty bit is set whenever the page is changed to
inform the operating system that the page in memory is different than the page on disk.

There are several virtual memory parameters set by a system designer:

Maximum Virtual Address space

The size of a program address is determined by the maximum size

of the virtual address space. The number of bits in a virtual
address is the log base 2 of this value.

Maximum Physical Address space

The amount of real memory that the system can support

determined the number of bits needed to address the physical
memory. The size of a physical address is log base 2 of this value.

Size of a page

This is the size of a virtual memory page and a physical memory

frame. It is always a power of 2.

The addresses that appear in programs are the virtual addresses or program addresses. For every
memory access, either to fetch an instruction or data, the CPU must translate the virtual address to a real
physical address. A virtual memory address can be considered to be composed of two parts: a page
number and an offset into the page. The page number determines which page contains the information
and the offset specifies which byte within the page. The size of the offset field is the log base 2 of the
size of a page.
Consider an example system with:

16MB Maximum Virtual Address space (24 bits)

8MB Maximum Physical Address space (23 bits)
1024byte Page size (10 bits)
The virtual addresses can be represented as
13 bits

10 bits

page number

offset

To convert a virtual address into a physical address, the CPU uses the page number as an index into the
page table. If the page is resident, the physical frame address in the page table is concatenated in front
of the offset to create the physical address.

(or)
b) Explain the structure of the cache memory with its characteristics and mapping techniques.
.
(16)
Cache memory, also called CPU memory, is random access memory (RAM) that a
computer microprocessor can access more quickly than it can access regular RAM.
Thismemory is typically integrated directly with the CPU chip or placed on a separate chipthat
has a separate bus interconnect with the CPU.

Memory cache configurations

Caching configurations continue to evolve, but memory cache traditionally works under three
different configurations:

Direct mapping, in which each block is mapped to exactly one cache location. Conceptually,
this is like rows in a table with three columns: the data block or cache line that contains the actual
data fetched and stored, a tag that contains all or part of the address of the fetched data, and
a flag bit that connotes the presence of a valid bit of data in the row entry.

Fully associative mapping is similar to direct mapping in structure, but allows a block to be
mapped to any cache location rather than to a pre-specified cache location (as is the case with direct
mapping).

Set associative mapping can be viewed as a compromise between direct mapping and fully
associative mapping in which each block is mapped to a subset of cache locations. It is sometimes
called N-way set associative mapping, which provides for a location in main memory to be cached
to any of "N" locations in the L1 cache.

QUESTION PAPER SETTER

HOD

PRINCIPAL