Basic Computer Organization and Design

Basic Computer Organization & Design
BASIC COMPUTER ORGANIZATION AND DESIGN
• Instruction Codes
• Computer Registers
• Computer Instructions
• Timing and Control
• Instruction Cycle
• Memory Reference Instructions
• Input-Output and Interrupt
• Complete Computer Description
• Design of Basic Computer
• Design of Accumulator Logic
1
Basic Computer Organization & Design Instruction codes
INSTRUCTION CODES
• Program:
A set of instructions that specify the operations, operands, and the
sequence by which processing has to occur
• Instruction Code:
A group of bits that tells the computer to perform a specific operation
• Instruction Code Format:
Opcode Operand (or Address)
- Operation code:
• A group of bits that define the operation (add, subtract, shift)
• The operation (or macrooperation) specifies a set of microoperations
- Operand (or address of operand)
• Data stored in registers or in the memory, on which the operation is to
be performed
2
STORED PROGRAM ORGANIZATION
24 = 16 operations 212 = 4096 words
Memory
4096 x 16
4 bits 12 bits
15 12 11 0
Instructions
Opcode Address
(program)
Instruction Format
15 0 Operands
Binary Operand (data)
15 0
Processor register
(Accumulator or AC)
3
ADDRESSING MODES
Opcode Operand (or Address)
Instruction Format
• Immediate Mode
Second part of instruction specifies an operand
• Direct Address Mode

Second part of instruction specifies the address of an operand
• Indirect Address Mode

Second part of instruction specifies an address of a memory
word in which the address of the operand is found
4
INDIRECT ADDRESS
Instruction Format
15 14 12 11 0
I = 0  Direct address
I Opcode Address I = 1  Indirect address
Direct Address Indirect address
22 0 ADD 457 35 1 ADD 300
300 1350
457 Operand
1350 Operand
Effective
Address
+ +
AC AC
Effective Address(EFA, EA)

The address of the operand in a computation-type instruction,
or the target address in a branch-type instruction
5
INSTRUCTION FORMAT - Example
Problem 5-1: A computer uses a memory unit with 256K words of 32 bits
each. A binary instruction code is stored in one word of memory. The
instruction has four parts: an indirect bit, an operation code, a register
code part to specify one of 64 registers, and an address part.
a. How many bits are there in the operation code, the register code part,
and the address part?
b. Draw the instruction word format and indicate the number of bits in
each part?
c. How many bits are there in the data and address inputs of the
memory?
6
Basic Computer Organization & Design Registers
COMPUTER REGISTERS
Registers in the Basic Computer (BC)
11 0
PC
11 0
AR Memory
15 0
4096 x 16
IR
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC
List of BC Registers
Symbol # of bits Name Function
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
7
Basic Computer Organization & Design Registers
COMMON BUS SYSTEM

S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1
LD INR CLR Bus Selection

PC 2 selected
S2 S1 S0 register
AC extended LD INR CLR
bit flip-flop for 0 0 0 none
carry-out and DR 3 0 0 1 AR
circulation 0 1 0 PC
LD INR CLR 0 1 1 DR
1 0 0 AC
Adder E 1 0 1 IR
and AC 4 1 1 0 TR
logic 1 1 1 Memory
LD INR CLR
INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
8
COMMON BUS SYSTEM - Example
Problem 5-4: The following register transfers are to be executed in the

basic computer (Figure 5-4). For each transfer, specify:
(1) the binary value that must be applied to bus select inputs S2, S1 and S0;
(2) the register whose LD control input must be active (if any);
(3) a memory read or write operation (if needed); and
(4) the operation in the adder and logic circuit (if any).
a. AR ← PC
b. IR ← M[AR]
c. M[AR] ← TR
d. AC ← DR, DR ← AC
9
Basic Computer Organization & Design Instructions
COMPUTER INSTRUCTIONS
Basic Computer Instruction Code Format
Memory-Reference Instructions (Opcode = 000 ~ 110)

15 14 12 11 0
I Opcode Address
Register-Reference Instructions (Opcode = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation
Input-Output Instructions (Opcode =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation
10
BASIC COMPUTER INSTRUCTIONS

Hex Code
Symbol I = 0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
Memory-Reference Instructions ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
15 14 12 11 0 STA 3xxx Bxxx Store content of AC into memory
I Opcode Address BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
000 - 110 ISZ 6xxx Exxx Increment and skip if zero
CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
Register-Reference Instructions CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
15 12 11 0 INC 7020 Increment AC
0 1 1 1 Register operation SPA 7010 Skip next instruction if AC is positive
SNA 7008 Skip next instruction if AC is negative
SZA 7004 Skip next instruction if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer
INP F800 Input character to AC

Input-Output Instructions OUT F400 Output character from AC
SKI F200 Skip on input flag
15 12 11 0 SKO F100 Skip on output flag
1 1 1 1 I/O operation ION F080 Interrupt on
IOF F040 Interrupt off
11
INSTRUCTION SET COMPLETENESS

A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function that is
known to be computable.
Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT
12
Basic Computer Organization & Design Timing and control
TIMING AND CONTROL

Control unit of basic computer
Instruction register (IR)
15 14 13 12 11 - 0 Other inputs
3x8
decoder
7 6543 210
D0
I .. Control
D7 Control
logic outputs
T15
gates
..
T0
15 14 . . . . 2 1 0
4 x 16
decoder
4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock
Control unit implementation

- Hardwired Implementation
- Micro programmed Implementation
13
TIMING SIGNALS
- Generated by 4-bit sequence counter and 4x16 decoder
- The SC can be incremented or cleared.
-Example: T0, T1, T2, T3, T4, T0, T1, . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC ← 0
T0 T1 T2 T3 T4 T0
Clock
T0
T1
T2
T3
T4
D3
CLR
SC
COUNT 0 1 2 3 4 0 1
14
TIMING SIGNALS
- Example: T0: AR ← PC 0 S2
1 S1 Bus
0 S0
AR 1
T0
LD
PC 2
Clock
Common bus
T0 T1
Clock
T0
T1
COUNT 0 1 2
Transfer occurs here
15
Basic Computer Organization & Design Instruction Cycle
INSTRUCTION CYCLE
Phases of Instruction cycle

- Fetch Instruction from memory
- Decode the instruction
- Read effective address from memory if the instruction has indirect address
- Execute the instruction
16
INSTRUCTION CYCLE
BC Instruction cycle: [Fetch Decode [Indirect] Execute]
Fetch T0: AR ← PC
T1: IR ← M[AR], PC ← PC + 1
Decode T2: D0, . . . , D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)
T1 S2
Control Signals: T0 S1 Bus

– When T0 =1: S0
» S2S1S0 = 010 Memory 7
» AR(LD) = 1 unit
Address
– When T1 = 1: Read
» S2S1S0 = 111
» Read = 1 AR 1
» IR(LD) = 1
LD
» PC(INC) = 1
PC 2
– When T2 = 1:
» S2S1S0 = 101 INR
» AR(LD) = 1
IR 5
LD Clock
Common bus
17
DETERMINE THE TYPE OF INSTRUCTION

Start
SC ← 0
T0
AR ← PC
T1
IR ← M[AR], PC ← PC + 1
T2
Decode Opcode in IR(12-14),
AR ← IR(0-11), I ← IR(15)
(Register or I/O) = 1 = 0 (Memory-reference)

D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I
T3 T3 T3 T3
Execute Execute AR ← M[AR] Nothing
input-output register-reference
instruction instruction
SC ← 0 SC ← 0 Execute
memory-reference
instruction
SC ← 0
D7' I T3: AR ← M[AR]

D7' I' T3: Nothing
D7 I' T3: Execute a register-reference instruction
D7 I T3: Execute an input-output instruction
18
REGISTER REFERENCE INSTRUCTIONS

I Opcode Register Operation
Symbol HEX B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CLA 7800 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
CLE 7400 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0
CMA 7200 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0
: : : : : :
SZA 7004 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0
SZE 7002 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0
HLT 7001 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1
r = D7 I’ T3 Bi = IR(i) , i=0,1,2,...,11
r: SC ← 0 Clear SC
CLA rB11: AC ← 0 Clear AC
CLE rB10: E←0 Clear E
CMA rB9: AC ← AC’ Complement AC
CME rB8: E ← E’ Complement E
CIR rB7: AC ← shr AC, AC(15) ← E, E ← AC(0) Circulate right
CIL rB6: AC ← shl AC, AC(0) ← E, E ← AC(15) Circulate left
INC rB5: AC ← AC + 1 Increment AC
SPA rB4: if (AC(15) = 0) then (PC ← PC+1) Skip if AC positive
SNA rB3: if (AC(15) = 1) then (PC ← PC+1) Skip if AC negative
SZA rB2: if (AC = 0) then (PC ← PC+1) Skip if AC zero
SZE rB1: if (E = 0) then (PC ← PC+1) Skip if E zero
HLT rB0: S ← 0 (S is a start-stop flip-flop) Halt computer
19
REGISTER REFERENCE INSTRUCTIONS - Example
Problem 5-9: The content of AC in the basic computer is hexadecimal

A937 and the initial value of E is 1. Determine the contents of AC, E, PC,
AR and IR in hexadecimal after the execution of the CLA instruction. The
initial value of PC is hexadecimal 021.
CLA instruction cycle:
T0: AR ← PC
T1: IR ← M [AR], PC ← PC + 1
T2: D0,…,D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)
D7I'T3B11: AC ← 0, SC ← 0
20
Basic Computer Organization & Design MR Instructions
MEMORY REFERENCE INSTRUCTIONS

T0: AR ← PC
T1: IR ← M [AR], PC ← PC + 1
T2: D0, . . . , D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)
D'7IT3: AR ← M[AR]
D'7I'T3: Nothing
Operation
Symbol Symbolic Description
Decoder
AND D0 AC ← AC ∧ M[AR]
ADD D1 AC ← AC + M[AR], E ← Cout
LDA D2 AC ← M[AR]
STA D3 M[AR] ← AC
BUN D4 PC ← AR
BSA D5 M[AR] ← PC, PC ← AR + 1
ISZ D6 M[AR] ← M[AR] + 1, if M[AR] + 1 = 0 then PC ← PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a clock cycle
- The execution of memory reference Instruction starts with T4
21

Symbol Symbolic Description
AND AC ← AC ∧ M[AR]
ADD AC ← AC + M[AR], E ← Cout
LDA AC ← M[AR]
STA M[AR] ← AC
AND to AC
D0T4: DR ← M[AR] Read operand
D0T5: AC ← AC ∧ DR, SC ← 0 AND with AC
ADD to AC
D1T4: DR ← M[AR] Read operand
D1T5: AC ← AC + DR, E ← Cout, SC ← 0 Add to AC and store carry in E
LDA: Load to AC
D2T4: DR ← M[AR]
D2T5: AC ← DR, SC ← 0
STA: Store AC
D3T4: M[AR] ← AC, SC ← 0
22

BUN: Branch Unconditionally
D4T4: PC ← AR, SC ← 0
Memory, PC, AR at time T4 Memory, PC after execution

20 0 BUN 135 20 0 BUN 135
PC = 21 Next Instruction
Next instruction in
program sequence
AR = 135 Instruction PC = 135 Next instruction
Program jumps
to instruction
out of sequence
Memory Memory
PC ← 135
23

BSA: Branch and Save Return Address
M[AR] ← PC, PC ← AR + 1
Memory, PC, AR at time T4 Memory, PC after execution

20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction
Subroutine call
Return address
AR = 135 135 21
136 Subroutine PC = 136 Subroutine
Subroutine return
1 BUN 135 1 BUN 135

Memory Memory
M[135] ← 21, PC ← 135 + 1 = 136
BSA:
D5T4: M[AR] ← PC, AR ← AR + 1
D5T5: PC ← AR, SC ← 0
24
ISZ: Increment and Skip if Zero

M[AR] ← M[AR] + 1, if (M[AR] + 1 = 0) then (PC ← PC + 1)
ISZ:
D6T4: DR ← M[AR]
D6T5: DR ← DR + 1
D6T6: M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ← 0
25
FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS
Memory-reference instruction
AND ADD LDA STA BUN BSA ISZ
D0T4 D 3T4 D4T4 D 5T 4 D6T4

D1T4 D2T4
M[AR] ← AC PC ← AR M[AR] ← PC DR ← M[AR]
DR ← M[AR] DR ← M[AR] DR ← M[AR]
SC ← 0 SC ← 0 AR ← AR + 1
D0T5 D1T 5 D2T5
D5T 5 D6T5
AC ← AC ∧ DR AC ← AC + DR AC ← DR
SC ← 0 E ← Cout SC ← 0 PC ← AR DR ← DR + 1
SC ← 0 SC ← 0
D6T6
M[AR] ← DR
If (DR = 0)
then (PC ← PC + 1)
SC ← 0
26
MEMORY REFERENCE INSTRUCTIONS - Example
Problem 5-11: Show the contents in hexadecimal of registers PC, AR, DR,
IR, and SC of the basic computer when an ISZ indirect instruction is
fetched from memory and executed: The initial content of PC is 7FF. The
content of memory at address 7FF is EA9F. The content of memory at
address A9F is 0C35. The content of memory at address C35 is FFFF.
Give the answer in a table with five columns, one for each register and a
row for each timing signal.
ISZ instruction cycle:

T0: AR ← PC
T1 : IR ← M [AR], PC ← PC + 1
T2: D0,…,D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)
if (indirect) D'7IT3: AR ← M[AR]
if (direct) D'7I'T3: Nothing
D6T4: DR ← M[AR]
D6T5: DR ← DR + 1
D6T6: M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ← 0
27
MEMORY REFERENCE INSTRUCTIONS - Example
Problem 5-13: In the Basic Computer, we want to change some memory

reference instructions. Give the sequence of register transfer statements
needed to execute the following new instruction starting from timing T4.
EA is the effective address that resides in AR during timing T4.
Symbol Opcode Symbolic description Description in words

XOR 000 AC ← AC ⊕ M[EA] Exclusive-OR to AC
28
Basic Computer Organization & Design I/O and Interrupt
INPUT-OUTPUT AND INTERRUPT
Input-Output Configuration
Serial Computer
Input - output communication registers and
terminal interface flip-flops
Printer Receiver
interface OUTR FGO
INPR Input register - 8 bits
OUTR Output register - 8 bits
FGI Input flag FF - 1 bit AC
FGO Output flag FF - 1 bit
Keyboard Transmitter
interface INPR FGI
Serial Communications Path

Parallel Communications Path
- FGI set to 1 by input device when information transmitted to INPR

- FGI cleared to 0 by computer when information transferred from INPR into AC
- FGO cleared to 0 by computer when information transferred from AC into OUTR
- FGO set to 1 by output device when information received from OUTR
29
PROGRAMMED CONTROL DATA TRANSFER

Input Data Transfer
-- CPU -- -- I/O Device --

/* Initially FGI = 0 */ (i.e.; INPR empty)
loop: If FGI = 1 goto loop (i.e.; not read)
loop: If FGI = 0 goto loop (i.e.; no data) INPR ← new data, FGI ← 1
AC ← INPR, FGI ← 0
Start
FGI ← 0
yes
FGI=0
no
AC ← INPR
yes More
Character
no
END
30
PROGRAMMED CONTROL DATA TRANSFER

Output Data Transfer
-- CPU -- -- I/O Device --
/* Initially FGO = 1 */ (i.e.; OUTR empty)
loop: If FGO = 1 goto loop (i.e.; no data)
loop: If FGO = 0 goto loop (i.e.; not read)
consume OUTR, FGO ← 1
OUTR ← AC, FGO ← 0
Start
AC ← Data
yes
FGO=0
no
OUTR ← AC
FGO ← 0
yes More
Character
no
END
31
INPUT-OUTPUT INSTRUCTIONS
Symbol HEX_
INP F800
OUT F400
SKI F200
SKO F100
D7IT3 = p ION F080
IR(i) = Bi, i = 6, …, 11 IOF F040
p: SC ← 0 Clear SC
INP pB11: AC(0-7) ← INPR, FGI ← 0 Input char. to AC
OUT pB10: OUTR ← AC(0-7), FGO ← 0 Output char. from AC
SKI pB9: if (FGI = 1) then (PC ← PC + 1) Skip on input flag
SKO pB8: if (FGO = 1) then (PC ← PC + 1) Skip on output flag
ION pB7: IEN ← 1 Interrupt enable on
IOF pB6: IEN ← 0 Interrupt enable off
32
PROGRAM-CONTROLLED INPUT/OUTPUT
• Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware
Input
LOOP, SKI /Check input flag
BUN LOOP /FGI=0, branch to check again
INP /FGI=1, input character
Output
LOOP, SKO /Check output flag
BUN LOOP /FGO=0, branch to check again
OUT /FGO=1, output character
33
INTERRUPT INITIATED INPUT/OUTPUT

- Open communication only when some data has to be passed  interrupt
- The I/O interface, instead of the CPU, monitors the I/O device
- When the interface finds that the I/O device is ready for data transfer, it
generates an interrupt request to the CPU
- Upon detecting an interrupt, the CPU stops momentarily the task

it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing
* IEN (Interrupt-enable flip-flop)
- can be set and cleared by instructions

- when cleared, the computer cannot be interrupted
34
FLOWCHART FOR INTERRUPT CYCLE
R = Interrupt FF
Instruction cycle =0 =1 Interrupt cycle
R
Fetch and decode Store return address

instruction in location 0
M[0] ← PC
Execute =0
IEN
instruction
=1 Branch to location 1
PC ← 1
=1
FGI
=0
IEN ← 0
=1
FGO R←0
=0
R←1
35
DEMONESTRATION OF INTERRUPT CYCLE
Memory
Interrupt cycle
Before interrupt After interrupt cycle
0 0 256
Store return address
in location 0 1 0 BUN 1120 PC = 1 0 BUN 1120
M[0] ← PC
255 Main 255 Main

PC = 256 Program 256 Program
Branch to location 1
PC ← 1
SKI
BUN NEXT
1120 1120
I/O INP
IEN ← 0 I/O NEXT, SKO
R←0 Program Program
BUN EXIT
OUT
1 BUN 0 1 BUN 0 EXIT, ION
Problem 5-18:
An output program resides in memory starting from address 2300.
a. What instruction must be placed at address 1?
b. What must be the last two instructions of the output program?
36
REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE
Instruction cycle =0 =1 Interrupt cycle

R
Fetch and decode Store return address

instruction in location 0
M[0] ← PC
Execute =0
IEN
instruction
=1 Branch to location 1
PC ← 1
=1
FGI
=0
IEN ← 0
=1
FGO R←0
=0
R←1
T0’T1’T2’ (IEN)(FGI + FGO): R ← 1
RT0: AR ← 0, TR ← PC
RT1: M[AR] ← TR, PC ← 0
RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0
37
Basic Computer Organization & Design Description
COMPLETE COMPUTER DESCRIPTION
Flowchart of Operations
start
SC ← 0, IEN ← 0, R ← 0
=0 (instruction cycle) =1 (interrupt cycle)

R
R’T0 RT0
AR ← PC AR ← 0, TR ← PC
R’T1 RT1
IR ← M[AR], PC ← PC + 1 M[AR] ← TR, PC ← 0
R’T2 RT2
AR ← IR(0~11), I ← IR(15) PC ← PC + 1, IEN ← 0
D0...D7 ← Decode IR(12 ~ 14) R ← 0, SC ← 0
=1 (Register or I/O) D7 =0 (Memory Ref)
=1 (I/O) =0 (register) =1 (indirect) =0 (direct)

I I
D7IT3 D7I’T3 D7’IT3 D7’I’T3

Execute Execute AR ← M[AR] Nothing
I/O reg-ref
Instruction Instruction
Execute mem-ref
Instruction
38
Microoperations
Fetch R’T0: AR ← PC
R’T1: IR ← M[AR], PC ← PC + 1
Decode R’T2: D0, ..., D7 ← Decode IR(12 ~ 14),
AR ← IR(0 ~ 11), I ← IR(15)
Indirect D7’IT3: AR ← M[AR]
Interrupt
T0’T1’T2’(IEN)(FGI + FGO): R←1
RT0: AR ← 0, TR ← PC
RT1: M[AR] ← TR, PC ← 0
RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0
Memory-Reference
AND D0 T 4 : DR ← M[AR]
D0 T 5 : AC ← AC ∧ DR, SC ← 0
ADD D1 T 4 : DR ← M[AR]
D1 T 5 : AC ← AC + DR, E ← Cout, SC ← 0
LDA D2 T 4 : DR ← M[AR]
D2 T 5 : AC ← DR, SC ← 0
STA D3 T 4 : M[AR] ← AC, SC ← 0
BUN D4 T 4 : PC ← AR, SC ← 0
BSA D5 T 4 : M[AR] ← PC, AR ← AR + 1
D5 T 5 : PC ← AR, SC ← 0
ISZ D6 T 4 : DR ← M[AR]
D6 T 5 : DR ← DR + 1
D6 T 6 : M[AR] ← DR, if(DR=0) then (PC ← PC + 1), SC ← 0
39
Microoperations
Register-Reference
D7I’T3 = r (Common to all register-reference instr)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC ← 0
CLA rB11: AC ← 0
CLE rB10: E←0
CMA rB9: AC ← AC’
CME rB8: E ← E’
CIR rB7: AC ← shr AC, AC(15) ← E, E ← AC(0)
CIL rB6: AC ← shl AC, AC(0) ← E, E ← AC(15)
INC rB5: AC ← AC + 1
SPA rB4: If(AC(15) =0) then (PC ← PC + 1)
SNA rB3: If(AC(15) =1) then (PC ← PC + 1)
SZA rB2: If(AC = 0) then (PC ← PC + 1)
SZE rB1: If(E=0) then (PC ← PC + 1)
HLT rB0: S←0
Input-Output D7IT3 = p (Common to all input-output instructions)

IR(i) = Bi (i = 6,7,8,9,10,11)
p: SC ← 0
INP pB11: AC(0-7) ← INPR, FGI ← 0
OUT pB10: OUTR ← AC(0-7), FGO ← 0
SKI pB9: If(FGI=1) then (PC ← PC + 1)
SKO pB8: If(FGO=1) then (PC ← PC + 1)
ION pB7: IEN ← 1
IOF pB6: IEN ← 0
40
Basic Computer Organization & Design Design of Basic Computer
DESIGN OF BASIC COMPUTER (BC)

Hardware Components of BC
Memory unit: 4096 x 16
Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops: I, S, E, R, IEN, FGI, and FGO
Decoders: 3x8 Opcode decoder, 4x16 timing decoder
Common bus: 16 bits
Control logic gates
Adder and Logic circuit connected to AC
The outputs of the Control Logic Gates are:

- Signals to control the inputs of the nine registers such as LD and INC
- Signals to control the read and write inputs of memory
- Signals to set, clear, or complement the flip-flops
- Signals for S2, S1, S0 to select a source register for the bus
- Signals to control the AC Adder and Logic circuit
41
CONTROL OF REGISTERS AND MEMORY

Address Register; AR
Scan all of the register transfer statements that change the content of AR:
R’T0:
R’T1:
AR ← PC
IR ← M[AR], PC ← PC + 1
R’T0: AR ← PC LD(AR)
R’T2: D0, ..., D7 ← Decode IR(12 ~ 14), R’T2: AR ← IR(0-11) LD(AR)
AR ← IR(0 ~ 11), I ← IR(15)
D7’IT3: AR ← M[AR] D’7IT3: AR ← M[AR] LD(AR)
RT0: AR ← 0, TR ← PC RT0: AR ← 0 CLR(AR)
RT1:
RT2:
M[AR] ← TR, PC ← 0
PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0
D5T4: AR ← AR + 1 INR(AR)
D0T4: DR ← M[AR]
D0T5: AC ← AC ∧ DR, SC ← 0
D1T4: DR ← M[AR] LD(AR) = R'T0 + R'T2 + D'7IT3
D1T5: AC ← AC + DR, E ← Cout, SC ← 0
D2T4: DR ← M[AR] CLR(AR) = RT0
D2T5: AC ← DR, SC ← 0 INR(AR) = D5T4
D3T4: M[AR] ← AC, SC ← 0
D4T4: PC ← AR, SC ← 0
D5T4: M[AR] ← PC, AR ← AR + 1
D5T5: PC ← AR, SC ← 0 12 12
D6T4: DR ← M[AR] From bus AR To bus
D6T5: DR ← DR + 1
D'7
D6T6: M[AR] ← DR, if(DR=0) then (PC ← PC + 1), I
Clock
SC ← 0 LD
T3
T2 INR
CLR
R
Problem 5-21: T0
Derive the control gates D5
associated with PC. T4
42
CONTROL OF REGISTERS AND MEMORY

Memory (Read Input)
Scan all of the register transfer statements that specify a read operation:
R’T : AR ← PC
0
R′T1: IR ← M[AR]
R’T : IR ← M[AR], PC ← PC + 1
1
R’T : D , ..., D ← Decode IR(12 ~ 14),
D7′IT3: AR ← M[AR]
D0T4: DR ← M[AR]
2 0 7
AR ← IR(0 ~ 11), I ← IR(15)
D ’IT : AR ← M[AR]
7 3
D1T4: DR ← M[AR]
RT : AR ← 0, TR ← PC
0
RT : M[AR] ← TR, PC ← 0 D2T4: DR ← M[AR]
D6T4: DR ← M[AR]
1
RT : PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0
2
D0T4: DR ← M[AR]
D0T5: AC ← AC ∧ DR, SC ← 0
D1T4: DR ← M[AR]
D1T5:
D2T4:
AC ← AC + DR, E ← Cout, SC ← 0
DR ← M[AR]
Read = R′T1 + D7′IT3 + (D0 + D1 + D2 + D6 )T4
D2T5: AC ← DR, SC ← 0
D3T4: M[AR] ← AC, SC ← 0 16 16
D4T4: PC ← AR, SC ← 0 From bus
M[AR] ← PC, AR ← AR + 1 D'7 To bus
D5T4: Memory
D5T5: PC ← AR, SC ← 0 I
D6T4: DR ← M[AR]
D6T5: DR ← DR + 1 T3 Read
T1
D6T6: M[AR] ← DR, if(DR=0) then (PC ← PC + 1),
SC ← 0 R
D0
T4
Problem 5-22: D1
Derive the control gates D2

for write input of memory.
D6
43
CONTROL OF FLIP-FLOPS
IEN: Interrupt Enable Flag
pB7: IEN ← 1 (I/O Instruction)
pB6: IEN ← 0 (I/O Instruction)
RT2: IEN ← 0 (Interrupt)
p = D7IT3 (Input/Output Instruction)
D
7
p
I J IEN
Q
B7
T3
B6
K
R
T2
Problem 5-23:
Show the complete logic of interrupt flip-flop R.
44
CONTROL OF COMMON BUS
selected
x1 x2 x3 x4 x5 x6 x7 S2 S1 S0 register
0 0 0 0 0 0 0 0 0 0 none
1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 0 0 0 0 0 1 1 1 1 Memory
x1
x2 S2
Multiplexer
x3
Encoder S1 bus select
x4
x5 inputs
x6 S0
x7
For AR D4T4: PC ← AR
D5T5: PC ← AR Problem 5-24:
Derive the Boolean
logic expression for x2.
x1 = D4T4 + D5T5
45
Basic Computer Organization & Design Design of AC Logic
DESIGN OF ACCUMULATOR LOGIC

Circuits associated with AC 16
Adder and
16 16 16
From DR logic AC
8 circuit To bus
From INPR
LD INR CLR Clock
Control
gates
All the statements that change the content of AC

D0T5: AC ← AC ∧ DR AND with DR
D1T5: AC ← AC + DR Add with DR
D2T5: AC ← DR Transfer from DR
pB11: AC(0-7) ← INPR Transfer from INPR Load
rB9: AC ← AC’ Complement
rB7 : AC ← shr AC, AC(15) ← E Shift right
rB6 : AC ← shl AC, AC(0) ← E Shift left
rB11 : AC ← 0 Clear Clear
rB5 : AC ← AC + 1 Increment Increment
46
CONTROL OF AC REGISTER
D0T5: AC ← AC ∧ DR
D1T5: AC ← AC + DR
D2T5: AC ← DR
pB11: AC(0-7) ← INPR
rB9: AC ← AC’
rB7 : AC ← shr AC, AC(15) ← E
rB6 : AC ← shl AC, AC(0) ← E From Adder 16 16
rB11 : AC ← 0 AC To bus
and Logic
rB5 : AC ← AC + 1
D0 D0T5 Clock
LD
T5 INR
D1 D1T5
CLR
D2 D2T5
T5
p pB11
p = D7IT3
B 11
r rB9
r = D7I’T3
B9
rB7
B7
rB6
B6
rB5
B5
rB11
B 11
47
ADDER AND LOGIC CIRCUIT

4X1 MUX
S’1S’0
S1
Select Output S1 I0
S’1S0
S0
S’1S’0 I0 I1 F
I0 4X1 F S0 S1S’0
S’1S0 I1 MUX
I2
I1
S1S’0 I2 S1S0
I2
I3
S1S0 I3 I3
D0T5
AC(i)
DR(i)
Select Output Ci D1T5

FA
Fi
D0T5 AC ← AC ∧ DR C i+1
D2T5
D1T5 AC ← AC + DR
D2T5 AC ← DR pB11
pB11 AC(0-7) ← INPR INPR(i)
rB9 AC ← AC’ rB9
rB7 AC ← shr AC
rB6 AC ← shl AC rB7
AC(i+1)
rB6
AC(i-1)
48
ADDER AND LOGIC CIRCUIT
One stage of Adder and Logic circuit
DR(i) AC(i)
D0T5
LD
Ci D1T5
FA Ii J Q
D2T5 AC(i)
C i+1
pB11 K
INPR(i)
rB9
One stage of AC register
rB7
AC(i+1)
rB6
AC(i-1)
49

Basic Computer Organization and Design

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Basic Computer Organization & Design

BASIC COMPUTER ORGANIZATION AND DESIGN

• Timing and Control

• Memory Reference Instructions

• Input-Output and Interrupt

• Complete Computer Description

• Design of Basic Computer

• Design of Accumulator Logic

• Instruction Code Format:

Opcode Operand (or Address)

STORED PROGRAM ORGANIZATION

24 = 16 operations 212 = 4096 words

Opcode Operand (or Address)

• Direct Address Mode

• Indirect Address Mode

Direct Address Indirect address

22 0 ADD 457 35 1 ADD 300

Effective Address(EFA, EA)

INSTRUCTION FORMAT - Example

COMMON BUS SYSTEM

LD INR CLR Bus Selection

COMMON BUS SYSTEM - Example

Problem 5-4: The following register transfers are to be executed in the

Basic Computer Instruction Code Format

Memory-Reference Instructions (Opcode = 000 ~ 110)

Register-Reference Instructions (Opcode = 111, I = 0)

Input-Output Instructions (Opcode =111, I = 1)

BASIC COMPUTER INSTRUCTIONS

CLA 7800 Clear AC

INP F800 Input character to AC

INSTRUCTION SET COMPLETENESS

TIMING AND CONTROL

4-bit Increment (INR)

Control unit implementation

Transfer occurs here

Phases of Instruction cycle

Control Signals: T0 S1 Bus

DETERMINE THE TYPE OF INSTRUCTION

(Register or I/O) = 1 = 0 (Memory-reference)

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

D7' I T3: AR ← M[AR]

REGISTER REFERENCE INSTRUCTIONS

REGISTER REFERENCE INSTRUCTIONS - Example

Problem 5-9: The content of AC in the basic computer is hexadecimal

CLA instruction cycle:

MEMORY REFERENCE INSTRUCTIONS

- Memory cycle is assumed to be short enough to complete in a clock cycle

- The execution of memory reference Instruction starts with T4

MEMORY REFERENCE INSTRUCTIONS

MEMORY REFERENCE INSTRUCTIONS

Memory, PC, AR at time T4 Memory, PC after execution

AR = 135 Instruction PC = 135 Next instruction

MEMORY REFERENCE INSTRUCTIONS

Memory, PC, AR at time T4 Memory, PC after execution

1 BUN 135 1 BUN 135

M[135] ← 21, PC ← 135 + 1 = 136

MEMORY REFERENCE INSTRUCTIONS

ISZ: Increment and Skip if Zero

FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS