Pic 17 C 75 X
Pic 17 C 75 X
Pic 17 C 75 X
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
PIC17C756
VDD
VSS
Microcontroller Core Features:
NC
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
Only 58 single word instructions to learn RD1/AD9 10 60 RA0/INT
RD0/AD8 11 59 RB0/CAP1
All single cycle instructions (121 ns) except for RE0/ALE 12 58 RB1/CAP2
program branches and table reads/writes which RE1/OE 13
14
57
56
RB3/PWM2
RE2/WR RB4/TCLK12
are two-cycle RE3/CAP4 15 55 RB5/TCLK3
MCLR/VPP 16 54 RB2/PWM1
Operating speed: TEST 17
PIC17C75X
53 VSS
NC 18 52 NC
- DC - 33 MHz clock input VSS
VDD
19
20
Top View 51
50
OSC2/CLKOUT
OSC1/CLKIN
- DC - 121 ns instruction cycle RF7/AN11 21 49 VDD
RF6/AN10 22 48 RB7/SDO
Memory
RF5/AN9 23 47 RB6/SCK
Device
RF4/AN8 24 46 RA3/SDI/SDA
RF3/AN7 25 45 RA2/SS/SCL
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
PIC17C752 8K 454
RG3/AN0/VREF+
RG2/AN1/VREF-
RG1/AN2
RG0/AN3
RG7/TX2/CK2
RG6/RX2/DT2
RA5/TX1/CK1
RA4/RX1/DT1
RF1/AN5
RF0/AN4
RG4/CAP3
RG5/PWM3
AVDD
AVSS
NC
VSS
VDD
PIC17C756 16K 902
Hardware Multiplier
Interrupt capability
16 level deep hardware stack
Direct, indirect, and relative addressing modes Special Microcontroller Features:
Internal/external program memory execution Power-on Reset (POR), Power-up Timer (PWRT)
Capable of addressing 64K x 16 program memory and Oscillator Start-up Timer (OST)
space Watchdog Timer (WDT) with its own on-chip RC
Peripheral Features: oscillator for reliable operation
50 I/O pins with individual direction control Brown-out Reset
High current sink/source for direct LED drive Code-protection
- RA2 and RA3 are open drain, high voltage Power saving SLEEP mode
(12V), high current (60 mA), I/O pins Selectable oscillator options
Four capture input pins CMOS Technology:
- Captures are 16-bit, max resolution 121 ns Low-power, high-speed CMOS EPROM
Three PWM outputs technology
- PWM resolution is 1- to 10-bits Fully static design
TMR0: 16-bit timer/counter with Wide operating voltage range (2.5V to 6.0V)
8-bit programmable prescaler Commercial and Industrial temperature ranges
TMR1: 8-bit timer/counter Low-power consumption
TMR2: 8-bit timer/counter - < 5 mA @ 5V, 4 MHz
TMR3: 16-bit timer/counter - 100 A typical @ 4.5V, 32 kHz
Two Universal Synchronous Asynchronous - < 1 A typical standby current @ 5V
Receiver Transmitters (USART/SCI)
- Independant baud rate generators
10-bit, 12 channel analog-to-digital converter
Synchronous Serial Port (SSP) with SPI and
I2C modes (including I2C master mode)
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
VDD
VSS
NC
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
RD1/AD9 10 60 RA0/INT
RD0/AD8 11 59 RB0/CAP1
RE0/ALE 12 58 RB1/CAP2
RE1/OE 13 57 RB3/PWM2
RE2/WR 14 56 RB4/TCLK12
RE3/CAP4 15 55 RB5/TCLK3
MCLR/VPP 16 54 RB2/PWM1
TEST 17 PIC17C75X 53 VSS
NC 18 52 NC
VSS 19 Top View 51 OSC2/CLKOUT
VDD 20 50 OSC1/CLKIN
RF7/AN11 21 49 VDD
RF6/AN10 22 48 RB7/SDO
RF5/AN9 23 47 RB6/SCK
RF4/AN8 24 46 RA3/SDI/SDA
RF3/AN7 25 45 RA2/SS/SCL
RF2/AN6 26 44 RA1/T0CKI
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
RG7/TX2/CK2
RG6/RX2/DT2
RA5/TX1/CK1
RA4/RX1/DT1
RF1/AN5
RF0/AN4
RG3/AN0/VREF+
RG2/AN1/VREF-
RG4/CAP3
RG5/PWM3
RG1/AN2
RG0/AN3
AVDD
AVSS
NC
VSS
VDD
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
VDD
VSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RD1/AD9 1 48 RA0/INT
RD0/AD8 2 47 RB0/CAP1
RE0/ALE 3 46 RB1/CAP2
RE1/OE 4 45 RB3/PWM2
RE2/WR 5 44 RB4/TCLK12
RE3/CAP4 6 43 RB5/TCLK3
MCLR/VPP 7 42 RB2/PWM1
TEST 8 PIC17C75X 41 VSS
VSS 9 Top View 40 OSC2/CLKOUT
VDD 10 39 OSC1/CLKIN
RF7/AN11 11 38 VDD
RF6/AN10 12 37 RB7/SDO
RF5/AN9 13 36 RB6/SCK
RF4/AN8 14 35 RA3/SDI/SDA
RF3/AN7 15 34 RA2/SS/SCL
RF2/AN6 16 33 RA1/T0CKI
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RG7/TX2/CK2
RG6/RX2/DT2
RA5/TX1/CK1
RA4/RX1/DT1
RF1/AN5
RF0/AN4
RG3/AN0/VREF+
RG2/AN1/VREF-
RG1/AN2
RG0/AN3
RG4/CAP3
RG5/PWM3
AVDD
AVSS
VSS
VDD
Applicable to 14 x 14 mm TQFP
VDD 1 64 VSS
RC0/AD0 2 63 RC1/AD1
RD7/AD15 3 62 RC2/AD2
RD6/AD14 4 61 RC3/AD3
RD5/AD13 5 60 RC4/AD4
RD4/AD12 6 59 RC5/AD5
RD3/AD11 7 58 RC6/AD6
RD2/AD10 8 57 RC7/AD7
RD1/AD9 9 56 RA0/INT
RD0/AD8 10 55 RB0/CAP1
RE0/ALE 11 54 RB1/CAP2
RE1/OE 12 53 RB3/PWM2
RE2/WR 13 52 RB4/TCLK12
RE3/CAP4 14 51 RB5/TCLK3
PIC17C75X
MCLR/VPP 15 50 RB2/PWM1
TEST 16 49 VSS
VSS 17 48 OSC2/CLKOUT
VDD 18 47 OSC1/CLKIN
RF7/AN11 19 46 VDD
RF6/AN10 20 45 RB7/SDO
RF5/AN9 21 44 RB6/SCK
RF4/AN8 22 43 RA3/SDI/SDA
RF3/AN7 23 42 RA2/SS/SCL
RF2/AN6 24 41 RA1/T0CKI
RF1/AN5 25 40 RA4/RX1/DT1
RF0/AN4 26 39 RA5/TX1/CK1
AVDD 27 38 RG6/RX2/DT2
AVSS 28 37 RG7/TX2/CK2
RG3/AN0/VREF+ 29 36 RG5/PWM3
RG2/AN1/VREF- 30 35 RG4/CAP3
RG1/AN2 31 34 VDD
RG0/AN3 32 33 VSS
PORTA
Clock
RA0/INT Q1, Q2, Generator OSC1,
IR<16> Q3, Q4 OSC2
RA1/T0CKI WREG<8> BITOP Power-on
RA2/SS/SCL Reset
RA3/SDI/SDA
Brown-out VDD, VSS
RA4/RX1/DT1 Reset
RA5/TX1/CK1
Chip_reset Watchdog
& Other Timer MCLR, VSS
PORTB Control
8 x 8 mult ALU Signals
RB0/CAP1 Test Mode
RB1/CAP2 Select Test
RB2/PWM1
RB3/PWM2 PRODH PRODL Shifter IR Latch <16>
RB4/TCLK12
RB5/TCLK3
RB6/SCK 8 8
RB7/SDO
IR<7>
8
PORTC BSR <7:4> 16 F1
RC0/AD0 IR <7:0> Decode
F9
RC1/AD1 12 Read/write
RC2/AD2 Instruction Decode
RC3/AD3 Decode for
RAM Registers
RC4/AD4 Address ROM Latch <16>
Mapped 8
RC5/AD5 Buffer in Data
RC6/AD6 Control Outputs Space
Data RAM
RC7/AD7 17C756
902 x 8
PORTD 17C752
RD0/AD8 454 x 8
AD<15:0>
RD1/AD9 Data Latch PORTC,
RD2/AD10 PORTD
RD3/AD11 BSR Literal Table
RD4/AD12 Data Latch
16
Stack
PORTF PCH PCL 16 x 16
RF0/AN4 16
RF1/AN5
RF2/AN6 16
RF3/AN7 Data Bus<8>
RF4/AN8
RF5/AN9
RF6/AN10 10-bit
RF7/AN11 Timer0 Timer2 USART1 PWM1 PWM3 Capture2 A/D SSP
IR<7>
PORTG
RG0/AN3
RG1/AN2 Interrupt
Timer1 Timer3 USART2 PWM2 Capture1 Capture3 Capture4
RG2/AN1/VREF- Module
RG3/AN0/VREF+
RG4/CAP3
RG5/PWM3
RG6/RX2/DT2
RG7/TX2/CK2
The internal oscillator circuit is used to generate the In XT or LF modes, a crystal or ceramic resonator is
device clock. Four device clock periods generate an connected to the OSC1/CLKIN and OSC2/CLKOUT
internal instruction clock (TCY). There are four modes pins to establish oscillation (Figure 4-2). The
that the oscillator can operate in. These are selected by PIC17CXXX oscillator design requires the use of a par-
the device configuration bits during device program- allel cut crystal. Use of a series cut crystal may give a
ming. These modes are: frequency out of the crystal manufacturers specifica-
tions.
LF Low Frequency (FOSC <= 2 MHz)
XT Standard Crystal/Resonator Frequency For frequencies above 20 MHz, it is common for the
(2 MHz <= FOSC <= 33 MHz) crystal to be an overtone mode crystal. Use of overtone
mode crystals require a tank circuit to attenuate the
EC External Clock Input
gain at the fundamental frequency. Figure 4-3 shows
(Default oscillator configuration)
an example circuit.
RC External Resistor/Capacitor
(FOSC <= 4 MHz) 4.1.2.1 OSCILLATOR / RESONATOR START-UP
There are two timers that offer necessary delays on As the device voltage increases from Vss, the oscillator
power-up. One is the Oscillator Start-up Timer (OST), will start its oscillations. The time required for the oscil-
intended to keep the chip in RESET until the crystal lator to start oscillating depends on many factors.
oscillator is stable. The other is the Power-up Timer These include:
(PWRT), which provides a fixed delay of 96 ms (nomi-
nal) on power-up only, designed to keep the part in Crystal / resonator frequency
RESET while the power supply stabilizes. With these Capacitor values used (C1 and C2)
two timers on-chip, most applications need no external Device VDD rise time.
reset circuitry. System temperature
Series resistor value (and type) if used
SLEEP mode is designed to offer a very low current Oscillator mode selection of device (which selects
power-down mode. The user can wake from SLEEP the gain of the internal oscillator inverter)
through external reset, Watchdog Timer Reset or
through an interrupt. Figure 4-1 shows an example of a typical oscillator /
resonator start-up. The peak-to-peak voltage of the
Several oscillator options are made available to allow oscillator waveform can be quite low (less than 50% of
the part to fit the application. The RC oscillator option device VDD) when the waveform is centered at VDD/2
saves system cost while the LF crystal option saves (refer to parameter number D033 and D043 in the elec-
power. Configuration bits are used to select various trical specification section).
options.
FIGURE 4-1: OSCILLATOR / RESONATOR
4.1 Oscillator Configurations START-UP
4.1.1 OSCILLATOR TYPES CHARACTERISTICS
XT Crystal/Resonator
EC External Clock Input
RC Resistor/Capacitor
The main difference between the LF and XT modes is
the gain of the internal inverter of the oscillator circuit
which allows the different frequency ranges.
For more details on the device configuration bits, see
Crystal Start-up Time
Section 17.0.
Time
C1 SLEEP
XTAL SLEEP C2
RF OSC2
OSC2
Note1
C2 To internal PIC17CXXX
logic 0.1 F
PIC17CXXX To filter the fundamental frequency
See Table 4-1 and Table 4-2 for recommended values of 1 =
LC2 (2f)2
C1 and C2.
Where f = tank circuit resonant frequency. This should be
Note 1: A series resistor (Rs) may be required for midway between the fundamental and the 3rd overtone
frequencies of the crystal.
AT strip cut crystals.
74AS04 OSC1
10k
XTAL
10k
20 pF 20 pF
To Other
330 k 330 k Devices
XTAL
For timing insensitive applications, the RC device As the device voltage increases, the RC will immedi-
option offers additional cost savings. RC oscillator fre- ately start its oscillations once the pin voltage levels
quency is a function of the supply voltage, the resistor meet the input threshold specifications (parameter
(Rext) and capacitor (Cext) values, and the operating number D032 and D042 in the electrical specification
temperature. In addition to this, oscillator frequency will section). The time required for the RC to start oscillat-
vary from unit to unit due to normal process parameter ing depends on many factors. These include:
variation. Furthermore, the difference in lead frame Resistor value used
capacitance between package types will also affect Capacitor value used
oscillation frequency, especially for low Cext values. Device VDD rise time
The user also needs to take into account variation due System temperature
to tolerance of external R and C components used.
Figure 4-7 shows how the R/C combination is con-
nected to the PIC17CXXX. For Rext values below
2.2 k, the oscillator operation may become unstable,
or stop completely. For very high Rext values (e.g.
1 M), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend to keep
Rext between 3 k and 100 k.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With little
or no external capacitance, oscillation frequency can
vary dramatically due to changes in external capaci-
tances, such as PCB trace capacitance or package
lead frame capacitance.
See Section 21.0 for RC frequency variation from part
to part due to normal process variation. The variation
is larger for larger R (since leakage current variation
will affect RC frequency more for large R) and for
smaller C (since variation of input capacitance will
affect RC frequency more).
See Section 21.0 for variation of oscillator frequency
due to VDD for given Rext/Cext values as well as fre-
quency variation due to operating temperature for
given R, C, and VDD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test pur-
poses or to synchronize other logic (see Figure 4-8 for
waveform).
FIGURE 4-7: RC OSCILLATOR MODE
VDD
PIC17CXXX
Rext Internal
OSC1 clock
Cext
VSS OSC2/CLKOUT
Fosc/4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
phase
Q3 clock
Q4
PC PC PC+1 PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is flushed from the pipeline while the new instruction is being fetched and then executed.
External
Reset
MCLR
BOR Brown-out
Module Reset
WDT WDT
Module
Time_Out
Reset
VDD rise
detect S
Power_On_Reset
VDD
OST/PWRT
Chip_Reset
OST R Q
Power_Up
Enable OST
OSC2
0 0 1 1 Power-on Reset
1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP
1 1 0 1 WDT Reset during normal operation
1 1 0 0 WDT Wake-up during SLEEP
1 1 1 1 MCLR Reset during normal operation
1 0 x x Brown-out Reset
0 0 0 x Illegal, TO is set on POR
0 0 x 0 Illegal, PD is set on POR
x x 1 1 CLRWDT instruction executed
Note 1: When BOR is enabled, else the BOR status bit is unknown
TABLE 5-3: RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
Unbanked
INDF0 00h N.A. N.A. N.A.
FSR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h 0000h 0000h PC + 1(2)
PCLATH 03h 0000 0000 0000 0000 uuuu uuuu
ALUSTA 04h 1111 xxxx 1111 uuuu 1111 uuuu
T0STA 05h 0000 000- 0000 000- 0000 000-
(3) 06h 1100(4) qquu(4) --uu qquu(4)
CPUSTA --11 --11
INTSTA 07h 0000 0000 0000 0000 uuuu uuuu(1)
INDF1 08h N.A. N.A. N.A.
FSR1 09h xxxx xxxx uuuu uuuu uuuu uuuu
WREG 0Ah xxxx xxxx uuuu uuuu uuuu uuuu
TMR0L 0Bh xxxx xxxx uuuu uuuu uuuu uuuu
TMR0H 0Ch xxxx xxxx uuuu uuuu uuuu uuuu
TBLPTRL 0Dh 0000 0000 0000 0000 uuuu uuuu
TBLPTRH 0Eh 0000 0000 0000 0000 uuuu uuuu
BSR 0Fh 0000 0000 0000 0000 uuuu uuuu
Bank 0
PORTA 10h 0-xx xxxx 0-uu uuuu u-uu uuuu
DDRB 11h 1111 1111 1111 1111 uuuu uuuu
PORTB 12h xxxx xxxx uuuu uuuu uuuu uuuu
RCSTA1 13h 0000 -00x 0000 -00u uuuu -uuu
RCREG1 14h xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA1 15h 0000 --1x 0000 --1u uuuu --uu
TXREG1 16h xxxx xxxx uuuu uuuu uuuu uuuu
SPBRG1 17h xxxx xxxx uuuu uuuu uuuu uuuu
Bank 1
DDRC 10h 1111 1111 1111 1111 uuuu uuuu
PORTC 11h xxxx xxxx uuuu uuuu uuuu uuuu
DDRD 12h 1111 1111 1111 1111 uuuu uuuu
PORTD 13h xxxx xxxx uuuu uuuu uuuu uuuu
DDRE 14h ---- 1111 ---- 1111 ---- uuuu
PORTE 15h ---- xxxx ---- uuuu ---- uuuu
PIR1 16h x000 0010 u000 0010 uuuu uuuu(1)
PIE1 17h 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: If Brown-out is enabled, else the BOR bit is unknown.
Bank 2
TMR1 10h xxxx xxxx uuuu uuuu uuuu uuuu
TMR2 11h xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 12h xxxx xxxx uuuu uuuu uuuu uuuu
TMR3H 13h xxxx xxxx uuuu uuuu uuuu uuuu
PR1 14h xxxx xxxx uuuu uuuu uuuu uuuu
PR2 15h xxxx xxxx uuuu uuuu uuuu uuuu
PR3/CA1L 16h xxxx xxxx uuuu uuuu uuuu uuuu
PR3/CA1H 17h xxxx xxxx uuuu uuuu uuuu uuuu
Bank 3
PW1DCL 10h xx-- ---- uu-- ---- uu-- ----
PW2DCL 11h xx0- ---- uu0- ---- uuu- ----
PW1DCH 12h xxxx xxxx uuuu uuuu uuuu uuuu
PW2DCH 13h xxxx xxxx uuuu uuuu uuuu uuuu
CA2L 14h xxxx xxxx uuuu uuuu uuuu uuuu
CA2H 15h xxxx xxxx uuuu uuuu uuuu uuuu
TCON1 16h 0000 0000 0000 0000 uuuu uuuu
TCON2 17h 0000 0000 0000 0000 uuuu uuuu
Bank 4
PIR2 10h 000- 0010 000- 0010 uuu- uuuu(1)
PIE2 11h 000- 0000 000- 0000 uuu- uuuu
Unimplemented 12h ---- ---- ---- ---- ---- ----
RCSTA2 13h 0000 -00x 0000 -00u uuuu -uuu
RCREG2 14h xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA2 15h 0000 --1x 0000 --1u uuuu --uu
TXREG2 16h xxxx xxxx uuuu uuuu uuuu uuuu
SPBRG2 17h xxxx xxxx uuuu uuuu uuuu uuuu
Bank 5
DDRF 10h 1111 1111 1111 1111 uuuu uuuu
PORTF 11h xxxx xxxx uuuu uuuu uuuu uuuu
DDRG 12h 1111 1111 1111 1111 uuuu uuuu
PORTG 13h xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 14h 0000 -0-0 0000 -0-0 uuuu uuuu
ADCON1 15h 000- 0000 000- 0000 uuuu uuuu
ADRESL 16h xxxx xxxx xxxx xxxx uuuu uuuu
ADRESH 17h xxxx xxxx xxxx xxxx uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: If Brown-out is enabled, else the BOR bit is unknown.
Bank 6
SSPADD 10h 0000 0000 0000 0000 uuuu uuuu
SSPCON1 11h 0000 0000 0000 0000 uuuu uuuu
SSPCON2 12h 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 13h 0000 0000 0000 0000 uuuu uuuu
SSPBUF 14h xxxx xxxx uuuu uuuu uuuu uuuu
Unimplemented 15h ---- ---- ---- ---- ---- ----
Unimplemented 16h ---- ---- ---- ---- ---- ----
Unimplemented 17h ---- ---- ---- ---- ---- ----
Bank 7
PW3DCL 10h xxx- ---- uuu- ---- uuu- ----
PW3DCH 11h xxxx xxxx uuuu uuuu uuuu uuuu
CA3L 12h xxxx xxxx uuuu uuuu uuuu uuuu
CA3H 13h xxxx xxxx uuuu uuuu uuuu uuuu
CA4L 14h xxxx xxxx uuuu uuuu uuuu uuuu
CA4H 15h xxxx xxxx uuuu uuuu uuuu uuuu
TCON3 16h -000 0000 -000 0000 -uuu uuuu
Unimplemented 17h ---- ---- ---- ---- ---- ----
Unbanked
PRODL 18h xxxx xxxx uuuu uuuu uuuu uuuu
PRODH 19h xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: If Brown-out is enabled, else the BOR bit is unknown.
VDD
BVDD Max.
BVDD Min.
Internal < 96 ms
Reset 96 ms
VDD
BVDD Max.
BVDD Min.
Internal
96 ms
Reset
TMR3IE
TMR2IF
INTSTA
TMR2IE
TMR1IF
TMR1IE
Wake-up (If in SLEEP mode)
CA2IF T0IF or terminate long write
CA2IE T0IE
CA1IF INTF
CA1IE INTE
TX1IF Interrupt to CPU
TX1IE T0CKIF
RC1IF T0CKIE
RC1IE PEIF
SSPIF
PEIE
SSPIE
BCLIF
PIR2 / PIE2
GLINTD (CPUSTA<4>)
BCLIE
ADIF
ADIE
CA4IF
CA4IE
CA3IF
CA3IE
TX2IF
TX2IE
RC2IF
RC2IE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
OSC2
RA0/INT or
RA1/T0CKI
INTF or
T0CKIF
GLINTD
PC PC PC + 1 Addr (Vector) YY YY + 1 PC + 1
System Bus
Instruction PC Inst (PC) Addr Inst (PC+1) Addr Inst (PC+1) Addr Inst (Vector) Addr RETFIE Addr Inst (YY + 1)
Fetched
Instruction
Inst (PC) Dummy Dummy RETFIE Dummy
executed
isters (SFRs). The operation of the SFRs that control Stack Level 16
the core are described here. The SFRs used to con-
trol the peripheral modules are described in the section Reset Vector 0000h
discussing each individual peripheral module. INT Pin Interrupt Vector 0008h
PIC17C75X devices have a 16-bit program counter T0CKI Pin Interrupt Vector 0018h
User Memory
Space (1)
The PIC17C75X can operate in one of four possible 1FFFh
program memory configurations. The configuration is (PIC17C752)
selected by configuration bits. The possible modes
are:
Microprocessor
Microcontroller
Extended Microcontroller 3FFFh
Protected Microcontroller (PIC17C756)
FOSC1 FE01h
code protection feature. WDTPS0 FE02h
The extended microcontroller mode accesses both the WDTPS1 FE03h
Space
PM0 FE04h
internal program memory as well as external program FE05h
Reserved
memory. Execution automatically switches between PM1 FE06h
internal and external memory. The 16-bits of address Reserved FE07h
allow a program memory range of 64K-words. FE08h
Reserved
FE0Dh
The microprocessor mode only accesses the external BODEN FE0Eh
program memory. The on-chip program memory is PM2 FE0Fh
FE10h
ignored. The 16-bits of address allow a program mem- Test EPROM
FF5Fh
ory range of 64K-words. Microprocessor mode is the FF60h
default mode of an unprogrammed device. Boot ROM
FFFFh
The different modes allow different access to the con-
figuration bits, test memory, and boot ROM. Table 7-1 Note 1: User memory space may be internal, external, or
lists which modes can access which areas in memory. both. The memory configuration depends on the
Test Memory and Boot Memory are not required for processor mode.
normal operation of the device. Care should be taken
to ensure that no unintended branches occur to these
areas.
Extended
Microcontroller
Access No Access
Protected
Microcontroller
Access Access
PROGRAM SPACE
External 2000h
Program
Memory
External
PIC17C752
Program
Memory
DATA SPACE
120h 120h 120h
Program
Memory
External
Program
PIC17C756
Memory
FFh 1FFh 2FFh 3FFh FFh 1FFh 2FFh 3FFh FFh 1FFh 2FFh 3FFh
The system bus requires that there is no bus conflict 25 MHz 160 ns -70
(minimal leakage), so the output value (address) will be
capacitively held at the desired value. 33 MHz 121 ns (1)
As the speed of the processor increases, external Note 1: The access times for this requires the use of
EPROM memory with faster access time must be used. fast SRAMs.
Table 7-2 lists external memory speed requirements for
a given PIC17C75X device frequency.
Memory Memory
A15-A0 (MSB) (LSB)
AD7-AD0 373 Ax-A0 Ax-A0
OE
WR
Data memory is partitioned into two areas. The first is All devices have some amount of GPR area. The GPRs
the General Purpose Registers (GPR) area, while the are 8-bits wide. When the GPR area is greater than
second is the Special Function Registers (SFR) area. 232, it must be banked to allow access to the additional
The SFRs control and give the status for the operation memory space.
of the device. All the PIC17C75X devices have banked memory in
Portions of data memory are banked, this occurs in the GPR area. To facilitate switching between these
both areas. The GPR area is banked to allow greater banks, the MOVLR bank instruction has been added to
than 232 bytes of general purpose RAM. the instruction set. GPRs are not initialized by a
Power-on Reset and are unchanged on all other resets.
Banking requires the use of control bits for bank selec-
tion. These control bits are located in the Bank Select 7.2.2 SPECIAL FUNCTION REGISTERS (SFR)
Register (BSR). If an access is made to the unbanked
region, the BSR bits are ignored. Figure 7-5 shows the The SFRs are used by the CPU and peripheral func-
data memory map organization. tions to control the operation of the device (Figure 7-5).
Instructions MOVPF and MOVFP provide the means to These registers are static RAM.
move values from the peripheral area (P) to any loca- The SFRs can be classified into two sets, those asso-
tion in the register file (F), and vice-versa. The defini- ciated with the core function and those related to the
tion of the P range is from 0h to 1Fh, while the F peripheral functions. Those registers related to the
range is 0h to FFh. The P range has six more loca- core are described here, while those related to a
tions than peripheral registers which can be used as peripheral feature are described in the section for each
General Purpose Registers. This can be useful in some peripheral feature.
applications where variables need to be copied to other The peripheral registers are in the banked portion of
locations in the general purpose RAM (such as saving memory, while the core registers are in the unbanked
status information during an interrupt). region. To facilitate switching between the peripheral
The entire data memory can be accessed either banks, the MOVLB bank instruction has been provided.
directly or indirectly through file select registers FSR0
and FSR1 (Section 7.4). Indirect addressing uses the
appropriate control bits of the BSR for accesses into
the banked areas of data memory. The BSR is
explained in greater detail in Section 7.8.
Bank 0 Bank 1 (1) Bank 2 (1) Bank 3 (1) Bank 4 (1) Bank 5 (1) Bank 6 (1) Bank 7 (1)
10h PORTA DDRC TMR1 PW1DCL PIR2 DDRF SSPADD PW3DCL
11h DDRB PORTC TMR2 PW2DCL PIE2 PORTF SSPCON1 PW3DCH
12h PORTB DDRD TMR3L PW1DCH DDRG SSPCON2 CA3L
13h RCSTA1 PORTD TMR3H PW2DCH RCSTA2 PORTG SSPSTAT CA3H
14h RCREG1 DDRE PR1 CA2L RCREG2 ADCON0 SSPBUF CA4L
15h TXSTA1 PORTE PR2 CA2H TXSTA2 ADCON1 CA4H
16h TXREG1 PIR1 PR3L/CA1L TCON1 TXREG2 ADRESL TCON3
17h SPBRG1 PIE1 PR3H/CA1H TCON2 SPBRG2 ADRESH
Unbanked
18h PRODL
19h PRODH
1Ah General
Purpose
1Fh RAM
FFh
Note 1: SFR file locations 10h - 17h are banked. The lower nibble of the BSR specifies the bank. All
unbanked SFRs ignore the Bank Select Register (BSR) bits.
2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh
are banked. The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select
Register (BSR) bits.
3: These RAM banks are not implemented on the PIC17C752. Reading any register in this bank reads
0s
Unbanked
00h INDF0 Uses contents of FSR0 to address data memory (not a physical register) ---- ---- ---- ----
01h FSR0 Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu
02h PCL Low order 8-bits of PC 0000 0000 0000 0000
03h(1) PCLATH Holding register for upper 8-bits of PC 0000 0000 uuuu uuuu
04h ALUSTA FS3 FS2 FS1 FS0 OV Z DC C 1111 xxxx 1111 uuuu
05h T0STA INTEDG T0SE T0CS T0PS3 T0PS2 T0PS1 T0PS0 0000 000- 0000 000-
(2) CPUSTA STKAV GLINTD TO PD POR BOR --11 1100 --11 qquu
06h
07h INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
08h INDF1 Uses contents of FSR1 to address data memory (not a physical register) ---- ---- ---- ----
09h FSR1 Indirect data memory address pointer 1 xxxx xxxx uuuu uuuu
0Ah WREG Working register xxxx xxxx uuuu uuuu
0Bh TMR0L TMR0 register; low byte xxxx xxxx uuuu uuuu
0Ch TMR0H TMR0 register; high byte xxxx xxxx uuuu uuuu
0Dh TBLPTRL Low byte of program memory table pointer 0000 0000 0000 0000
0Eh TBLPTRH High byte of program memory table pointer 0000 0000 0000 0000
0Fh BSR Bank select register 0000 0000 0000 0000
Bank 0
Bank 1
10h DDRC Data direction register for PORTC 1111 1111 1111 1111
RC7/ RC6/ RC5/ RC4/ RC3/ RC2/ RC1/ RC0/
11h PORTC xxxx xxxx uuuu uuuu
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
12h DDRD Data direction register for PORTD 1111 1111 1111 1111
RD7/ RD6/ RD5/ RD4/ RD3/ RD2/ RD1/ RD0/
13h PORTD xxxx xxxx uuuu uuuu
AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8
14h DDRE Data direction register for PORTE ---- 1111 ---- 1111
15h RE3/
PORTE RE2/WR RE1/OE RE0/ALE ---- xxxx ---- uuuu
CAP4
16h PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010
17h PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
Bank 2
10h TMR1 Timer1s register xxxx xxxx uuuu uuuu
11h TMR2 Timer2s register xxxx xxxx uuuu uuuu
12h TMR3L Timer3s register; low byte xxxx xxxx uuuu uuuu
13h TMR3H Timer3s register; high byte xxxx xxxx uuuu uuuu
14h PR1 Timer1s period register xxxx xxxx uuuu uuuu
15h PR2 Timer2s period register xxxx xxxx uuuu uuuu
16h PR3L/CA1L Timer3s period register - low byte/capture1 register; low byte xxxx xxxx uuuu uuuu
17h PR3H/CA1H Timer3s period register - high byte/capture1 register; high byte xxxx xxxx uuuu uuuu
Bank 3
10h PW1DCL DC1 DC0 xx-- ---- uu-- ----
11h PW2DCL DC1 DC0 TM2PW2 xx0- ---- uu0- ----
12h PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
13h PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
14h CA2L Capture2 low byte xxxx xxxx uuuu uuuu
15h CA2H Capture2 high byte xxxx xxxx uuuu uuuu
16h TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
Bank 4:
10h PIR2 SSPIF BCLIF ADIF CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h PIE2 SSPIE BCLIE ADIE CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h RCSTA2 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
14h RCREG2 Serial Port Receive Register for USART2 xxxx xxxx uuuu uuuu
15h TXSTA2 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
16h TXREG2 Serial Port Transmit Register for USART2 xxxx xxxx uuuu uuuu
17h SPBRG2 Baud Rate Generator for USART2 xxxx xxxx uuuu uuuu
Bank 5:
10h DDRF Data Direction Register for PORTF 1111 1111 1111 1111
11h PORTF RF7/ RF6/ RF5/ RF4/ RF3/ RF2/ RF1/ RF0/
0000 0000 0000 0000
AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4
12h DDRG Data Direction Register for PORTG 1111 1111 1111 1111
13h PORTG RG7/ RG6/ RG5/ RG4/ RG3/ RG2/ RG1/ RG0/
xxxx 0000 uuuu 0000
TX2/CK2 RX2/DT2 PWM3 CAP3 AN0 AN1 AN2 AN3
14h ADCON0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 -0-0 0000 -0-0
15h ADCON1 ADCS1 ADCS0 ADFM PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000
16h ADRESL A/D Result Register low byte xxxx xxxx uuuu uuuu
17h ADRESH A/D Result Register high byte xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
Bank 6:
10h SSPADD SSP Address register in I2C slave mode. SSP baud rate reload register in I2C master mode. 0000 0000 0000 0000
11h SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
12h SSPCON2 GCEN AKSTAT AKDT AKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
13h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
14h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
Bank 7:
11h PW3DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
16h TCON3 CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
Unbanked
18h (5) PRODL Low Byte of 16-bit Product (8 x 8 Hardware Multiply) xxxx xxxx uuuu uuuu
(5) PRODH High Byte of 16-bit Product (8 x 8 Hardware Multiply) xxxx xxxx uuuu uuuu
19h
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
0000 1:1
0001 1:2
0010 1:4
0011 1:8
0100 1:16
0101 1:32
0110 1:64
0111 1:128
1xxx 1:256
Address
Range
0 1 2 3 4 5 6 7 8 15
10h SFR (Peripheral)
Banks
17h
Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 15
0 1 2 3 4 15
20h GPR (RAM)
Banks
FFh
Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 15
Note 1: Only Banks 0 through 7 are implemented. Selection of an unimplemented bank is not recommended.
Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.
2: Bank 0 and Bank 1 are implemented for the PIC17C752, and Banks 0 through 3 are implemented for the PIC17C756.
Selection of an unimplemented bank is not recommended.
TABLE POINTER
TBLPTRH TBLPTRL
TABLATH TABLATL Note 1: 8-bit value, from register 'f', loaded into the
high or low byte in TABLAT (16-bit).
TLWT 1,f TLWT 0,f 2: 16-bit TABLAT value written to address
DATA
Program Memory (TBLPTR).
MEMORY PROGRAM MEMORY 3: If i = 1, then TBLPTR = TBLPTR + 1,
If i = 0, then TBLPTR is unchanged.
f
1
3 3
DATA TABLRD 1,i,f TABLRD 0,i,f
MEMORY PROGRAM MEMORY
DATA
MEMORY PROGRAM MEMORY
f
1
f
1
Prog-Mem
(TBLPTR)
2
A table write operation to internal memory causes a An interrupt source or reset are the only events that
long write operation. The long write is necessary for terminate a long write operation. Terminating the long
programming the internal EPROM. Instruction execu- write from an interrupt source requires that the inter-
tion is halted while in a long write cycle. The long write rupt enable and flag bits are set. The GLINTD bit only
will be terminated by any enabled interrupt. To ensure enables the vectoring to the interrupt address.
that the EPROM location has been well programmed, If the T0CKI, RA0/INT, or TMR0 interrupt source is
a minimum programming time is required (see specifi- used to terminate the long write; the interrupt flag, of
cation #D114). Having only one interrupt enabled to the highest priority enabled interrupt, will terminate the
terminate the long write ensures that no unintentional long write and automatically be cleared.
interrupts will prematurely terminate the long write.
The sequence of events for programming an internal Note 1: If an interrupt is pending, the TABLWT is
program memory location should be: aborted (an NOP is executed). The
1. Disable all interrupt sources, except the source highest priority pending interrupt, from
to terminate EPROM program write. the T0CKI, RA0/INT, or TMR0 sources
2. Raise MCLR/VPP pin to the programming volt- that is enabled, has its flag cleared.
age. Note 2: If the interrupt is not being used for the
3. Clear the WDT. program write timing, the interrupt
4. Do the table write. The interrupt will terminate should be disabled. This will ensure that
the long write. the interrupt is not lost, nor will it termi-
5. Verify the memory location (table read). nate the long write prematurely.
Note 1: Programming requirements must be If a peripheral interrupt source is used to terminate the
met. See timing specification in electrical long write, the interrupt enable and flag bits must be
specifications for the desired device. set. The interrupt flag will not be automatically cleared
Violating these specifications (including upon the vectoring to the interrupt vector address.
temperature) may result in EPROM The GLINTD bit determines whether the program will
locations that are not fully programmed branch to the interrupt vector when the long write is
and may lose their state over time. terminated. If GLINTD is clear, the program will vector,
Note 2: If the VPP requirement is not met, the if GLINTD is set, the program will not vector to the
table write is a 2 cycle write and the pro- interrupt address.
gram memory is unchanged.
Table writes to external memory are always two-cycle The i operand of the TABLWT instruction can specify
instructions. The second cycle writes the data to the that the value in the 16-bit TBLPTR register is auto-
external memory location. The sequence of events for matically incremented (for the next write). In
an external memory write are the same for an internal Example 8-1, the TBLPTR register is not automatically
write. incremented.
EXAMPLE 8-1: TABLE WRITE
Note: If an interrupt is pending or occurs during
the TABLWT, the two cycle table write
completes. The RA0/INT, TMR0, or CLRWDT ; Clear WDT
MOVLW HIGH (TBL_ADDR) ; Load the Table
T0CKI interrupt flag is automatically
MOVWF TBLPTRH ; address
cleared or the pending peripheral inter- MOVLW LOW (TBL_ADDR) ;
rupt is acknowledged. MOVWF TBLPTRL ;
MOVLW HIGH (DATA) ; Load HI byte
TLWT 1, WREG ; in TABLATH
MOVLW LOW (DATA) ; Load LO byte
TABLWT 0,0,WREG ; in TABLATH
; and write to
; program memory
; (Ext. SRAM)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
ALE
OE
'1'
WR
Note: If external write, and GLINTD = '1', and Enable bit = '1', then when '1' Flag bit, Do table write.
The highest pending interrupt is cleared.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0 PC PC+1 TBL1 Data out 1 PC+2 TBL2 Data out 2 PC+3
Instruction
fetched TABLWT1 TABLWT2 INST (PC+2) INST (PC+3)
Instruction INST (PC-1) TABLWT1 cycle1 TABLWT1 cycle2 TABLWT2 cycle1 TABLWT2 cycle2 INST (PC+2)
executed
Data write cycle Data write cycle
ALE
OE
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
ALE
OE
'1'
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
ALE
OE
'1'
WR
MULTIPLICATION
MOVPF PRODH, RES1 ;
ALGORITHM
MOVPF PRODL, RES0 ;
;
MOVFP ARG1H, WREG
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L MULWF ARG2H ; ARG1H * ARG2H ->
= (ARG1H ARG2H 216) + ; PRODH:PRODL
MOVPF PRODH, RES3 ;
(ARG1H ARG2L 2 8) + MOVPF PRODL, RES2 ;
(ARG1L ARG2H 28) + ;
MOVFP ARG1L, WREG
(ARG1L ARG2L) MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVFP PRODL, WREG ;
ADDWF RES1, F ; Add cross
MOVFP PRODH, WREG ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
;
MOVFP ARG1H, WREG ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVFP PRODL, WREG ;
ADDWF RES1, F ; Add cross
MOVFP PRODH, WREG ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
MULTIPLICATION
;
MOVFP ARG1H, WREG
ALGORITHM MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
RES3:RES0 MOVPF PRODH, RES3 ;
= ARG1H:ARG1L ARG2H:ARG2L MOVPF PRODL, RES2 ;
;
= (ARG1H ARG2H 216) + MOVFP ARG1L, WREG
(ARG1H ARG2L 28) + MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
(ARG1L ARG2H 28) + MOVFP PRODL, WREG ;
(ARG1L ARG2L) + ADDWF RES1, F ; Add cross
MOVFP PRODH, WREG ; products
(-1 ARG2H<7> ARG1H:ARG1L 216) + ADDWFC RES2, F ;
(-1 ARG1H<7> ARG2H:ARG2L 216) CLRF WREG, F ;
ADDWFC RES3, F ;
;
MOVFP ARG1H, WREG ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVFP PRODL, WREG ;
ADDWF RES1, F ; Add cross
MOVFP PRODH, WREG ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
GOTO SIGN_ARG1 ; no, check ARG1
MOVFP ARG1L, WREG ;
SUBWF RES2 ;
MOVFP ARG1H, WREG ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
GOTO CONT_CODE ; no, done
MOVFP ARG2L, WREG ;
SUBWF RES2 ;
MOVFP ARG2H, WREG ;
SUBWFB RES3
;
CONT_CODE
:
RD_PORTA
(Q2)
SSP Mode
1 Q CK WR_PORTA
(Q4) Data Bus
0 SCL out
Buffer
Name Bit0 Function
Type
RA0/INT bit0 ST Input or external interrupt input.
RA1/T0CKI bit1 ST Input or clock input to the TMR0 timer/counter, and/or an external interrupt
input.
RA2/SS/SCL bit2 ST Input/Output or slave select input for the SPI or clock input for the I2C bus.
Output is open drain type.
RA3/SDI/SDA bit3 ST Input/Output or data input for the SPI or data for the I2C bus.
Output is open drain type.
RA4/RX1/DT1 bit4 ST Input/Output or USART1 Asynchronous Receive or
USART1 Synchronous Data.
RA5/TX1/CK1 bit5 ST Input/Output or USART1 Asynchronous Transmit or
USART1 Synchronous Clock.
RBPU bit7 Control bit for PORTB weak pull-ups.
Legend: ST = Schmitt Trigger input.
TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH PORTA
Value on
Value on
all other
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
resets
BOR
(Note1)
RBPU (PORTA<7>)
Weak
Pull-Up Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
CK
D
Port
Q
Data WR_PORTB (Q4)
CK
Note: I/O pins have protection diodes to VDD and VSS.
RBPU (PORTA<7>)
Weak
Pull-Up Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
CK
D R
Port
Q
Data WR_PORTB (Q4)
CK
Peripheral_output
Peripheral_enable
RBPU (PORTA<7>)
Weak
Pull-Up Match Signal
from other
port pins
RBIF
D Q Data Bus
EN
RD_DDRB (Q2)
RD_PORTB (Q2)
OE D
Q
WR_DDRB (Q4)
CK
P
0 Port
Data
1 Q D
N WR_PORTB (Q4)
CK
Q
SPI output
SPI output enable
RBPU (PORTA<7>)
Weak
Pull-Up Match Signal
from other
port pins
RBIF
D Q Data Bus
EN
EN
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE Q
WR_DDRB (Q4)
CK
P
0 Port SS output disable
Data
1 Q D
N WR_PORTB (Q4)
CK
Q
SPI output
SPI output enable
Note: I/O pins have protection diodes to VDD and Vss.
RB7/ RB6/ RB5/ RB4/ RB3/ RB2/ RB1/ RB0/ xxxx xxxx uuuu uuuu
12h PORTB
SDO SCK TCLK3 TCLK12 PWM2 PWM1 CAP2 CAP1
11h, Bank 0 DDRB Data direction register for PORTB 1111 1111 1111 1111
RA5/ RA4/ RA3/ RA2/ 0-xx xxxx 0-uu uuuu
10h, Bank 0 PORTA RBPU RA1/T0CKI RA0/INT
TX1/CK1 RX1/DT1 SDI/SDA SS/SCL
06h, Unbanked CPUSTA STKAV GLINTD TO PD POR BOR --11 1100 --11 qq11
07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = Value depends on condition.
Shaded cells are not used by PORTB.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
to D_Bus IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTC
Port D
0 Q
Data
1 WR_PORTC
CK
RD_DDRC
Q D
WR_DDRC
CK
R S
EX_EN
FIGURE 10-10: BLOCK DIAGRAM OF RD7:RD0 PORT PINS (IN I/O PORT MODE)
to D_Bus IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTD
Port D
0 Q
Data
1 WR_PORTD
CK
RD_DDRD
Q D
WR_DDRD
CK
R S
EX_EN
Note:
; RE<7:4> are always
Three pins of this port are configured as ; read as '0'
the system bus when the devices configu-
ration bits are selected to Microprocessor
or Extended Microcontroller modes. The
other pin is a general purpose I/O or
Capture4 pin. In the two other microcon-
troller modes, RE2:RE0 are general pur-
pose I/O pins.
Data Bus
TTL
Input
Buffer
RD_PORTE
Port D
0 Q
Data WR_PORTE
1
CK
RD_DDRE
Q D
WR_DDRE
CK
R S
EX_EN
CNTL SYS BUS
DRV_SYS Control
Peripheral In
Data Bus
D Q
EN
EN
VDD
RD_PORTE
Q D
Port WR_PORTE
Data CK
Q
N
RD_DDRE
Q D
WR_DDRE
CK
Q S
15h, Bank 1 PORTE RE3/CAP4 RE2/WR RE1/OE RE0/ALE ---- xxxx ---- uuuu
14h, Bank 1 DDRE Data direction register for PORTE ---- 1111 ---- 1111
14h, Bank 7 CA4L Capture4 low byte xxxx xxxx uuuu uuuu
15h, Bank 7 CA4H Capture4 high byte xxxx xxxx uuuu uuuu
16h, Bank 7 TCON3 CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
Data bus
D Q
VDD
WR PORTF
CK Q
P
Data Latch
I/O pin
D Q
N
WR DDRF
CK Q VSS
DDRF Latch
ST
input
RD DDRF buffer
Q D
EN
EN
RD PORT
PCFG3:PCFG0
To other pads
VAN
CHS3:CHS0
To other pads
10h, Bank 5 DDRF Data Direction Register for PORTF 1111 1111 1111 1111
11h, Bank 5 PORTF RF7/ RF6/ RF5/ RF4/ RF3/ RF2/ RF1/ RF0/ 0000 0000 0000 0000
AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTF.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
Data bus
D Q
VDD
WR PORTG
CK Q
P
Data Latch
I/O pin
D Q
N
WR DDRG
CK Q VSS
DDRG Latch
ST
input
RD DDRG buffer
Q D
EN
EN
RD PORT
PCFG3:PCFG0
To other pads
VAN
CHS3:CHS0
To other pads
Peripheral Data In
Data Bus
D Q
EN
EN
RD_PORTG
D
VDD
WR_PORTG
CK
P Q
RD_DDRG
Q D
N WR_DDRG
Q CK
Data Bus
D Q
NEN
RD_PORTG
Q D
Port
WR_PORTG
VDD Data CK
1 Q
P 0
RD_DDRG
Q D
WR_DDRG
N CK
Q R
OUTPUT
OUTPUT ENABLE
12h, Bank 5 DDRG Data Direction Register for PORTG 1111 1111 1111 1111
13h, Bank 5 PORTG RG7/ RG6/ RG5/ RG4/ RG3/ RG2/ RG1/ RG0/ xxxx 0000 uuuu 0000
TX2/CK2 RX2/DT2 PWM3 CAP3 AN0 AN1 AN2 AN3
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTG.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
FIGURE 12-3: TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Prescaler
output
(PSOUT) (note 3)
Sampled (note 2)
Prescaler
output
(note 1)
Increment
TMR0
TMR0 T0 T0 + 1 T0 + 2
Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.
2: = PSOUT is sampled here.
3: The PSOUT high time is too short and is missed by the sampling circuit.
Although TMR0 is a 16-bit timer/counter, only 8-bits at Since writing to either TMR0L or TMR0H will effectively
a time can be read or written during a single instruction inhibit increment of that half of the TMR0 in the next
cycle. Care must be taken during any read or write. cycle (following write), but not inhibit increment of the
other half, the user must write to TMR0L first and
12.3.1 READING 16-BIT VALUE TMR0H second in two consecutive instructions, as
shown in Example 12-2. The interrupt must be dis-
The problem in reading the entire 16-bit value is that
abled. Any write to either TMR0L or TMR0H clears the
after reading the low (or high) byte, its value may
prescaler.
change from FFh to 00h.
Example 12-1 shows a 16-bit read. To ensure a proper EXAMPLE 12-2: 16-BIT WRITE
read, interrupts must be disabled during this routine. BSF CPUSTA, GLINTD ; Disable interrupts
EXAMPLE 12-1: 16-BIT READ MOVFP RAM_L, TMR0L ;
MOVFP RAM_H, TMR0H ;
MOVPF TMR0L, TMPLO ;read low tmr0 BCF CPUSTA, GLINTD ; Done, enable
MOVPF TMR0H, TMPHI ;read high tmr0 ; interrupts
MOVFP TMPLO, WREG ;tmplo > wreg
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
ALE
Fetch
MOVFP W,TMR0L MOVFP TMR0L,W MOVFP TMR0L,W MOVFP TMR0L,W
Instruction Write to TMR0L Read TMR0L Read TMR0L Read TMR0L
executed
(Value = NT0) (Value = NT0) (Value = NT0 +1)
TMR0H
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
ALE
WR_TRM0L
WR_TMR0H
RD_TMR0L
TMR0H 12 12 13 AB
TMR0L FE FF 56 57 58
In this example, old TMR0 value is 12FEh, new value of AB56h is written.
05h, Unbanked T0STA INTEDG T0SE T0CS T0PS3 T0PS2 T0PS1 T0PS0 0000 000- 0000 000-
06h, Unbanked CPUSTA STKAV GLINTD TO PD POR BOR --11 1100 --11 qq11
07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
0Bh, Unbanked TMR0L TMR0 register; low byte xxxx xxxx uuuu uuuu
0Ch, Unbanked TMR0H TMR0 register; high byte xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition, Shaded cells are not used by Timer0.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
Fosc/4 0
Reset
TMR1
1 Set TMR1IF
TMR1ON (PIR1<4>)
(TCON2<0>) Comparator<8>
Comparator x8
Equal
TMR1CS
(TCON1<0>) PR1
RB4/TCLK12
1
Reset
TMR2
Fosc/4 0 Set TMR2IF
TMR2ON (PIR1<5>)
(TCON2<1>) Comparator<8>
Comparator x8
Equal
TMR2CS
(TCON1<1>) PR2
RB4/TCLK12 0
Fosc/4
TMR1ON
(TCON2<0>)
MSB LSB
TMR1CS
(TCON1<0>) Reset
TMR2 x 8 TMR1 x 8
Comparator<8>
Comparator x16
Set Interrupt TMR1IF Equal
(PIR1<4>)
PR2 x 8 PR1 x 8
16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
16h, Bank 7 TCON3 CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
10h, Bank 2 TMR1 Timer1s register xxxx xxxx uuuu uuuu
11h, Bank 2 TMR2 Timer2s register xxxx xxxx uuuu uuuu
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
06h, Unbanked CPUSTA STKAV GLINTD TO PD POR BOR --11 1100 --11 qq11
14h, Bank 2 PR1 Timer1 period register xxxx xxxx uuuu uuuu
15h, Bank 2 PR2 Timer2 period register xxxx xxxx uuuu uuuu
10h, Bank 3 PW1DCL DC1 DC0 xx-- ---- uu-- ----
11h, Bank 3 PW2DCL DC1 DC0 TM2PW2 xx0- ---- uu0- ----
10h, Bank 7 PW3DCL DC1 DC0 TM2PW3 xx0- ---- uu0- ----
12h, Bank 3 PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
13h, Bank 3 PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
11h, Bank 7 PW3DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition,
shaded cells are not used by Timer1 or Timer2.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
0 10 20 30 40 0
PWM
output
Frequency (kHz)
period of PWM3 = [(PR1) + 1] x 4TOSC or
[(PR2) + 1] x 4TOSC PWM
Frequency 32.2 64.5 90.66 128.9 515.6
The duty cycle of PWMx is determined by the 10-bit
value DCx<9:0>. The upper 8-bits are from register PRx Value 0xFF 0x7F 0x5A 0x3F 0x0F
PWxDCH and the lower 2-bits are from PWxDCL<7:6> High 10-bit 9-bit 8.5-bit 8-bit 6-bit
(PWxDCH:PWxDCL<7:6>). Table 13-4 shows the Resolution
maximum PWM frequency (FPWM) given the value in
Standard 8-bit 7-bit 6.5-bit 6-bit 4-bit
the period register.
Resolution
The number of bits of resolution that the PWM can
achieve depends on the operation frequency of the 13.1.3.2 PWM INTERRUPTS
device as well as the PWM frequency (FPWM).
The PWM modules makes use of the TMR1 and/or
Maximum PWM resolution (bits) for a given PWM fre- TMR2 interrupts. A timer interrupt is generated when
quency: TMR1 or TMR2 equals its period register and on the
following increment is cleared to zero. This interrupt
log ( FFPWM
OSC
) also marks the beginning of a PWM cycle. The user
= bits can write new duty cycle values before the timer
log (2) roll-over. The TMR1 interrupt is latched into the
TMR1IF bit and the TMR2 interrupt is latched into the
where: FPWM = 1 / period of PWM TMR2IF bit. These flags must be cleared in software.
The PWMx duty cycle is as follows:
PWMx Duty Cycle =(DCx) x TOSC
where DCx represents the 10-bit value from
PWxDCH:PWxDCL.
16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
16h, Bank 7 TCON3 CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
10h, Bank 2 TMR1 Timer1s register xxxx xxxx uuuu uuuu
11h, Bank 2 TMR2 Timer2s register xxxx xxxx uuuu uuuu
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
06h, Unbanked CPUSTA STKAV GLINTD TO PD POR BOR --11 1100 --11 qq11
14h, Bank 2 PR1 Timer1 period register xxxx xxxx uuuu uuuu
15h, Bank 2 PR2 Timer2 period register xxxx xxxx uuuu uuuu
10h, Bank 3 PW1DCL DC1 DC0 xx-- ---- uu-- ----
11h, Bank 3 PW2DCL DC1 DC0 TM2PW2 xx0- ---- uu0- ----
10h, Bank 7 PW3DCL DC1 DC0 TM2PW3 xx0- ---- uu0- ----
12h, Bank 3 PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
13h, Bank 3 PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
11h, Bank 7 PW3DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends on conditions,
shaded cells are not used by PWM Module.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
FIGURE 13-8: TIMER3 WITH THREE CAPTURE AND ONE PERIOD REGISTER BLOCK DIAGRAM
Capture2
Edge select, Enable
Prescaler select
RB1/CAP2
2 CA2H CA2L
Capture3
Edge select, Enable
Prescaler select
RG4/CAP3
2 CA3H CA3L
Capture4
Edge select, Enable
Prescaler select
RE3/CAP4
2 CA4H CA4L
RB5/TCLK3 TMR3ON
TMR3CS (TCON2<2>)
(TCON1<2>)
16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
16h, Bank 7 TCON3 CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
12h, Bank 2 TMR3L Holding register for the low byte of the 16-bit TMR3 register xxxx xxxx uuuu uuuu
13h, Bank 2 TMR3H Holding register for the high byte of the 16-bit TMR3 register xxxx xxxx uuuu uuuu
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF BCLIF ADIF CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
06h, Unbanked CPUSTA STKAV GLINTD TO PD POR BOR --11 1100 --11 qq11
16h, Bank 2 PR3L/CA1L Timer3 period register, low byte/capture1 register, low byte xxxx xxxx uuuu uuuu
17h, Bank 2 PR3H/CA1H Timer3 period register, high byte/capture1 register, high byte xxxx xxxx uuuu uuuu
14h, Bank 3 CA2L Capture2 low byte xxxx xxxx uuuu uuuu
15h, Bank 3 CA2H Capture2 high byte xxxx xxxx uuuu uuuu
12h, Bank 7 CA3L Capture3 low byte xxxx xxxx uuuu uuuu
13h, Bank 7 CA3H Capture3 high byte xxxx xxxx uuuu uuuu
14h, Bank 7 CA4L Capture4 low byte xxxx xxxx uuuu uuuu
15h, Bank 7 CA4H Capture4 high byte xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition,
shaded cells are not used by Capture.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
When TMR3CS is set, the 16-bit TMR3 increments on Since Timer3 is a 16-bit timer and only 8-bits at a time
the falling edge of clock input TCLK3. The input on the can be read or written, care should be taken when
RB5/TCLK3 pin is sampled and synchronized by the reading or writing while the timer is running. The best
internal phase clocks twice every instruction cycle. This method is to stop the timer, perform any read or write
causes a delay from the time a falling edge appears on operation, and then restart Timer3 (using the TMR3ON
TCLK3 to the time TMR3 is actually incremented. For bit). However, if it is necessary to keep Timer3 free-run-
the external clock input timing requirements, see the ning, care must be taken. For writing to the 16-bit
Electrical Specification section. Figure 13-10 shows TMR3, Example 13-2 may be used. For reading the
the timing diagram when operating from an external 16-bit TMR3, Example 13-3 may be used. Interrupts
clock. must be disabled during this routine.
FIGURE 13-10: TIMER1, TIMER2, AND TIMER3 OPERATION (IN COUNTER MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TCLK12
or TCLK3
WR_TMR
RD_TMR
TMRxIF
MOVWF MOVFP MOVFP
Instruction TMRx TMRx,W TMRx,W
executed Write to TMRx Read TMRx Read TMRx
AD15:AD0
ALE
Instruction MOVWF MOVF MOVF MOVLB 3 BSF NOP BCF NOP NOP NOP NOP
fetched TMR1 TMR1, W TMR1, W TCON2, 0 TCON2, 0
Write TMR1 Read TMR1 Read TMR1 Stop TMR1 Start TMR1
TMR1 04h 05h 03h 04h 05h 06h 07h 08h 00h
PR1
TMR1ON
WR_TMR1
WR_TCON2
TMR1IF
RD_TMR1
TMR1 TMR1
reads 03h reads 04h
BRG 4
Clock 16
Start 0 1 7 8 Stop
DT Load
TXEN/
Write to TXREG
8 Bit Count
TXREG 0 1 7
Interrupt
TXSTA<0>
Data Bus
TXIE
Master/Slave Sync/Async
Sync Async/Sync
RCIE
enable
Buffer
Logic Bit Count
CK 16
START
SPEN Detect SREN/
CREN/
Buffer Majority RSR Start_Bit
Clock
Logic Detect
RX MSb LSb
Data
Stop 8 7 1 0
FIFO
RX9 Logic
Async/Sync
RCREG
RX9D 7 1 0 Clk
FERR
FIFO
FERR RX9D 7 1 0
Data Bus
13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
USART1
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud rate generator register xxxx xxxx uuuu uuuu
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
USART2
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud rate generator register xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used by the Baud Rate
Generator.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
Write to TXREG
Word 1
BRG output
(shift clock)
TX
(TX/CK pin) Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit
Word 1
TXIF bit
Word 1
Transmit Shift Reg
TRMT bit
Write to TXREG
Word 1 Word 2
BRG output
(shift clock)
TX
(TX/CK pin) Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit Start Bit Bit 0
Word 1 Word 2
TXIF bit
Word 1 Word 2
Transmit Shift Reg. Transmit Shift Reg.
TRMT bit
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
16h, Bank 0 TXREG1 Serial port transmit register (USART1) xxxx xxxx uuuu uuuu
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud rate generator register (USART1) xxxx xxxx uuuu uuuu
10h, Bank 4 PIR2 SSPIF BCLIF ADIF CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
16h, Bank 4 TXREG2 Serial port transmit register (USART2) xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud rate generator register (USART2) xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous
transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
x16 CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Samples
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank 0 RCREG1 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud rate generator register xxxx xxxx uuuu uuuu
10h, Bank 4 PIR2 SSPIF BCLIF ADIF CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank 4 RCREG2 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud rate generator register xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous
reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
16h, Bank 0 TXREG1 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 xxxx xxxx uuuu uuuu
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud rate generator register xxxx xxxx uuuu uuuu
10h, Bank 4 PIR2 SSPIF BCLIF ADIF CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
16h, Bank 4 TXREG2 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud rate generator register xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous
master transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
TRMT
'1'
TXEN
CK
(TX/CK pin)
Write to
TXREG
TXIF bit
TRMT bit
Once synchronous mode is selected, reception is 1. Initialize the SPBRG register for the appropriate
enabled by setting either the SREN (RCSTA<5>) bit or baud rate. See Section 14.1 for details.
the CREN (RCSTA<4>) bit. Data is sampled on the 2. Enable the synchronous master serial port by
RX/DT pin on the falling edge of the clock. If SREN is setting bits SYNC, SPEN, and CSRC.
set, then only a single word is received. If CREN is set, 3. If interrupts are desired, then set the RCIE bit.
the reception is continuous until CREN is reset. If both 4. If 9-bit reception is desired, then set the RX9 bit.
bits are set, then CREN takes precedence. After clock- 5. If a single reception is required, set bit SREN.
ing the last bit, the received data in the Receive Shift For continuous reception set bit CREN.
Register (RSR) is transferred to RCREG (if it is empty).
6. The RCIF bit will be set when reception is com-
If the transfer is complete, the interrupt bit RCIF is set.
plete and an interrupt will be generated if the
The actual interrupt can be enabled/disabled by set-
RCIE bit was set.
ting/clearing the RCIE bit. RCIF is a read only bit which
is RESET by the hardware. In this case it is reset when 7. Read RCSTA to get the ninth bit (if enabled) and
RCREG has been read and is empty. RCREG is a dou- determine if any error occurred during reception.
ble buffered register; i.e., it is a two deep FIFO. It is 8. Read the 8-bit received data by reading
possible for two bytes of data to be received and trans- RCREG.
ferred to the RCREG FIFO and a third byte to begin 9. If any error occurred, clear the error by clearing
shifting into the RSR. On the clocking of the last bit of CREN.
the third byte, if RCREG is still full, then the overrun
error bit OERR (RCSTA<1>) is set. The word in the
RSR will be lost. RCREG can be read twice to retrieve Note: To terminate a reception, either clear the
the two bytes in the FIFO. The OERR bit has to be SREN and CREN bits, or the SPEN bit.
cleared in software. This is done by clearing the CREN This will reset the receive logic, so that it
bit. If OERR is set, transfers from RSR to RCREG are will be in the proper state when receive is
inhibited, so it is essential to clear the OERR bit if it is re-enabled.
set. The 9th receive bit is buffered the same way as the
receive data. Reading the RCREG register will allow
the RX9D and FERR bits to be loaded with values for
the next received data; therefore, it is essential for the
user to read the RCSTA register before reading
RCREG in order not to lose the old FERR and RX9D
information.
SREN bit
CREN bit '0' '0'
RCIF bit
Read
RCREG
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank 0 RCREG1 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud rate generator register xxxx xxxx uuuu uuuu
10h, Bank 4 PIR2 SSPIF BCLIF ADIF CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank 4 RCREG2 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud rate generator register xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous
master reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
16h, Bank 0 TXREG1 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 xxxx xxxx uuuu uuuu
17h, Bank 0 SPBRG1 Baud rate generator register xxxx xxxx uuuu uuuu
10h, Bank 4 PIR2 SSPIF BCLIF ADIF CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
16h, Bank 4 TXREG2 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud rate generator register xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous
slave transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
16h, Bank1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010
17h, Bank1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
13h, Bank0 RCSTA1 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank0 RCREG1 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud rate generator register xxxx xxxx uuuu uuuu
10h, Bank 4 PIR2 SSPIF BCLIF ADIF CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank 4 RCREG2 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud rate generator register xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous
slave reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
SS Control shift
Enable clock
SS SSPSR reg
Edge
Select SDA MSb LSb
2 Addr Match
Match detect
Clock Select
SSPM3:SSPM0
SSPADD reg
SMP:CKE 4 TMR2 output
2 2
Start and Stop bit Set/Clear S bit
Edge and
Select detect / generate Clear/Set P, bits
Prescaler TOSC
SCK 4, 16, 64 (SSPSTAT reg)
and Set SSPIF
Data to TX/RX in SSPSR
Data direction bit
(SPI MODE)
appropriately programmed. That is:
SDI is automatically controlled by the SPI module
Internal
data bus SDO must have DDRB<7> cleared
Read Write SCK (Master mode) must have DDRB<6> cleared
SCK (Slave mode) must have DDRB<6> set
SSPBUF reg SS must have PORTA<2> set
Note: The SS pin must be configured as an input
for the slave select to operate. This is done
by writing a 1 to PORTA<2>.
SSPSR reg
Any serial port function that is not desired may be over-
SDI bit0 shift
clock ridden by programming the corresponding data direc-
tion (DDR) register to the opposite value. An example
SDO would be in master mode where you are only sending
data (to a display driver), then both SDI and SS could
be used as general purpose open drain outputs by writ-
SS Control ing a 0.
Enable
Figure 15-9 shows a typical connection between two
SS Edge microcontrollers. The master controller (Processor 1)
Select initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
2 grammed clock edge, and latched on the opposite
Clock Select
edge of the clock. Both processors should be pro-
grammed to same Clock Polarity (CKP), then both con-
SSPM3:SSPM0
SMP:CKE 4 trollers would send and receive data at the same time.
TMR2 output Whether the data is meaningful (or dummy data)
2 2
Edge depends on the application software. This leads to
Select Prescaler TOSC three scenarios for data transmission:
SCK 4, 16, 64 Master sends data Slave sends dummy data
Data to TX/RX in SSPSR Master sends data Slave sends data
Data direction bit Master sends dummy data Slave sends data
15.1.1 MASTER MODE MSB is transmitted first. In master mode, the SPI clock
rate (bit rate) is user programmable to be one of the fol-
The master can initiate the data transfer at any time lowing:
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 15-9) is to broad- FOSC/4 (or TCY)
cast data by the software protocol. FOSC/16 (or 4 TCY)
In master mode the data is transmitted/received as FOSC/64 (or 16 TCY)
soon as the SSPBUF register is written to. If the SPI is Timer2 output/2
only going to receive, the SCK output could be disabled This allows a maximum bit clock frequency (at 33 MHz)
(programmed as an input). The SSPSR register will of 8.25 MHz.
continue to shift in the signal present on the SDI pin at
Figure 15-8 Shows the waveforms for master mode.
the programmed clock rate. As each byte is received, it
When CKE = 1, the SDO data is valid before there is a
will be loaded into the SSPBUF register as if a normal
clock edge on SCK. The change of the input sample is
received byte (interrupts and status bits appropriately
shown based on the state of the SMP bit. The time
set). This could be useful in receiver applications as a
when the SSPBUF is loaded with the received data is
line activity monitor mode.
shown.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON1<4>). This then would give
waveforms for SPI communication as shown in
Figure 15-8, Figure 15-11, and Figure 15-12 where the
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 clock
SCK modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
In slave mode, the data is transmitted and received as The SS pin allows a synchronous slave mode. The
the external clock pulses appear on SCK. When the SPI must be in slave mode with SS pin control
last bit is latched the interrupt flag bit SSPIF (PIR2<7>) enabled (SSPCON1<3:0> = 04h). The pin must not
is set. be driven low for the SS pin to function as an input.
While in slave mode the external clock is supplied by The RA2 Data Latch must be high. When the SS pin
the external clock source on the SCK pin. This external is low, transmission and reception are enabled and
clock must meet the minimum high and low times as the SDO pin is driven. When the SS pin goes high,
specified in the electrical specifications. the SDO pin is no longer driven, even if in the
middle of a transmitted byte, and becomes a
While in sleep mode, the slave can transmit/receive floating output. External pull-up/ pull-down resistors
data and wake the device from sleep. may be desirable, depending on the application.
Note: When the SPI is in Slave Mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is set
to VDD.
Note: If the SPI is used in Slave Mode with
CKE = '1', then the SS pin control must be
enabled.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
In Figure 15-11 the SS pin terminates the transmis-
sion/reception. The SSPIF bit is set after the last edge
of the SCK. In Figure 15-12 the SS pin causes the first
bit of the data to be output. The SSPIF bit in set after
the last SCK edge.
SDO SDI
SDI SDO
Shift Register Shift Register
(SSPSR) (SSPSR)
PROCESSOR 1 PROCESSOR 2
SS
optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI bit0
(SMP = 0) bit7 bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
SS
optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI
(SMP = 0) bit7 bit0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
SS
not optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDI
(SMP = 0) bit7 bit0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF BCLIF ADIF CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
14h, Bank 6 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
11h, Bank 6 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
13h, Bank 6 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
SSPADD reg
15.2.1 SLAVE MODE a) The SSPSR register value is loaded into the
SSPBUF register.
In slave mode, the SCL and SDA pins must be config-
b) The buffer full bit, BF is set.
ured as inputs. The SSP module will override the input
state with the output data when required (slave-trans- c) An ACK pulse is generated.
mitter). d) SSP interrupt flag bit, SSPIF (PIR2<7>) is set
(interrupt is generated if enabled) - on the falling
When an address is matched or the data transfer after
edge of the ninth SCL pulse.
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and In 10-bit address mode, two address bytes need to be
then load the SSPBUF register with the received value received by the slave. The five Most Significant bits
currently in the SSPSR register. (MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
There are certain conditions that will cause the SSP
so the slave device will receive the second address
module not to give this ACK pulse. These are if either
byte. For a 10-bit address the first byte would equal
(or both):
1111 0 A9 A8 0, where A9 and A8 are the two MSbs
a) The buffer full bit BF (SSPSTAT<0>) was set of the address. The sequence of events for a 10-bit
before the transfer was received. address is as follows, with steps 7- 9 for slave-transmit-
b) The overflow bit SSPOV (SSPCON1<6>) was ter:
set before the transfer was received. 1. Receive first (high) byte of Address (bits SSPIF,
In this case, the SSPSR register value is not loaded BF, and bit UA (SSPSTAT<1>) are set).
into the SSPBUF, but bit SSPIF (PIR2<7>) is set. 2. Update the SSPADD register with second (low)
Table 15-2 shows what happens when a data transfer byte of Address (clears bit UA and releases the
byte is received, given the status of bits BF and SCL line).
SSPOV. The shaded cells show the condition where 3. Read the SSPBUF register (clears bit BF) and
user software did not properly clear the overflow condi- clear flag bit SSPIF.
tion. Flag bit BF is cleared by reading the SSPBUF reg-
4. Receive second (low) byte of Address (bits
ister while bit SSPOV is cleared through software.
SSPIF, BF, and UA are set).
The SCL clock input must have a minimum high and 5. Update the SSPADD register with the first (high)
low time for proper operation. The high and low times byte of Address, if match occurs releases the
of the I2C specification as well as the requirement of SCL line, this will clear bit UA.
the SSP module is shown in timing parameter #100
6. Read the SSPBUF register (clears bit BF) and
and parameter #101.
clear flag bit SSPIF.
15.2.1.1 ADDRESSING 7. Receive repeated START condition.
8. Receive first (high) byte of Address (bits SSPIF
Once the SSP module has been enabled, it waits for a and BF are set).
START condition to occur. Following the START condi-
9. Read the SSPBUF register (clears bit BF) and
tion, the 8-bits are shifted into the SSPSR register. All
clear flag bit SSPIF.
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is Note: Following the RESTART condition (step 7)
compared to the value of the SSPADD register. The in 10-bit mode, the user only needs to
address is compared on the falling edge of the eighth match the first 7-bit address. The user
clock (SCL) pulse. If the addresses match, and the BF does not update the SSPADD for the sec-
and SSPOV bits are clear, the following events occur: ond half of the address.
When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set
address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the
register is cleared. The received address is loaded into SSPSTAT register is set. The received address is
the SSPBUF register. loaded into the SSPBUF register. The ACK pulse will
When the address byte overflow condition exists, then be sent on the ninth bit, and the SCLpin is held low. The
no acknowledge (ACK) pulse is given. An overflow con- transmit data must be loaded into the SSPBUF register,
dition is defined as either bit BF (SSPSTAT<0>) is set which also loads the SSPSR register. Then SCL pin
or bit SSPOV (SSPCON1<6>) is set. should be enabled by setting bit CKP (SSPCON1<4>).
The master must monitor the SCL pin prior to asserting
An SSP interrupt is generated for each data transfer another clock pulse. The slave devices may be holding
byte. Flag bit SSPIF (PIR2<7>) must be cleared in soft- off the master by stretching the clock. The eight data
ware. The SSPSTAT register is used to determine the bits are shifted out on the falling edge of the SCL input.
status of the byte. This ensures that the SDA signal is valid during the
Note: The SSPBUF will be loaded if the SSPOV SCL high time (Figure 15-16).
bit = 1 and the BF flag = 0. If a read of the
SSPBUF was performed, but the user did
not clear the state of the SSPOV bit before
the next receive occured. The ACK is not
sent and the SSPBUF is updated.
SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Data in SCL held low
sampled while CPU
responds to SSPIF
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
cleared in software From SSP interrupt
SSPBUF is written in software service routine
CKP (SSPCON1<4>)
Transmitting Data
Receive First Byte of Address R/W = 0 Receive Second Byte of Address Receive First Byte of Address R/W=1 ACK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P
CKP has to be set for clock to be released
SSPIF
(PIR1<3>)
Cleared in software Cleared in software Cleared in software Bus Master
terminates
BF (SSPSTAT<0>) transfer
Preliminary
SSPBUF is written with Dummy read of SSPBUF Dummy read of SSPBUF Write of SSPBUF
contents of SSPSR to clear BF flag to clear BF flag initiates transmit
FIGURE 15-17: I2C SLAVE-TRANSMITTER (10-BIT ADDRESS)
UA (SSPSTAT<1>)
DS30264A-page 137
DS30264A-page 138
Bus Master
PIC17C75X
terminates
Clock is held low until transfer
update of SSPADD has
taken place
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF
(PIR1<3>)
Cleared in software Cleared in software
Preliminary
FIGURE 15-18: I2C SLAVE-RECEIVER (10-BIT ADDRESS)
BF (SSPSTAT<0>)
SSPBUF is written with Dummy read of SSPBUF Dummy read of SSPBUF Read of SSPBUF
contents of SSPSR to clear BF flag to clear BF flag clears BF flag
UA (SSPSTAT<1>)
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPIF (PIR2<7>)
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF BCLIF ADIF CA4IF CA3IF TX2IF RC2IF 00-- 0000 00-- 0000
11h, Bank 4 PIE2 SSPIE BCLIE ADIE CA4IE CA3IE TX2IE RC2IE 00-- 0000 00-- 0000
10h. Bank 6 SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
14h, Bank 6 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
11h, Bank 6 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
12h, Bank 6 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
13h, Bank 6 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in I2C mode.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
Internal SSPM3:SSPM0
data bus SSPADD<6:0>
Read Write
SSPBUF Baud
rate
generator
SDA shift
Acknowledge
Generate
SCL
In multi-master mode, the interrupt generation on the The master device generates all of the serial clock
detection of the START and STOP conditions allows pulses and the START and STOP conditions. A trans-
the determination of when the bus is free. The STOP fer is ended with a STOP condition or with a repeated
(P) and START (S) bits are cleared from a reset or START condition. Since the repeated START condi-
when the SSP module is disabled. Control of the I 2C tion is also the beginning of the next serial transfer, the
bus may be taken when bit P (SSPSTAT<4>) is set, or I2C bus will not be released.
the bus is idle with both the S and P bits clear. When In Master transmitter mode serial data is output
the bus is busy, enabling the SSP Interrupt will gener- through SDA, while SCL outputs the serial clock. The
ate the interrupt when the STOP condition occurs. first byte transmitted contains the slave address of the
In multi-master operation, the SDA line must be moni- receiving device, (7 bits) and the data direction bit. In
tored to see if the signal level is the expected output this case the data direction bit (R/W) will be logic '0'.
level. This check is performed in hardware, with the Serial data is transmitted 8 bits at a time. After each
result placed in the BCLIF bit. byte is transmitted, an acknowledge bit is received.
The states where arbitration can be lost are: START and STOP conditions are output to indicate the
beginning and the end of a serial transfer.
Address Transfer
Data Transfer In Master receive mode the first byte transmitted con-
A Start Condition tains the slave address of the transmitting device
A Restart Condition (7 bits) and the data direction bit. In this case the data
An Acknowledge Condition direction bit (R/W) will be logic '1'. Thus the first byte
transmitted is a 7-bit slave address followed by a '1' to
15.2.5 I2C MASTER MODE SUPPORT indicate receive bit. Serial data is received via SDA
while SCL outputs the serial clock. Serial data is
Master Mode is enabled by setting and clearing the received 8 bits at a time. After each byte is received,
appropriate SSPM bits in SSPCON1 and by setting an acknowledge bit is transmitted. START and STOP
the SSPEN bit. Once master mode is enabled, the conditions indicate the beginning and end of transmis-
user has six options. sion.
- Assert a start condition on SDA and SCL. The baud rate generator used for SPI mode operation
- Assert a restart condition on SDA and SCL. is now used to set the SCL clock frequency for either
- Write to the SSPBUF register initiating trans- 100 kHz, 400 kHz, or 1 MHz I2C operation. The baud
mission of data/address. rate generator reload value is contained in the lower 7
- Generate a stop Condition on SDA and SCL. bits of the SSPADD register. The baud rate generator
- Configure the I2C port to receive data. will automatically begin counting on a write to the
- Generate an acknowledge condition at the end SSPBUF. Once the given operation is complete (i.e.
of a received byte of data. transmission of the last data bit is followed by ACK)
the internal clock will automatically stop counting and
the SCL pin will remain in its last state
Note: The SSP Module when configured in I2C
Master Mode does not allow queueing of A typical transmit sequence would go as follows:
events. For instance: The user is not 1. The user generates a Start Condition by setting
allowed to intitiate a start condition, and the START enable bit (SEN) in SSPCON2.
immediately write the SSPBUF register to 2. SSPIF is set. The module will wait the required
initate transmission before the START con- start time before any other operation takes
dition is complete. In this case the SSP- place.
BUF will not be written to, and the WCOL 3. The user loads the SSPBUF with address to
bit will be set, indicating that a write to the transmit.
SSPBUF did not occur.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The SSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
6. The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
7. The user loads the SSPBUF with eight bits of
data.
8. DATA is shifted out the SDA pin until all 8 bits
are transmitted.
SSPM3:SSPM0 SSPADD<6:0>
SDA DX DX-1
BRG
00h 03h 02h 01h 00h XX 03h 02h 01h 00h
value
SCL is sampled high, reload takes
place, and BRG starts its count.
BRG
reload
Note: There are two baud rate overflows per clock period. Clock period may be of variable time due to clock arbitration.
SCL TBRG
S
SSPEN = 1,
SSPCON1<3:0> = 1000
Idle Mode
SEN (SSPCON2<0> = 1)
Yes
No
Yes No No BRG
SCL= 0? SDA = 0? Rollover?
Yes Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>,
Set S bit and SSPIF.
No No BRG
SCL = 0? rollover?
Yes
Yes
Reset BRG
Force SCL = 0,
Start Condition Done,
Clear SEN.
1st Bit
SDA
Falling edge of ninth clock Write to SSPBUF occurs here.
End of Xmit
TBRG
SCL TBRG
Sr = Restart
Start
B
Idle Mode,
SSPEN = 1,
SSPCON1<3:0> = 1000
RSEN = 1(SSPCON2<1>)
Force SCL = 0
No
SCL = 0?
Yes
Release SDA,
Load BRG with
SSPADD<6:0>
BRG No
rollover?
Yes
Release SCL
(Clock Arbitration)
No
SCL = 1?
Yes
Bus Collision,
No
Set BCLIF, SDA = 1?
Release SDA,
Clear RSEN
Yes
C A
B
C A
Yes
No No No BRG
SCL = 1? SDA = 0? rollover?
Yes Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>
Set S,
Set SSPIF
No BRG
rollover?
Yes
Force SCL = 0,
Restart condition done,
Clear RSEN
Transmission of a data byte, a 7-bit address, or the In transmit mode, the BF bit (SSPSTAT<0>) is set
either half of a 10-bit address is accomplished by sim- when the CPU writes to SSPBUF and is cleared when
ply writing a value to SSPBUF register. This action will all 8 bits are shifted out.
set the buffer full flag (BF) and allow the baud rate
generator to begin counting and start the next trans- 15.2.9.2 WCOL STATUS FLAG
mission. Each bit of address/data will be shifted out
If the user writes the SSPBUF when a transmit is
onto the SDA pin after the falling edge of SCL is
already in progress (i.e. SSPSR is still shifting out a
asserted (see data hold time spec). SCL is held low
data byte), then WCOL is set and the contents of the
for one baud rate generator roll over count (TBRG).
buffer are unchanged (the write doesnt occur).
Data should be valid before SCL is released high (see
Data setup time spec). When the SCL pin is released WCOL must be cleared in software.
high, it is held that way for TBRG, the data on the SDA
15.2.9.3 AKSTAT STATUS FLAG
pin must remain stable for that duration and some hold
time after the next falling edge of SCL. After the In transmit mode, the AKSTAT bit (SSPCON2<6>) is
eighth bit is shifted out (the falling edge of the eighth cleared when the slave has sent an acknowledge
clock), the BF flag is cleared and the master releases (ACK = 0), and is set when the slave does not
SDA allowing the slave device being addressed to acknowledge (ACK = 1). A slave sends an acknowl-
respond with an ACK bit during the ninth bit time, if an edge when it has recognized its address (including a
address match occurs or if data was received properly. general call), or when the slave has properly received
The status of ACK is read into the SSPCON2 register its data.
bit6 on the falling edge of the ninth clock. If the master
receives an acknowledge, the acknowledge status bit
(AKSTAT) is cleared. If not, the bit is set. After the
ninth clock the SSPIF is set, and the master clock
(baud rate generator) is suspended until the next data
byte is loaded into the SSPBUF leaving SCL low and
SDA unchanged. (Figure 15-29)
Idle Mode
Write SSPBUF
Num_Clocks = 0,
BF = 1
Force SCL = 0
No
Load BRG with
Load BRG with SSPADD<6:0>,
SSPADD<6:0>, start BRG count
start BRG count,
SDA = Current Data bit
BRG No
rollover?
BRG No
rollover?
Yes
Yes
Yes
Load BRG with
SSPADD<6:0>,
Bus collision detected count high time
SDA = No
Data bit? Set BCLIF, hold prescale off
Clear XMIT enable
Yes No
Rollover?
Load BRG with
SSPADD<6:0>,
count SCL high time
Yes
Yes Read SDA and place into
AKSTAT bit (SSPCON2<6>)
No No No
BRG SDA =
rollover? SCL = 0? Data bit?
Force SCL = 0,
Yes BF = 0,
Set SSPIF
Yes Reset BRG
Num_Clocks
= Num_Clocks + 1
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
Preliminary
BF (SSPSTAT<0>)
PEN
FIGURE 15-29: I 2C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)
PIC17C75X
DS30264A-page 151
PIC17C75X
15.2.10 I2C MASTER MODE RECEPTION 15.2.10.1 BF STATUS FLAG
Master mode reception is enabled by programming In receive operation, BF is set when an address or
the receive enable bit, RCEN (SSPCON2<3>). data byte is loaded into SSPBUF from SSPSR. It is
Note:
cleared when SSPBUF is read.
The SSP Module must be in IDLE mode
before the RCE bit is set, or the RCEN bit 15.2.10.2 SSPOV STATUS FLAG
will be disreguarded.
In receive operation, SSPOV is set when 8 bits are
The baud rate generator begins counting, and on
received into the SSPSR, and the BF flag is already
each rollover, the state of the SCL pin changes (high
set from a previous reception.
to low/low to high), and data is shifted into the SSPSR.
After the falling edge of the eighth clock, the receive 15.2.10.3 WCOL STATUS FLAG
enable flag is automatically cleared, the contents of
the SSPSR are loaded into the SSPBUF, the BF flag is If the user writes the SSPBUF when a receive is
set, the SSPIF is set, and the baud rate generator is already in progress (i.e. SSPSR is still shifting in a
suspended from counting, holding SCL low. The SSP data byte), then WCOL is set and the contents of the
is now in IDLE state, awaiting the next command. buffer are unchanged (the write doesnt occur).
When the buffer is read by the CPU, the BF flag is
automatically cleared. The user can then send an
acknowledge bit at the end of reception, by setting the
acknowledge sequence enable bit, ACKEN
(SSPCON2<4>).
RCEN = 1
Num_Clocks = 0,
Release SDA
Force SCL=0,
Load BRG w/
SSPADD<6:0>,
start count
BRG No
rollover?
Yes
Release SCL
(Clock Arbitration)
No
SCL = 1?
Yes
BRG No
rollover?
Yes
Sample SDA,
Shift data into SSPSR
Num_Clocks
= Num_Clocks + 1
No
Num_Clocks
= 8?
Yes
Force SCL = 0,
Set SSPIF,
Set BF.
Move contents of SSPSR
into SSPBUF,
Clear RCEN.
Bus Master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Set SSPIF at end
of recieve Set SSPIF interrupt
Set SSPIF interrupt at end of acknow-
Set SSPIF interrupt ledge sequence
SSPIF at end of recieve
at end of acknowledge
(PIR2<7>) sequence
Set P bit
Cleared in software Cleared in software Cleared in software (SSPSTAT<4>)
Preliminary
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPIF
responds to SSPIF
BF
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
FIGURE 15-31: I 2C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS)
ACKEN
An acknowledge sequence is enabled by setting the If the user writes the SSPBUF when an acknowledege
acknowledge sequence enable bit, ACKEN sequence is in progress, then WCOL is set and the
(SSPCON2<4>). When this bit is set, the SCL pin is contents of the buffer are unchanged (the write doesnt
pulled low and the contents of the acknowledge data occur).
bit is presented on the SDA pin. If the user wishes to
generate an acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an acknowledge sequence. The baud
rate generator then counts for one rollover period
(TBRG), and the SCL pin is de-asserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
the baud rate generator counts for TBRG . The SCL
pin is then pulled low for one TBRG. Following this,
the ACKEN bit is automatically cleared, the baud rate
generator is turned off, and the SSP module then goes
into IDLE mode. (Figure 15-32)
TBRG TBRG
SDA D0 ACK
SCL 8 9
SSPIF
Idle mode
Set ACKEN
Force SCL = 0
BRG Yes
rollover?
No
No
SCL = 0?
Yes
Force SCL = 0,
Yes SCL = 0? Reset BRG Clear ACKEN
Yes
No BRG
rollover?
Yes
SDA = 1?
Yes
No
Force SCL = 1
Yes
Write to SSPCON2
Set PEN SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high, PEN bit (SSPCON2<2>) is
Falling edge of automatically cleared. P bit (SSPSTAT<4>) is set
9th clock
TBRG
SCL
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
Idle Mode,
SSPEN = 1,
SSPCON1<3:0> = 1000
Force SDA = 0
SCL doesnt change
BRG No
rollover?
Yes
No
SDA = 0? Release SDA,
Start BRG
Yes
Start BRG
BRG No
rollover?
BRG No Yes
rollover?
Bus Collision detected,
No
Yes P bit Set? Set BCLIF,
Clear SPEN
De-assert SCL,
SCL = 1
Yes
Yes
SCL
SDA
SDA
BCLIF
SDA
SCL
Set SEN, enable start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL=1 SSP module reset into idle state.
SEN
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1
SSPIF and BCLIF are
cleared in software.
SSPIF
SDA = 0, SCL = 1
TBRG TBRG
SDA
SSPIF
FIGURE 15-40: BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA = 0, SCL = 1
Set S, SSPIF
Less than TBRG TBRG
S
SCL Set SEN, enable start
sequence if SDA = 1, SCL = 1
SEN
BCLIF
SSPIF
SDA = 0, SCL = 1 Interrupts cleared
Set S, SSPIF in software.
SDA
SCL
RSEN
BCLIF
Cleared in software
S
SSPIF
TBRG TBRG
SDA
SCL
SSPIF
PEN
BCLIF
SSPIF
SDA
Assert SDA SCL goes low before SDA goes high
Set BCLIF
SCL
PEN
BCLIF
SSPIF
Rp Rp DEVICE
Rs Rs
SDA
SCL
2 Cb=10 - 400 pF
NOTE: I C devices with input levels related to VDD must have one common supply
line to which the pull up resistor is also connected.
16.0 ANALOG-TO-DIGITAL The A/D module has four registers. These registers
CONVERTER (A/D) MODULE are:
A/D Result High Register (ADRESH)
The analog-to-digital (A/D) converter module has
twelve analog inputs for the PIC17C75X devices. A/D Result Low Register (ADRESL)
A/D Control Register0 (ADCON0)
The A/D allows conversion of an analog input signal to
a corresponding 10-bit digital number. The output of the A/D Control Register1 (ADCON1)
sample and hold is the input into the converter, which The ADCON0 register, shown in Figure 16-1, controls
generates the result via successive approximation. the operation of the A/D module. The ADCON1 regis-
The analog reference voltages (positive and negative ter, shown in Figure 16-2, configures the functions of
supply) are software selectable to either the devices the port pins. The port pins can be configured as ana-
supply voltages (AVDD, AVss) or the voltage level on log inputs (RG3 and RG2 can also be the voltage refer-
the RG3/AN0/VREF+ and RG2/AN1/VREF- pins. ences) or as digital I/O.
PCFG3:PCFG1 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
000 A A A A A A A A A A A A
001 A A A A D A A A A A A A
010 A A A A D D A A A A A A
011 A A A A D D D A A A A A
100 A A A A D D D D A A A A
101 D A A A D D D D D A A A
110 D D A A D D D D D D A A
111 D D D D D D D D D D D D
A = Analog input D = Digital I/O
The ADRESH:ADRESL registers contains the 10-bit 2. Configure A/D interrupt (if desired):
result of the A/D conversion. When the A/D conversion Clear ADIF bit
is complete, the result is loaded into this A/D result reg- Set ADIE bit
ister pair, the GO/DONE bit (ADCON0<2>) is cleared,
Clear GLINTD bit
and A/D interrupt flag bit ADIF is set. The block dia-
grams of the A/D module are shown in Figure 16-3. 3. Wait the required acquisition time.
4. Start conversion:
After the A/D module has been configured as desired,
the selected channel must be acquired before the con- Set GO/DONE bit (ADCON0)
version is started. The analog input channels must 5. Wait for A/D conversion to complete, by either:
have their corresponding DDR bits selected as inputs. Polling for the GO/DONE bit to be cleared
To determine acquisition time, see Section 16.1. After
OR
this acquisition time has elapsed the A/D conversion
can be started. The following steps should be followed Waiting for the A/D interrupt
for doing an A/D conversion: 6. Read A/D Result register pair
1. Configure the A/D module: (ADRESH:ADRESL), clear bit ADIF if required.
Configure analog pins / voltage reference / 7. For next conversion, go to step 1 or step 2 as
and digital I/O (ADCON1) required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
Select A/D input channel (ADCON0)
required before next acquisition starts.
Select A/D conversion clock (ADCON0)
Turn on A/D module (ADCON0)
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
0100
AN4
VIN
(Input voltage) 0011
AN3
0010
A/D AN2
Converter
0001
AN1
PCFG0 0000
AN0
VREF-
(Reference AVSS
voltage)
VREF+
AVDD
16.1 A/D Acquisition Requirements Example 16-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
For the A/D converter to meet its specified accuracy,
based on the following application system assump-
the charge holding capacitor (CHOLD) must be allowed
tions.
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 16-4. The source CHOLD = 200 pF
impedance (RS) and the internal sampling switch (RSS) Rs = 10 k
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS) 1/2 LSb error
impedance varies over the device voltage (VDD), VDD = 5V Rss = 7 k
Figure 16-4. The source impedance affects the offset Temp (application system max.) = 50C
voltage at the analog input (due to pin leakage current).
The maximum recommended impedance for ana- VHOLD = 0 @ t = 0
log sources is 10 k. After the analog input channel is
selected (changed) this acquisition must be done Note 1: The reference voltage (VREF) has no
before the conversion can be started. effect on the equation, since it cancels
itself out.
To calculate the minimum acquisition time,
Equation 16-1 may be used. This equation calculates Note 2: The charge holding capacitor (CHOLD) is
the acquisition time to within 1/2 LSb error (1024 steps not discharged after each conversion.
for the A/D). The 1/2 LSb error is the maximum error Note 3: The maximum recommended impedance
allowed for the A/D to meet its specified accuracy. for analog sources is 10 k. This is
required to meet the pin leakage specifi-
EQUATION 16-1: A/D MINIMUM CHARGING cation.
TIME (FOR CHOLD) Note 4: After a conversion has completed, a
VHOLD = (VREF - (VREF/2048)) (1 - e(-Tcap/CHOLD(RIC + RSS + RS))) 2.0TAD delay must complete before acqui-
sition can begin again. During this time the
given VHOLD = (VREF/2048), for 1/2 LSb resolution
holding capacitor is not connected to the
VREF = VREF+ - VREF- selected A/D input channel.
or
Tcap = -(200 pF)(1 k + RSS + RS) ln(1/2047)
CHOLD
VA CPIN I leakage = DAC capacitance
5 pF VT = 0.6V 500 nA = 200 pF
VSS
EXAMPLE 16-1: CALCULATING THE 16.2 Selecting the A/D Conversion Clock
MINIMUM REQUIRED The A/D conversion time per bit is defined as TAD. The
ACQUISITION TIME A/D conversion requires a minimum 12TAD per 10-bit
TACQ = Amplifier Settling Time + conversion. The source of the A/D conversion clock is
Holding Capacitor Charging Time + software selected. The four possible options for TAD
Temperature Coefficient are:
TABLE 16-1: TAD vs. DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
Note 1: When reading the port register, any pin Note: The GO/DONE bit should NOT be set in
configured as an analog input channel will the same instruction that turns on the A/D.
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an ana- Clearing the GO/DONE bit during a conversion will
log input. Analog levels on a digitally abort the current conversion. The A/D result register
configured input will not affect the conver- pair will NOT be updated with the partially completed
sion accuracy. A/D conversion sample. That is, the
ADRESH:ADRESL registers will continue to contain
Note 2: Analog levels on any pin that is defined as the value of the last completed conversion (or the last
a digital input (including the AN11:AN0 value written to the ADRESH:ADRESL registers). After
pins), may cause the input buffer to con- the A/D conversion is aborted, a 2TAD wait is required
sume current that is out of the devices before the next acquisition is started. After this 2TAD
specification. wait, acquisition on the selected channel is automati-
cally started.
10-Bit Result
ADFM = 1 ADFM = 0
7 2107 0 7 0765 0
0000 00 RESULT RESULT 0000 00
10-bits 10-bits
1 LSb
1.5 LSb
2 LSb
2.5 LSb
3 LSb
1022 LSb
1022.5 LSb
1023 LSb
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
No No
No No
Wait 2TAD
11h, Bank 5 PORTF RF7/ RF6/ RF5/ RF4/ RF3/ RF2/ RF1/ RF0/ 0000 0000 0000 0000
AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4
12h, Bank 5 DDRG Data Direction register for PORTG 1111 1111 1111 1111
13h, Bank 5 PORTG RG7/ RG6/ RG5/ RG4/ RG3/ RG2/ RG1/ RG0/ xxxx 0000 uuuu 0000
TX2/CK2 RX2/DT2 PWM3 CAP3 AN0/VREF+ AN1/VREF AN2 AN3
-
14h, Bank 5 ADCON0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 -0-0 0000 -0-0
15h, Bank 5 ADCON1 ADCS1 ADCS0 ADFM PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000
16h, Bank 5 ADRESL A/D Result Low Register xxxx xxxx uuuu uuuu
17h, Bank 5 ADRESH A/D Result High Register xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
U-x U-x R/P - 1 U - x R/P - 1 R/P - 1 R/P - 1 R/P - 1 R/P - 1 Low (L) Table Read Addr.
PM1 PM0 WDTPS1 WDTPS0 FOSC1 FOSC0 FE07h - FE00h
bit15 bit 8 bit 7 bit 0
Bit Address
FOSC0 FE00h
FOSC1 FE01h
WDTPS0 FE02h
WDTPS1 FE03h
PM0 FE04h
PM1 FE06h
BODEN FE0Eh
PM2 FE0Fh
The Watchdog Timers function is to recover from The WDT and postscaler are cleared when:
software malfunction. The WDT uses an internal free The device is in the reset state
running on-chip RC oscillator for its clock source. This
A SLEEP instruction is executed
does not require any external components. This RC
oscillator is separate from the RC oscillator of the A CLRWDT instruction is executed
OSC1/CLKIN pin. That means that the WDT will run, Wake-up from SLEEP by an interrupt
even if the clock on the OSC1/CLKIN and The WDT counter/postscaler will start counting on the
OSC2/CLKOUT pins have been stopped, for example, first edge after the device exits the reset state.
by execution of a SLEEP instruction. During normal
operation and SLEEP mode, a WDT time-out 17.3.3 WDT PROGRAMMING CONSIDERATIONS
generates a device RESET. The WDT can be
permanently disabled by programming the configura- It should also be taken in account that under worst case
tion bits WDTPS1:WDTPS0 as '00' (Section 17.1). conditions (VDD = Min., Temperature = Max., max.
WDT postscaler) it may take several seconds before a
Under normal operation, the WDT must be cleared on WDT time-out occurs.
a regular interval. This time is less the minimum WDT
overflow time. Not clearing the WDT in this time frame The WDT and postscaler is the Power-up Timer during
will cause the WDT to overflow and reset the device. the Power-on Reset sequence.
The WDT has a nominal time-out period of 12 ms, (with When the WDT is selected as a normal timer, the clock
postscaler = 1). The time-out periods vary with temper- source is the device clock. Neither the WDT nor the
ature, VDD and process variations from part to part (see postscaler are directly readable or writable. The over-
DC specs). If longer time-out periods are desired, a flow time is 65536 TOSC cycles. On overflow, the TO bit
postscaler with a division ratio of up to 1:256 can be is cleared (device is not reset). The CLRWDT instruction
assigned to the WDT. Thus, typical time-out periods up can be used to set the TO bit. This allows the WDT to
to 3.0 seconds can be realized. be a simple overflow timer. The simple timer does not
increment when in sleep.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and pre-
vent it from timing out thus generating a device RESET
condition.
The TO bit in the CPUSTA register will be cleared upon
a WDT time-out.
4 - to - 1 MUX WDTPS1:WDTPS0
WDT Enable
Config See Figure 17-1 for location of WDTPSx bits in Configuration Word. (Note 2) (Note 2)
06h, Unbanked CPUSTA STKAV GLINTD TO PD POR BOR --11 1100 --11 qq11
Legend: - = unimplemented read as '0', q - value depends on condition, shaded cells are not used by the WDT.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
2: This value will be as the device was programmed, or if unprogrammed, will read as all '1's.
INT
(RA0/INT pin)
INTF flag Interrupt Latency (2)
GLINTD bit
Processor
INSTRUCTION FLOW in SLEEP
Tosc
Description: The contents of WREG are added to Encoding: 0000 111d ffff ffff
the 8-bit literal 'k' and the result is Description: Add WREG to register 'f'. If 'd' is 0 the
placed in WREG. result is stored in WREG. If 'd' is 1 the
Words: 1 result is stored back in register 'f'.
Cycles: 1 Words: 1
ADDWFC ADD WREG and Carry bit to f ANDLW And Literal with WREG
Syntax: [ label ] ADDWFC f,d Syntax: [ label ] ANDLW k
Operands: 0 f 255 Operands: 0 k 255
d [0,1] Operation: (WREG) .AND. (k) (WREG)
Operation: (WREG) + (f) + C (dest) Status Affected: Z
Status Affected: OV, C, DC, Z Encoding: 1011 0101 kkkk kkkk
Encoding: 0001 000d ffff ffff
Description: The contents of WREG are ANDed with
Description: Add WREG, the Carry Flag and data the 8-bit literal 'k'. The result is placed in
memory location 'f'. If 'd' is 0, the result is WREG.
placed in WREG. If 'd' is 1, the result is Words: 1
placed in data memory location 'f'.
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Q Cycle Activity: Decode Read literal Process Write to
Q1 Q2 Q3 Q4 'k' Data WREG
Decode Read Process Write to
register 'f' Data destination
Example: ANDLW 0x5F
Before Instruction
Example: ADDWFC REG 0
WREG = 0xA3
Before Instruction After Instruction
Carry bit = 1 WREG = 0x03
REG = 0x02
WREG = 0x4D
After Instruction
Carry bit = 0
REG = 0x02
WREG = 0x50
Q Cycle Activity:
Q1 Q2 Q3 Q4 Example: BTG PORTC, 4
Description: Compares the contents of data memory Description: Compares the contents of data memory
location 'f' to the contents of WREG by location 'f' to the contents of the WREG
performing an unsigned subtraction. by performing an unsigned subtraction.
If 'f' = WREG then the fetched instruc- If the contents of 'f' are greater than the
tion is discarded and an NOP is exe- contents of WREG then the fetched
cuted instead making this a two-cycle instruction is discarded and an NOP is
instruction. executed instead making this a
two-cycle instruction.
Words: 1
Words: 1
Cycles: 1 (2)
Cycles: 1 (2)
Q Cycle Activity:
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process No
Q1 Q2 Q3 Q4
register 'f' Data operation Decode Read Process No
register 'f' Data operation
If skip:
If skip:
Q1 Q2 Q3 Q4
No No No No
Q1 Q2 Q3 Q4
operation operation operation operation No No No No
operation operation operation operation
Description: Decrement register 'f'. If 'd' is 0 the Encoding: 0001 011d ffff ffff
result is stored in WREG. If 'd' is 1 the Description: The contents of register 'f' are decre-
result is stored back in register 'f'. mented. If 'd' is 0 the result is placed in
Words: 1 WREG. If 'd' is 1 the result is placed
back in register 'f'.
Cycles: 1 If the result is 0, the next instruction,
Q Cycle Activity: which is already fetched, is discarded,
and an NOP is executed instead mak-
Q1 Q2 Q3 Q4
ing it a two-cycle instruction.
Decode Read Process Write to
register 'f' Data destination Words: 1
Cycles: 1(2)
Example: DECF CNT, 1 Q Cycle Activity:
Before Instruction Q1 Q2 Q3 Q4
CNT = 0x01 Decode Read Process Write to
Z = 0 register 'f' Data destination
After Instruction If skip:
CNT = 0x00 Q1 Q2 Q3 Q4
Z = 1
No No No No
operation operation operation operation
Description: The contents of register 'f' are incre- Encoding: 0001 111d ffff ffff
mented. If 'd' is 0 the result is placed in Description: The contents of register 'f' are incre-
WREG. If 'd' is 1 the result is placed mented. If 'd' is 0 the result is placed in
back in register 'f'. WREG. If 'd' is 1 the result is placed
Words: 1 back in register 'f'.
If the result is 0, the next instruction,
Cycles: 1 which is already fetched, is discarded,
Q Cycle Activity: and an NOP is executed instead mak-
ing it a two-cycle instruction.
Q1 Q2 Q3 Q4
Decode Read Process Write to Words: 1
register 'f' Data destination Cycles: 1(2)
Q Cycle Activity:
Example: INCF CNT, 1
Q1 Q2 Q3 Q4
Before Instruction Decode Read Process Write to
CNT = 0xFF register 'f' Data destination
Z = 0
If skip:
C = ?
Q1 Q2 Q3 Q4
After Instruction
No No No No
CNT = 0x00
operation operation operation operation
Z = 1
C = 1
Example: HERE INCFSZ CNT, 1
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT + 1
If CNT = 0;
PC = Address(ZERO)
If CNT 0;
PC = Address(NZERO)
Q1 Q2 Q3 Q4 Before Instruction
BSR register = 0x22
Decode Read Process Write
register 'f' Data register 'p' After Instruction
BSR register = 0x25 (Bank 5)
Example: MOVFP REG1, REG2
Before Instruction
REG1 = 0x33,
REG2 = 0x11
After Instruction
REG1 = 0x33,
REG2 = 0x33
Example: MOVLR 5
Before Instruction
BSR register = 0x22
After Instruction
BSR register = 0x52
Example: RETFIE
Example: CALL TABLE ; WREG contains table
After Interrupt ; offset value
PC = TOS ; WREG now has
; table value
GLINTD = 0 :
TABLE
ADDWF PC ; WREG = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruction
WREG = 0x07
After Instruction
WREG = value of k7
RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry
Syntax: [ label ] RLNCF f,d Syntax: [ label ] RRCF f,d
Operands: 0 f 255 Operands: 0 f 255
d [0,1] d [0,1]
Operation: f<n> d<n+1>; Operation: f<n> d<n-1>;
f<7> d<0> f<0> C;
Status Affected: None C d<7>
Description: The contents of register 'f' are rotated Encoding: 0001 100d ffff ffff
one bit to the left. If 'd' is 0 the result is Description: The contents of register 'f' are rotated
placed in WREG. If 'd' is 1 the result is one bit to the right through the Carry
stored back in register 'f'. Flag. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
register f
back in register 'f'.
Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Decode Read Process Write to Q Cycle Activity:
register 'f' Data destination Q1 Q2 Q3 Q4
Decode Read Process Write to
Example: RLNCF REG, 1 register 'f' Data destination
Before Instruction
C = 0 Example: RRCF REG1,0
REG = 1110 1011 Before Instruction
After Instruction REG1 = 1110 0110
C = C = 0
REG = 1101 0111 After Instruction
REG1 = 1110 0110
WREG = 0111 0011
C = 0
Program Data
Memory 15 0
Memory
TBLPTR
15 8 7 0
16 bits 8 bits
TBLAT
Encoding: 1011 0100 kkkk kkkk Encoding: 0000 110d ffff ffff
Description: The contents of WREG are XORed Description: Exclusive OR the contents of WREG
with the 8-bit literal 'k'. The result is with register 'f'. If 'd' is 0 the result is
placed in WREG. stored in WREG. If 'd' is 1 the result is
stored back in the register 'f'.
Words: 1
Words: 1
Cycles: 1
Cycles: 1
Q Cycle Activity:
Q Cycle Activity:
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Decode Read Process Write to
literal 'k' Data WREG Decode Read Process Write to
register 'f' Data destination
DS30264A-page 222
ICEPIC Low-Cost
In-Circuit Emulator
Emulator Products
MPLAB
PIC17C75X
Integrated
Development
Environment
MPLAB C
Compiler
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
Software Tools
MP-DriveWay
Applications
Code Generator
Total Endurance
Software Model
PICSTART
DEVELOPMENT TOOLS FROM MICROCHIP
Programmers
Programmer
KEELOQ
Programmer
SEEVAL
Designers Kit
PICDEM-1
PICDEM-2
PICDEM-3
Demo Boards
KEELOQ
JW Devices
PIC17LC752-08 PIC17C752-25 PIC17C752-33
OSC (Ceramic Windowed
PIC17LC756-08 PIC17C756-25 PIC17C756-33
Devices)
RC VDD: 3.0V to 6.0V VDD: 4.5V to 6.0V VDD: 4.5V to 6.0V VDD: 4.5V to 6.0V
IDD : 6 mA max. IDD : 6 mA max. IDD : 6 mA max. IDD : 6 mA max.
IPD : 5 A max. at 5.5V IPD : 5 A max. at 5.5V IPD : 5 A max. at 5.5V IPD : 5 A max. at 5.5V
Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max.
XT VDD: 3.0V to 6.0V VDD: 4.5V to 6.0V VDD: 4.5V to 6.0V VDD: 4.5V to 6.0V
IDD : 12 mA max. IDD : 38 mA max. IDD : 50 mA max. IDD : 50 mA max.
IPD : 5 A max. at 5.5V IPD : 5 A max. at 5.5V IPD : 5 A max. at 5.5V IPD : 5 A max. at 5.5V
Freq: 8 MHz max. Freq: 25 MHz max. Freq: 33 MHz max. Freq: 33 MHz max.
EC VDD: 3.0V to 6.0V VDD: 4.5V to 6.0V VDD: 4.5V to 6.0V VDD: 4.5V to 6.0V
IDD : 12 mA max. IDD : 38 mA max. IDD : 50 mA max. IDD : 50 mA max.
IPD : 5 A max. at 5.5V IPD : 5 A max. at 5.5V IPD : 5 A max. at 5.5V IPD : 5 A max. at 5.5V
Freq: 8 MHz max. Freq: 25 MHz max. Freq: 33 MHz max. Freq: 33 MHz max.
LF VDD: 3.0V to 6.0V VDD: 4.5V to 6.0V VDD: 4.5V to 6.0V VDD: 3.0V to 6.0V
IDD : 115 A max. at 32 kHz IDD : 85 A typ. at 32 kHz IDD : 85 A typ. at 32 kHz IDD : 115 A max. at 32 kHz
IPD : 5 A max. at 5.5V IPD : < 1 A typ. at 5.5V IPD : < 1 A typ. at 5.5V IPD : 5 A max. at 5.5V
Freq: 2 MHz max. Freq: 2 MHz max. Freq: 2 MHz max. Freq: 2 MHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications.
It is recommended that the user select the device type that ensures the specifications required.
The WDT, BOR,and A/D circuitry are disabled.
Note 1: When using the Table Write for internal programming, the device temperature must be less than 40C.
Note 2: For In-circuit Serial Programming (ISP), refer to the device programming specification.
Data in invalid
0.9 VDD
0.1 VDD
Rise Time Fall Time
LOAD CONDITIONS
Load Condition 1
Pin
CL
VSS
50 pF CL
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4
4
2
OSC2
Param.
No. Sym Characteristic Min Typ Max Units Conditions
Fosc External CLKIN Frequency DC 8 MHz EC osc mode - 08 devices (8 MHz devices)
(Note 1) DC 25 MHz - 25 devices (25 MHz devices)
DC 33 MHz - 33 devices (33 MHz devices)
Oscillator Frequency DC 4 MHz RC osc mode
(Note 1) 1 8 MHz XT osc mode - 08 devices (8 MHz devices)
1 25 MHz - 25 devices (25 MHz devices)
1 33 MHz - 33 devices (33 MHz devices)
DC 2 MHz LF osc mode
1 Tosc External CLKIN Period 125 ns EC osc mode - 08 devices (8 MHz devices)
(Note 1) 40 ns - 25 devices (25 MHz devices)
30.3 ns - 33 devices (33 MHz devices)
Oscillator Period 250 ns RC osc mode
(Note 1) 125 1,000 ns XT osc mode - 08 devices (8 MHz devices)
40 1,000 ns - 25 devices (25 MHz devices)
30.3 1,000 ns - 33 devices (33 MHz devices)
500 ns LF osc mode
2 TCY Instruction Cycle Time 121.2 4/Fosc DC ns
(Note 1)
3 TosL, Clock in (OSC1) 10 ns EC oscillator
TosH high or low time
4 TosR, Clock in (OSC1) 5 ns EC oscillator
TosF rise or fall time
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at min. values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the max. cycle time limit is DC (no clock) for all devices.
Q4 Q1 Q2 Q3
OSC1
10 11
22
OSC2 23
13 12
18
14 19 16
I/O Pin
(input)
17 15
VDD
MCLR
30
Internal
POR / BOR
33
PWRT
Timeout
OSC 32
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
35
Address /
Data
TABLE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param.
No. Sym Characteristic Min Typ Max Units Conditions
RA1/T0CKI
40 41
42
TCLK12
or
TCLK3
45 46
47
48
48
TMRx
CAP pin
(Capture Mode)
50 51
52
PWM pin
(PWM Mode)
53 54
SS
70
SCK
(CKP = 0)
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76
SS
81
SCK
(CKP = 0)
71 72
79
73
SCK
(CKP = 1)
80
78
75, 76
74
SS
70
SCK
(CKP = 0) 83
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76 77
74
73
Refer to Figure 20-1 for load conditions.
82
SS
70
SCK 83
(CKP = 0)
71 72
SCK
(CKP = 1)
80
75, 76 77
SDI
MSB IN BIT6 - - - -1 LSB IN
74
Refer to Figure 20-1 for load conditions.
SCL
91 93
90 92
SDA
START STOP
Condition Condition
This specification ensured by design. For the value required by the I2C specification, please refer to Figure E-11.
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
SDA
Out
Note: Refer to Figure 20-1 for load conditions
TX/CK
pin 121 121
RX/DT
pin
120 122
TX/CK
pin 125
RX/DT
pin
126
A50 IREF VREF input current (Note 2) 10 1000 A During VAIN acquisition.
Based on differential of VHOLD to VAIN.
To charge CHOLD see Section 16.1.
10 A During A/D conversion cycle
*These parameters are characterized but not tested.
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from RG0 and RG1 pins or AVDD and AVSS pins, whichever is selected as reference input.
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
ALE
OE
151
WR
150 154
AD<15:0> addr out data out addr out
152 153
OSC1
166
ALE
164
168
OE 160
165 161
AD<15:0> Addr out Data in Addr out
150 162
151 163
'1' 167 '1'
WR
1.10
Rext 10 k
1.08 Cext = 100 pF
1.06
1.04
1.02
1.00
VDD = 5.5V
0.98
0.96
0.94
VDD = 3.5V
0.92
0.90
0 10 20 25 30 40 50 60 70
T(C)
4.0
3.5
3.0 R = 10k
2.5
FOSC (MHz)
2.0
1.5
Cext = 22 pF, T = 25C
1.0
0.5
0.0 R = 100k
4.0 4.5 5.0 5.5 6.0 6.5
VDD (Volts)
4.0
3.5
R = 3.3k
3.0
2.5
FOSC (MHz)
R = 5.1k
2.0
1.5
1.0 R = 10k
Cext = 100 pF, T = 25C
0.5 R = 100k
0.0
4.0 4.5 5.0 5.5 6.0 6.5
VDD (Volts)
2.0
1.8
1.6
1.4 R = 3.3k
1.2
R = 5.1k
FOSC (MHz)
1.0
0.8
R = 10k
0.6
0.4
Cext = 300 pF, T = 25C
0.2
R = 160k
0.0
4.0 4.5 5.0 5.5 6.0 6.5
VDD (Volts)
Average
Cext Rext
Fosc @ 5V, 25C
22 pF 10k 3.33 MHz 12%
100k 353 kHz 13%
100 pF 3.3k 3.54 MHz 10%
5.1k 2.43 MHz 14%
10k 1.30 MHz 17%
100k 129 kHz 10%
300 pF 3.3k 1.54 MHz 14%
5.1k 980 kHz 12%
10k 564 kHz 16%
160k 35 kHz 18%
500
450
400
350
Max @ -40C
300
gm(A/V)
Typ @ 25C
250
200
150
Min @ 85C
100
50
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
20
18
Max @ -40C
16
14
Typ @ 25C
12
gm(mA/V)
10
6
Min @ 85C
4
2
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
10000
IDD (A)
1000
7.0V
6.5V
6.0V
5.5V
5.0V
100 4.5V
4.0V
10
10k 100k 1M 10M 100M
External Clock Frequency (Hz)
FIGURE 21-8: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK 125C TO -40C)
100000
10000
IDD (A)
1000 7.0V
6.5V
6.0V
5.5V
5.0V
4.5V
4.0V
100
10k 100k 1M 10M 100M
External Clock Frequency (Hz)
12
10
8
IPD(nA)
0
4.0 4.5 5.0 5.5 6.0 6.5 7.0
VDD (Volts)
1900
1800
1700
1600
1500
1400
1300
1200
1100 Temp. = 85C
IPD(nA)
1000
900
800
700
600
500 Temp. = 70C
400
300
200 Temp. = 0C
100
0 Temp. = -40C
4.0 4.5 5.0 5.5 6.0 6.5 7.0
VDD (Volts)
30
25
20
IPD(A)
15
10
0
4.0 4.5 5.0 5.5 6.0 6.5 7.0
VDD (Volts)
60
50
-40C
70C
40
0C
IPD(A)
85C
30
20
10
0
4.0 4.5 5.0 5.5 6.0 6.5 7.0
VDD (Volts)
30
25
Max. 85C
20
WDT Period (ms)
Max. 70C
10
Min. -40C
0
4.0 4.5 5.0 5.5 6.0 6.5 7.0
VDD (Volts)
-2
-4
-6
IOH(mA)
Min @ 85C
-8
-12
-14
Max @ -40C
-16
-18
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOH (Volts)
-5
-10
Min @ 85C
-15
IOH(mA)
-20
Max @ -40C
-25
Typ @ 25C
-30
-35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOH (Volts)
30
Max. -40C
25
Typ. 25C
20
IOL(mA)
15
Min. +85C
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
90
80
70
Max @ -40C
60 Typ @ 25C
IOL(mA)
50
Min @ +85C
40
30
20
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
FIGURE 21-18: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS (TTL) VS. VDD
2.0
1.8
Max (-40C to +85C)
1.6
Typ @ 25C
VTH(Volts)
1.4
1.2
1.0
Min (-40C to +85C)
0.8
0.6
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
1.5
1.0
0.5
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
3.4
3.2
2.6
VTH,(Volts)
2.4
2.2
2.0
Min (-40C to +85C)
1.8
1.6
1.4
1.2
1.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
e/2
A
E1 A E
DETAIL A
e
E/2
See Detail A
8 Places
11/13 0 min.
A
A2
See Detail B Datum Plane
0.25
b 0.08
with Lead Finish A1 R min. 0-7
Gauge Plane
0.09/0.20 0.09/0.16 0.20 min.
L
b1 1.00 ref.
Base Metal
DETAIL B
E1 E C
eA
Pin No. 1 eB
Indicator Area
D
S S1
Base
Plane
Seating
Plane L
B1 e1 A1 A2 A
B
D1
D 0.812/0.661 N Pics
0.177 1.27 .032/.026
.007 S B D-E S .050
2 Sides -H- 0.177
-A- .007 S B A S
D1 A
A1 2 Sides
-D- 3 9
D3/E3
0.101 Seating
D2 D
.004 Plane
0.38 -C-
3 .015 F-G S 4
3 -G-
8 E2
-F-
E1 E
0.38
.015 F-G S 4
-B-
3 -E- 0.177
.007 S A F-G S
10
0.812/0.661
0.254 0.254 3
.032/.026
.010 Max 11 .010 Max 11
1.524
0.508 0.508
2 -H- .060 Min
.020 .020 -H- 2
6
6
-C-
5
1.651 1.651 0.64 Min 0.533/0.331
.065 .065 .025 .021/.013
R 1.14/0.64 R 1.14/0.64
.045/.025 .045/.025 0.177
, D-E S
.007 M A F-G S
MMMMMMMMMMMMMMMMM PIC17C756-04/CL
AABBCDE 9750CAE
MMMMMMMMMM PIC17C752
MMMMMMM -08I/PT
AABBCDE 9717CAE
MMMMMMMMMM PIC17C756
MMMMMMM -08/L
AABBCDE 9748CAE
MMMMMMMMMMMMMMMMM PIC17C752-04I/SP
AABBCDE 9736CAE
Term Description
Receiver The device that receives the data from the bus.
Master The device which initiates the transfer, generates the clock and terminates the transfer.
Multi-master More than one master device in a system. These masters can attempt to control the bus at the
same time without corrupting the message.
Arbitration Procedure that ensures that only one of the master devices will control the bus. This ensure that
the transfer data does not get corrupted.
Synchronization Procedure where the clock signals of two or more devices are synchronized.
S
MSb LSb Start Clock Pulse for
Condition Acknowledgment
S R/W ACK
SDA
MSB acknowledgment acknowledgment
signal from receiver byte complete signal from receiver
interrupt with receiver
clock line held low while
interrupts are serviced
SCL S 1 2 7 8 9 1 2 38 9 P
Start Stop
Condition Address R/W ACK Wait Data ACK
State Condition
S Slave Address R/W A Data A/A Sr Slave Address R/W A Data A/A P
Combined format:
Sr Slave Address R/W A Slave Address A Data A Data A/A Sr Slave Address R/W A Data A Data A P
First 7 bits Second byte First 7 bits
(write) (read)
Combined format - A master addresses a slave with a 10-bit address, then transmits
data to this slave and reads data from this slave.
A = acknowledge (SDA low)
From master to slave A = not acknowledge (SDA high)
S = Start Condition
From slave to master P = Stop Condition
ARBITRATION
period, Figure E-10.
DATA 2 CLK
1
SDA counter
CLK reset
SCL 2
SCL
SCL
91 93
90 92
SDA
START STOP
Condition Condition
SDA
Out
Bank 0 Bank 1 (1) Bank 2 (1) Bank 3 (1) Bank 4 (1) Bank 5 (1) Bank 6 (1) Bank 7 (1)
10h PORTA DDRC TMR1 PW1DCL PIR2 DDRF SSPADD PW3DCL
11h DDRB PORTC TMR2 PW2DCL PIE2 PORTF SSPCON1 PW3DCH
12h PORTB DDRD TMR3L PW1DCH DDRG SSPCON2 CA3L
13h RCSTA1 PORTD TMR3H PW2DCH RCSTA2 PORTG SSPSTAT CA3H
14h RCREG1 DDRE PR1 CA2L RCREG2 ADCON0 SSPBUF CA4L
15h TXSTA1 PORTE PR2 CA2H TXSTA2 ADCON1 CA4H
16h TXREG1 PIR1 PR3L/CA1L TCON1 TXREG2 ADRESL TCON3
17h SPBRG1 PIE1 PR3H/CA1H TCON2 SPBRG2 ADRESH
Unbanked
18h PRODL
19h PRODH
1Ah General
Purpose
1Fh RAM
FFh
Note 1: SFR file locations 10h - 17h are banked. The lower nibble of the BSR specifies the bank. All
unbanked SFRs ignore the Bank Select Register (BSR) bits.
2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh
are banked. The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select
Register (BSR) bits.
3: These RAM banks are not implemented on the PIC17C752. Reading any register in this bank reads
0s.
0000 1:1
0001 1:2
0010 1:4
0011 1:8
0100 1:16
0101 1:32
0110 1:64
0111 1:128
1xxx 1:256
PCFG3:PCFG1 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
000 A A A A A A A A A A A A
001 A A A A D A A A A A A A
010 A A A A D D A A A A A A
011 A A A A D D D A A A A A
100 A A A A D D D D A A A A
101 D A A A D D D D D A A A
110 D D A A D D D D D D A A
111 D D D D D D D D D D D D
A = Analog input D = Digital I/O
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C5XX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip sales office for availability of these devices.
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability. All PIC16C6X Family devices use serial programming with clock pin RB6 and data pin RB7.
Features In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes
Brown-out Reset Yes Yes Yes Yes Yes
Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP,
SOIC; SOIC SOIC; SOIC; SOIC, SSOP SOIC, SSOP
20-pin SSOP 20-pin SSOP 20-pin SSOP
PIC16C73A PIC16C74A
Clock Maximum Frequency of Operation (MHz) 20 20
EPROM Program Memory (x14 words) 4K 4K
Memory
Data Memory (bytes) 192 192
Timer Module(s) TMR0, TMR0,
TMR1, TMR1,
TMR2 TMR2
Peripherals Capture/Compare/PWM Module(s) 2 2
Serial Port(s) (SPI/I2C, USART) SPI/I2C, USART SPI/I2C, USART
Parallel Slave Port Yes
A/D Converter (8-bit) Channels 5 8
Interrupt Sources 11 12
I/O Pins 22 33
Voltage Range (Volts) 2.5-6.0 2.5-6.0
In-Circuit Serial Programming Yes Yes
Features
Brown-out Reset Yes Yes
Packages 28-pin SDIP, 40-pin DIP;
SOIC 44-pin PLCC,
MQFP,
TQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capabil-
ity. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip sales office for availability of these devices.
PIN COMPATIBILITY
Devices that have the same package type and VDD,
VSS and MCLR pin locations are said to be pin
compatible. This allows these different devices to
operate in the same socket. Compatible devices may
only requires minor software modification to allow
proper operation in the application socket
(ex., PIC16C56 and PIC16C61 devices). Not all
devices in the same package size are pin compatible;
for example, the PIC16C62 is compatible with the
PIC16C63, but not the PIC16C55.
Pin compatibility does not mean that the devices offer
the same features. As an example, the PIC16C54 is
pin compatible with the PIC16C71, but does not have
an A/D converter, weak pull-ups on PORTB, or
interrupts.
A
Baud Rate Generator ....................................................... 143
Baud Rate Generator (BRG) ............................................ 110
A/D Baud Rates
Accuracy/Error .......................................................... 174 Asynchronous Mode................................................. 112
ADCON0 Register..................................................... 167 Synchronous Mode................................................... 111
ADCON1 Register..................................................... 168 BCF .................................................................................. 190
ADIF bit ..................................................................... 169 BCLIE ..................................................................................32
Analog Input Model Block Diagram........................... 170 BCLIF ..................................................................................34
Analog-to-Digital Converter....................................... 167 BF ............................................................. 124, 135, 149, 152
Block Diagram........................................................... 169 Bit Manipulation ................................................................ 184
Configuring Analog Port Pins.................................... 172 Block Diagrams
Configuring the Interrupt ........................................... 169 A/D............................................................................ 169
Configuring the Module............................................. 169 Analog Input Model................................................... 170
Connection Considerations....................................... 174 Baud Rate Generator ............................................... 143
Conversion Clock...................................................... 171 BSR Operation ............................................................53
Conversions .............................................................. 172 External Brown-out Protection Circuit (Case1)............28
Converter Characteristics ......................................... 245 External Power-on Reset Circuit .................................22
Delays ....................................................................... 170 External Program Memory Connection .......................41
Effects of a Reset...................................................... 174 I2C Master Mode ...................................................... 141
Equations .................................................................. 170 I2C Module................................................................ 134
Flowchart of A/D Operation....................................... 175 Indirect Addressing......................................................50
GO/DONE bit ............................................................ 169 On-chip Reset Circuit ..................................................21
Internal Sampling Switch (Rss) Impedence .............. 170 PORTD ........................................................................74
Operation During Sleep ............................................ 173 PORTE ........................................................................76
Sampling Requirements............................................ 170 Program Counter Operation ........................................52
Sampling Time .......................................................... 170 PWM............................................................................97
Source Impedence.................................................... 170 RA0 and RA1...............................................................65
Time Delays .............................................................. 170 RA2..............................................................................66
Transfer Function...................................................... 174 RA3..............................................................................66
A/D Interrupt........................................................................ 34 RA4 and RA5...............................................................66
A/D Interrupt Flag bit, ADIF................................................. 34 RB3:RB2 Port Pins ......................................................69
A/D Module Interrupt Enable, ADIE .................................... 32 RB7:RB4 and RB1:RB0 Port Pins ...............................68
ACK........................................................................... 135, 268 RC7:RC0 Port Pins......................................................72
Acknowledge Data bitr, AKD............................................. 126 SSP (I2C Mode)........................................................ 134
Acknowledge Pulse........................................................... 135 SSP (SPI Mode) ....................................................... 128
Acknowledge Sequence Enable bit, AKE ......................... 126 SSP Module (I2C Master Mode) ............................... 123
Acknowledge Status bit, AKS ........................................... 126 SSP Module (I2C Slave Mode) ................................. 123
ADCON0 ............................................................................. 45 SSP Module (SPI Mode) .......................................... 123
ADCON1 ............................................................................. 45 Timer3 with One Capture and One Period Register. 100
ADDLW ............................................................................. 188 TMR1 and TMR2 in 16-bit Timer/Counter Mode .........95
ADDWF ............................................................................. 188 TMR1 and TMR2 in Two 8-bit Timer/Counter Mode ...94
ADDWFC .......................................................................... 189 TMR3 with Two Capture Registers........................... 102
ADIE.................................................................................... 32 Using CALL, GOTO.....................................................52
ADIF.................................................................................... 34 WDT ......................................................................... 179
ADRES Register ............................................................... 167 BODEN ................................................................................28
ADRESH ............................................................................. 45 Borrow ...................................................................................9
ADRESL.............................................................................. 45 BRG .......................................................................... 110, 143
AKD................................................................................... 126 Brown-out Protection ...........................................................28
AKE................................................................................... 126 Brown-out Reset (BOR).......................................................28
AKS........................................................................... 126, 149 BSF................................................................................... 191
ALU ....................................................................................... 9 BSR .............................................................................. 44, 53
ALUSTA ...................................................................... 44, 184 BSR Operation ....................................................................53
ALUSTA Register................................................................ 47 BTFSC .............................................................................. 191
ANDLW ............................................................................. 189 BTFSS .............................................................................. 192
ANDWF ............................................................................. 190 BTG .................................................................................. 192
Application Note AN552,"Implementing Wake-up Buffer Full bit, BF .............................................................. 135
on Keystroke"...................................................................... 68 Buffer Full Status bit, BF................................................... 124
Application Note AN578, "Use of the SSP Module in Bus Arbitration .................................................................. 160
the I2C Multi-Master Environment."................................... 123 Bus Collision
Assembler ......................................................................... 220 Section...................................................................... 160
Asynchronous Master Transmission ................................. 114 Bus Collision During a RESTART Condition .................... 163
Asynchronous Transmitter ................................................ 113 Bus Collision During a Start Condition ............................. 161
Bus Collision During a Stop Condition.............................. 164
B Bus Collision Interrupt Enable, BCLIE .................................32
Bank Select Register (BSR)................................................ 53 Bus Collision Interrupt Flag bit, BCLIF ................................34
Banking ......................................................................... 42, 53
U
UA ..................................................................................... 124
Update Address, UA ......................................................... 124
Upward Compatibility ............................................................ 5
USART
Asynchronous Master Transmission......................... 114
Asynchronous Mode ................................................. 113
Asynchronous Receive ............................................. 115
Asynchronous Transmitter ........................................ 113
Baud Rate Generator................................................ 110
Synchronous Master Mode ....................................... 117
Synchronous Master Reception................................ 119
Synchronous Master Transmission........................... 117
Synchronous Slave Mode ......................................... 121
Synchronous Slave Transmit .................................... 121
USART1 Receive Interrupt ......................................... 33, 280
USART1 Transmit Interrupt ........................................ 33, 280
USART2 Receive Interrupt Enable, RC2IE......................... 32
USART2 Receive Interrupt Flag bit, RC2IF ........................ 34
USART2 Receive Interrupt Flag bit, TX2IF ......................... 34
USART2 Transmit Interrupt Enable, TX2IE ........................ 32
V
VDD ........................................................................... 225, 226
W
Wake-up from SLEEP ....................................................... 180
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