ADE7768
ADE7768
ADE7768
ADE7768
POWER
SUPPLY MONITOR SIGNAL
PROCESSING
BLOCK
V2P 2 + ...110101...
-
ADC MULTIPLIER
V2N 3
PHASE LPF
CORRECTION
V1N 4 ...11011001...
-
ADC HPF
V1P 5 +
INTERNAL DIGITAL-TO-FREQUENCY
OSCILLATOR CONVERTER
2.5V 4k
05331-001
REFERENCE
7 11 8 10 9 12 14 16 15
REFIN/OUT RCLKIN SCF S0 S1 REVP CF F1 F2
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com
registered trademarks are the property of their respective owners. Fax: 781.461.3113 2005 Analog Devices, Inc. All rights reserved.
ADE7768* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
ADE7768
TABLE OF CONTENTS
Specifications..................................................................................... 3 Power Supply Monitor ............................................................... 12
Typical Performance Characteristics ............................................. 8 Evaluation Board and Reference Design Board ..................... 16
Analog Inputs.............................................................................. 11
Revision History
8/05Sp0 to Rev. A
Rev. A | Page 2 of 20
ADE7768
SPECIFICATIONS
VDD = 5 V 5%, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 k, 0.5% 50 ppm/C, TMIN to TMAX = 40C to +85C,
unless otherwise noted.
Table 1.
Parameter Value Unit Test Conditions/Comments
ACCURACY 1 , 2
Measurement Error on Channel V1 0.1 % reading typ Channel V2 with full-scale signal (165 mV),
25C over a dynamic range 500 to 1,
line frequency = 45 Hz to 65 Hz
Phase Error1 Between Channels
V1 Phase Lead 37 (PF = 0.8 Capacitive) 0.1 Degrees () max
V1 Phase Lag 60 (PF = 0.5 Inductive) 0.1 Degrees () max
AC Power Supply Rejection1
Output Frequency Variation (CF) 0.2 % reading typ S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms @
50 Hz, ripple on VDD of 200 mV rms @ 100 Hz
DC Power Supply Rejection1
Output Frequency Variation (CF) 0.3 % reading typ S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms,
VDD = 5 V 250 mV
ANALOG INPUTS See the Analog Inputs section
Channel V1 Maximum Signal Level 30 mV max V1P and V1N to AGND
Channel V2 Maximum Signal Level 165 mV max V2P and V2N to AGND
Input Impedance (DC) 320 k min OSC = 450 kHz, RCLKIN = 6.2 k, 0.5% 50 ppm/C
Bandwidth (3 dB) 7 kHz nominal OSC = 450 kHz, RCLKIN = 6.2 k, 0.5% 50 ppm/C
ADC Offset Error1, 2 18 mV max See the Terminology and the Typical Performance
Characteristics sections
Gain Error1 4 % ideal typ External 2.5 V reference, V1 = 21.2 mV rms,
V2 = 116.7 mV rms
OSCILLATOR FREQUENCY (OSC) 450 kHz nominal RCLKIN = 6.2 k, 0.5% 50 ppm/C
Oscillator Frequency Tolerance1 12 % reading typ
Oscillator Frequency Stability1 30 ppm/C typ
REFERENCE INPUT
REFIN/OUT Input Voltage Range 2.65 V max 2.45 V nominal
2.25 V min 2.45 V nominal
Input Capacitance 10 pF max
ON-CHIP REFERENCE 2.45 V nominal
Reference Error 200 mV max
Temperature Coefficient 20 ppm/C typ
LOGIC INPUTS 3
SCF, S0, S1
Input High Voltage, VINH 2.4 V min VDD = 5 V 5%
Input Low Voltage, VINL 0.8 V max VDD = 5 V 5%
Input Current, IIN 1 A max Typically 10 nA, VIN = 0 V to VDD
Input Capacitance, CIN 10 pF max
LOGIC OUTPUTS3
F1 and F2
Output High Voltage, VOH 4.5 V min ISOURCE = 10 mA, VDD = 5 V, ISINK = 10 mA, VDD = 5 V
Output Low Voltage, VOL 0.5 V max
CF
Output High Voltage, VOH 4 V min ISOURCE = 5 mA, VDD = 5 V, ISINK = 5 mA, VDD = 5 V
Output Low Voltage, VOL 0.5 V max
Frequency Output Error1, 2 (CF) 10 % ideal typ External 2.5 V reference, V1 = 21.2 mV rms,
V2 = 116.7 mV rms
Rev. A | Page 3 of 20
ADE7768
Parameter Value Unit Test Conditions/Comments
POWER SUPPLY For specified performance
VDD 4.75 V min 5 V 5%
5.25 V max 5 V + 5%
IDD 5 mA max Typically 4 mA
1
See the Terminology section for an explanation of specifications.
2
See the figures in the Typical Performance Characteristics section.
3
Sample tested during initial release and after any redesign or process change that may affect this parameter.
TIMING CHARACTERISTICS
VDD = 5 V 5%, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 k, 0.5% 50 ppm/C, TMIN to TMAX = 40C to +85C,
unless otherwise noted. Sample tested during initial release and after any redesign or process change that may affect this parameter.
See Figure 2.
Table 2.
Parameter Specifications Unit Test Conditions/Comments
t1 1 120 ms F1 and F2 pulse width (logic low)
t2 See Table 6 sec Output pulse period. See the Transfer Function section.
t3 1/2 t2 sec Time between the F1 and F2 falling edges.
t41, 2 90 ms CF pulse width (logic high).
t5 See Table 7 sec CF pulse period. See the Transfer Function section.
t6 2 s Minimum time between the F1 and F2 pulses.
1
The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section.
2
The CF pulse is always 35 s in high frequency mode. See the Frequency Outputs section and Table 7.
t1
F1
t6
t2
F2 t3
t4 t5
05331-002
CF
Rev. A | Page 4 of 20
ADE7768
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.
Rev. A | Page 5 of 20
ADE7768
TERMINOLOGY
Measurement Error ADC Offset Error
The error associated with the energy measurement made by the This refers to the small dc signal (offset) associated with the
ADE7768 is defined by the following formula: analog inputs to the ADCs. However, the HPF in Channel V1
eliminates the offset in the circuitry. Therefore, the power
Energy Registered by ADE7768 True Energy calculation is not affected by this offset.
% Error = 100%
True Energy
Frequency Output Error (CF)
The frequency output error of the ADE7768 is defined as the
Phase Error Between Channels
difference between the measured output frequency (minus the
The high-pass filter (HPF) in the current channel (Channel V1)
offset) and the ideal output frequency. The difference is
has a phase-lead response. To offset this phase response and
expressed as a percentage of the ideal frequency. The ideal
equalize the phase response between channels, a phase-
frequency is obtained from the ADE7768 transfer function.
correction network is also placed in Channel V1. The phase-
correction network matches the phase to within 0.1 over a Gain Error
range of 45 Hz to 65 Hz, and 0.2 over a range 40 Hz to 1 kHz The gain error of the ADE7768 is defined as the difference
(see Figure 24 and Figure 25). between the measured output of the ADCs (minus the offset)
and the ideal output of the ADCs. The difference is expressed
Power Supply Rejection (PSR)
as a percentage of the ideal of the ADCs.
This quantifies the ADE7768 measurement error as a
percentage of reading when the power supplies are varied. Oscillator Frequency Tolerance
The oscillator frequency tolerance of the ADE7768 is defined as
For the ac PSR measurement, a reading at nominal supplies
the part-to-part frequency variation in terms of percentage at
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
room temperature (25C). It is measured by taking the differ-
onto the supplies and a second reading is obtained under the
ence between the measured oscillator frequency and the
same input signal levels. Any error introduced is expressed as a
nominal frequency defined in the Specifications section.
percentage of readingsee the Measurement Error definition.
Oscillator Frequency Stability
For the dc PSR measurement, a reading at nominal supplies
Oscillator frequency stability is defined as frequency variation
(5 V) is taken. The supplies are then varied 5% and a second
in terms of the parts-per-million drift over the operating
reading is obtained with the same input signal levels. Any error
temperature range. In a metering application, the temperature
introduced is again expressed as a percentage of the reading.
range is 40C to +85C. Oscillator frequency stability is
measured by taking the difference between the measured
oscillator frequency at 40C and +85C and the measured
oscillator frequency at +25C.
Rev. A | Page 6 of 20
ADE7768
V2P 2 15 F2
V2N 3 14 CF
ADE7768
V1N 4 TOP VIEW 13 DGND
REFIN/OUT 7 10 S0
05331-003
SCF 8 9 S1
Rev. A | Page 7 of 20
ADE7768
+
100nF 10F
1
VDD U3 K7
602k
2 V2P F1 16 1 4
220V 200 150nF F2 15
U1
ADE7768 CF 14
2 3
200
3 V2N K8
40A TO PS2501-1
40mA 150nF
820
REVP 12
200
5 V1P 6.2k
+ RCLKIN 11
150nF VDD
350
200
4 V1N 10k
150nF
S0 10
S1 9
+
7 REFIN/OUT
1F 100nF SCF 8
AGND DGND 10nF 10nF 10nF
6 13
05331-004
Figure 4. Test Circuit for Performance Curves
1.0 1.0
PF = 1 PF = 1
0.8 ON-CHIP REFERENCE 0.8 EXTERNAL REFERENCE
0.6 0.6
ERROR (% of Reading)
ERROR (% of Reading)
0 0
05331-021
0.8 0.8
1.0 1.0
0.1 1 10 100 0.1 1 10 100
Figure 5. Error as a % of Reading over Temperature Figure 7. Error as a % of Reading over Temperature
with On-Chip Reference (PF = 1) with External Reference (PF = 1)
1.0 1.0
PF = 0.5 IND PF = 0.5 IND
0.8 ON-CHIP REFERENCE 0.8 EXTERNAL REFERENCE
ERROR (% of Reading)
0.4 0.4
0.2 0.2
+25C, PF = 0.5 IND
0.4 +85C, PF = 0.5 IND 0.4 +25C, PF = 0.5 IND
0.6 0.6
40C, PF = 0.5 IND
05331-020
05331-022
0.8 0.8
1.0 1.0
0.1 1 10 100 0.1 1 10 100
Figure 6. Error as a % of Reading over Temperature Figure 8. Error as a % of Reading over Temperature
with On-Chip Reference (PF = 0.5 IND) with External Reference (PF = 0.5 IND)
Rev. A | Page 8 of 20
ADE7768
0.5 40
DISTRIBUTION CHARACTERISTICS
0.4 MEAN = 2.247828
SDs = 1.367176 EXTERNAL REFERENCE
MIN = 2.09932 TEMPERATURE = 25C
0.3 MAX = +5.28288
30 NO. OF POINTS = 100
ERROR (% of Reading)
0.2
PF = 0.5 IND
PF = 1
FREQUENCY
0.1
0 20
0.1
05331-018
05331-025
0.4
0.5 0
45 50 55 60 65 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9
Figure 9. Error as a % of Reading over Input Frequency Figure 12. Channel V1 Offset Distribution
1.0 50
PF = 1 DISTRIBUTION CHARACTERISTICS
0.8 ON-CHIP REFERENCE MEAN = 1.563484
SDs = 2.040699
MIN = 6.82969 EXTERNAL REFERENCE
0.6 40 MAX = +2.6119 TEMPERATURE = 25C
NO. OF POINTS = 100
ERROR (% of Reading)
0.4
5.25V
0.2 FREQUENCY 30
5V
0
0.2 4.75V 20
0.4
0.6 10
05331-023
05331-026
0.8
1.0 0
0.1 1 10 100 12 10 8 6 4 2 0 2 4 6 8 10 12
Figure 10. PSR with On-Chip Reference, PF = 1 Figure 13. Channel V2 Offset Distribution
1.0 1000
PF = 1 DISTRIBUTION CHARACTERISTICS
0.8 EXTERNAL REFERENCE MEAN = 0%
SDs = 1.55% EXTERNAL REFERENCE
MIN = 11.79% TEMPERATURE = 25C
0.6 800 MAX = +6.08%
NO. OF POINTS = 3387
ERROR (% of Reading)
0.4 5.25V
FREQUENCY
0.2 600
5V
0
0.4
0.6 200
05331-024
05331-027
0.8
1.0 0
0.1 1 10 100 10 8 6 4 2 0 2 4 6 8 10 12
Figure 11. PSR with External Reference, PF = 1 Figure 14. Part-to-Part CF Deviation from Mean
Rev. A | Page 9 of 20
ADE7768
FUNCTIONAL DESCRIPTION
THEORY OF OPERATION
MAGNITUDE
The two ADCs in the ADE7768 digitize the voltage signals from
the current and voltage sensors. These ADCs are 16-bit -s
with an oversampling rate of 450 kHz. This analog input
ACTIVE ENERGY
structure greatly simplifies sensor interfacing by providing a 0Wh
MAGNITUDE
by simplifying the antialiasing filter design. A high-pass filter
in the current channel removes any dc component from the
current signal. This eliminates any inaccuracies in the real INSTANTANEOUS
POWER
power calculation due to offsets in the voltage or current 0W
signals.
05331-028
The real power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by Figure 16. Positive-Only Energy Accumulation
a direct multiplication of the current and voltage signals. To
extract the real power component (the dc component), the Power Factor Considerations
instantaneous power signal is low-pass filtered. Figure 15 The method used to extract the real power information from
illustrates the instantaneous real power signal and shows how the instantaneous power signal (that is, by low-pass filtering) is
the real power information can be extracted by low-pass still valid even when the voltage and current signals are not in
filtering the instantaneous power signal. In the ADE7768, phase. Figure 17 displays the unity power factor condition and a
this signal is compared to 0 and only positive real power is displacement power factor (DPF) = 0.5 (a current signal lagging
accumulated for F1, F2, and CF pulse outputs. This scheme the voltage by 60). Assuming that the voltage and current
correctly calculates real power for sinusoidal current and waveforms are sinusoidal, the real power component of the
voltage waveforms at all power factors. All signal processing instantaneous power signal (that is, the dc term) is given by
is carried out in the digital domain for superior stability over
V I
cos (60)
temperature and time.
(1)
DIGITAL-TO-
FREQUENCY 2
F1
CH1 ADC
HPF
F2 This is the correct real power calculation.
MULTIPLIER 0 DIGITAL-TO-
LPF FREQUENCY INSTANTANEOUS INSTANTANEOUS REAL
POWER SIGNAL POWER SIGNAL
CH2 ADC POWER
CF
0V TIME
05331-005
CURRENT
VOLTAGE
TIME TIME
INSTANTANEOUS REAL
POWER INSTANTANEOUS POWER SIGNAL
Figure 15. Signal Processing Block Diagram POWER SIGNAL
Rev. A | Page 10 of 20
ADE7768
Nonsinusoidal Voltage and Current ANALOG INPUTS
The real power calculation method also holds true for non- Channel V1 (Current Channel)
sinusoidal current and voltage waveforms. All voltage and The voltage output from the current sensor is connected to the
current waveforms in practical applications have some ADE7768 here. Channel V1 is a fully differential voltage input.
harmonic content. Using the Fourier transform, instantaneous V1P is the positive input with respect to V1N.
voltage and current waveforms can be expressed in terms of
their harmonic content. The maximum peak differential signal on Channel V1 should
be less than 30 mV (21 mV rms for a pure sinusoidal signal)
for specified operation.
v(t ) = V0 + 2 Vh sin(ht + h )
(2)
h0 V1
+30mV
where: V1P
v(t) is the instantaneous voltage. DIFFERENTIAL INPUT
30mV MAX PEAK V1
V1N
V0 is the average value. VCM
Vh is the rms value of voltage harmonic h. COMMON-MODE
6.25mV MAX VCM
05331-007
30mV AGND
i (t ) = I O + 2 I h sin(h t + h ) (3)
h o
Figure 18. Maximum Signal Levels, Channel V1
h = h h
05331-008
165mV AGND
Rev. A | Page 11 of 20
ADE7768
Typical Connection Diagrams HPF and Offset Effects
Figure 20 shows a typical connection diagram for Channel V1. Figure 23 shows the effect of offsets on the real power calcula-
A shunt is the current sensor selected for this example because tion. As can be seen, offsets on Channel V1 and Channel V2
of its low cost compared to other current sensors, such as the contribute a dc component after multiplication. Because this dc
current transformer (CT). This IC is ideal for low current component is extracted by the LPF and used to generate the real
meters. power information, the offsets contribute a constant error to the
RF V1P real power calculation. This problem is easily avoided by the
CF built-in HPF in Channel V1. By removing the offsets from at
SHUNT 30mV V1N
least one channel, no error component can be generated at dc
RF CF by the multiplication. Error terms at the line frequency () are
removed by the LPF and the digital-to-frequency conversion
05331-009
AGND
(see the Digital-to-Frequency Conversion section).
PHASE NEUTRAL
VOS IOS
05331-012
The ADE7768 contains an on-chip power supply monitor. 0
FREQUENCY (RAD/s)
The power supply (VDD) is continuously monitored by the
ADE7768. If the supply is less than 4 V, the ADE7768 becomes Figure 23. Effect of Channel Offset on the Real Power Calculation
inactive. This is useful to ensure proper device operation at The HPF in Channel V1 has an associated phase response that
power-up and power-down. The power supply monitor has
is compensated for on chip. Figure 24 and Figure 25 show the
built-in hysteresis and filtering, which provide a high degree
phase error between channels with the compensation network
of immunity to false triggering from noisy supplies.
activated. The ADE7768 is phase compensated up to 1 kHz as
In Figure 22, the trigger level is nominally set at 4 V. The toler- shown. This ensures correct active harmonic power calculation
ance on this trigger level is within 5%. The power supply and even at low power factors.
0.30
decoupling for the part should be such that the ripple at VDD
does not exceed 5 V 5%, as specified for normal operation. 0.25
0.20
VDD
5V
PHASE (Degrees)
4V 0.15
0.10
0.05
0V
0
TIME
0.05
05331-013
INTERNAL 0.10
ACTIVATION INACTIVE ACTIVE INACTIVE 0 100 200 300 400 500 600 700 800 900 1000
05331-011
FREQUENCY (Hz)
Figure 22. On-Chip Power Supply Monitor Figure 24. Phase Error Between Channels (0 Hz to 1 kHz)
Rev. A | Page 12 of 20
ADE7768
0.30 F1
FREQUENCY
DIGITAL-TO-
0.25 FREQUENCY
F1
V
0.20 F2
TIME
0
PHASE (Degrees)
FREQUENCY
0.10 I CF
LPF TO EXTRACT
0.05 REAL POWER
(DC TERM)
VI TIME
0
2
COS (2)
0.05 ATTENUATED BY LPF
05331-014
0.10
40 45 50 55 60 65 70
FREQUENCY (Hz) 0 2
FREQUENCY (RAD/s)
05331-015
Figure 25. Phase Error Between Channels (40 Hz to 70 Hz) INSTANTANEOUS REAL POWER SIGNAL
(FREQUENCY DOMAIN)
Rev. A | Page 13 of 20
ADE7768
CF
temperature drift to ensure stability and linearity of the chip.
FREQUENCY
RIPPLE The oscillator frequency is inversely proportional to the
RCLKIN, as shown in Figure 28. Although the internal
AVERAGE
10%
FREQUENCY oscillator operates when used with RCLKIN values between
5.5 k and 20 k, choosing a value within the range of the
nominal value, as shown in Figure 28, is recommended.
TIME 490
MCU 480
ADE7768
COUNTER 470
CF
FREQUENCY (kHz)
460
450
05331-016
TIMER
440
05331-017
410
in a given integration time, which is determined by an MCU 400
internal timer. The average power proportional to the average 5.8 5.9 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7
RESISTANCE (k)
frequency is given by
Figure 28. Effect of RCLKIN on Internal Oscillator Frequency (OSC)
Counter
Average Frequency = Average Power = (8) TRANSFER FUNCTION
Time
Frequency Outputs F1 and F2
The energy consumed during an integration period is given by
The ADE7768 calculates the product of two voltage signals
Counter
Energy = Average Power Time = Time = Counter (9) (on Channel V1 and Channel V2) and then low-pass filters this
Time product to extract positive-only real power information. This
positive-only real power information is then converted to a
For the purpose of calibration, this integration time could be
frequency. The frequency information is output on F1 and F2
10 seconds to 20 seconds, to accumulate enough pulses to
in the form of active low pulses. The pulse rate at these outputs
ensure correct averaging of the frequency. In normal operation,
is relatively lowfor example, 0.175 Hz maximum for ac signals
the integration time could be reduced to 1 second or 2 seconds,
with S0 = S1 = 0 (see Table 6). This means that the frequency at
depending, for example, on the required update rate of a
these outputs is generated from positive-only real power
display. With shorter integration times on the MCU, the
information accumulated over a relatively long period of time.
amount of energy in each update may still have some small
The result is an output frequency that is proportional to the
amount of ripple, even under steady load conditions. However,
average positive-only real power. The averaging of the positive-
over a minute or more the measured energy has no ripple.
only real power signal is implicit to the digital-to-frequency
Power Measurement Considerations conversion. The output frequency or pulse rate is related to the
Calculating and displaying power information always has some input voltage signals by the following equation:
associated ripple, which depends on the integration period used 494.75 V1rms V2rms F1 4
Freq = (10)
in the MCU to determine average power and also on the load. VREF 2
For example, at light loads, the output frequency may be 10 Hz.
With an integration period of 2 seconds, only about 20 pulses where:
are counted. The possibility of missing one pulse always exists, Freq is the output frequency on F1 and F2 (Hz).
because the ADE7768 output frequency is running asynchro- V1rms is the differential rms voltage signal on Channel V1 (V).
nously to the MCU timer. This results in a 1-in-20 or 5% error V2rms is the differential rms voltage signal on Channel V2 (V).
in the power measurement. When REVP is logic high, the VREF is the reference voltage (2.45 V 200 mV) (V).
ADE7768 does not generate any pulse on F1, F2, and CF. F14 are one of four possible frequencies selected by using the
S0 and S1 logic inputs (see Table 5).
INTERNAL OSCILLATOR (OSC)
The nominal internal oscillator frequency is 450 kHz when
used with RCLKIN, with a nominal value of 6.2 k. The
frequency outputs are directly proportional to the oscillator
frequency, thus RCLKIN must have low tolerance and low
Rev. A | Page 14 of 20
ADE7768
Table 5. F14 Frequency Selection Table 7. Maximum Output Frequency on CF
1 2
S1 S0 OSC Relation F14 at Nominal OSC (Hz) SCF S1 S0 CF Max for AC Signals (Hz) 1
0 0 OSC/219 0.86 1 0 0 128 F1, F2 = 22.4
0 1 OSC/218 1.72 0 0 0 64 F1, F2 = 11.2
1 0 OSC/217 3.43 1 0 1 64 F1, F2 = 22.4
1 1 OSC/216 6.86 0 0 1 32 F1, F2 = 11.2
1
F14 is a binary fraction of the internal oscillator frequency. 1 1 0 32 F1, F2 = 22.4
2
Values are generated using the nominal frequency of 450 kHz. 0 1 0 16 F1, F2 = 11.2
1 1 1 16 F1, F2 = 22.4
Example
0 1 1 2048 F1, F2 = 2.867 kHz
In this example, with ac voltages of 30 mV peak applied to 1
Values are generated using the nominal frequency of 450 kHz.
V1 and 165 mV peak applied to V2, the expected output
frequency is calculated as follows: SELECTING A FREQUENCY FOR AN ENERGY
F14 = OSC/219 Hz, S0 = S1 = 0 METER APPLICATION
V1rms = 0.03/2 V As shown in Table 5, the user can select one of four frequencies.
V2rms = 0.165/2 V This frequency selection determines the maximum frequency
VREF = 2.45 V (nominal reference value) on F1 and F2. These outputs are intended for driving an energy
register (electromechanical or other). Because only four
Note that if the on-chip reference is used, actual output
different output frequencies can be selected, the available
frequencies may vary from device to device due to the
frequency selection has been optimized for a meter constant
reference tolerance of 200 mV.
of 100 imp/kWh with a maximum current of between 10 A
494.75 0.03 0.165 F1 (11) and 120 A. Table 8 shows the output frequency for several
Freq = = 0.204 F1 = 0.175
2 2 2.45 2 maximum currents (IMAX) with a line voltage of 220 V. In all
cases, the meter constant is 100 imp/kWh.
Table 6. Maximum Output Frequency on F1 and F2 Table 8. F1 and F2 Frequency at 100 imp/kWh
S1 S0 OSC Relation 1
Max Frequency or AC Inputs (Hz) IMAX (A) F1 and F2 (Hz)
0 0 0.204 F1 0.175 12.5 0.076
0 1 0.204 F2 0.35 25.0 0.153
1 0 0.204 F3 0.70 40.0 0.244
1 1 0.204 F4 1.40 60.0 0.367
1
80.0 0.489
Values are generated using the nominal frequency of 450 kHz.
120.0 0.733
Frequency Output CF
The pulse output CF (calibration frequency) is intended for The F14 frequencies allow complete coverage of this range of
calibration purposes. The output pulse rate on CF can be up output frequencies (F1, F2). When designing an energy meter,
to 2048 times the pulse rate on F1 and F2. The lower the F14 the nominal design voltage on Channel V2 (voltage) should be
frequency selected, the higher the CF scaling (except for the set to half-scale to allow calibration of the meter constant. The
high frequency mode SCF = 0, S1 = S0 = 1). Table 7 shows current channel should also be no more than half scale when
how the two frequencies are related, depending on the states the meter sees maximum load. This allows overcurrent signals
of the logic inputs S0, S1, and SCF. Due to its relatively high and signals with high crest factors to be accommodated. Table 9
pulse rate, the frequency at the CF logic output is proportional shows the output frequency on F1 and F2 when both analog
to the instantaneous positive-only real power. As with F1 and inputs are half scale. The frequencies in Table 9 align very well
F2, CF is derived from the output of the low-pass filter after with those in Table 8 for maximum load.
multiplication. However, because the output frequency is Table 9. F1 and F2 Frequency with Half-Scale AC Inputs
high, this positive-only real power information is accumulated Frequency on F1 and F2
over a much shorter time. Therefore, less averaging is carried S1 S0 F14 (Hz) CH1 and CH2 Half-Scale AC Input1
out in the digital-to-frequency conversion. With much less 0 0 0.86 0.051 F1 0.044 Hz
averaging of the positive-only real power signal, the CF output 0 1 1.72 0.051 F2 0.088 Hz
is much more responsive to power fluctuations (see the signal 1 0 3.43 0.051 F3 0.176 Hz
processing block diagram in Figure 15). 1 1 6.86 0.051 F4 0.352 Hz
1
Values are generated using the nominal frequency of 450 kHz.
Rev. A | Page 15 of 20
ADE7768
When selecting a suitable F14 frequency for a meter design, the For example, for an energy meter with a meter constant of
frequency output at IMAX (maximum load) with a meter constant 100 imp/kWh on F1, F2 using F3 (3.43 Hz), the minimum
of 100 imp/kWh should be compared with Column 4 of output frequency at F1 or F2 would be 0.00244% of 3.43 Hz or
Table 9. The closest frequency in Table 9 determines the best 8.38 105 Hz. This would be 2.68 103 Hz at CF (32 F1 Hz)
choice of frequency (F14). For example, if a meter with a max- when SCF = S0 = 1, S1 = 0. In this example, the no-load
imum current of 25 A is being designed, the output frequency threshold would be equivalent to 3 W of load or a start-up
on F1 and F2 with a meter constant of 100 imp/kWh is 0.153 Hz current of 13.72 mA at 220 V. Compare this value to the
at 25 A and 220 V (from Table 8). In Table 9, the closest fre- IEC62053-21 specification which states that the meter must
quency to 0.153 Hz in Column 4 is 0.176 Hz. Therefore, as start up with a load equal to or less than 0.4% Ib. For a 5 A (Ib)
shown in Table 5, F3 (3.43 Hz) is selected for this design. meter, 0.4% of Ib is equivalent to 20 mA.
NO-LOAD THRESHOLD
The ADE7768 includes a no-load threshold and start-up
current feature that eliminates any creep effects in the meter.
The ADE7768 is designed to issue a minimum output
frequency. Any load generating a frequency lower than this
minimum frequency does not cause a pulse to be issued on F1,
F2, or CF. The minimum output frequency is given as 0.00244%
for each of the F14 frequency selections (see Table 5).
Rev. A | Page 16 of 20
ADE7768
OUTLINE DIMENSIONS
10.00 (0.3937)
9.80 (0.3858)
16 9
4.00 (0.1575) 6.20 (0.2441)
3.80 (0.1496) 1 8 5.80 (0.2283)
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADE7768AR 40C to +85C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADE7768AR-RL 40C to +85C 16-Lead Standard Small Outline Package [SOIC_N] REEL R-16
ADE7768ARZ 1 40C to +85C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADE7768ARZ-RL1 40C to +85C 16-Lead Standard Small Outline Package [SOIC_N] REEL R-16
ADE7768AR-REF Reference Board
EVAL-ADE7768EB Evaluation Board
1
Z = Pb-free part.
Rev. A | Page 17 of 20
ADE7768
NOTES
Rev. A | Page 18 of 20
ADE7768
NOTES
Rev. A | Page 19 of 20
ADE7768
NOTES
Rev. A | Page 20 of 20