PC Lab

EC&PC lab manual Dept.
ECE
GEETHANJALI COLLEGE OF ENGINEERING AND

TECHNOLOGY
Cheeryal (V), Keesara (M), R. R. District
ELECTRONIC CIRCUITS AND PULSE CIRCUITS LAB
STUDENTS MANUAL
striving toward perfection
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
Lab Incharge: HOD-ECE:
EC lab: J. Mrudula Dr.P.Srihari

Associate Professor
PC lab: Prof.K.Somasekhara rao
M.Muthamma
Assistant Professor
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EC&PC lab manual Dept. ECE
GEETHANJALI COLLEGE OF ENGINEERING & TECHNOLOGY

Cheeryal (V), Keesara (M), R. R. District
striving toward perfection
LABORATORY MANUAL
FOR
ELECTRONIC CIRCUITS AND PULSE CIRCUITS LAB
Prepared by: Checked by:

PC lab: Prof. K. Somasekhara Rao, Prof. K. Somasekhara Rao,
M.Muthamma Dean of Academics, Dept., of ECE
Assistant Professor
Approved by:
Dr.P.Srihari ,HOD
Dept., of ECE
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GEETHANJALI COLLEGE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF Electrical and Electronics Engineering
(Name of the Subject / Lab Course) : Electronic circuits and Pulse circuits Lab
(JNTU CODE -) A40484 Programme : UG
Branch: ECE Version No : 01
Year: II Updated on : 10/12/2014
Semester: II No. of pages :
Classification status (Unrestricted / Restricted ): Unrestricted
Distribution List :Department , Lab, Library, Lab incharge
Prepared by : 1) Name : Prof.K.Somasekhara rao (PC lab) 1) Name : M.Muthamma
Design : Dean of Academics
Sign :
Name : J. Mrudula (EC lab)
Sign : 2) Sign :
3) Design : Associate professor 3) Design : Assistant Professor
4) Date : 26/11/15 4) Date :
Verified by : 1) Name :Prof. K. Somasekhara Rao * For Q.C Only.
2) Sign : 1) Name :
3) Design : Professor 2) Sign :
4) Date : 3) Design :
4) Date :
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Approved by : (HOD ) 1) Name : Dr. P.Srihari
2) Sign :
3) Date :
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ECE DEPARTMENT
Vision of the Department
To impart quality technical education in Electronics and Communication Engineering
emphasizing analysis, design/synthesis and evaluation of hardware/embedded software using
various Electronic Design Automation (EDA) tools with accent on creativity, innovation and
research thereby producing competent engineers who can meet global challenges with societal
commitment.
Mission of the Department
i. To impart quality education in fundamentals of basic sciences, mathematics, electronics and

communication engineering through innovative teaching-learning processes.
ii. To facilitate Graduates define, design, and solve engineering problems in the field of
Electronics and Communication Engineering using various Electronic Design Automation
(EDA) tools.
iii. To encourage research culture among faculty and students thereby facilitating them to be
creative and innovative through constant interaction with R & D organizations and Industry.
iv. To inculcate teamwork, imbibe leadership qualities, professional ethics and social
responsibilities in students and faculty.
Program Educational Objectives of B. Tech (ECE) Program:
I. To prepare students with excellent comprehension of basic sciences, mathematics and

engineering subjects facilitating them to gain employment or pursue postgraduate studies
with an appreciation for lifelong learning.
II. To train students with problem solving capabilities such as analysis and design with
adequate practical skills wherein they demonstrate creativity and innovation that would
enable them to develop state of the art equipment and technologies of multidisciplinary
nature for societal development.
III. To inculcate positive attitude, professional ethics, effective communication and
interpersonal skills which would facilitate them to succeed in the chosen profession
exhibiting creativity and innovation through research and development both as team
member and as well as leader.
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Program Outcomes of B.Tech ECE Program:
1. An ability to apply knowledge of Mathematics, Science, and Engineering to solve complex

engineering problems of Electronics and Communication Engineering systems.
2. An ability to model, simulate and design Electronics and Communication Engineering
systems, conduct experiments, as well as analyze and interpret data and prepare a report
with conclusions.
3. An ability to design an Electronics and Communication Engineering system, component,
or process to meet desired needs within the realistic constraints such as economic,
environmental, social, political, ethical, health and safety, manufacturability and
sustainability.
4. An ability to function on multidisciplinary teams involving interpersonal skills.
5. An ability to identify, formulate and solve engineering problems of multidisciplinary
nature.
6. An understanding of professional and ethical responsibilities involved in the practice of
Electronics and Communication Engineering profession.
7. An ability to communicate effectively with a range of audience on complex engineering
problems of multidisciplinary nature both in oral and written form.
8. The broad education necessary to understand the impact of engineering solutions in a
global, economic, environmental and societal context.
9. A recognition of the need for, and an ability to engage in life-long learning and acquire the
capability for the same.
10. A knowledge of contemporary issues involved in the practice of Electronics and
Communication Engineering profession
11. An ability to use the techniques, skills and modern engineering tools necessary for
engineering practice.
12. An ability to use modern Electronic Design Automation (EDA) tools, software and
electronic equipment to analyze, synthesize and evaluate Electronics and Communication
Engineering systems for multidisciplinary tasks.
13. Apply engineering and project management principles to one's own work and also to
manage projects of multidisciplinary nature.
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SYLLABUS
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Mapping of the Course Outcomes related to laboratory experiments with Program

Outcomes (POs):
Experiment Course Outcome Linkage to the Linkage to Mapping of
No/Experiment Theoretical Concept Other Courses POs
Name
Electronic The student will be Single stage and Multi Analog and PO2,PO3,PO
Circuits: able to design and stage Amplifier Digital 4,PO5,
implement analog Design by using BJT communication PO11,PO12
1. Common electronic circuits and FET. systems, Linear
emitter using transistors
amplifier Integrated
(like BJT, FET, Concept of topology
2.Common UJT) and diodes. Circuits
of feedback amplifiers
source An ability to use
amplifier multi-sim software
3.Two stage to validate analog
RC coupled circuits
amplifier
4. Current shunt
and voltage
series feedback
amplifier
5.MOS
Amplifier
6.RC phase The student will be Conditions of Analog PO2,PO3,PO
shift oscillator able to design and oscillations and basic Communications 4,PO5,
using transistors implement analog principles oscillators. (AC), PO11,PO12
7.Hartley electronic circuits Concept of feedback
oscillator and using transistors Linear integrated
colpitts network,
(like BJT, FET, circuits
oscillator UJT) and diodes. Characteristics of UJT
8.UJT An ability to use
relaxation multi-sim software
oscillator to validate analog
circuits
The student will be power Amplifiers and Analog PO2,PO3,PO

9.Class-A able to design and concept of transformer Communications 4,PO5,
power amplifier implement analog load, (AC), PO11,PO12
(Transformer electronic circuits
load) using transistors Linear integrated
(like BJT, FET, circuits
UJT) and diodes.
An ability to use
multi-sim software
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to validate analog
circuits
10.Linear wave Able to gain Working principle of EDC,DSP,AC, PO2,PO3,PO
shaping expertise in RC low pass and high 5,PO11,
pass circuits PO12
a)RC low pass designing of pulse
circuit for shaping circuits by
different time
analyzing different
constants
characteristics of
b)RC high pass
circuits
circuit for
different time
constants
11.Non-linear Able to extend and concept of clippers PO2,PO3,PO

wave shaping: comprehend the and clampers 5,PO11,
concepts of circuit working principles of Analog PO12
a)Transfer modeling to design Communications .
series and shunt
characteristics linear & non-linear
wave shaping and clippers, working
and response of principles of positive
multi-vibrators
clippers and negative Clampers
i)Positive and
negative
clippers
ii)Clipping at
two
independent
levels
b)The steady
state out put
wave form of
clampers for a
square wave
input
i)Positive and
negative
clampers
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ii)Clamping at
reference
voltage
12.Comparison Able to extend and Concept of basic Linear integrated PO2,PO3,PO

operation of comprehend the clippers circuits, Analog 5,PO11,
comparators concepts of circuit communications PO12
modeling to design
linear & non-linear
wave shaping and
multi-vibrators
13.Switching The student will be Basic concepts Digital integrated PO2,PO3,PO
characteristics able to design and operation of BJT circuits, VLSI 5,PO11,
of transistor implement analog Design PO12
electronic circuits
using transistors
(like BJT, FET,
UJT) and diodes.
An ability to use
multi-sim software
to validate analog
circuits
14.Design an An ability to The principles of Linear integrated PO2,PO3,PO

Astable multi- design, implement multi-vibrators circuits, Analog 5,PO11,
vibrators and and manage the communications PO12
electronic projects
draw its
for real world
waveforms applications
15.Design an
mono stable
multi-vibrators
and draw its
waveforms
16.Response of
Schmitt trigger
circuit for loop
gain less than
and greater than
one
Additional The student will be Single stage and Multi Analog and PO2,PO3,PO
Experiments: able to design and stage Amplifier Digital 4,PO5,
implement analog Design by using BJT communication
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1. Two electronic circuits and FET. systems, Linear PO11,PO12

stage using transistors Integrated
FET (like BJT, FET, Concept of topology Circuits
UJT) and diodes. of feedback amplifiers
amplifie
An ability to use
r.
multi-sim software
2. Commo to validate analog
circuits
n
collector
amplifie
r
The students will be
3. Boot able to use design
Strap time base
Sweep generators using
Circuit BJTs
INSTRUCTIONS
Instruction for students:-
1. Do not handle any equipment without reading the instructions /Instruction manuals.
2. Observe type of sockets of equipment power to avoid mechanical damage.
3. Do not insert connectors forcefully in the sockets.
4. Strictly observe the instructions given by the Teacher/ Lab Instructor.
5. After the experiment is over, the students must hand over the Bread board, Trainer kits, wires,
CRO probes and other components to the lab assistant/teacher.
6. It is mandatory to come to lab in a formal dress (Shirts, Trousers, ID card, and Shoes for boys).
Strictly no Jeans for both Girls and Boys.
7. It is mandatory to come with observation book and lab record in which previous experiment should
be written in Record and the present labs experiment in Observation book.
8. Observation book of the present lab experiment should be get corrected on the same day and
Record should be corrected on the next scheduled lab session.
9. Mobile Phones should be Switched OFF in the lab session.
10. Students have to come to lab in-time. Late comers are not allowed to enter the lab.
11. Prepare for the viva questions. At the end of the experiment, the lab faculty will ask the viva
questions and marks are allotted accordingly.
12. Bring all the required stationery like graph sheets, pencil & eraser, different color pens etc. for the
lab class.
13. While shorting 2 or more wires for common connections like grounding, do not twist wires. Use
shorting link on the bread board.
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Instructions to Laboratory Teachers:-
1. Observation book and lab records submitted for the lab work are to be checked and signed before
the next lab session.
2. Students should be instructed to switch ON the power supply after the connections are checked by
the lab assistant / teacher.
3. The promptness of submission of records/ observation books should be strictly insisted by awarding
the marks accordingly.
4. Ask viva questions at the end of the experiment.
5. Do not allow students who come late to the lab class.
6. Encourage the students to do the experiments innovatively.
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PART- II PULSE CIRCUITS
INDEX.
SNO EXP.NAME PAGE NO
1. LINEAR WAVE SHAPING

2. NON LINEAR WAVE SHAPING -CLIPPERS.
3. NON LINEAR WAVE SHAPING- CLAMPERS
4. SWITCHING CHARACTERISTICS OF TRANSISTOR
5. ASTABLE MULTIVIBRATOR
6. MONOSTABLE MULTIVIBRATOR
7. BISTABLE MULTIVIBRATOR.
8. UJT RELAXATION OSCILLATOR
ADDITIONAL EXPERIMENT
1 SCHMITT TRIGGER
2 BOOT STRAP SWEEP CIRCUIT
DESIGN EXPERIMENT
GENERATION OF DIFFERENT TYPES OF
WAVEFORMS FROM BASIC SINUSOIDAL
WAVEFORM
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PART-II
PULSE CIRCUITS
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LINEAR WAVE SHAPING

Experiment no. 1
Prior to Lab session:
1. Study the working principle of high pass and low pass RC circuits for non-sinusoidal signal inputs.
2. Study the definitions of % tilt, time constant, cut-off frequencies and rise time of RC circuits.
3. Study the procedure for conducting the experiment in the lab.
Objective::
1. To design High pass and Low pass RC circuits for different time constants and verify their responses
for a square wave input of given frequency.
2. To find the % tilt of high pass RC circuit for large time constant.
3. To study the operation of high pass RC circuit as a differentiator and low pass circuit as an integrator.
Apparatus:
1. CRO (Dual Channel 0-20 MHz) - 1 No.

2. Signal Generator ( 1Hz to 1 MHz) - 1No.
3. Decade capacitance box - 1 No.
Or Capacitors: 0.1F, 0.01 F, 0.001 F - 1 No. each
4. Resistor (100 K) - 1 No.
5. Connecting wires
6. Bread board
Circuit Diagrams:
Fig 1.1 High Pass RC circuit Fig 1.2 Low Pass RC circuit
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ECA LAB MANUAL ECE DEPT
Theory:
Resistors and Capacitors can be connected in series or parallel in various combinations.

The RC circuits can be configured in two ways as shown in the above circuit diagrams.
i.e. i) High Pass RC circuit ii) Low Pass RC circuit
High Pass RC circuit:
The reactance of the capacitor depends upon the frequency of operation. At very high
frequencies, the reactance of the capacitor is very low. Hence the capacitor in fig.1.1 acts as short circuit
for high frequencies. As a result the entire input almost appears at the output across the resistor.
At low frequencies, the reactance of the capacitor is very high. So the capacitor acts as almost
open circuit. Hence the output is very low. Since the circuit allows only high frequencies, it is called as
high pass RC circuit.
High - pass RC circuit as a differentiator:
In high pass RC circuit, if the time constant is very small in comparison with the time
required for the input signal to make an appreciable change, the circuit is called a Differentiator.
Under these circumstances, the voltage drop across R will be very small in comparison with the drop
across C. Hence we may consider that the total input Vi appears across C, so that the current is
determined entirely by the capacitor. i = C dVi/dt.
The output voltage across R is, Vo = RC (dVi/dt).
i.e. The output voltage is proportional to the differential of the input signal. Hence the high pass
RC circuit acts as a differentiator when RC << T.
Low Pass RC circuit:
The reactance of the capacitor depends upon the frequency of operation. At very high
frequencies, the reactance of the capacitor is almost zero. Hence the capacitor in fig.1.2 acts as short
circuit. As a result, the output will fall to zero.
At low frequencies, the reactance of the capacitor is infinite. So the capacitor acts as open circuit.
As a result the entire input appears at the output. Since the circuit allows only low frequencies, it
is called as low pass RC circuit.
Low Pass RC circuit as an integrator:
In low pass circuit, if the time constant is very large in comparison with the time required for the
input signal to make an appreciable change, the circuit is called an integrator. Under these
circumstances the voltage drop across C will be very small in comparison to the drop across R and
almost the total input Vi appears across R .i.e. i = Vi/R.
17
The output signal across C is
i.e. The output is proportional to the integral of the input signal. Hence the low pass RC circuit acts as a
integrator for RC >> T.
Design:
RC high pass circuit:
i) Large time constant: RC > > T :

Where RC is the time constant and T is time period of Input signal.
Let RC = 10 T, Choose R = 100k, f = 1kHz.
C = 10 / (103X 100X103 ) = 0.1f
ii) Medium time constant: RC = T
C = T/R = 1/ (103X100X103 ) = 0.01f
iii) Short time constant: RC < < T
RC = T/10 C = T/10R = 1/(10X103X100X103) = 0.001 f.
RC low pass circuit: (Design procedure is same as RC high pass circuit)

i) Large time constant : RC > > T, C = O.1f
ii) Medium time constant : RC = T, C = 0.01 f
iii) Short time constant : RC = T/10, C = 0.001 f
Expected output wave forms of High pass RC circuit for square wave input:
Consider the input at V1 during T1 and V11 during T2 then the voltages V1, V11, V2 , V2 1 are
given by following equations.
V11- V2 = V
V1-V21 = V
For a symmetrical square wave
and
and because of symmetry V1= -V2 V11= -V21
The percentage tilt P is defined by P= (V1-V11) / (V/2) X 100 -------------1.1
18
Input wave Form
a) RC = T
b) RC >> T ( RC = 10T)
c) RC << T (RC = 0.1T)
19
Expected output wave forms of Low pass RC circuit for square wave input:
Consider the input at V1 during T1 and V11 during T2 then the voltages V01, VO2 during T1
and T2 is given by following equations.
For a symmetrical square wave V2= V/2(tanhx) and V1= -V2 where x = T/(4RC)
a) RC = T
b) RC >> T
20
c) RC << T
21
Procedure:
1. Connect the circuits as shown in the above figures (fig.1.1 and fig 1.2).
2. Apply the Square wave input to this circuit (Vi = 2 VP-P, f = 1KHz)
3. Observe the output waveform for (a) RC = T, (b) RC<<T, (c) RC>>T
4. Verify the values with theoretical calculations.
Observations:
High pass RC circuit Low pass RC circuit:
Time Voltage
S.No. constant levels Time Voltage
S.No constant levels
V1
nt V1
V11
1 RC=T V2
1. RC=T V2
V21 1. V1
V1
2 RC>>T V2
V11 ( RC=10T)
2
RC>>T V2
RC=T V1
( RC=10T)
V21 3 RC<<T
( RC=0.1T) V2
V1
RC<<T
V11
3 Table 1.2
3 RC<<T V2
( RC=0.1T)
V2 1
Table 1.1
22
Time Voltage levels Voltage levels %Tilt %Tilt (use

Constant (Theoretical) (Practical) (Theoretical) equation 1.1)
(Practical)
V1 V11 V1 V1 V11 V
RC<<T
RC=T
RC>>T
Result:
1. The responses of Low pass and High pass RC circuits have been verified for square wave inputs
for different time constants.
2. Verified the theoretical and practical values of %P.
3. Observed the operation of differentiator and integrator circuits.
Viva questions
1. What is a linear network? What is linear wave shaping?

2. Define Time constant. What is its formula?
3. Define % tilt and rise time. Write the expressions for the same.
4. When High pass RC circuit is used as Differentiator? What is the formula for the output, when
operated as differentiator?
5. When Low pass RC circuit is used as Integrator? What is the formula for the output, when the
circuit is operated as Integrator?
6. What is the Difference between Low pass and High pass RC circuits.
7. A Capacitor blocks __ signal and passes __ signal. The voltage across the ___ will not change
suddenly.
8. Explain 3 dB values for a LP and HP circuit.
9. A differentiator converts a square wave into what form? An integrator converts a square wave
into what form?
10. What are the formulae for charging a capacitor from an initial voltage of Vi to a final voltage of
Vo.
11. Instead of using RC components for a low pass or high pass, how the circuit changes , if we want
to use RL components? What are the values for the Time constant for RL circuits?
12. When a capacitor in a low pass circuit charges to 99.3 % ( treated as fully charged) for a step
input to a Low pass filter?
13. What is a peaking circuit?
14. What is a ringing circuit?
15. Why resistive attenuators are to be compensated?
Design Problems
1. Design RC Differentiator circuit for frequency of 2kHz.
2. Design RC high circuit for a square wave input signal of frequency 2.5KHz for
i) RC=10T ii)RC=T iii)RC=T/10
3. Design low pass circuit for a square wave signal of 3KHz for
i) RC=5T ii) RC=T iii) RC = T/5
23
4. Verify the output of circuits given in Fig1.1 and Fig 1.2 for input square wave of frequencies
10KHz and 500Hz.
5. Verify the RC high pass circuit output for sinusoidal input.
Outcomes: After finishing this experiment the students are able to

1. Design High pass and Low pass circuits with different time constants.
2. Find % Tilt
3. Observe the output waveforms for a given square wave.
24
Experiment No: 2
NON LINEAR WAVE SHAPING - CLIPPERS
Prior to the Lab session:
1. Study the operation and working principle of Diode under Forward bias and Reverse bias
conditions.
2. Study the Classification of clipper circuits and their operation with positive reference, negative
reference and zero reference voltages.
Objective:
1. To study the various clipper circuits and to plot the output waveforms for a sinusoidal input of
given peak amplitude.(Choose f=1 kHz, Vp-p =10v)
2. To observe the transfer characteristics of all the clipping circuits on CRO.
Apparatus:
1. CRO (Dual Channel 0 to 20 MHz) - 1 No.

2. Signal Generator ( 1Hz to 1 MHz) - 1 No.
3. Diode (1N4007) - 1 No.
4. Resistor (2.2 K) - 2 Nos.
5. D.C Power Supply (0 30 V (dual)) - 1 No.
6. Connecting wires
7. Bread board
Theory:
The process whereby the form of sinusoidal signals is going to be altered by transmitting through
a non-linear network is called non-linear wave shaping. Non-linear elements (like diodes, transistors) in
combination with resistors can function as clipper circuit.
Clipping circuits are used to select transmission of that part of an arbitrary wave form which
lies above or below some particular reference voltage level. Clipping circuits are also referred to as
Limiters, Amplitude selectors or Slicers.
Clipping circuits are constructed using a combination of resistors, diodes or transistor and
reference voltage. Clipping circuits are classified based on the position of diode as
i) Series diode clipper ii) Shunt diode clipper
and further they are classified as, with 0 reference, with +ve reference, with ve reference; also as
positive clipper , negative clipper.
25
Procedure:
1. Connect the circuit as shown in the figures given below.

2. In each case, apply 10 V P-P, 1 KHz Sine wave as Input using a signal generator.
3. Observe the Output waveform (VO in the circuit) on the CRO and compare it with Input waveform.
4. Sketch the Input as well as Output waveforms and mark the voltage levels.
5. Note the changes in the Output due to variations in the reference voltage VR = 0V, 2V.. etc.
6. Obtain the transfer characteristics of Clipper circuit, by keeping CRO in X-Y mode.
7. Repeat the above steps for all the clipping circuits.
Precautions:
1. Set the CRO Output channel in DC mode always.

2. Observe the waveforms simultaneously in two channels by keeping the same reference ground.
3. See that there is no DC component in the INPUT.
4. To find transfer characteristics, apply input to the X-Channel, Output to Y-Channel, adjust the dot at
the center of the screen when CRO is in X-Y mode. Both the channels must be in ground, then remove
ground and plot the transfer characteristics
26
Circuit diagrams:
Input Signal
Transfer characteristics:
Fig 2.1 Negative clipper with zero reference (Series clipper)
27
Fig 2.2 Positive clipper with zero reference (Series clipper)
Fig 2.3 Negative clipper with zero reference (Shunt clipper)
28
Fig 2.4 Positive clipper with zero reference (Shunt clipper)
Fig. 2.5 Positive clipper with positive reference (Series clipper)
29
Fig. 2.6 Positive clipper with positive reference (Shunt clipper)
30
Fig. 2.7 Negative clipper with positive reference (Series clipper)
Fig.2.8 Negative clipper with positive reference (Shunt clipper)
Fig.2.9 Clipping at two independent levels.
31
Observations:
S. No. Type of Clipper Reference Practical

Voltage Clipping Voltage levels
0V V1
V2
1 Series Positive Clipper 2V V1
V2
0V V1
V2
2 Series Negative Clipper 2V V1
V2
0V V1
V2
3 Shunt Positive Clipper 2V V1
V2
0V V1
V2
4 Shunt Negative Clipper 2V V1
V2
5 Two level clipper V1
V2
Inference: The different types of clippers circuits are studied and observed the response for various
combinations of VR and clipping diodes.
Viva Questions:
1. Define non linear wave shaping? What are the non-linear components?
2. Define clipping circuit? What are the other names for clippers?
3. Write the piecewise linear characteristics of a diode?
4. What are the different types of clippers?
5. Which kind of a clipper is called a slicer circuit?
6. What are the applications of Clipper Circuits?
7. What is the figure of merit for diodes used in clipping circuits?
8. What is the influence of the practical diode compared to the ideal diode, in the above circuits?
9. Instead of sinusoidal wave form as input, if we give other wave forms like triangular or square,
then how the clipping action is performed?
10. What is V for Ge diode and V for Si diode?
Design Problems
1. Design a clipper circuit to get the output shown in below for a sinusoidal input with 10V peak to
peak.
32
2. Design a clipper circuit using zener diode with 4.7V break down voltage.
3. Verify the output of clipper circuit for square & triangular inputs.
Outcomes: After finishing this experiment, students are able to design different types of clipper circuits
and observe the input output waveforms in the CRO and obtain the transfer characteristics for each
circuit.
33
Experiment No: 3
NON LINEAR WAVE SHAPING-CLAMPPERS
1. Study the operation and working principle of Clamper circuits

2. Study the Classification of clamper circuits and its operation with positive reference, negative
reference and zero reference voltages.
Objective:
l. To study the various clamping circuits and to plot the output waveforms for a sinusoidal input of given
peak amplitude. (Choose f=l KHz, Vp-p =l0 V)
Apparatus:
l. CRO (Dual Channel 0 to 20 MHz) - l No.

2. Signal Generator ( 1Hz to 1 MHz) - l No.
3. Diode (lN4007) - l No.
4. Resistor (l00 K) - l No.
5. Capacitor (0.l pF) - l No.
6. D.C Power Supply 0 30 V (dual) - l No.
7. Connecting wires
8. Bread board
Theory:
The process where sinusoidal signals are going to be altered by transmitting through a non-linear
network is called non-linear wave shaping. Non-linear elements (like diodes) in combination with
resistors and capacitors can function as clamping circuit.
Clamping circuits add a DC level to an AC signal. A clamper is also referred to as DC restorer or

DC re-inserter. The Clampers clamp the given waveform either above or below the reference level, which
are known as positive or negative clampers respectively.
Clamping circuits are classified as two types.
i) Negative Clampers ii) Positive Clampers
Procedure:
l. Connect the circuit as shown in the figure 3.1 below.
34
2. Apply a Sine wave of l0V P-P, l KHz at the input terminals with the help of Signal Generator.
3. Observe the Input & Output waveforms on CRO and plot the waveforms and mark the values with
VR = 0V, 3V, etc.
4. Output is taken across the load RL.
5. Repeat the above steps for all clamping circuits ( fig 3.2 to fig 3.6) as shown.
6. Draw the waveforms, assuming the diode is practical.
Circuit diagrams:
Input Signal
Fig.3.l Negative clamping with zero reference voltage
Fig.3.2 positive clamping with zero reference voltage
35
Fig.3.3 Negative clamping with Negative reference voltage
Fig.3.4 positive clamping positive reference voltage
Fig.3.5 Negative clamping with Positive reference voltage
Fig.3.6 Positive clamping with Negative reference voltage
36
Observations:
Reference Practical clamping reference Voltage

Sl No. Type of Clamper
Voltage levels
0V V1
V2
l Positive Clamper
2V V1
V2
-2V V1
V2
0V V1
V2
2 Negative Clamper
2V V1
V2
-2V V1
V2
Inference:
The different types of clamping circuits are studied and the response was observed for various
combinations of VR, capacitors and diodes.
Viva Questions
1. What are the applications of clamping circuits?

2. What is the synchronized clamping?
3. Explain the Principle of operation of Clampers.
4. What is clamping circuit theorem.
5. What is the function of the capacitor in clamper circuit?
6. What are the effects of diode characteristics on the output of the Clamper?
7. If we interchange the diode and the capacitor in fig 1 above, how the circuit behaves?
8. Calculate the power dissipation in the Resistor for any one of the above circuits?
9. What is the difference between a clipper and a clamper?
10. What are the other names for clampers?
Design Problems
1. Design a circuit that clamps the positive peaks to zero that can effectively provide DC restoration
to input with frequency extending up to 1.5KHz.
2. How much voltage will get across capacitor in clamper circuit with input voltage of 20Vp-p
37
3. Design a negative clamper circuit from positive clamper circuit.
Outcomes: After finishing this experiment students are able to design different types of clamper circuits.
38
Experiment No: 4
TRANSISTOR AS A SWITCH
l. Study the operation and working principle of the Transistor in all regions.
2. Study the procedure for conducting this experiment in the lab.
Objective:
l. To study the Switching characteristics of a transistor.

2. Design Transistor to act as a Switch and verify the operation. Choose VCC = l0V, ICmax= l0 mA, hfe = 50, VCESat
VCESat = 0.2V, Vin = 4Vp-p, VBESat = O.6 V.
Apparatus:
l. CRO 0 20 MHz (Dual Channel) - l No.

2. Function Generator 1Hz 1 MHz - l No.
3. Resistor (l K, 8.2 K) - l each
4. Transistor (BC l07) - l No.
5. D.C Power Supply 0-30V (dual) - l No.
6. Connecting wires
7. Bread board
Circuit diagram:
Theory:
The Transistor can act as a switch. To operate the transistor as a switch, it has to be operated in saturation
region for ON state and to be operated in cut off region for OFF state.
When the Input voltage Vi is negative or zero, transistor is cut-off and no current flows through Rc. Hence
V0 is approximately equal to VCC . When Input Voltage Vi is changed to positive voltage, transistor will be driven
into saturation. Then, V0 = Vcc ICRC VCESat., which is a very small voltage.
39
Design procedure:
When Transistor is ON, RC = (VCC - VCEsat)/ICmax

= (10-0.2) / 10mA
= 1K
IB ICmax /hfe
10mA /50
IB 0.2mA
To keep transistor remain in ON, IB should be greater then IBmin =0.2mA
Vin= IBRB + VBEsat
2V=0.2mA. RB+ 0.6 V
RB = 7 K (Choose Practical values as 8.2 K)
Procedure:
l. Connect the circuit as shown in the above figure.

2. Apply the Square wave of 4 Vp-p at frequency of l KHz
3. Observe the waveforms at Collector and Base of the transistor and plot it.
Precautions:
l. Keep the CRO in DC mode while measuring the Output waveform at collector and base,
2. For measuring VBE Sat and VCE Sat keep volts/div switch at either O.2 or O.5 position.
3. When the square wave is being applied, ensure that there is no DC voltage in that. This can be
checked by CRO in either in AC or DC mode. There should not be any jumps/distortion in waveform on
the screen.
Waveforms:
40
Inference:
Transistor as a switch has been designed operated and Output waveforms are observed.
Viva Questions
1. Mention typical values of VBE Sat, VCE Sat for both Si, Ge Transistors?
2. Define ON time and OFF time of the transistor?
3. Define Rise time & fall time of a transistor switch?
4. Define Storage time and delay time?
5. What is the phase difference between the input and the output, when the transistor is conducting?
6. What modifications are to be done in the above circuit if we use PNP transistor instead of NPN
transistor?
7. How to calculate IC in the above circuit, when the transistor is ON?
8. What is the output voltage swing for the above circuit?
9. Why square wave is given as input instead of a sinusoidal wave for switching ON and OFF of the
transistor?
10. In which regions Transistor acts as a switch?
Design problem
1. Design transistor switch to get an output of 12Vp-p swing.
2. Can we apply sinusoidal signal to transistor as switch & verify the output for the same.
3. Design a high speed transistor switch.
Outcomes: After finishing this experiment, the students are able to design a transistor switch circuit and
observe the waveforms.
41
Experiment No: 5
UJT RELAXATION OSCILLATOR

1. Study the operation and working of Uni-Junction Transistor.
Objective:
1.To Study the operation of UJT as a Relaxation Oscillator
2.Calculate sweep time and flyback time of UJT relaxation oscillator.
Apparatus:
1. CRO 0 20 MHz (Dual channel) - 1No.

2. Function generator 1Hz 1 MHz - 1No.
3. Capacitor (0.1F) - 1 No
4. Resistors (1k, 33K, 510) - 1 No each.
5. Uni- junction transistor (2N2646) - 1 No.
6. Regulated Power supply 0-30 VDC (dual ) - 1 No.
7. Connecting wires
8. Bread board
Circuit diagram:
42
Theory:
Pin assignment of UJT:
Viewing from the side of pins
The uni-junction transistor (UJT) has two doped regions with three external leads. It has one
emitter and two bases. The emitter is heavily doped having many holes. The n-region is lightly doped.
For this reason, the resistance between the bases is relatively high, typically 5K to 10 K when the
emitter is open. This is called Inter-base Resistance RBB.
Operation:
The inter-base resistance between B2 and B1 of the silicon bar is, RBB=RB1+ RB2.
With emitter terminal open, if voltage VBB is applied between the two bases, a voltage gradient is
established along the n-type bar.
The voltage drop across RB1 is given by = VBB, where the intrinsic stand-off ratio
=RB1/( RB1 + RB2)
The typical value of ranges from 0.56 to 0.75.
This voltage V1 reverse biases the PN-junction and emitter current is cut-off. But a small
leakage current flows from B2 to emitter due to minority carriers.
The equivalent circuit of UJT is shown in figure below.
43
Fig.5.2 UJT equivalent circuit.
If a negative voltage is applied to the emitter, PN-junction remains reverse biased and the emitter
current is cut-of. The device is now in the OFF state.
If a positive voltage VE is applied to the emitter, the PN-junction will remain reverse biased so
long as VE is less than Vi. If VE exceeds Vi by the cut-in voltage vy, the diode becomes forward
biased. Under this condition, holes are injected into n-type bar. These holes are repelled by the terminal
B2 and are attracted by the terminal B1. Accumulations of holes in E to B1 region reduce the
resistance in this section and hence emitter current IE is increased and is limited by V E. The
device is now in the ON state.
Characteristics of UJT:
Figure below shows the input characteristics of UJT.
Fig.5.3 Characteristics of UJT
Here, up to the peak point, the diode is reverse biased and hence, the region to the left of the peak
point is called cut-off region.
At P, the peak voltage VP = VBB +V , the diode starts conducting and holes are injected into
n-layer. Hence, resistance decreases thereby decreasing V E for the increase in IE. So there is a negative
resistance region from peak point P to valley point V.
After the valley point, the device is driven into saturation and behaves like a conventional
forward biased PN-junction diode. The region to the right of the valley point is called saturation region.
In the valley point, the resistance changes from negative to positive. The resistance remains
positive in the saturation region.
44
Due to the negative resistance property, a UJT can be employed in a variety of applications, viz.,
a saw-tooth wave generator, pulse generator, switching, and timing and phase control circuits.
Frequency of oscillations:
The time period and hence the frequency of the saw-tooth wave can be calculated as follows:
Assuming that the capacitor is initially uncharged, the voltage VC across the capacitor prior to breakdown
is given by
VC = VBB (1- e t/ RECE)
Where RECE = charging time constant of resistor-capacitor circuit, and t= time from the
commencement of the waveform.
The discharge of the capacitor occurs when VC is equal to the peak-point voltage VP, i.e,
VP = VBB = VBB (1- e t/ RECE)
= 1- e t/ RECE
e t/ RECE = 1-
t = RECE loge(1/(1- ))
= 2.303 RECE log10(1/(1- ))
If the discharge time of the capacitor is neglected, then t=T, the period of the wave.
Therefore, frequency of oscillations of saw-tooth wave,
F = 1/T = 1/(2.303 RECE log10(1/(1- )))

Procedure
1. Connect the circuit as shown in figure.
2. Apply 12V DC power supply to the circuit.
3. Observe the output waveform on the CRO at B1, B2 and VO and Plot the graphs
4. Vary the time constant (RC) by varying capacitor (C) or potentiometer (R) and observe the variations
in the output pulses on the CRO at B1, B2 and VO.
45
Expected Graphs :
Fig.5.4 output waveforms of UJT relaxation oscillator
Inference: The operation of UJT as relaxation oscillator is studied.
Viva Questions:
1. What is a relaxation oscillator?
2. The most useful applications of a relaxation oscillator waveform are _, _
3. What is meant by intrinsic stand off ratio of an UJT?
4. Why UJT is called as negative resistance device? When the negative resistance exists in UJT
characteristics.
5. Draw the equivalent circuit of an UJT.
6. The deviation from linearity of a relaxation oscillator is expressed in three ways. What are they?
7. The other names of Relaxation oscillator are _, _ & _.
8. The time during which the output increases linearly is called the __ and the time required by the sweep
voltage to return to the initial value is called the __
9. When __ of a relaxation oscillator output is zero, a saw-tooth or ramp output waveform is obtained.
10. What are Peak point and valley point for an UJT? Write formula for Peak voltage.
Design problems
1. Design UJT relaxation oscillator with sweep amplitude of 6V, with sweep interval of 3ms neglect
flyback time and es=0.75.
2. Design UJT relaxation oscillator with sweep amplitude of 10V, with sweep interval of 2ms neglect
Outcomes: After finishing this experiment students are able to understand the operation of UJT as a
relaxation oscillator.
46
Experiment No. 6
ASTABLE MULTIVIBRATOR
1. Study the operation and working principle of Astable Multivibrator.

Objective:
1. To study the operation and observe the wave forms of Astable Multivibrator.
2. To Design an Astable Multivibrator to generate a square wave of 1 KHz frequency using Transistor.
Apparatus:
1. CRO 0 to 20 MHz (Dual Channel) - 1 No.
2. Function Generator 1Hz to 1 MHz - 1 No.
3. Bread board - 1 No.
5. Resistor (1 K, 10 K) - 2 Nos each
6. Capacitors (0.1F) - 2 Nos
6. Transistor (BC 107) - 2 Nos
7. Regulated D.C Power Supply 0 to 30V (dual) - 1 No.
8. Connecting wires
9. Bread board
Circuit diagram:
47
Theory:
The Astable circuit has two quasi-stable states. Without external triggering signal the Astable
configuration will make successive transitions from one quasi-stable state to the other. The Astable
circuit is an oscillator. It is also called as free running multivibrator and is used to generate Square
Wave. Since it does not require triggering signal, fast switching is possible.
Operation:
When the power is applied, due to some imbalance in the circuit, the transistor Q2
conducts more than Q1 i.e. current flowing through transistor Q2 is more than the current flowing in
transistor Q1. The voltage VC2 drops. This drop is coupled by the capacitor C1 to the base by Q1 there by
reducing its forward base-emitter voltage and causing Q1 to conduct less. As the current through Q1
decreases, VC1 rises. This rise is coupled by the capacitor C2 to the base of Q2. There by
increasing its base- emitter forward bias. This Q2 conducts more and more and Q1 conducts less and less,
each action reinforcing the other. Ultimately Q2 gets saturated and becomes fully ON and Q1 becomes
OFF. During this time C1 has been charging towards VCC exponentially with a time constant T1 = R1C1.
The polarity of C1 should be such that it should supply voltage to the base of Q1. When C1 gains sufficient
voltage, it drives Q1 ON. Then VC1 decreases and makes Q2 OFF. VC2 increases and makes Q1 fully
saturated. During this time C2 has been charging through VCC, R2, C2 and Qi with a time constant T2 =
R2C2. The polarity of C2 should be such that it should supply voltage to the base of Q2. When C2 gains
sufficient voltage, it drives Q2 ON, and the process repeats.
Design Procedure:
The period T is given by
T = T 1 + T2 = O.69 (R1C1 + R2C2)
For symmetrical circuit, with R1 = R2 = R & C1 = C2 = C
T = 1.38 RC
Let VCC = 12V; hfe = 51 (for BC107), VBESat = 0.7V; VCESat = 0.3V Let C = 0.1F & T=1mSec.
T = 1.38 RC
10 -3 = 1.38 x R X 0.1 X 10-6
R = 7.24 K (Practically choose 10K) i.e R1 and R2 resistors.
Let ICmax=10mA
RC= = = 1.17K ( 1 K is selected for Rc1 and Rc2)
48
Procedure:
1. Make then connections as per the circuit diagram.

2. Observe the Base Voltage and Collector Voltages of Q1 & Q2 on CRO in DC mode and measure the
frequency (f = 1/T).
3. Trace the waveforms at collector and base as each transistor with the help of dual trace CRO and plot
the waveforms.
4. Verify the practical output frequency with theoretical values f = 1/T, where T = 1.38 RC
Expected Waveforms:
49
Theoretical calculations: F= 1/ T= (1/1.38RC)
R= 10K C=0.1F
Result: An Astable Multivibrator is designed; the waveforms are observed and verified the results
theoretically.
Viva questions
1. What are the other names of Astable multivibrator?

2. The smaller allowable interval between two triggers is called the __ of the flip-flop.
3. Explain charging and discharging of capacitors in an Astable Multivibrator?
4. How can an Astable multivibrator be used as VCO?
5. What are symmetrical triggering and unsymmetrical triggering?
6. What are the applications of Astable Multivibrator?
7. Which multivibrator has two quasi-stable states? What is duty cycle?
8. What is the formula for frequency of oscillations?
9. An astable multivibrator is used as a ___ generator.
10. Design R and C for a frequency of 2KHz of a symmetric Astable oscillator.
Design problems
1. Design a collector coupled astable multivibrator using 2-BC107 transistors to operate at 1.5KHz
and with a duty cycle of 45% hfe min)=40, VCC=12V, IC(sat)=10mA.
2. Design voltage to frequency converter using astable multivibrator.
Outcomes: After finishing this experiment students are able to design Astable Multivibrator and explain
the operation of the same.
50
Experiment No: 7
MONOSTABLE MULTIVIBRATOR
Pre-Lab:
1. Study the operation and working principle Monostable Multivibrator.

Objectives:
1. To study the operation and observe the wave forms of Monostable Multivibrator.
2. To Design a Monostable multivibrator for the pulse width of 0.3mSec.
Apparatus:
1. CRO 0 to 20 MHz (Dual channel) - 1No.

2. Function generator 1Hz to 1 MHz - 1No.
3. Capacitors (0.033F) - 2 No.
4. Capacitor(0.01 F)) - 1 No.
5. Resistors (1 k, 10k, 100K, 47K) - 2, 2, 1 and 1 Nos .
6. Transistor (BC 107) - 2 No.
7. Diode(IN4148) - 1 No.
8. Regulated Power supply 0 30 V(dual ) - 1 No.
9. Connecting wires
10. Bread board
Circuit diagram:
51
Theory:
The monostable circuit has one permanently stable and one quasi-stable state. In the monostable
configuration, a triggering signal is required to induce a transition from the stable state to the quasi- stable
state. The circuit remains in its quasi-stable for a time equal to RC time constant of the circuit. It returns
from the quasi-stable state to its stable state without any external triggering pulse. It is also called as one-
shot, a single cycle, a single step circuit or a univibrator.
Operation:
Assume initially transistor Q2 is in saturation as it gets base bias from V CC through R. coupling
from Q2 collector to Q1 base ensures that Q1 is in cutoff. If an appropriate negative trigger pulse
applied at collector of Q1 (VC1) induces a transition in Q2, then Q2 goes to cutoff. The output at Q2 goes
high. This high output when coupled to Q1 base, turns it ON. The Q1 collector voltage falls by IC1
RC1 and Q2 base voltage falls by the same amount, as voltage across a capacitor C cannot
change instantaneously.
The moment, a negative trigger is applied at VC1, Q2 goes to cutoff and Q1 starts conducting.
There is a path for capacitor C to charge from VCC through R and the conducting transistor Q1. The
polarity should be such that Q2 base potential rises. The moment, it exceeds Q2 base cut-in voltage, it
turns ON Q2 which due to coupling through R1 from collector of Q2 to base of Q1, turns Q1 OFF.
Now we are back to the original state i.e. Q2 is ON and Q1 is OFF. Whenever trigger the circuit into the
other state, it cannot stay there permanently and it returns back after a time period decided by R and C.
Pulse width is given as T = 0.69RCsec.F
Design Procedure:
To design a monostable multivibrator for the Pulse width of 0.3 mSec.
52
Let ICmax = 15mA, VCC = 15V, VBB = 15V, R1 = 10K.

T =0.69RC
Choose C = 10nf(0.01F) T = 0.69 RC
0.3 x 10-3Sec = 0.69 x R x 10 x 10-9
R = 43.47 K 47K
RC = (VCC- VCESAT) / ICMAX = (15 0.3) / 15 X 10-3
= 1 K
Minimum requirement of | VB1| 0.1
For more margin, given VB1 = -1.185
VB1 = +
Substitute the values , R1=10k we will get R2= 100K
Procedure:
1. Make the connections as per the circuit diagram.

2. Select the triggering pulse such that the frequency is less than 1/T
3. Apply the triggering input to the circuit and to the CROs channel and Connect the CRO channel-2 to
the collector and base of the Transistor Q1&Q2.
4. Adjust the triggering pulse frequency to get stable pulse on the CRO and now measure the pulse width
and verify with the theoretical value.
5. Obtain waveforms at different points like VB1, VB2, VC1 & VC2 and plot the graph.
Expected Waveforms:
Trigger input
53
Theoretical calculations: TON = 0.69 RC
R= 47K and C = 10nF or 0.01F
Note: Normally Monostable Multivibrator generates single pulse output whenever a trigger is given. To
observe this output storage oscilloscope is required.
Result: Monostable Multivibrator is designed; the waveforms are observed and verified the results
theoretically.
Viva Questions:
1. What is a multivibrator? What is a quasi state?

2. What are applications of Monostable Multivibrator?
3. The monostable multivibrator is also called __, ___, __, ___ or ___.
4. A Monostable Multivibrator generates __ waveform.
5. Why is the time period T also called Delay time?
6. Justify, Why Monostable Multivibrator is called one-shot circuit?
7. In monostable multivibrator, the coupling elements are __.
54
8. What is the formula for the pulse width of a Monostable multivibrator? To get a pulse width of 2
mSec., get the values of R and C.
9. ___ triggering is used in monostable multivibrator.
10. What is monostable multivibrator and define its working states.
Design Projects
1. Design a collector coupled monostable multivibrator using 2-BC107 transistor with 5ms quasi
stable state duration VCC=10V , hfe(min)=30 IC(sat)=5mA.
2. Verify the output of monostable multivibrator by using different triggering methods.
Outcomes: After finishing this experiment students are able to design Monostable Multivibrator and able
to explain its operation.
55
Experiment No: 8
BISTABLE MULTIVIBRATOR
1. Study the operation and working principle Bistable Multivibrator.

Objective
1. To Design a Bistable Multivibrator & observe its response.
Apparatus:
1. CRO 0 to 20 MHz (Dual channel) - 1No.

2. Function generator 1Hz to 1 MHz - 1No.
3. Capacitor (0.001F, 0.33 F) - 2 Nos each.
4. Resistors (1 k, 10k, 100K) - 2 Nos each.
5. Transistor (BC 107) - 2 No. each.
6. Diode (IN4007) - 4 No. each.
7. Regulated Power supply 0 30 V(dual ) - 1 No.
8. Connecting wires
9. Bread board
Circuit diagram:
56
Theory:
A Bistable circuit is one which can exist indefinitely in either of two stable states and which
can be induced to make an abrupt transition from one state to the other by means of external
excitation. The Bistable circuit is also called as Bistable multivibrator, Eccles Jordon circuit, Trigger
circuit, Scale-of-2 toggle circuit, Flip-Flop & Binary.
A Bistable multivibratior is used in a many digital operations such as counting and the storing
of binary information. It is also used in the generation and processing of pulse-type
waveform. They can be used to control digital circuits and as frequency dividers.
There are two outputs available which are complements of one another. i.e. when one output is
high the other is low and vice versa .
Operation:
When VCC is applied, one transistor will start conducting slightly more than that of the other,
because of some differences in the characteristics of a transistor. Let Q2 be ON and Q1 be OFF. When Q2
is ON, The potential at the collector of Q2 decreases, which in turn will decrease the potential at the
base of Q1 due to potential divider action of R1 and R2. The potential at the collector of Q1
increases which in turn further increases the base to emitter voltage at the base of Q2. The voltage at the
collector of Q2 further decreases, which in turn further reduces the voltage at the base of Q1. This action
will continue till Q2 becomes fully saturated and Q1 becomes fully cutoff.
Thus the stable state of binary is such that one device remains in cut-off and other device
remains at saturation. It will be in that state until the triggering pulse is applied to it. It has two stable
states. For every transition of states triggering is required. At a time only one device will be conducting.
NEED OF COMMUTATING CAPACITORS (SPEED UP CAPACITORS):
It is desired that the transition should take place as soon as the trigger pulse is applied but such is
not the case.
When transistor is in active region it stores charge in its base and when it is in the
saturation region it stores even more charge. Hence transistor cannot come out of saturation to cut- off.
Until all such charges are removed. The interval during which conduction transfer one transistor to other
is called as the transition
Design Procedure:
RC = = = 1K
VB1 = +
57
-1.2 = (-15R1+0.2R2) /(R1+R2) ; given R1=10K
R2= 100K
Fmax= (R1+R2)/2C R1 R2 R 1=10K , R2 = 100K and C= 0.1F
= (10+100)X103/(2X0.3X10-6X10X100X106) = 55KHz
Procedure:
1. Make the connections as per the circuit diagram.
2. Apply trigger pulse of 1 KHz 5v (p-p) from function generator.
3. Obtain waveforms at different points such as VB1, VB2, VC1 & VC2.
4. Trace the waveform at collector and base of each transistor with the help of dual trace CRO. Note the
Time relation of waveforms.
Expected Waveforms:
Inference: Bistable Multivibrator is designed; and the waveforms are observed
Viva Questions:
1. What are the other names of Bistable Multivibrator?
2. What are the applications of a Bitable Multivibrator?
3. Describe the operation of commutating capacitors?
4. Commutating capacitors are also called as __ or __ .
5. What is the meaning of a stable state in a multi-vibrator?
6. Mention the names of different kinds of triggering used in the circuit shown?
7. What are the disadvantages of direct coupled Binary?
8. The diodes used in a bistable multivibrator to maintain a constant output swing are called __ diodes.
9. The interval during which conduction transfers from one transistor to another is called the __.
58
10. What are the coupling elements of a Bi-stable Multivibrator?

Design Projects
1. Design a fixed bias binary employing two n-p-n silicon transistor to operate max frequency of
16KHz, VCC=VBB=10V, IC(sat)=5mA, hfe(min)=30.
2. Design and verify the bistable multivibrator by using different triggering methods.
Outcomes: After finishing this experiment students are able to design Bistable Multivibrator and able to
explain its operation.
59
Experiment : 9
ADDITIONAL EXPERIMENT
SCHMITT TRIGGER
Pre-Lab:
1. Study the operation and working principle of Schmitt Trigger.

Objectives:
1. To design the circuit of Schmitt trigger with UTP=2.2V and LTP=1V.
2. To obtain square wave from sine wave.
3. To obtain UTP and LTP values practically
Apparatus:
1. CRO 0-20 MHz (Dual channel) - 1No.
2. Function generator 0- 1MHz - 1No.
3. Capacitor (0.1F) - 1 No.
4. Resistors (1k, 2.2K, 330) - 1 No. each
5. Resistor (1.2 K) - 3 No.
6. Transistor (BC 107) - 2 No.
7. Regulated Power supply 0-30 V (dual ) - 1 No.
8. Connecting wires
9. Bread board
Circuit diagram:
60
Theory:
In digital circuits fast waveforms are required i.e, the circuit remain in the active region for a
very short time (of the order of nano seconds) to eliminate the effects of noise or undesired parasitic
oscillations causing malfunctions of the circuit. Also if the rise time of the input waveform is long,
it requires a large coupling capacitor. Therefore circuits which can convert a slow changing
waveform (long rise time) in to a fast changing waveform (small rise time) are required. The
circuit which performs this operation is known as Schmitt Trigger.
In Schmitt trigger circuit, the output is in one of the two levels namely low or high. When
the input voltage is raising above the UTP (upper threshold point) i.e. V1, the output changes to high
level. Similarly when a falling output voltage passes through a voltage V 2 known as lower
threshold point (LTP), the output changes to low. The level of the output changes V1 is always greater
than V2.The differences of these two voltages is known as Hysteresis.
Design Procedure:
The voltage required to drive the transistor Q1 from CFF to CN is called upper trigger point.
UTP = V1 = V1 0.1
Where V1 = V = ( VCCR2)/ (R1+R2+RC1)
The voltage required to drive the transistor Q1 from ON to OFF is called lower trigger point.
LTP = V2= VBE(active)+ (V1-V2) .Re/(aRcth+Re)
Where Rcth =(RC1(R1+R2))/( R1+R2+RC1) a =R2/(R1+R2)
Choose BC107 transistor with hfe= 200
Let Vcc=12V, R1=2.2K , R2=1.2K
Set UTP = V1 0.1 2.2= V1 0.1 V1= 2.3V
But V1= (12X15)/(2.2+1.5+RC1) RC1=4.12K= 4K
Rcth = (4X 103(2.2+1.5))/(2.1+1.2+4.4K) = 1.97K
a= 0.3529
LTP =V2= VBE(active)+ (V1-V2) .Re/(aRcth+Re)
= 0.7+(2.3-0.6).330/(0.35X1.97K+330)
= 1.21V
VE=V1-VBE= 2.3-0.7 = 1.6V
IB2= VE/RE(1+hfe) = 1.6/330(1+200) = 0.0030A
IC2 = hfeIB2 =0.6V
When Vin < V2, output =1V
61
(VC-output)/IC2 = RC2 (12-1)/0.6 = RC2= 18.33
Procedure:
1. Connect the circuit diagram as shown in fig 4.1.

2. Apply a sine wave input of 15 Vp-p amplitude and 1 KHz frequency to the circuit
3. Observe the output voltage on CRO.
4. Obtain the output voltage at which LOW to HIGH transition occurs and measure the corresponding
input voltage. This input voltage is called UTP (Upper threshold point)
5. Now, Obtain the output voltage at which HIGH to LOW transition occurs and measure the
corresponding input voltage. This input voltage is called LTP (Lower threshold point).
6. Compare these practical values with theoretical values.
Expected Waveforms:
Fig.4.2 input & output waveforms of Schmitt Trigger
62
Inference: Schmitt trigger circuit with the given values is designed; and the response is observed.
Viva Questions:
1. What is Schmitt Trigger?

2. What are the applications of Schmitt Trigger?
3. Define hysteresis action?
4. Why Schmitt Trigger is called a squaring circuit?
5. Define UTP? Write its expression.
6. Define LTP? Write its expression.
7. What is the difference between a Binary and Schmitt Trigger?
8. How noise can be eliminated on a given signal using Schmitt Trigger?
9. Explain how a Schmitt Trigger converts a sine wave to a square wave?
10. A Schmitt trigger exhibits hysteresis when loop gain is ___.
Design Projects
1. Design Schmitt trigger circuit to get UTP=5V and LTP=7V for VCC=15V.
Outcomes: After finishing this experiment students are able to Design Schmitt trigger circuit using
transistor and they are able to find UTP and LTP.
63
Experiment 10
BOOT STRAP SWEEP CIRCUIT
Pre-Lab:
1. Study the operation and working principle of Boot-strap Sweep Circuit.

Objectives:
1. To design a Boot-strap Sweep Circuit.
2. To obtain a sweep wave form.
Components Required:
1. Resistors 100k , 5.6k , 10 K - 1 each

2. Capacitors 0.1 F, 10 F, 100 F - 1 each
3. IN4007 Diode 1 No.
4. 2N2369 Transistors 2 Nos.
5. Bread Board
Apparatus Required:
a. Power supply (0V-30V)

b. CRO(1Hz-20MHz)
c. Signal generator (1Hz-1MHZ)
d. Connecting Wires.
CIRCUIT DIAGRAM
64
THEORY:
The input to Q1 is the gating waveform. Before the application of the gating waveform, at t = 0,
transistor Q1 is in saturation. The voltage across the capacitor C and at the base of Q2 is VCE(sat). To ensure
Q1 to be in saturation for t = 0, it is necessary that its current be at least equal to ICE / hFE so that Rb < hfeR.
With the application of the gating waveform at t = 0, Q1 is driven OFF. The current IC1 now flow into C
and assuming units gain in the emitter follower V0 . When the sweep starts, the diode is reverse biased, as
already explained above, the current through R is supplied by C1. The current VCC / R through C and R
now flows from base to emitter of Q2.if the output V0 reaches the voltage VCC in a time TS / Tg, then
from above we have TS = RC.
PROCEDURE:
Connect the circuit as shown in figure.

Apply the square wave or rectangular wave form at the input terminals.
Connect the CRO at output terminals now plug the power card into line switch on and observe the
power indication.
As mentioned in circuit practical calculation. Observe and record the output waveforms from CRO
and compare with theoretical values.
EXPECTED WAVEFORMS :
Conclusion:
Conclusions can be made on sweep time Ts and retrace time TR and sweep voltage Vs of the sweep
waveform theoretically and practically and also made on if the output waveform of the Bootstrap are
identical with the theoretical wave forms or not.
VIVA QUESTIONS:
1. Define a Voltage time base generator, a current time base generator and a linear time base generator.
2. What is the relation between the slope error, displacement error and transmission error?
3. What are the various methods of generating time base wave-form?
65
4. Which amplifier is used in Boot-strap time base generator?

5. Which type of sweep does a bootstrap time-base generator produce?
6. What is the gain of the amplifier used in Bootstrap time base generator?
7. What is retrace time? Write the formula for the same for Bootstrap time base generator.
8. What is the formula for sweep amplitude in Bootstrap time base generator?
9. To have less flatness time of sweep signal, then the gate signal time has to be __.
10. A Bootstrap sweep circuit employs __ type of feedback.
Design problem:
1. Design Boot-strap Sweep Circuit with sweep amplitude of 8V, with sweep interval of 1ms neglect
2. Design Boot-strap Sweep Circuit with sweep amplitude of 15V, with sweep interval of 2ms neglect
Outcomes: After finishing this experiment students are able to Design Boot-strap sweep circuit and able
to generate a sweep voltage waveform.
66
Design Experiment
GENERATION OF DIFFERENT TYPES OF WAVEFORMS FROM BASIC SINUSOIDAL

WAVEFORM
67

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EC&PC lab manual Dept.

GEETHANJALI COLLEGE OF ENGINEERING AND

Cheeryal (V), Keesara (M), R. R. District

ELECTRONIC CIRCUITS AND PULSE CIRCUITS LAB

striving toward perfection

ELECTRONICS AND COMMUNICATION ENGINEERING

Lab Incharge: HOD-ECE:

EC lab: J. Mrudula Dr.P.Srihari

GEETHANJALI COLLEGE OF ENGINEERING & TECHNOLOGY

striving toward perfection

Prepared by: Checked by:

GEETHANJALI COLLEGE OF ENGINEERING AND TECHNOLOGY

(JNTU CODE -) A40484 Programme : UG

Branch: ECE Version No : 01

Year: II Updated on : 10/12/2014

Semester: II No. of pages :

Classification status (Unrestricted / Restricted ): Unrestricted

Distribution List :Department , Lab, Library, Lab incharge

Prepared by : 1) Name : Prof.K.Somasekhara rao (PC lab) 1) Name : M.Muthamma

Design : Dean of Academics

Name : J. Mrudula (EC lab)

3) Design : Associate professor 3) Design : Assistant Professor

4) Date : 26/11/15 4) Date :

Verified by : 1) Name :Prof. K. Somasekhara Rao * For Q.C Only.

3) Design : Professor 2) Sign :

Approved by : (HOD ) 1) Name : Dr. P.Srihari

Mission of the Department

i. To impart quality education in fundamentals of basic sciences, mathematics, electronics and

Program Educational Objectives of B. Tech (ECE) Program:

I. To prepare students with excellent comprehension of basic sciences, mathematics and

Program Outcomes of B.Tech ECE Program:

1. An ability to apply knowledge of Mathematics, Science, and Engineering to solve complex

Mapping of the Course Outcomes related to laboratory experiments with Program

The student will be power Amplifiers and Analog PO2,PO3,PO

11.Non-linear Able to extend and concept of clippers PO2,PO3,PO

12.Comparison Able to extend and Concept of basic Linear integrated PO2,PO3,PO

14.Design an An ability to The principles of Linear integrated PO2,PO3,PO

1. Two electronic circuits and FET. systems, Linear PO11,PO12

Instructions to Laboratory Teachers:-

PART- II PULSE CIRCUITS

SNO EXP.NAME PAGE NO

1. LINEAR WAVE SHAPING

LINEAR WAVE SHAPING

Prior to Lab session:

1. CRO (Dual Channel 0-20 MHz) - 1 No.

Resistors and Capacitors can be connected in series or parallel in various combinations.

High Pass RC circuit:

High - pass RC circuit as a differentiator:

The output voltage across R is, Vo = RC (dVi/dt).

Low Pass RC circuit:

Low Pass RC circuit as an integrator:

The output signal across C is

RC high pass circuit:

i) Large time constant: RC > > T :

RC low pass circuit: (Design procedure is same as RC high pass circuit)

ii) Medium time constant : RC = T, C = 0.01 f

iii) Short time constant : RC = T/10, C = 0.001 f

For a symmetrical square wave