A Comparison of Three-Level Converters Versus Two-Level Converters For Low-Voltage Drives, Traction, and Utility Applications
A Comparison of Three-Level Converters Versus Two-Level Converters For Low-Voltage Drives, Traction, and Utility Applications
A Comparison of Three-Level Converters Versus Two-Level Converters For Low-Voltage Drives, Traction, and Utility Applications
Abstract—This paper evaluates three-level topologies as alterna- converters. With the emerging need for higher switching fre-
tives to two-level topologies in converters for low-voltage applica- quencies in applications such as high-speed drives, a desire for
tions. Topologies, semiconductor losses, filter aspects, part count, smaller and lighter (filter) components in grid-connected and
initial cost, and life-cycle cost are compared for a grid interface, a
conventional drive application, and a high-speed drive application. traction converters, a three-level-based low-voltage converter
family appears to be one technologically attractive solution.
Index Terms—Life-cycle cost, multilevel converters, semicon- A first indication of a commercial interest was stated in [1]
ductor losses.
and [2]. References [3] and [4] explore the utilization of
high-volume automotive components to build cost-effective
I. INTRODUCTION three-level low-voltage drive converters. Reference [5] shows
the efficiency gains of three-level converters over two-level
T HE low-voltage power conversion market (nominal
line-to-line voltage up to 690 V (IEC); 575 V
(ANSI)) is almost exclusively satisfied by the conventional
converters in wind power applications with a high share of
partial load operation. A three-level converter technology is
two-level dc-voltage link hard-switching converter topology. discussed for three typical application cases. Insulated gate
Alternatives such as matrix converters or soft-switching con- bipolar transistor (IGBT) semiconductor losses and switching
verters have failed to penetrate this market. Technological frequency boundaries are discussed for state-of-the-art IGBT
progress has been slow, relying mainly on semiconductor technology. Initial cost and life-cycle cost comparisons will
device improvements and control intelligence refinements, as conclude the evaluation.
well as on better integration and packaging techniques.
In contrast, the medium-voltage power conversion market II. TOPOLOGIES
offers some diversity with the presence of a dc-current link
converter and various dc-voltage link multilevel converter struc- DC-voltage link multilevel converters were proposed in
tures. In particular, the multilevel converters became very suc- several configurations. The diode-clamped multilevel con-
cessful in the past decade. While the development of the multi- verter (DCMLC) [6], also known as the neutral-point-clamped
level structures was mainly driven by the limited semiconductor multilevel converter, the flying-capacitor multilevel converter
voltage blocking capability in conjunction with static and dy- (FCMLC) [6], also known as the imbricated cell converter, and
namic voltage-sharing concerns, it turned out that the multilevel the series-connected/cascaded multilevel converter (SCMLC)
topology offered some additional benefits. Among those are are distinguished [6]. A comparison of these topologies was
a superior harmonic spectrum for a given gate switching fre- presented in [6] and [7]. The common roots of DCMLC and
quency, a lower overvoltage stress at cables and end windings the FCMLC topologies were shown in [8]. It should be added
of transformers/motors, a lower common-mode voltage, and that the total semiconductor losses and the terminal voltage
substantially lower semiconductor switching losses. spectrum of a three-level diode-clamped converter and a
The objective of this paper is the evaluation of the poten- three-level flying-capacitor converter are exactly the same for
tial benefits of a three-level topology in low-voltage power any given operating point in terms of modulation index and
displacement angle. Unidirectional and partially bidirectional
converters as shown in [9] also feature exactly the same total
Paper IPCSD-04-075, presented at the 2003 Industry Applications Society semiconductor losses and terminal voltage spectrum if operated
Annual Meeting, Salt Lake City, UT, October 12–16, and approved for publica- within functional boundaries. Despite using different current
tion in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial
Power Converter Committee of the IEEE Industry Applications Society. Manu- paths, the device number and device types conducting during
script submitted for review March 1, 2004 and released for publication February each switching state and their duty cycles remain the same.
3, 2005. This work was supported by ABB Corporate Research, Germany. Only the distribution of the semiconductor losses among the
R. Teichmann is with GE Global Research, Niskayuna, NY 12309 USA
(e-mail: teichman@crd.ge.com). semiconductor modules is different. This assumes a comparable
S. Bernet is with the Fakultät IV Elektrotechnik und Informatik, Institut modulation technique, a neutral point clamp/auxiliary diode
für Energie- und Automatisierungstechnik, Fachgebiet Leistungselek- technology similar to that found in the inverse diodes of the
tronik, Technische Universität Berlin, D-10587 Berlin, Germany (e-mail:
steffen.bernet@tu-berlin.de). main switches, and disregards the influence of parasitic circuit
Digital Object Identifier 10.1109/TIA.2005.847285 elements.
0093-9994/$20.00 © 2005 IEEE
856 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 3, MAY/JUNE 2005
TABLE I
IGBT LOSS DATA FOR MITSUBISHI (PT-IGBT) AND EUPEC (NPT-IGBT) DEVICES [10],[11]
TABLE II
SEMICONDUCTOR LOSS CHARACTERISTICS AND COEFFICIENTS
losses are attributed to devices being in the on-state. Switching passive device turn-off loss energy;
losses are distributed to the devices involved in a commutation instantaneous commutation voltage;
whenever a state transition takes place. The losses during the device manufacturer’s test voltage;
sampling period and the switching loss energies were calculated instantaneous device current;
by sampling period;
curve-fitting parameter.
On-state voltages and loss energies as a function of the de-
(1)
vice current for the IGBT and diode were obtained from man-
(2) ufacturer data sheets [11], [12]. The curve-fitting parameters
are summarized in Table II. For simplicity, the variation of the
(3)
semiconductor losses as a function of junction temperature is
neglected; the values specified for a junction temperature of
(4) C were assumed. Details of the semiconductor loss
evaluation tool can also be found in [13] and [14]. For the semi-
(5) conductor loss and switching frequency boundary evaluation the
converters were assumed to be operated in steady state at a con-
where stant case temperature of C and a maximum junction
active device on-state loss energy in sampling period; temperature of C.
passive device on-state loss energy in sampling Fig. 3 shows the total semiconductor losses in a three-phase
period; two- and three-level inverter as a function of device technology
active device turn-on loss energy; (PT, NPT, trench/conventional, fast/low ) and carrier fre-
active device turn-off loss energy; quency at one operating point ( V, ,
858 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 3, MAY/JUNE 2005
B. Load Current
The magnitude of the load current in relation to the device
current rating has a substantial influence on the switching fre-
quency above which the three-level converter becomes superior.
This crossover switching frequency is shifted to lower values as
the load current becomes smaller. This is due to the fact that
on-state losses decline faster ( quadratic dependency) than
switching losses ( linear dependency) with falling device cur-
rent and both loss categories are of roughly the same magni-
tude. Fig. 4 shows an equi-loss line (identical semiconductor
losses of two- and three-level converters) of a dc/ac inverter
( V, , , A) as a func-
tion of the load current. For any given load current, switching
frequencies above the lines are preferably implemented with a
three-level converter. Most converters are typically operated in
Fig. 4. Equi-loss line (two-level/three-level converter) as a function of load
current and parameter semiconductor technology (sine-triangle modulation with a load range between 0.4–0.7 per unit. A three-level topology
added third harmonic, m = 0:95, V = 700 V, DPF = 0:9, I = 147 A). therefore becomes a very attractive solution for switching fre-
quencies as low as – kHz.
, A). Both 1200- and 600-V modules C. Modulation Depth, Displacement Power Factor
have the same nominal current rating. A device developed for
fast switching operation (FF200R12KS4, mJ, A variation of the modulation depth and the terminal dis-
mJ, V at A) was included for com- placement angle changes the total semiconductor losses and
parison purposes. loss distribution among active and passive semiconductors.
Despite the higher conduction losses (two devices in current Figs. 5–8 depict the loss characteristics with the acronyms
path) the three-level topology quickly features lower total PconD, PconT, PonT, PoffT, and PoffD describing diode con-
semiconductor losses than conventional and fast IGBTs in duction losses, IGBT conduction losses, IGBT turn-on losses,
a two-level topology as the switching frequency increases. At IGBT turn-off losses, and diode turn-off losses, respectively.
this operating point the three-level topology features fewer total In a two-level converter feeding a three-phase balanced load
semiconductor losses at switching frequencies above 4/5 kHz the losses of all diode chips are the same and the losses of all
for trench-gate PT as well as planar NPT IGBTs. Clearly, IGBT chips are the same [15], [16]. Fig. 5 shows that the total
the recent introduction of the trench-gate technologies shifts conduction losses vary with the displacement power factor with
this crossover point to smaller switching frequencies in favor maximum conduction losses in the IGBT and the inverse diodes
of the three-level converter. Some of the loss curves are not at and , respectively. The switching losses
extended to the upper switching frequency range, indicating of each individual chip are not affected by the displacement
that the losses cannot be dissipated from the device within power factor. References [15] and [16] have shown that the con-
the thermal specifications ( C, C). duction losses of the IGBT chips increase almost linearly with
TEICHMANN AND BERNET: COMPARISON OF THREE-LEVEL CONVERTERS VERSUS TWO-LEVEL CONVERTERS 859
Fig. 7. Semiconductor loss distribution of three-level converter in inverter decline. The influence of different continuous and discontinuous
mode as function of modulation index (sine-triangle modulation with added PWM schemes on the losses of a three-level DCMLC was dis-
third harmonic, V = 400 V, V = 700 V, DPF = 0:9, T = 125 C,
I = 147 A, f = 10 kHz, 6 2
IGBT: CM200DU12F).
cussed in [17].
B. Filter
Transient overvoltages caused by the pulsewidth-modu-
lation (PWM) switching operation are a major concern for
transformers/generators/motors connected with long cables.
The overvoltage phenomenon due to fast switching transients
(high ) in long cables has been discussed in several
papers [19]–[26]. The overvoltage at the machine/transformer
terminals is caused by a reflection of the voltage pulse of the
inverter due to a mismatch in load and cable surge impedance.
If the voltage pulse takes longer than one-third of the voltage
VI. EVALUATION OF PACKAGING AND CONTROLS
rise time to travel from the inverter to the machine/transformer
a full reflection will occur at the machine/transformer terminals A. Packaging
and the voltage pulse amplitude will approximately double
[22]. A 50% reduction in the pulse magnitude in the three-level The design of the packaging is highly application dependent.
converter will obviously reduce the overvoltage stress at the Until higher production volumes justify an integration of com-
load terminals in a design without additional filter. plete converter legs, the three-level topology requires at least the
The drastically reduced switching losses of the three-level additional NPC diode modules. In cases where single 1.2-kV
converter can also be used to reduce the using the IGBT modules can be replaced by a dual 600-V module (typically,
gate units. A potential avoidance of the filter at the con- when device current rating is set by thermal considerations) the
verter terminals may justify the increased switching losses. main switch arrangement must not be modified.
Specifically for an introduction of a three-level converter into
C. AC Filter a dc/ac converter with 1.2-kV IGBTs, the arrangement of the
dc-link capacitors must not be modified. Other voltage levels
The high-frequency content in the terminal voltage of the
require a re-design of the dc capacitor arrangement (Table III).
three-level converter is substantially smaller due to the three-
The total size and weight of the converter will certainly ben-
level characteristic with an effective commutation voltage of
efit from the smaller cooling unit and smaller passive compo-
50% of that of the two-level converter. The resulting harmonic
nents. In certain applications a transition of the cooling method
currents are reduced by the same factor [24]. Because the high-
to simpler convection cooling might reduce maintenance efforts
frequency losses are a function of the square of the high-fre-
and increase reliability.
quency content of the current, the application of a three-level
converter at a given inductance, i.e., motor/generator, will re-
sult in substantially smaller losses. Alternatively, the ac filter B. Sensors/Controls
inductance can be smaller/less heavy for a three-level topology The number of dc-link voltage sensors, in some cases as
to meet a given specification in terms of voltage or current har- simple as a resistive divider, is increased by a factor of two.
monics. The number of -processors remains the same. For example,
Specifically, for a three-phase system with a modulation the widely used fixed-point TMS320F24x series offers between
scheme without a phase difference in the carrier signals, the 7–16 dedicated PWM channels. An additional benefit exists
carrier switching frequency is a common-mode signal and for larger manufacturers that can reuse their medium-voltage
is not present in the line-to-line voltages. Only the typically converter control platform, producing a unified control platform
smaller side bands around the switching frequency need to be for low- and medium-voltage converters.
attenuated, additionally reducing filter size and losses. The stabilization of the center point potential in the three-
level diode-clamped converter imposes one additional control
D. DC Filter criteria. Control of the dc-link center point can be achieved un-
Two- and three-level converters show ripple current com- less the converter is operated in overmodulation [26], [27]. Un-
ponents on the dc side at side bands that are centered around doubtedly, the biggest disadvantage of the three-level converter
the switching frequency. The three-level converter additionally is the higher number of gate units with its accompanying isola-
shows a third harmonic (and other triplen harmonics) at the dc tion requirements. The number of gate drivers must be increased
side [25]. The three-level converter requires a dc-link center by a factor of two. However, since each gate unit is subject
point management. Despite the fact that these points are intrin- to only half the switching frequency on average, the total gate
sically stable, device asymmetries and variations in component drive power remains the same. Simplified gate drive units for
values will offset this balance. three-level structures were presented in [4].
TEICHMANN AND BERNET: COMPARISON OF THREE-LEVEL CONVERTERS VERSUS TWO-LEVEL CONVERTERS 861
A. Grid Converter
Grid converters operate in rectifier and inverter mode
depending on the application. Both types of operation are
characterized by a relatively constant modulation index and
power factor. Variations are to be expected in the current due
to varying load conditions. Typical mains frequencies are Fig. 11. Total semiconductor losses during grid operation of converter (V =
50/60 Hz. Certain utility interconnect requirements regarding 750 V, f = 8 kHz, m = 0:85, DPF = 0:98=00:98, T = 125 C, 3 2
the current quality and the behavior during grid irregularities
CM200DU24F, 6 2 CM200DU12F).
must be fulfilled, e.g., IEEE 519-1992. A switching frequency
between 2–4 kHz is typically chosen at this power level, which For a switching frequency of kHz, the semiconductor
has traditionally been regarded as a good compromise between losses are displayed in Fig. 11. In this case, the three-level con-
filter size/losses and converter efficiency. verter is clearly superior in both applications over the entire load
The following parameters were set for the purpose of the range. For both rectifier and inverter operation the loss savings
evaluation of a grid-connected load and a grid-connected gen- amount to roughly 50%–55% and 25% at 0.2 and 1 p.u., respec-
eration unit: kVA, V, V, tively. It should be noted that the two-level converter cannot be
, and kHz. Fig. 10 depicts the operated at a switching frequency of kHz and the thermal
semiconductor losses of the two- and three-level converter as a requirements of C and C with the
function of the load current for the PT trench-gate technology MITSUBISHI 200-A devices. In contrast, the three-level con-
and a switching frequency of kHz. While for inverter op- verter can be operated with the 200-A devices up to a switching
eration the three-level converter is superior over the entire load frequency of 28 and 10 kHz in inverter and rectifier mode, re-
range, in rectifier mode the three-level converter is superior up spectively.
to a load current of about 0.8 p.u. at this switching frequency. An LCL filter is designed to meet grid current quality criteria
The loss savings amount to roughly 30%–35% at 0.2 p.u. current set forth in the recommendations of IEEE 519-1992. The design
for both rectifier and inverter operation. During rectifier opera- rules are outlined in [16]. In order to attenuate the switching
tion at rated load the losses of the three-level converter are 8% harmonics below the limits required, the inductance values and
higher than that for the two-level converter. filter capacitor values (Y-connected) as shown in Table IV are
862 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 3, MAY/JUNE 2005
TABLE IV
FILTER INDUCTANCE VALUES
TABLE V
COMPONENT COST ANALYSIS
load for both rectifier and inverter operation. This indicates that 5) Substantial reductions in filter size/weight and cost (
substantial cost savings can be achieved throughout the entire 30%) are possible due to the lower voltage harmonics
product life cycle. Even if the initial costs of the three-level in the three-level converter.
converter are slightly above those of the two-level converter 6) Reliability concerns can be mitigated by adequate design
the three-level converter is paying off in high energy price choices. The reduction of semiconductor losses will re-
markets like Japan. At a switching frequency of kHz, duce the average temperature at the components and, thus,
the application of the three-level converter is also justified decrease the failure rate.
in all markets due to the higher initial semiconductor cost 7) The three-level converter is economically viable in high-
in comparison to the two-level converter which needs 400-A energy-cost markets, even at low switching frequencies.
devices. Note that potential loss savings in the filter and the
machine are not yet included. The same statement is valid for REFERENCES
the conventional converter driving an induction machine. A [1] T. Tanaka. (2003) Yaskawa Tech. Rev. (Special Issue on Inverter Drive).
filter will, if needed, improve the cost balance in favor [Online] Available: http://www.yaskawa.co.jp/en/technology/gihou/65-
2/t01.htm
of the three-level converter. The utilization of a three-level [2] A. Buente, T. Oezgen, and T. Ortmann, “Dreipunkt-wechselrichter fuer
topology for high-speed drives and other high-switching-fre- hochgeschwindigkeitsantriebe,” in Conf. Rec. PCIM Europe, Nurem-
berg, Germany, 2003.
quency applications is recommended due to significant cost [3] B. A. Welchko, M. B. R. Correa, and T. A. Lipo, “A cost effective three-
reduction in both initial and operating costs. level MOSFET inverter for low power drives,” in Proc. IEEE IECON’02,
vol. 2, 2002, pp. 1267–1272.
[4] S. Park and T. M. Jahns, “A self-boost charge pump topology for a
gate drive high-side power supply,” in Proc. CPES Seminar, 2002, pp.
267–272.
X. CONCLUSION [5] O. Al-Naseem, R. W. Erickson, and P. Carlin, “Prediction of switching
loss variations by averaged switch modeling,” in Proc. IEEE APEC’00,
Three-level topologies are highly attractive for low-voltage vol. 1, 2000, pp. 242–248.
[6] Y. Shakweh and E. A. Lewis, “Assessment of medium voltage PWM
power converters, specifically for applications with medium to VSI topologies for multi-megawatt variable speed drive applications,”
high switching frequencies. in Proc. IEEE PESC’99, vol. 2, 1999, pp. 965–971.
[7] R. Teodorescu, R. Blaabjerg, and J. K. Pedersen, “Multi-level converters
1) The difference in switching loss energies between IGBTs – A survey,” in Conf. Rec. EPE’99, 1999, pp. 408–418.
of the same current class and commonly adjacent voltage [8] F. Z. Peng, “A generalized multilevel inverter topology with self voltage
classes is a factor of 3–5. This is the key device character- balancing,” in Conf. Rec. IEEE-IAS Annu. Meeting, vol. 3, 2000, pp.
2024–2031.
istic enabling low switching losses. [9] K. A. Corzine, J. R. Baker, and J. Yuen, “Reduced parts-count multi-
2) Due to the specific correlation of switching and conduc- level rectifiers,” in Conf. Rec. IEEE-IAS Annu. Meeting, vol. 1, 2001,
tion losses with load current, a three-level topology is su- pp. 589–596.
[10] (2000) IGBT Datasheet. IXYS Corp. [Online]. Available: www.ixys.com
perior in terms of total semiconductor losses at switching [11] (2000) IGBT Data Sheets: BSM200GB120DLC, BSM200GB06DLC,
frequencies as low as and beyond 2–3 kHz in practical FF200R12KS4, FF200R12KE3, FF200R17KE3. EUPEC Corp. [On-
applications. At switching frequencies above 5 kHz, the line]. Available: www.eupec.com
[12] (2000) IGBT Data Sheets: CM200DU24F, CM200DU12F. MIT-
three-level converter always features lower losses. SUBISHI Corp. [Online]. Available: www.mitsubishichips.com
3) Compared to the two-level converter, the three-level con- [13] F. Blaabjerg, U. Jaeger, S. Munk-Nielsen, and J. K. Pedersen, “Power
verter enables substantially higher switching frequencies losses in PWM-VSI inverter using NPT or PT IGBT devices,” IEEE
Trans. Power Electron., vol. 10, no. 3, pp. 358–367, May 1995.
( 4 ) applying devices of the same technology and cur- [14] R. Teichmann, “Auxiliary resonant commutated pole converters,” Ph.D.
rent class in both converters. dissertation, Dept. elect. Eng. Inf. Technol., Dresden Univ. Technol.,
4) The introduction of low on-state voltage trench-gate Dresden, Germany, 2002.
[15] S. Bernet and R. Teichmann, “Potential and risks of the matrix converter
IGBTs has a higher leverage effect on three-level con- for modern AC-drives,” in Conf. Rec. COBEP, Belo Horizonte, Brazil,
verters than on two-level converters. 1997, pp. A1–A10.
TEICHMANN AND BERNET: COMPARISON OF THREE-LEVEL CONVERTERS VERSUS TWO-LEVEL CONVERTERS 865
[16] S. Bernet, S. Ponnaluri, and R. Teichmann, “Design and loss compar- Ralph Teichmann received the MS. and Ph.D.
ison of matrix converters and voltage source converters for modern AC degrees in electrical engineering from Dresden
drives,” IEEE Trans. Ind. Electron., vol. 49, no. 2, pp. 304–314, Apr. University, Dresden, Germany, in 1997 and 2002,
2002. respectively.
[17] T. Brückner and D. G. Holmes, “Optimal pulse width modulation He was a Visiting Student at the University of Wis-
for three-level inverters,” in Proc. IEEE PESC’03, vol. 1, 2003, pp. consin, Madison, in 1995–1996 and a Research As-
165–170. sistant at Nagasaki University, Japan, in 1998–1999.
[18] K. R. M. N. Ratnayake and Y. Murai, “A novel PWM scheme to elim- Since 1997, he has been an independent consultant
inate common mode voltage in three-level voltage source inverter,” in for various companies, including ABB Corporate Re-
Proc. IEEE PESC’98, vol. 1, 1998, pp. 269–274. search and Philips Medical Systems. He is currently
[19] E. Persson, “Transient effects in applications of PWM inverters to in- with GE Global Research, Niskayuna, NY. His re-
duction motors,” IEEE Trans. Ind. Appl., vol. 28, no. 5, pp. 1095–1101, search interests include high-power conversion, renewable energies, distributed
Sep./Oct. 1992. generation, hard- and soft-switching converter topologies, as well as converter
[20] P. van Poucke, R. Belmans, W. Geysen, and E. Ternier, “Over-voltages in controls.
inverter fed induction machines using high frequency power electronics Dr. Teichmann has been the recipient of several awards, including two schol-
components,” in Proc. IEEE APEC’94, vol. 1, 1994, pp. 542–548. arships, one industrial fellowship, an IEEE paper award, and a German electrical
[21] A. H. Bonnett, “Analysis of the impact of pulse-width modulated in- engineering society publication award.
verter voltage waveforms on AC induction motors,” IEEE Trans. Ind.
Appl., vol. 32, no. 2, pp. 386–392, Mar./Apr. 1996.
[22] A. von Jouanne, D. Rendusara, P. Enjeti, and W. Gray, “Filtering tech-
niques to minimize the effect of long motor leads on PWM inverter fed
AC motor drive systems,” IEEE Trans. Ind. Appl., vol. 32, no. 4, pp.
919–926, Jul./Aug. 1996. Steffen Bernet (M’97) was born in Ilmenau, Ger-
[23] P. T. Finlayson, “Output filters for PWM drives with induction motors,” many, in 1963. He received the Diploma degree
IEEE Ind. Appl. Mag., vol. 4, no. 1, pp. 46–52, Jan./Feb. 1998. from Dresden University of Technology, Dresden,
[24] P. Guggenbach, “Pulse removal in sinusoidal PWM with constant Germany, in 1990, and the Ph.D. degree from the Il-
switching frequency to reduce switching frequency or current har- menau University of Technology, Ilmenau, Germany,
monics,” in Proc. IEEE PESC’98, 1998, pp. 294–301. in 1995, both in electrical engineering. The subject
[25] F. Jenni and D. Wuest, Steuerverfahren Fuer Selbstgefuehrte Strom- of his Ph.D. dissertation was the investigation of
richter. Zurich, Switzerland: vdf Hochschulverlag Zurich, 1995. power semiconductors in soft-switching converters.
[26] S. Ogasawara and H. Akagi, “Analysis of variation of neutral point po- He was a Development Engineer in the Depart-
tential in neutral point clamped voltage source PWM inverters,” in Conf. ment of Private Communication Systems at Siemens
Rec. IEEE-IAS Annu. Meeting, 1993, pp. 965–970. from 1994 to 1995. During 1995 and 1996, he was
[27] C. Newton and M. Summer, “Neutral point control for multi-level a Postdoctoral Researcher in the Electrical and Computer Engineering Depart-
inverters: Theory, design, and operational limitations,” in Conf. Rec. ment, University of Wisconsin, Madison. In 1996, he joined ABB Corporate Re-
IEEE-IAS Annu. Meeting, 1995, pp. 2451–2458. search, Heidelberg, Germany, where he led several strategic power electronics
[28] O. V. Thorsen and M. Dalva, “A survey of the reliability with an analysis and drives research projects for low-voltage and medium-voltage applications.
of faults on variable frequency drives in industry,” in Conf. Rec. EPE’95, He led the Electrical Drives Group at ABB Corporate Research from 1998 to
1995, pp. 1033–1038. 2001. From 1999 to 2000, he was responsible for ABB research worldwide in
[29] J. J. Stroker, “What is the real cost of higher efficiency,” IEEE Ind. Appl. the areas of power electronic systems, electric drives, and electric machines. In
Mag., vol. 9, no. 3, pp. 32–37, May/Jun. 2003. 2001, he joined the Berlin University of Technology, Berlin, Germany, as a Pro-
[30] (2004). Austerlitz Electronic GmbH. [Online]. Available: www.auster- fessor of Power Electronics. His main research areas are high-power converter
litz-electronic.de topologies, power semiconductors, and motor drives.