Lovely Professional University, Punjab

Course Code Course Title Course Planner Lectures Tutorials Practicals Credits
ECE425 ADVANCED DIGITAL SYSTEM DESIGN 15929::Abhinav Vishnoi 3.0 0.0 0.0 3.0
Course Category Courses with numerical and conceptual focus

TextBooks
Sr No Title Author Edition Year Publisher Name
T-1 AN ENGINEERING APPROACH WILLIAM I. FLETCHER 11th 2002 2. PRENTICE HALL
TO DIGITAL DESIGN
Reference Books
Sr No Title Author Edition Year Publisher Name
R-1 DIGITAL DESIGN MORRIS MANO 5th 2013 PEARSON EDUCATION
R-2 DIGITAL SYSTEM DESIGN USING CHARLES H. ROTH, JR., 2nd 2008 THOMSON
VHDL LIZY KURIAN JOHN
R-3 VERILOG HDL, A GUIDE TO SAMIR PALNITKAR 2nd 2006 PHI (PRETICE HALL INDIA)
DIGITAL DESIGN AND
SYNTHESIS

Other Reading

Sr No Journals articles as Compulsary reading (specific articles, complete reference)

OR-1 Switching and Finite Automata by Zvi Kohavi ,
OR-2 Digital Fundamentals (10th Edition) by Thomas L. Floyd ,
OR-3 Low-Power and Area-Efficient Carry Select Adder- IEEE transaction on VLSI ,

Relevant Websites
Sr No (Web address) (only if relevant to the course) Salient Features
RW-1 http://nptel.iitm.ac.in/video.php?subjectId=117105080 lectures on DSD

RW-2 http://www.nptel.iitm.ac.in/video.php?subjectId=106105083 video lectures on fsm

LTP week distribution: (LTP Weeks)

Weeks before MTE 7
Weeks After MTE 7
Spill Over 3

Detailed Plan For Lectures

Week Lecture Broad Topic(Sub Topic) Chapters/Sections of Other Readings, Lecture Description Learning Outcomes Pedagogical Tool Live Examples
Number Number Text/reference Relevant Websites, Demonstration/
books Audio Visual Aids, Case Study /
software and Virtual Images /
Labs animation / ppt
etc. Planned
Week 1 Lecture 1 Review of Digital R-1: 4.1-4.3 knowledge of basic students will learn to Xillinx tool and Digital watch
Fundamentals(Introduction gates like and ,or ,not make a basic digital Discussion with the
to combinational and ,nand ,hexa decimal design of forming capability of
sequential circuits) number system ,binary SOP form and POS showing
number representation form of any function humidity,
using basic gates pressure along
with time.
Lecture 2 Review of Digital R-1: 4.1-4.3 knowledge of basic students will learn to Xillinx tool and Digital watch
Fundamentals(Introduction gates like and ,or ,not make a basic digital Discussion with the
to combinational and ,nand ,hexa decimal design of forming capability of
sequential circuits) number system ,binary SOP form and POS showing
number representation form of any function humidity,
using basic gates pressure along
with time.
Lecture 3 Review of Digital T-1: 4.3-4.5 adders used in digital students will learn to Xillinx tool and
Fundamentals(Full Adder design ,the design steps make combinational Discussion
and Half Adder) of half adder like the circuits using adders
truth table ,logic
diagram ,internal design
of making full adder
using two half adders
Review of Digital T-1: 4.3-4.5 knowledge of digital students will learn to Xillinx tool and
Fundamentals(Half circuits using half design digital circuits Animation
subtractor and full subtractor and full using subtractors
subtractor) subtractor and
implementing digital
signal subtraction using
half subtractors
Review of Digital T-1: 4.3-4.5 knowledge of processing students will learn to Xillinx tool and
Fundamentals(MUX and various digital signals design functions Brain Storming
DEMUX) using multiplexer ,using using multiplexer
the design of
multiplexer and
demultiplexer in digital
communication
Week 2 Lecture 4 Review of Digital T-1: 4.3-4.5 knowledge of processing students will learn to Xillinx tool and
Fundamentals(MUX and various digital signals design functions Brain Storming
DEMUX) using multiplexer ,using using multiplexer
the design of
multiplexer and
demultiplexer in digital
communication
Week 2 Lecture 4 Review of Digital T-1: 4.3-4.5 knowledge of digital students will learn to Xillinx tool and
Fundamentals(Half circuits using half design digital circuits Animation
subtractor and full subtractor and full using subtractors
subtractor) subtractor and
implementing digital
signal subtraction using
half subtractors
Review of Digital T-1: 4.3-4.5 adders used in digital students will learn to Xillinx tool and
Fundamentals(Full Adder design ,the design steps make combinational Discussion
and Half Adder) of half adder like the circuits using adders
truth table ,logic
diagram ,internal design
of making full adder
using two half adders
Lecture 5 Review of Digital T-1: 4.5-4.6 implementing a digital design decoder and Xillinx tool and
Fundamentals(Decoder and function using decoder encoder as a part of Virtual lab
Encoder) and a or gate by using digital
the truth table of communication will
decoder be learnt
Review of Digital T-1: 4.6 knowledge of designing students will learn to Xillinx tool and
Fundamentals(Code code converters like use basic gates to Brain Storming
Converters) BCD to excess-3 ,binary implement various
to grey code conversion code converters
using basic gates
Review of Digital R-1:1.6 knowledge of basic students will learn to Xillinx tool and
Fundamentals(Types of sequential circuits using implement digital Discussion
Traditional FlipFlops) latches and flip flops,the design with feedback
characteristic table of sr
latch ,jk flip
flop,excitation table of
all flip flops
Review of Digital R-2: 1.10 implement set up time students will learn to Xillinx tool and
Fundamentals(Practical and hold time in digital implement timing Brain Storming
Clocking Aspects) circuits and design constraints of the
timers clock signal
Lecture 6 Review of Digital T-1: 5.14 basic operation of latch students will learn the Xillinx tool and
Fundamentals(The D Latch and D flip usage of d flip flop Discussion
Flip-Flop) flop,characteristic table
,logic diagram of d flip
flop
Review of Digital T-1: 5.14 Basic operation of JK students will learn the Xillinx tool and
Fundamentals(Clocked JK flip flop and T flip operation of JK flip Discussion
and T Flip-Flop) flop,their characteristic flop and thier usage
table ,excitation table as counter
and converting jk flip
flop to t flip flop
Week 2 Lecture 6 Review of Digital T-1: 6.15-6.18 implementing serial Design of various Brain Storming
Fundamentals(Shift and parallel shift shift registers using d and Discussion
Registers) registers using D flip flip flop
flop characteristic
equation
Review of Digital T-1: 6.12-6.15 implementation of students will learn to Xillinx tool and
Fundamentals(Counters) ripple counter ,johnson design ripple counter Brain Storming
counter using the ,johnson counter
excitation table of jk flip using t flip flop and
flop jk flip flop
Week 3 Lecture 7 Review of Digital T-1: 6.12-6.15 implementation of students will learn to Xillinx tool and
Fundamentals(Counters) ripple counter ,johnson design ripple counter Brain Storming
counter using the ,johnson counter
excitation table of jk flip using t flip flop and
flop jk flip flop
Review of Digital T-1: 6.15-6.18 implementing serial Design of various Brain Storming
Fundamentals(Shift and parallel shift shift registers using d and Discussion
Registers) registers using D flip flip flop
flop characteristic
equation
Review of Digital T-1: 5.14 Basic operation of JK students will learn the Xillinx tool and
Fundamentals(Clocked JK flip flop and T flip operation of JK flip Discussion
and T Flip-Flop) flop,their characteristic flop and thier usage
table ,excitation table as counter
and converting jk flip
flop to t flip flop
Review of Digital T-1: 5.14 basic operation of latch students will learn the Xillinx tool and
Fundamentals(The D Latch and D flip usage of d flip flop Discussion
Flip-Flop) flop,characteristic table
,logic diagram of d flip
flop
Lecture 8 Basics of verilog R-3: 1.4 3.1-3.2 Knowledge of basic student will learn Xillinx tool and
programming(lexical syntax in verilog how to write a Discussion
conventions) programming,writing comment and the
comments and variable other basic rules of
declarations verilog programming
L8 is reserved for
contingency
Basics of verilog R-3: 1.4 3.1-3.2 knowledge of basic student will learn the Xillinx tool and
programming(Need of HDL) hardware description history of HDL and Discussion
languages like VHDL, the requirement of
and comparison of these HDL
languages with c
language
Lecture 9 Basics of verilog R-3: 1.4 3.1-3.2 knowledge of basic student will learn the Xillinx tool and
programming(Need of HDL) hardware description history of HDL and Discussion
languages like VHDL, the requirement of
and comparison of these HDL
languages with c
language
Week 3 Lecture 9 Basics of verilog R-3: 1.4 3.1-3.2 Knowledge of basic student will learn Xillinx tool and
programming(lexical syntax in verilog how to write a Discussion
conventions) programming,writing comment and the
comments and variable other basic rules of
declarations verilog programming
L8 is reserved for
contingency
Week 4 Lecture 10 Basics of verilog R-3:3.2 and 4.2 Knowledge of various students will learn Xillinx tool and
programming(Data types) data types like integers how to declare Discussion
and characters used in various variables as
verilog programming integers and
characters
Basics of verilog R-3:3.2 and 4.2 knowledge of starting a students will learn Xillinx tool and
programming(Modules and program using with file how to start a file Discussion
ports) name and ports and name and how to
saving the file with declare the variables
required extensions along with a file
name
Lecture 11 Quiz,Test1
Lecture 12 Basics of verilog R-3:5.1-5.2 knowledge of students will learn to Xillinx tool and
programming(Gate-level implementing a digital implement half adder Brain Storming
Modeling) designs like multiplexer ,full adder
adder using gate level ,multiplexer designs
mmodelling using gate level
modelling
Basics of verilog R-3:5.1-5.2 knowledge of various students will learn to Xillinx tool and
programming(Timing and delay associated with implement Brain Storming
delays) gate level modelling combinational
circuits using gate
level modelling along
with delay
Week 5 Lecture 13 Basics of verilog R-3:5.1-5.2 knowledge of various students will learn to Xillinx tool and
programming(Timing and delay associated with implement Brain Storming
delays) gate level modelling combinational
circuits using gate
level modelling along
with delay
Basics of verilog R-3:5.1-5.2 knowledge of students will learn to Xillinx tool and
programming(Gate-level implementing a digital implement half adder Brain Storming
Modeling) designs like multiplexer ,full adder
adder using gate level ,multiplexer designs
mmodelling using gate level
modelling
Lecture 14 Basics of verilog R-3:5.1-5.2 knowledge of students will learn to Xillinx tool and
programming(Gate-level implementing a digital implement half adder Brain Storming
Modeling) designs like multiplexer ,full adder
adder using gate level ,multiplexer designs
mmodelling using gate level
modelling
Week 5 Lecture 14 Basics of verilog R-3:5.1-5.2 knowledge of various students will learn to Xillinx tool and
programming(Timing and delay associated with implement Brain Storming
delays) gate level modelling combinational
circuits using gate
level modelling along
with delay
Lecture 15 Behavioural and Dataflow R-3:6.3-6.4 Knowledge of various students will learn to Xillinx tool and
Modelling(Operators in operators which are used use various operators white board
verilog) in dataflow modelling such as conditional ,
bitwise etc in
dataflow modelling
Week 6 Lecture 16 Behavioural and Dataflow R-3:6.2 and 7.3 knowledge of students will learn to Xillinx tool and
Modelling(Timing implementation of delay introduce delay brain storming
constraints in in dataflow modelling during dataflow
dataflow modelling) modelling of any
design
Behavioural and Dataflow R-3:6.2 and 7.3 Knowledge of various students will learn to Xillinx tool and
Modelling(Timing controls representations of delay introduce delay with white board
in behavioural modelling) in dataflow modelling various representions
in dataflow
modelling
Lecture 17 Behavioural and Dataflow R-3:6.2 and 7.3 Knowledge of various students will learn to Xillinx tool and
Modelling(Timing controls representations of delay introduce delay with white board
in behavioural modelling) in dataflow modelling various representions
in dataflow
modelling
Behavioural and Dataflow R-3:6.2 and 7.3 knowledge of students will learn to Xillinx tool and
Modelling(Timing implementation of delay introduce delay brain storming
constraints in in dataflow modelling during dataflow
dataflow modelling) modelling of any
design
Lecture 18 Behavioural and Dataflow R-3:7.6 Knowledge of for loop design of digital Xillinx tool and
Modelling(Loops in ,while loop using circuit using various brain storming
behavioural modelling) behavioural modelling loops in behavioural
modelling
Week 7 Lecture 19 Behavioural and Dataflow R-3:7.6 Knowledge of for loop design of digital Xillinx tool and
Modelling(Loops in ,while loop using circuit using various brain storming
behavioural modelling) behavioural modelling loops in behavioural
modelling
Lecture 20 Behavioural and Dataflow R-3:7.6 features of behavioural students will learn to Xilinx tool and
Modelling(Blocking and non modelling like blocking write blocking and white board
blocking assignment) and non blocking non blocking
assignment assignment in
L19 is reserved for behavioural
contingency modelling
Behavioural and Dataflow R-3:7.2 and 7.7 various ways of writing programming in Xilinx tool and
Modelling(Sequential and behavioural modelling behavioural brain storming
parallel blocks) modelling
Week 7 Lecture 21 Behavioural and Dataflow R-3:7.2 and 7.7 various ways of writing programming in Xilinx tool and
Modelling(Sequential and behavioural modelling behavioural brain storming
parallel blocks) modelling
Behavioural and Dataflow R-3:7.6 features of behavioural students will learn to Xilinx tool and
Modelling(Blocking and non modelling like blocking write blocking and white board
blocking assignment) and non blocking non blocking
assignment assignment in
L19 is reserved for behavioural
contingency modelling

MID-TERM
Week 8 Lecture 22 Switch Level Modelling R-3:11.1 knowledge of PMOS students will learn to Xillinx tool and
And Primitives(Introduction and NMOS circuit level implement design white board
to Switch Level implementation using PMOS and
Modelling) NMOS transistors
Lecture 23 Switch Level Modelling R-3:11.2 Implementing of devices Analysis using switch virtual labs and
And Primitives using switch level level modelling white board
(Implementation of Devices modelling
at Switch Level)
Switch Level Modelling R-3:11.2 Implementing of devices Analysis using switch virtual labs and
And Primitives using switch level level modelling brain storming
(Implementation of modelling
Expressions)
Lecture 24 Switch Level Modelling R-3:11.2 Implementing of devices Analysis using switch virtual labs and
And Primitives using switch level level modelling brain storming
(Implementation of modelling
Expressions)
Switch Level Modelling R-3:11.2 Implementing of devices Analysis using switch virtual labs and
And Primitives using switch level level modelling white board
(Implementation of Devices modelling
at Switch Level)
Week 9 Lecture 25 Switch Level Modelling R-3:12.1-12.2 knowledge of basic implementation of Brain Storming
And Primitives(Importance primitives and need of designs using UDP and White Board
of UDP) User defined primitives
Lecture 26 Quiz,Test2
Lecture 27 Switch Level Modelling R-3:13.1 Implementing design Decreasing of Brain Storming
And Primitives(Task and using task and function complexity using task and White Board
Functions) and function will be
learnt
Week 10 Lecture 28 Finite State Machines and R-2:1.4 Knowledge of students will learn to Brain Storming
System Controllers Design implementing State use flip flops and and White Board
(Introduction to FSM) machine design using design sequence
flip flops detectors
Lecture 29 Finite State Machines and R-2:1.6 knowledge of varioius Analysis of FSM Brain Storming
System Controllers Design state machines for using all conditions and White Board
(Sequence overlaping and non of overlaping and non
detector Implementation) overlaping case overlaping
Week 10 Lecture 30 Finite State Machines and R-2:1.6 knowledge of varioius Analysis of FSM Brain Storming
System Controllers Design state machines for using all conditions and White Board
(Sequence overlaping and non of overlaping and non
detector Implementation) overlaping case overlaping
Week 11 Lecture 31 Finite State Machines and R-2:1.7-1.9 Knowledge of students will learn to Xilinx tool and
System Controllers Design implementing FSM design FSM using white board
(Programming of various using if else statements behavioural
FSM) modelling
Finite State Machines and R-2:1.7-1.9 Knowledge of state Student will learn to Xilinx tool and
System Controllers Design reduction in Finite state implement fsm along brain storming
(State Reduction) machine with state reduction
Lecture 32 Finite State Machines and R-2:1.7-1.9 Knowledge of state Student will learn to Xilinx tool and
System Controllers Design reduction in Finite state implement fsm along brain storming
(State Reduction) machine with state reduction
Finite State Machines and R-2:1.7-1.9 Knowledge of students will learn to Xilinx tool and
System Controllers Design implementing FSM design FSM using white board
(Programming of various using if else statements behavioural
FSM) modelling
Lecture 33 Quiz,Test3
Week 12 Lecture 34 Finite State Machines and T-1:7.2 7.11 Knowledge of Design of students will learn to Xilinx tool and
System Controllers Design system controllers using implement data white board
(Introduction to system data logger logger using various
control) circuits
Lecture 35 Asynchronous Finite State T-1:10.1-10.4 knowledge of Design of Analysis and Xilinx tool and
machine Design asynchronous circuits implementation of white board
(Introduction and Scope of asynchronous circuits
Asynchronous
Circuits)
Asynchronous Finite State T-1:10.1-10.4 knowledge of Design of students will learn to Xilinx tool and
machine Design asynchronous circuits analyse and white board
(Asynchronous Analysis and like flip flops and other implement
Design of Asynchronous sequential circuits asynchronous circuits
Machines) by using flip flops
Lecture 36 Asynchronous Finite State T-1:10.6-10.7 Design of Excitation Analysis of Xilinx tool and
machine Design(Cycles and map for asynchronous Asynchronous white board
Races) circuits circuits
Asynchronous Finite State T-1:10.6-10.7 Design of Excitation student will learn the Xilinx tool and
machine Design(Plotting map for asynchronous Analysis of white board
and Reading Excitation circuits Asynchronous
Map) circuits using
exitation map
Week 13 Lecture 37 Asynchronous Finite State T-1:10.6-10.7 Design of Excitation student will learn the Xilinx tool and
machine Design(Plotting map for asynchronous Analysis of white board
and Reading Excitation circuits Asynchronous
Map) circuits using
exitation map
Asynchronous Finite State T-1:10.6-10.7 Design of Excitation Analysis of Xilinx tool and
machine Design(Cycles and map for asynchronous Asynchronous white board
Races) circuits circuits
Week 13 Lecture 38 Asynchronous Finite State T-1:10.8-10.9 knowledge of essential implementation of Xilinx tool and
machine Design(Essential Hazards in essential hazards in white board
Hazards) Asynchronous circuits Asynchronous
circuits
Lecture 39 Asynchronous Finite State T-1:10.8-10.9 knowledge of essential implementation of Xilinx tool and
machine Design(Essential Hazards in essential hazards in white board
Hazards) Asynchronous circuits Asynchronous
circuits
Asynchronous Finite State T-1:10.8-10.9 knowledge of static Implementation of Xilinx tool and
machine Design(Hazards) Hazards and dynamic hazards in white board
hazards in Asynchronous
Asynchronous circuits circuits will be learnt
Week 14 Lecture 40 Asynchronous Finite State T-1:10.11 knowledge of student will learn to Xilinx tool and
machine Design(Map Asynchronous circuit implement white board
Entered Variable using map entered Asynchronous
Approaches to variable method of flip circuits using MEV
Asynchronous Design) flops method
Asynchronous Finite State T-1:10.11 knowledge of student will learn Xilinx tool and
machine Design Designing contemporary method white board
(Contemporary Approach to Asynchronous circuit of implementing
Asynchronous Design) using various methods , Asynchronous
L40 is reserved for circuits
contingency
Lecture 41 Asynchronous Finite State T-1:10.11 knowledge of student will learn Xilinx tool and
machine Design Designing contemporary method white board
(Contemporary Approach to Asynchronous circuit of implementing
Asynchronous Design) using various methods , Asynchronous
L40 is reserved for circuits
contingency
Asynchronous Finite State T-1:10.11 knowledge of student will learn to Xilinx tool and
machine Design(Map Asynchronous circuit implement white board
Entered Variable using map entered Asynchronous
Approaches to variable method of flip circuits using MEV
Asynchronous Design) flops method
Lecture 42 Asynchronous Finite State T-1:10.13 knowledge of Various hazards in MEV Xilinx tool and
machine Design(Hazards in hazards in MEV method method will be learnt white board
Circuits Developed by MEV implemented for flip by eliminating the
Method) flops hazard with various
methods

SPILL OVER
Week 15 Lecture 43 Spill Over
Lecture 44 Spill Over
Lecture 45 Spill Over

Scheme for CA:

 Component Frequency Out Of Each Marks Total Marks
Quiz,Test 2 3 10 20

Total :- 10 20

Details of Academic Task(s)

AT No. Objective Topic of the Academic Task Nature of Academic Task Evaluation Mode Allottment /
(group/individuals/field submission Week
work
Quiz1 Knowledge of Fundamentals of digital electronics ,combinational circuits and Individual 30 multiple choice 3/4
students on sequential circuits and basics of verilog programming questions with 25
theoritical concepts percent negative
marking
Test1 Knowledge and Implementing all the digital design using various modelling Individual six subjective 8/9
understanding of the techniques of verilog programming questions each of
students in design five marks will be
part of the subject given and student
has to attempt all
the questions
Test2 To Assess the Finite state machines and Asynchronous circuits Individual Six subjective 10 / 11
Knowledge of the Questions Each of
Students on Five Marks ans
designing student has to
attempt all
questions