TL43xx Precision Programmable Reference: 1 Features 3 Description
TL43xx Precision Programmable Reference: 1 Features 3 Description
TL43xx Precision Programmable Reference: 1 Features 3 Description
Device Information(1)
PART NUMBER PACKAGE (PIN) BODY SIZE (NOM)
SOT-23-3 (3) 2.90 mm x 1.30 mm
SOT-23-5 (5) 2.90 mm x 1.60 mm
TL43xx SOIC (8) 4.90 mm x 3.90 mm
PDIP (8) 9.50 mm x 6.35 mm
SOP (8) 6.20 mm x 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
Input VKA
IKA
Vref
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL431, TL431A, TL431B
TL432, TL432A, TL432B
SLVS543O – AUGUST 2004 – REVISED JANUARY 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Parameter Measurement Information ................ 18
2 Applications ........................................................... 1 9 Detailed Description ............................................ 19
3 Description ............................................................. 1 9.1 Overview ................................................................. 19
4 Simplified Schematic............................................. 1 9.2 Functional Block Diagram ....................................... 19
5 Revision History..................................................... 2 9.3 Feature Description................................................. 20
9.4 Device Functional Modes........................................ 20
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 4 10 Applications and Implementation...................... 21
10.1 Application Information.......................................... 21
7.1 Absolute Maximum Ratings ...................................... 4
10.2 Typical Applications .............................................. 21
7.2 ESD Ratings.............................................................. 4
10.3 System Examples ................................................. 26
7.3 Thermal Information .................................................. 4
7.4 Recommended Operating Conditions....................... 4 11 Power Supply Recommendations ..................... 29
7.5 Electrical Characteristics, TL431C, TL432C ............. 5 12 Layout................................................................... 29
7.6 Electrical Characteristics, TL431I, TL432I ................ 6 12.1 Layout Guidelines ................................................. 29
7.7 Electrical Characteristics, TL431Q, TL432Q............. 7 12.2 Layout Example .................................................... 29
7.8 Electrical Characteristics, TL431AC, TL432AC ........ 8 13 Device and Documentation Support ................. 30
7.9 Electrical Characteristics, TL431AI, TL432AI ........... 9 13.1 Related Links ........................................................ 30
7.10 Electrical Characteristics, TL431AQ, TL432AQ.... 10 13.2 Trademarks ........................................................... 30
7.11 Electrical Characteristics, TL431BC, TL432BC .... 11 13.3 Electrostatic Discharge Caution ............................ 30
7.12 Electrical Characteristics, TL431BI, TL432BI ....... 12 13.4 Glossary ................................................................ 30
7.13 Electrical Characteristics, TL431BQ, TL432BQ.... 13 14 Mechanical, Packaging, and Orderable
7.14 Typical Characteristics .......................................... 14 Information ........................................................... 30
5 Revision History
Changes from Revision N (January 2014) to Revision O Page
• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, ,
Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
• Added Applications. ................................................................................................................................................................ 1
• Moved Typical Characteristics into Specifications section. ................................................................................................. 14
• Deleted TA values under TEST CONDITIONS for VI(dev) and II(dev) PARAMETERS in the Electrical Characteristics table. .. 5
ANODE
CATHODE
NC 2 5 NC
ANODE
ANODE REF 3 4 NC
REF
REF NC − No internal connection
TL431, TL431A, TL431B . . . D (SOIC) PACKAGE TL431, TL431A, TL431B . . . P (PDIP), PS (SOP),
(TOP VIEW) OR PW (TSSOP) PACKAGE
(TOP VIEW)
CATHODE 1 8 REF
ANODE 2 7 ANODE CATHODE 1 8 REF
ANODE 3 6 ANODE NC 2 7 NC
NC 4 5 NC NC 3 6 ANODE
NC 4 5 NC
NC − No internal connection
NC − No internal connection
TL431, TL431A, TL431B . . . PK (SOT-89) PACKAGE TL432, TL432A, TL432B . . . PK (SOT-89) PACKAGE
(TOP VIEW) (TOP VIEW)
CATHODE REF
ANODE
ANODE
ANODE ANODE
REF CATHODE
TL431, TL431A, TL431B . . . DBZ (SOT-23-3) PACKAGE TL432, TL432A, TL432B . . . DBZ (SOT-23-3) PACKAGE
(TOP VIEW) (TOP VIEW)
CATHODE 1 REF 1
3 ANODE 3 ANODE
REF 2 CATHODE 2
Pin Functions
PIN
TLV431x TLV432x
TYPE DESCRIPTION
NAME P, PS
DBZ DBV PK D LP KTP DCK DBZ DBV PK
PW
CATHODE 1 3 3 1 1 1 1 1 2 4 1 I/O Shunt Current/Voltage input
REF 2 4 1 8 8 3 3 3 1 5 3 I Threshold relative to common anode
2, 3,
ANODE 3 5 2 6 2 2 6 3 2 2 O Common pin, normally connected to ground
6, 7
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VKA Cathode voltage (2) 37 V
IKA Continuous cathode current range –100 150 mA
II(ref) Reference input current range –0.05 10 mA
TJ Operating virtual junction temperature 150 °C
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ANODE, unless otherwise noted.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
(1) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I
(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I
(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I
(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I
(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I
(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I
(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I
(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I
(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I
2600 5
VKA = Vref R1 = 10 kΩ
2580 IKA = 10 mA R2 =∞
Vref = 2550 mV IKA = 10 mA
2560 4
V ref − Reference Voltage − mV
2520 3
Vref = 2495 mV
2500
2480 2
2460
2420
2400 0
−75 −50 −25 0 25 50 75 100 125 −75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 1. Reference Voltage vs Free-Air Temperature Figure 2. Reference Current vs Free-Air Temperature
150 800
VKA = Vref VKA = Vref
125 TA = 25°C TA = 25°C
100 600
I KA − Cathode Current − µ A
I KA − Cathode Current − mA
75 Imin
50 400
25
0 200
−25
−50 0
−75
−100 −200
−2 −1 0 1 2 3 −1 0 1 2 3
VKA − Cathode Voltage − V VKA − Cathode Voltage − V
Figure 3. Cathode Current vs Cathode Voltage Figure 4. Cathode Current vs Cathode Voltage
2.5 − 0.85
VKA = 36 V
VKA = 3 V to 36 V
Vref = 0
− 0.95
I off − Off-State Cathode Current − µA
2
∆V ref / ∆V KA − mV/V
−1.05
1.5
−1.15
1
−1.25
0.5
−1.35
16 16
0 −1.45
−75 −50 −25 0 25 50 75 100 125 −75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 5. Off-State Cathode Current Figure 6. Ratio of Delta Reference Voltage to Delta Cathode
vs Free-Air Temperature Voltage vs Free-Air Temperature
220 3
2
200
1
180 0
−1
160
−2
140 −3
−4 f = 0.1 to 10 Hz
120 IKA = 10 mA
16 −5
TA = 25°C
100 −6
10 100 1k 10 k 100 k 0 1 2 3 4 5 6 7 8 9 10
f − Frequency − Hz t − Time − s
Figure 8. Equivalent Input Noise Voltage Over a 10-S Period
Figure 7. Equivalent Input Noise Voltage vs Frequency
19.1 V
1 kΩ
500 µF 910 Ω
2000 µF
VCC VCC
1 µF
TL431
(DUT) TLE2027
AV = 10 V/mV
+ 22 µF
820 Ω + TLE2027 To
− 16 kΩ 16 kΩ Oscilloscope
16 Ω −
160 kΩ 1 µF 33 kΩ
0.1 µF AV = 2 V/V
33 kΩ
VEE VEE
Figure 9. Test Circuit for Equivalent Input Noise Voltage Over a 10-S Period
60 IKA = 10 mA
IKA = 10 mA
TA = 25°C
A V − Small-Signal V oltage Amplification − dB
TA = 25°C
50
40 Output
IKA
30 15 kΩ 232 Ω
20
9 µF
+
10 −
8.25 kΩ
0
1k 10 k 100 k 1M 10 M
f − Frequency − Hz
GND
Figure 10. Small-Signal Voltage Amplification
vs Frequency Figure 11. Test Circuit for Voltage Amplification
IKA
10 50 Ω
−
+
1
GND
0.1
1k 10 k 100 k 1M 10 M
f − Frequency − Hz
Figure 12. Reference Impedance vs Frequency
6 220 Ω
TA = 25°C
Output
Input
5
Input and Output V oltage − V
Pulse
4
Generator 50 Ω
f = 100 kHz
3
Output
2 GND
1
Figure 15. Test Circuit for Pulse Response
0
−1 0 1 2 3 4 5 6 7
t − Time − µs
Figure 14. Pulse Response
100 150 Ω
A V KA = Vref TA = 25°C
90 B V KA =5V
C VKA = 10 V IKA
80 D VKA = 15 Vf +
B CL VBATT
I KA − Cathode Current − mA
70
−
Stable
60
Stable C
50
A
40
TEST CIRCUIT FOR CURVE A
30
D
20
IKA
10 R1 = 10 kΩ 150 Ω
0
0.001 0.01 0.1 1 10 CL
CL − Load Capacitance − µF +
R2 VBATT
The areas under the curves represent conditions that may cause the −
device to oscillate. For curves B, C, and D, R2 and V+ are adjusted
to establish the initial VKA and IKA conditions, with CL = 0. VBATT and
CL then are adjusted to determine the ranges of stability.
Figure 16. Stability Boundary Conditions for All TL431 and TEST CIRCUIT FOR CURVES B, C, AND D
TL431A Devices Figure 17. Test Circuits for Stability Boundary Conditions
(Except for SOT23-3, SC-70, and Q-Temp Devices)
70 −
TA = 25°C
60
Stable C
Stable
50
A
40 TEST CIRCUIT FOR CURVE A
A
30
D
20 IKA
B R1 = 10 kΩ 150 Ω
10
CL
0
0.001 0.01 0.1 1 10 +
R2 VBATT
CL − Load Capacitance − µF
−
The areas under the curves represent conditions that may cause the
device to oscillate. For curves B, C, and D, R2 and V+ are adjusted
to establish the initial VKA and IKA conditions, with CL = 0. VBATT and
CL then are adjusted to determine the ranges of stability. TEST CIRCUIT FOR CURVES B, C, AND D
Figure 18. Stability Boundary Conditions for All TL431B, Figure 19. Test Circuit for Stability Boundary Conditions
TL432, SOT-23, SC-70, and Q-Temp Devices
Vref
Input VKA
IKA
R1 Iref
R2 Vref æ R1 ö
VKA = Vref ç 1 + ÷ + Iref × R1
è R2 ø
Input VKA
Ioff
9 Detailed Description
9.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications, ranging from power
to signal path. This is due to it's key components containing an accurate voltage reference & opamp, which are
very fundamental analog building blocks. TL43xx is used in conjunction with it's key components to behave as a
single voltage reference, error amplifier, voltage clamp or comparator with integrated reference.
TL43xx can be operated and adjusted to cathode voltages from 2.5V to 36V, making this part optimum for a wide
range of end equipments in industrial, auto, telecom & computing. In order for this device to behave as a shunt
regulator or error amplifier, >1mA (Imin(max)) must be supplied in to the cathode pin. Under this condition,
feedback can be applied from the Cathode and Ref pins to create a replica of the internal reference voltage.
Various reference voltage options can be purchased with initial tolerances (at 25°C) of 0.5%, 1%, and 2%. These
reference options are denoted by B (0.5%), A (1.0%) and blank (2.0%) after the TL431 or TL432. TL431 & TL432
are both functionaly, but have separate pinout options.
The TL43xxC devices are characterized for operation from 0°C to 70°C, the TL43xxI devices are characterized
for operation from –40°C to 85°C, and the TL43xxQ devices are characterized for operation from –40°C to
125°C.
CATHODE
REF +
_
Vref
ANODE
CATHODE
800 Ω 800 Ω
20 pF
REF
150 Ω
3.28 kΩ 4 kΩ 10 kΩ
2.4 kΩ 7.2 kΩ 20 pF
1 kΩ
800 Ω
ANODE
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
Rsup
Vout
CATHODE
R1
VL
RIN
VIN REF
+
R2
2.5V
ANODE
10.2.1.2.1.1 Overdrive
Slow or inaccurate responses can also occur when the reference pin is not provided enough overdrive voltage.
This is the amount of voltage that is higher than the internal virtual reference. The internal virtual reference
voltage will be within the range of 2.5 V ±(0.5%, 1.0% or 1.5%) depending on which version is being used. The
more overdrive voltage provided, the faster the TL431 will respond.
For applications where TL431 is being used as a comparator, it is best to set the trip point to greater than the
positive expected error (i.e. +1.0% for the A version). For fast response, setting the trip point to >10% of the
internal VREF should suffice.
For minimal voltage drop or difference from Vin to the ref pin, it is recommended to use an input resistor <10kΩ
to provide Iref.
5.5
5
4.5
4
3.5
Voltage (V)
3
2.5
2
1.5
1
Vin
0.5 Vka(Rsup=10k:)
0 Vka(Rsup=1k:)
-0.5
-0.001 -0.0006 -0.0002 0.0002 0.0006 0.001
Time (s) D001
Figure 26. Output Response With Various Cathode Currents
10.2.2.2.3 Stability
Though TL43xx is stable with no capacitive load, the device that receives the shunt regulator's output voltage
could present a capacitive load that is within the TL43xx region of stability, shown inFigure 16 and Figure 18.
Also, designers may use capacitive loads to improve the transient response or for power supply decoupling.
When using additional capacitance between Cathode and Anode, refer to Figure 16 and Figure 18. Also,
application note SLVA482 will provide a deeper understanding of this devices stability characteristics and aid the
user in making the right choices when choosing a load capacitor.
27
Vsup
24
Vka=Vref
21 R1=10k: & R2=10k:
R1=38k: & R2=10k:
18
15
Voltage (V)
12
9
6
3
0
-3
-6
-5E-6 -3E-6 -1E-6 1E-6 3E-6 5E-6
Time (s) D001
Figure 28. TL43xx Start-up Response
2N222
30 Ω
0.01 µF 4.7 kΩ
TL431 VO
R1
R2 æ R1 ö
0.1% VO = ç 1 +
0.1% ÷ Vref
è R2 ø
VI(BATT)
IN
OUT
uA7805 VO
Common R1
(
VO = 1 + R1 Vref (
R2
TL431 Minimum V V + 5V
O = ref
R2
VI(BATT) VO
R1 (
VO = 1 + R1 Vref(
R2
R2 TL431
VI(BATT) VO
R1
TL431
C
(see Note A)
R2
A. Refer to the stability boundary conditions in Figure 16 and Figure 18 to determine allowable values for C.
IN OUT
VI(BATT) LM317 VO ≈5 V, 1.5 A
8.2 kΩ Adjust
243 Ω
0.1%
TL431
243 Ω
0.1%
VI(BATT) VO ≈5 V
Rb
(see Note A) 27.4 kΩ
0.1%
TL431
27.4 kΩ
0.1%
12 V
VCC
6.8 kΩ
5V 10 kΩ
−
10 kΩ
+
0.1% TL598
X
TL431 Not
10 kΩ Used
0.1%
Feedback
R3
(see Note A)
VI(BATT)
R4
R1A R1B
(see Note A)
Low Limit = 1 + R1B V ref
R2B
TL431
High Limit = 1 + R1A V ref
R2A
LED on When Low Limit < VI(BATT) < High Limit
R2A R2B
A. Select R3 and R4 to provide the desired LED intensity and cathode current ≥1 mA to the TL431 at the available
VI(BATT).
650 Ω
12 V
R 2 kΩ
TL431
C æ 12 V ö
On Delay = R × C × In çç
Off 12 V – V ÷÷
è ref ø
RCL IO
0.1% V ref
VI(BATT) Iout = + IKA
R CL
R1 V I(BATT)
TL431 R1 = I
O
h FE + IKA
VI(BATT)
IO
Vref
IO =
RS
TL431
RS
0.1%
12 Layout
CL
GND
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
www.ti.com 26-Sep-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL431AIDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (TAI3, TAIS, TAIU)
& no Sb/Br)
TL431AIDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T5U
& no Sb/Br)
TL431AIDCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T5U
& no Sb/Br)
TL431AIDCKT ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T5U
& no Sb/Br)
TL431AIDCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T5U
& no Sb/Br)
TL431AIDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 431AI
& no Sb/Br)
TL431AIDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 431AI
& no Sb/Br)
TL431AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 431AI
& no Sb/Br)
TL431AILP ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431AI
(RoHS)
TL431AILPE3 ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431AI
(RoHS)
TL431AILPM ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431AI
(RoHS)
TL431AILPME3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431AI
(RoHS)
TL431AILPR ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431AI
(RoHS)
TL431AILPRE3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431AI
(RoHS)
TL431AIP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TL431AIP
& no Sb/Br)
TL431AIPE4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TL431AIP
& no Sb/Br)
TL431AIPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 4B
& no Sb/Br)
TL431AIPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 4B
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL431AQDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (TAQG, TAQU)
& no Sb/Br)
TL431AQDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (TAQG, TAQU)
& no Sb/Br)
TL431AQDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (TAQ3, TAQS, TAQU)
& no Sb/Br)
TL431AQDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (TAQ3, TAQS, TAQU)
& no Sb/Br)
TL431AQDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (TAQS, TAQU)
& no Sb/Br)
TL431AQDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (TAQS, TAQU)
& no Sb/Br)
TL431AQDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T7U
& no Sb/Br)
TL431AQDCKT ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T7U
& no Sb/Br)
TL431AQPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 4D
& no Sb/Br)
TL431AQPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 4D
& no Sb/Br)
TL431BCD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431B
& no Sb/Br)
TL431BCDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (T3GG, T3GU)
& no Sb/Br)
TL431BCDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (T3GG, T3GU)
& no Sb/Br)
TL431BCDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T3GG
& no Sb/Br)
TL431BCDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (T3G3, T3GS, T3GU)
& no Sb/Br)
TL431BCDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (T3G3, T3GS, T3GU)
& no Sb/Br)
TL431BCDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (T3G3, T3GS, T3GU)
& no Sb/Br)
TL431BCDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (T3G3, T3GS, T3GU)
& no Sb/Br)
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL431BCDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T2U
& no Sb/Br)
TL431BCDCKT ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T2U
& no Sb/Br)
TL431BCDE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431B
& no Sb/Br)
TL431BCDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431B
& no Sb/Br)
TL431BCDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431B
& no Sb/Br)
TL431BCLP ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type 0 to 70 T431B
(RoHS)
TL431BCLPE3 ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type 0 to 70 T431B
(RoHS)
TL431BCLPR ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type 0 to 70 T431B
(RoHS)
TL431BCP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 TL431BCP
& no Sb/Br)
TL431BCPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 4C
& no Sb/Br)
TL431BCPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 4C
& no Sb/Br)
TL431BCPSR ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431B
& no Sb/Br)
TL431BCPWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431B
& no Sb/Br)
TL431BID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z431B
& no Sb/Br)
TL431BIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (T3FG, T3FU)
& no Sb/Br)
TL431BIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (T3FG, T3FU)
& no Sb/Br)
TL431BIDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3FG
& no Sb/Br)
TL431BIDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T3F3, T3FS, T3FU)
& no Sb/Br)
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL431BIDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T3F3, T3FS, T3FU)
& no Sb/Br)
TL431BIDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T3F3, T3FS, T3FU)
& no Sb/Br)
TL431BIDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T3F3, T3FS, T3FU)
& no Sb/Br)
TL431BIDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3U
& no Sb/Br)
TL431BIDCKT ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3U
& no Sb/Br)
TL431BIDCKTE4 ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3U
& no Sb/Br)
TL431BIDCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3U
& no Sb/Br)
TL431BIDE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z431B
& no Sb/Br)
TL431BIDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z431B
& no Sb/Br)
TL431BIDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 Z431B
& no Sb/Br)
TL431BIDRE4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z431B
& no Sb/Br)
TL431BIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z431B
& no Sb/Br)
TL431BILP ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type -40 to 85 Z431B
(RoHS)
TL431BILPE3 ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type -40 to 85 Z431B
(RoHS)
TL431BILPR ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 Z431B
(RoHS)
TL431BILPRE3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 Z431B
(RoHS)
TL431BIP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TL431BIP
& no Sb/Br)
TL431BIPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 4I
& no Sb/Br)
Addendum-Page 6
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
Addendum-Page 7
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL431BQLPME3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 125 T431BQ
(RoHS)
TL431BQLPR ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 125 T431BQ
(RoHS)
TL431BQLPRE3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 125 T431BQ
(RoHS)
TL431BQPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 3H
& no Sb/Br)
TL431BQPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 3H
& no Sb/Br)
TL431BQPSR PREVIEW SO PS 8 2000 TBD Call TI Call TI -40 to 125
TL431CD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL431C
& no Sb/Br)
TL431CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (T3CG, T3CS)
& no Sb/Br)
TL431CDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (T3CG, T3CS)
& no Sb/Br)
TL431CDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T3CG
& no Sb/Br)
TL431CDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (T3C3, T3CS, T3CU)
& no Sb/Br)
TL431CDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (T3C3, T3CS, T3CU)
& no Sb/Br)
TL431CDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (T3CS, T3CU)
& no Sb/Br)
TL431CDBZTG4 ACTIVE SOT-23 DBZ 3 250 TBD Call TI Call TI 0 to 70 (T3CS, T3CU)
Addendum-Page 8
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
Addendum-Page 9
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL431IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (T3IG, T3IU)
& no Sb/Br)
TL431IDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T3I3, T3IS, T3IU)
& no Sb/Br)
TL431IDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T3I3, T3IS, T3IU)
& no Sb/Br)
TL431IDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T3IS, T3IU)
& no Sb/Br)
TL431IDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T3IS, T3IU)
& no Sb/Br)
TL431IDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL431I
& no Sb/Br)
TL431IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 TL431I
& no Sb/Br)
TL431IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL431I
& no Sb/Br)
TL431IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL431I
& no Sb/Br)
TL431ILP ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431I
(RoHS)
TL431ILPE3 ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431I
(RoHS)
TL431ILPR ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431I
(RoHS)
TL431ILPRE3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431I
(RoHS)
TL431IP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TL431IP
& no Sb/Br)
TL431IPE4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TL431IP
& no Sb/Br)
TL431IPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 3I
& no Sb/Br)
TL431IPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 3I
& no Sb/Br)
TL431QD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T431Q
& no Sb/Br)
Addendum-Page 10
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL431QDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (T3QG, T3QU)
& no Sb/Br)
TL431QDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T3QG
& no Sb/Br)
TL431QDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (T3QG, T3QU)
& no Sb/Br)
TL431QDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (T3Q3, T3QS, T3QU)
& no Sb/Br)
TL431QDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (T3Q3, T3QS, T3QU)
& no Sb/Br)
TL431QDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (T3QS, T3QU)
& no Sb/Br)
TL431QDBZTG4 ACTIVE SOT-23 DBZ 3 250 TBD Call TI Call TI -40 to 125 (T3QS, T3QU)
TL431QDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T6U
& no Sb/Br)
TL431QDCKT ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T6U
& no Sb/Br)
TL431QDCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T6U
& no Sb/Br)
TL431QDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T431Q
& no Sb/Br)
TL431QPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 3Q
& no Sb/Br)
TL431QPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 3Q
& no Sb/Br)
TL432ACDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (T4BG, T4BU)
& no Sb/Br)
TL432ACDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (T4B3, T4BS, T4BU)
& no Sb/Br)
TL432ACDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (T4B3, T4BS, T4BU)
& no Sb/Br)
TL432ACDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (T4BS, T4BU)
& no Sb/Br)
TL432ACDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (T4BS, T4BU)
& no Sb/Br)
Addendum-Page 11
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL432AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (T4AG, T4AU)
& no Sb/Br)
TL432AIDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T4A3, T4AS, T4AU)
& no Sb/Br)
TL432AIDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T4A3, T4AS, T4AU)
& no Sb/Br)
TL432AIDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T4A3, T4AS, T4AU)
& no Sb/Br)
TL432AIDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T4A3, T4AS, T4AU)
& no Sb/Br)
TL432AIPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 2E
& no Sb/Br)
TL432AQDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T4DU
& no Sb/Br)
TL432AQDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T4DU
& no Sb/Br)
TL432AQDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T4DU
& no Sb/Br)
TL432AQDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (T4D3, T4DS, T4DU)
& no Sb/Br)
TL432AQDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (T4D3, T4DS, T4DU)
& no Sb/Br)
TL432AQDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (T4DS, T4DU)
& no Sb/Br)
TL432AQDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (T4DS, T4DU)
& no Sb/Br)
TL432AQPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 2F
& no Sb/Br)
TL432AQPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 2F
& no Sb/Br)
TL432BCDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TBCU
& no Sb/Br)
TL432BCDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (TBCS, TBCU)
& no Sb/Br)
TL432BCDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (TBCS, TBCU)
& no Sb/Br)
Addendum-Page 12
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL432BCDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (TBCS, TBCU)
& no Sb/Br)
TL432BCPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 2G
& no Sb/Br)
TL432BIDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T4F3, T4FS, T4FU)
& no Sb/Br)
TL432BIDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T4F3, T4FS, T4FU)
& no Sb/Br)
TL432BIDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T4F3, T4FS, T4FU)
& no Sb/Br)
TL432BIDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T4F3, T4FS, T4FU)
& no Sb/Br)
TL432BIPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 2H
& no Sb/Br)
TL432BQDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (T4H3, T4HS, T4HU)
& no Sb/Br)
TL432BQDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (T4H3, T4HS, T4HU)
& no Sb/Br)
TL432BQPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 2J
& no Sb/Br)
TL432CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (T4CG, T4CU)
& no Sb/Br)
TL432CDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (T4CS, T4CU)
& no Sb/Br)
TL432CPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 2A
& no Sb/Br)
TL432IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (T4IG, T4IU)
& no Sb/Br)
TL432IDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T4IS, T4IU)
& no Sb/Br)
TL432IDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (T4IS, T4IU)
& no Sb/Br)
TL432IPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 2B
& no Sb/Br)
TL432QDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (T4QS, T4QU)
& no Sb/Br)
Addendum-Page 13
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL432QPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 2C
& no Sb/Br)
TL432QPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 2C
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 14
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2018
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 15
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Sep-2018
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Sep-2018
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Sep-2018
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Sep-2018
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Sep-2018
Pack Materials-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Sep-2018
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL431ACPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431ACPSR SO PS 8 2000 367.0 367.0 38.0
TL431ACPWR TSSOP PW 8 2000 367.0 367.0 35.0
TL431AIDBVR SOT-23 DBV 5 3000 183.0 183.0 20.0
TL431AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431AIDBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431AIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431AIDBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
TL431AIDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL431AIDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431AIDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431AIDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431AIDCKR SC70 DCK 6 3000 203.0 203.0 35.0
TL431AIDCKT SC70 DCK 6 250 203.0 203.0 35.0
TL431AIDR SOIC D 8 2500 340.5 338.1 20.6
TL431AIDR SOIC D 8 2500 364.0 364.0 27.0
TL431AIDRG4 SOIC D 8 2500 340.5 338.1 20.6
TL431AIPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431AQDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431AQDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431AQDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL431AQDBZRG4 SOT-23 DBZ 3 3000 202.0 201.0 28.0
TL431AQDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431AQDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431AQDCKR SC70 DCK 6 3000 203.0 203.0 35.0
TL431AQDCKT SC70 DCK 6 250 203.0 203.0 35.0
TL431AQPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431BCDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431BCDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431BCDBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
TL431BCDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431BCDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL431BCDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431BCDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431BCDCKR SC70 DCK 6 3000 203.0 203.0 35.0
TL431BCDCKT SC70 DCK 6 250 203.0 203.0 35.0
TL431BCDR SOIC D 8 2500 340.5 338.1 20.6
TL431BCPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431BCPSR SO PS 8 2000 367.0 367.0 38.0
TL431BCPWR TSSOP PW 8 2000 367.0 367.0 35.0
TL431BIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431BIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431BIDBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
TL431BIDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
Pack Materials-Page 6
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Sep-2018
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL431BIDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL431BIDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431BIDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431BIDCKR SC70 DCK 6 3000 203.0 203.0 35.0
TL431BIDCKT SC70 DCK 6 250 203.0 203.0 35.0
TL431BIDR SOIC D 8 2500 364.0 364.0 27.0
TL431BIDR SOIC D 8 2500 340.5 338.1 20.6
TL431BIDRG4 SOIC D 8 2500 340.5 338.1 20.6
TL431BIPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431BQDBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
TL431BQDBVT SOT-23 DBV 5 250 203.0 203.0 35.0
TL431BQDBZR SOT-23 DBZ 3 3000 203.0 203.0 35.0
TL431BQDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL431BQDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL431BQDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431BQDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431BQDCKR SC70 DCK 6 3000 203.0 203.0 35.0
TL431BQDCKT SC70 DCK 6 250 203.0 203.0 35.0
TL431BQDR SOIC D 8 2500 340.5 338.1 20.6
TL431CDBVR SOT-23 DBV 5 3000 183.0 183.0 20.0
TL431CDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431CDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431CDBVT SOT-23 DBV 5 250 183.0 183.0 20.0
TL431CDBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
TL431CDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431CDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL431CDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431CDR SOIC D 8 2500 364.0 364.0 27.0
TL431CDR SOIC D 8 2500 340.5 338.1 20.6
TL431CDRG4 SOIC D 8 2500 340.5 338.1 20.6
TL431CPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431CPKE6 SOT-89 PK 3 1000 182.4 182.4 17.3
TL431CPSR SO PS 8 2000 367.0 367.0 38.0
TL431CPWR TSSOP PW 8 2000 367.0 367.0 35.0
TL431IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431IDBVR SOT-23 DBV 5 3000 183.0 183.0 20.0
TL431IDBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431IDBZR SOT-23 DBZ 3 3000 203.0 203.0 35.0
TL431IDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL431IDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL431IDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431IDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431IDR SOIC D 8 2500 340.5 338.1 20.6
Pack Materials-Page 7
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Sep-2018
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL431IDR SOIC D 8 2500 364.0 364.0 27.0
TL431IDRG4 SOIC D 8 2500 340.5 338.1 20.6
TL431IPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431QDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431QDBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431QDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431QDBZR SOT-23 DBZ 3 3000 203.0 203.0 35.0
TL431QDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL431QDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431QDCKR SC70 DCK 6 3000 203.0 203.0 35.0
TL431QDCKT SC70 DCK 6 250 203.0 203.0 35.0
TL431QDR SOIC D 8 2500 340.5 338.1 20.6
TL432ACDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL432ACDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432ACDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432ACDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL432ACDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL432AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL432AIDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432AIDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432AIDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL432AIDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL432AIPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL432AQDBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
TL432AQDBVT SOT-23 DBV 5 250 203.0 203.0 35.0
TL432AQDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432AQDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432AQDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL432AQDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL432AQPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL432BCDBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
TL432BCDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432BCDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL432BCDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL432BCPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL432BIDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432BIDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432BIDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL432BIDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL432BIPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL432BQDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432BQDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432BQPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL432CDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
Pack Materials-Page 8
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Sep-2018
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL432CDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432CPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL432IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL432IDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432IDBZT SOT-23 DBZ 3 250 183.0 183.0 20.0
TL432IPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL432QDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432QPK SOT-89 PK 3 1000 340.0 340.0 38.0
Pack Materials-Page 9
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA
1 5
2X 0.95
3.05
2.75
1.9 1.9
2
4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
4214839/C 04/2017
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA
1 5
2X 0.95
3.05
2.75
1.9 1.9
2
4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
4214839/C 04/2017
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
C
6.6 SEATING PLANE
TYP
6.2
A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1
3.1 2X
2.9
NOTE 3 1.95
4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.75 0.15
0 -8 0.05
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8
SYMM
6X (0.65)
5
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8
SYMM
6X (0.65)
5
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
LP0003A SCALE 1.200 SCALE 1.200
TO-92 - 5.34 mm max height
TO-92
5.21
4.44
EJECTOR PIN
OPTIONAL
5.34
4.32
(1.5) TYP
(2.54) SEATING
2X NOTE 3 PLANE
4 MAX
(0.51) TYP
6X
0.076 MAX
SEATING
PLANE
3X
12.7 MIN
0.43
2X 0.55 3X
3X 0.35
2.6 0.2 0.38
2X 1.27 0.13
FORMED LEAD OPTION
OTHER DIMENSIONS IDENTICAL STRAIGHT LEAD OPTION
TO STRAIGHT LEAD OPTION
2.67
3X
2.03 4.19
3.17
3 2 1
3.43 MIN
4215214/B 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Lead dimensions are not controlled within this area.
4. Reference JEDEC TO-226, variation AA.
5. Shipping method:
a. Straight lead option available in bulk pack only.
b. Formed lead option available in tape and reel or ammo pack.
c. Specific products can be offered in limited combinations of shipping medium and lead options.
d. Consult product folder for more information on available options.
www.ti.com
EXAMPLE BOARD LAYOUT
LP0003A TO-92 - 5.34 mm max height
TO-92
FULL R
0.05 MAX (1.07) TYP
ALL AROUND METAL 3X ( 0.85) HOLE
TYP TYP
2X
METAL
(1.5) 2X (1.5)
2X
SOLDER MASK
OPENING
1 2 3
(R0.05) TYP 2X (1.07)
(1.27)
SOLDER MASK
(2.54)
OPENING
METAL
2X
1 2 3 SOLDER MASK
(R0.05) TYP
(2.6) OPENING
SOLDER MASK
OPENING (5.2)
4215214/B 04/2017
www.ti.com
TAPE SPECIFICATIONS
LP0003A TO-92 - 5.34 mm max height
TO-92
13.7
11.7
32
23
16.5
15.5
11.0 9.75
8.5 8.50
19.0
17.5
4215214/B 04/2017
www.ti.com
4203227/C
PACKAGE OUTLINE
DBZ0003A SCALE 4.000
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
2.64 C
2.10
1.12 MAX
1.4
B A
1.2 0.1 C
PIN 1
INDEX AREA
0.95
3.04
1.9 2.80
3
2
0.5
3X
0.3
0.10
0.2 C A B (0.95) TYP
0.01
0.25
GAGE PLANE 0.20
TYP
0.08
0.6
TYP SEATING PLANE
0 -8 TYP 0.2
4214838/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
www.ti.com
EXAMPLE BOARD LAYOUT
DBZ0003A SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
(R0.05) TYP
(2.1)
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
4214838/C 04/2017
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DBZ0003A SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
(R0.05) TYP
(2.1)
4214838/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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