Rekha S S, Assistant Professor, Dept.

of
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ECE, PESU
BASIC MOS TRANSISTORS


Rekha S S, Assistant Professor, Dept. of

2
ECE, PESU
nMOS Enhancement Transistors


Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
nMOS Enhancement Transistors


Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
Enhancement mode transistor action

 Cut-off Region

Vt – threshold voltage ( positive voltage)

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
Enhancement mode transistor action

 Linear or Non-saturated Region

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
Enhancement mode transistor action

 Linear or Non-saturated Region

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
Enhancement mode transistor action

 Saturated Region

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Depletion Mode Transistor Action


The channel may also be established, under
the condition Vgs = 0

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Depletion Mode Transistor Action


 The channel may also be established, under the condition Vgs = 0

Is done by implanting suitable impurities in

the region between source and drain during
manufacture and prior to depositing the
insulation and the gate.

Rekha S S, Assistant Professor, Dept. of

10
ECE, PESU
 Depletion Mode Transistor Action


 The channel may also be established, under the condition Vgs = 0
 Is done by implanting suitable impurities in the region between source and
drain during manufacture and prior to depositing the insulation and the gate.

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Depletion Mode Transistor Action


 The channel may also be established, under the condition Vgs = 0
 Is done by implanting suitable impurities in the region between source and
drain during manufacture and prior to depositing the insulation and the gate.

the channel may be

closed by applying
a suitable negative
voltage to the gate.
Thus, Vt (threshold voltage) is negative

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
pMOS enhancement mode transistor


Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
pMOS enhancement mode transistor


 Gate voltage is ???

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
pMOS enhancement mode transistor


 Gate voltage is Negative Voltage

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
pMOS enhancement mode transistor


 Threshold voltage is ????

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
pMOS enhancement mode transistor


 Threshold voltage is Negative

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
pMOS enhancement mode transistor


 Source is at ____________ potential

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
pMOS enhancement mode transistor


 Source is at Higher potential

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
pMOS enhancement mode transistor


 Drain is at ____________ potential

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
pMOS enhancement mode transistor


 Drain is at Lower potential

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
Transistor Circuit Symbols


Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
Transistor Circuit Symbols


Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
Transistor Circuit Symbols


Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Conduction characteristics for enhancement
and depletion mode MOS transistors
(assuming fixed Vds)

 Enhancement Mode  Depletion Mode

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Conduction characteristics for enhancement
and depletion mode MOS transistors
(assuming fixed Vds)

 Enhancement Mode (nMOS )  Depletion Mode (nMOS)

Rekha S S, Assistant Professor, Dept. of

26
ECE, PESU
 Conduction characteristics for enhancement
and depletion mode MOS transistors
(assuming fixed Vds)

 Enhancement Mode (nMOS)  Depletion Mode(nMOS)

Rekha S S, Assistant Professor, Dept. of

27
ECE, PESU
 Conduction characteristics for enhancement
and depletion mode MOS transistors
(assuming fixed Vds)

 Enhancement Mode (pMOS)  Depletion Mode(pMOS)

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Conduction characteristics for enhancement
and depletion mode MOS transistors
(assuming fixed Vds)

 Enhancement Mode (pMOS)  Depletion Mode(pMOS)

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Conduction characteristics for enhancement
and depletion mode MOS transistors
(assuming fixed Vds)

 Enhancement Mode  Depletion Mode

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Drain to source current Ids
versus Voltage Vds relationship

 The whole concept of the MOS transistor evolves
from the use of the voltage on the gate to induce a
charge in the channel between drain and source
 Which may then be caused to move from source to
drain under the influence of an electric field created
by Vds.

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
Ids depends on
- how much charge in the channel?
- how fast is the charge moving?


Transit time:

But velocity

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Linear / Non-saturated Region

 Charge induced in channel is due to gate
voltage(voltage difference between the gate and the
channel) ---- average voltage is Vds/2.
 The effective gate voltage Vg = Vgs – Vt

 Charge /unit area =

 Thus induced charge in the channel

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 
Where D = oxide thickness
Thus

Or
where

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Alternative forms

where
in terms of Gate capacitance (Cg)

in terms of gate capacitance per unit area(co)

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Saturation Region

 Saturation begins when Vds  Vgs – Vt
 IR drop in the channel is equal to effective gate to
channel voltage at the drain.

Rekha S S, Assistant Professor, Dept. of

36
ECE, PESU
 MOS Transistor Trans conductance gm
 Trnasconductance expresses the relationship
between output current and the input voltage

 consider that the charge in channel Qc is such that
 Thus change in current

 Thus
 But change in charge

 In Saturation

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
Noise Margin


Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Alternate forms of Pull-Up

 Load Resistance RL:

 Is not often used because of the large space requirements

of resistors produced in a silicon substrate.
Rekha S S, Assistant Professor, Dept. of
41
ECE, PESU
 nMOS Depletion mode transistor in pull-up
 nMOS Inverter (Depletion Load nMOS Inverter):

Vin Vout Operating region

Driver Load
VOL VOH
VIL VOH
Vinv Vinv
VIH Small
Rekha S S, Assistant Professor, Dept. of
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ECE, PESU
VOH VOL
 nMOS Depletion mode transistor in pull-up
 nMOS Inverter (Depletion Load nMOS Inverter):

Vin Vout Operating region

Driver Load
VOL VOH Cut-off Linear
VIL VOH Saturation Linear
Vinv Vinv Saturation Saturation
VIH Small
Rekha LinearDept. of
S S, Assistant Professor, Saturation
43
ECE, PESU
VOH VOL Linear Saturation
 nMOS Depletion mode transistor in pull-up
 nMOS Inverter (Depletion Load nMOS Inverter):

 Limitations
a. Dissipation is high since rail to rail current flows when Vin =
logical ‘1’
b. Switching of the output from 1 to 0 begins when Vin exceeds
Vt of PD device.
c. When switching the output from 1 to 0, the PU device is non-
saturated initially and this presents lower resistance through
which to charge capacitive loads.
Rekha S S, Assistant Professor, Dept. of
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ECE, PESU
nMOS enhancement mode pull-up

i. Dissipation is high since current flows when Vin = logical 1 (VGG

is returned to VDD)
ii. Vout can never reach VDD (logical 1) if VGG = VDD as is normally
the case.
iii. VGG may be derived from a switching source, for example, one
phase of a clock, so that dissipation can be greatly reduced.
iv. If VGG is higher than VDD then an extra supply rail is required.
Rekha S S, Assistant Professor, Dept. of
45
ECE, PESU
 Complementary transistor pull-up(CMOS)

CMOS Inverter:
 DC Response: Vout

vs. V for a gate
in
 Ex: Inverter
 When Vin = 0 -> Vout = VDD
 When Vin = VDD -> Vout = 0 VDD
 In between, Vout depends on
Idsp
transistor size and current Vin Vout
 By KCL, must settle such that Idsn
Idsn = |Idsp|
 We could solve equations
 But graphical solution gives more insight

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Transistor Operation

 Current depends on region of transistor behavior
 For what Vin and Vout are nMOS and pMOS in
 Cutoff?
 Linear?
 Saturation?

Rekha S S, Assistant Professor, Dept. of

47
ECE, PESU
 nMOS Operation

Cutoff Linear Saturated
Vgsn < Vgsn > Vgsn >

Vdsn < Vdsn >

VDD

Idsp
Vin Vout
Idsn
Rekha S S, Assistant Professor, Dept. of
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ECE, PESU
 nMOS Operation

Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

VDD

Idsp
Vin Vout
Idsn
Rekha S S, Assistant Professor, Dept. of
49
ECE, PESU
 nMOS Operation

Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

VDD

Vgsn = Vin Idsp

Vin Vout
Vdsn = Vout Idsn
Rekha S S, Assistant Professor, Dept. of
50
ECE, PESU
 nMOS Operation

Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn
VDD

Vgsn = Vin Idsp

Vin Vout
Vdsn = Vout Idsn
Rekha S S, Assistant Professor, Dept. of
51
ECE, PESU
 pMOS Operation

Cutoff Linear Saturated
Vgsp > Vgsp < Vgsp <

Vdsp > Vdsp <

VDD

Idsp
Vin Vout
Idsn
Rekha S S, Assistant Professor, Dept. of
52
ECE, PESU
 pMOS Operation

Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

VDD
Vgsp = Vin - VDD
Vdsp = Vout - VDD Idsp
Vin Vout
Vtp < 0 Idsn
Rekha S S, Assistant Professor, Dept. of
53
ECE, PESU
 pMOS Operation

Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp
VDD
Vgsp = Vin - VDD
Vdsp = Vout - VDD Idsp
Vin Vout
Vtp < 0 Idsn
Rekha S S, Assistant Professor, Dept. of
54
ECE, PESU
 I-V Characteristics
nMOS such that b = b
 Make pMOS is wider than n p

Vgsn5

Vgsn4
Idsn

Vgsn3
-Vdsp
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5 Rekha S S, Assistant Professor, Dept. of

55
ECE, PESU
 Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Load Line Analysis
 For a given V :
 Plot I , I vs. V
dsn
 in
dsp out
VDD

Idsp
Vin Vout
Idsn
Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout
Rekha S S, Assistant Professor, Dept. of
57
ECE, PESU
 Load Line Analysis
 Vin =0 
Vin0

Idsn, |Idsp|

Vin0
VDD
Vout
Rekha S S, Assistant Professor, Dept. of
58
ECE, PESU
 Load Line Analysis

 Vin = 0.2VDD

Vin1
Idsn, |Idsp|

Vin1
VDD
Vout
Rekha S S, Assistant Professor, Dept. of
59
ECE, PESU
 Load Line Analysis

 Vin = 0.4VDD

Idsn, |Idsp|

Vin2
Vin2

VDD
Vout
Rekha S S, Assistant Professor, Dept. of
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ECE, PESU
 Load Line Analysis
 Vin = 0.6V

DD

Idsn, |Idsp|

Vin3
Vin3

VDD
Vout

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Load Line Analysis
 Vin = 0.8V

DD

Vin4
Idsn, |Idsp|

Vin4
VDD
Vout

Rekha S S, Assistant Professor, Dept. of

62
ECE, PESU
 Load Line Analysis
 Vin =V

DD

Vin0 Vin5

Vin1
Idsn, |Idsp|

Vin2
Vin3
Vin4
VDD
Vout

Rekha S S, Assistant Professor, Dept. of

63
ECE, PESU
 Load Line Summary

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 DC Transfer Curve

 Transcribe points onto V vs. V plot
in out

VDD
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3 Vin2 D
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

Rekha S S, Assistant Professor, Dept. of

65
ECE, PESU
 Operating Regions

 Revisit transistor operating regions

VDD

Region nMOS pMOS A B

A Vout
C
B
C
D
E
D 0 Vtn VDD/2 VDD+Vtp
VDD
E Vin

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Operating Regions

VDD
A B

Vout
 Revisit transistor operating regions C

D
Region nMOS pMOS E
0 Vtn VDD/2 VDD+Vtp
A Cutoff Linear VDD
Vin
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Region A

 0  Vin  Vtn
 n-device  Cut-off and p-device  Linear region.
 Idsn = 0 , Idsn = -Idsp
 Idsp = 0

Rekha S S, Assistant Professor, Dept. of

68
ECE, PESU
 Region B
 VTn ≤ Vin ≤ VDD/2
 n-device Saturation

 p-device Linear
 the saturation current Idsn for the n-device

 The current for the p-device

Rekha S S, Assistant Professor, Dept. of

69
ECE, PESU
 Region D
 VDD/2 < Vin < VDD- VTp

 p-device in saturation while n-device is operating in
linear region.
 Idsp = - (bp / 2) (Vin – VDD – Vtp)2
 Idsn = (bn / 2)[ (Vin– Vtn ) Vout – Vout2 / 2 ]

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Region E
 Vin  VDD – Vtp

 p-device is cut-off , Idsp = 0

 n-device is in linear mode

 Vgsp = Vin – VDD

 Vout = 0

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Region C

 In this region both the n- and p-devices are in
saturation.
 Idsp = - (bp / 2) (Vin – VDD – Vtp)2

 Idsn = (bn / 2) (Vin– Vtn)2

With Idsp = -Idsp

By setting Vtn = -Vtp snf bn = bp

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
Region C


Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 At this point bn and bp must be equal

 Then the device geometries must be such that



Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Region C

 Region C exists only for one value of Vin
 The possible values of Vout in this region as follows:
n-channel: Vin-Vout < Vtn
Vout > Vin –Vtn

p- device: Vin-Vout > Vtp

Vout < Vin –Vtp

Vin –Vtn< Vout < Vin –Vtp

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
CMOS Inverter current versus Vin


Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Latch-UP in CMOS Circuits

 Latch up is a condition in which the

parasitic components give rise to
the establishment of low-
resistance conducting path
between Vdd and Vss/GND
with unsuccessful results. Careful
control during
fabrication is required.

Rekha S S, Assistant Professor, Dept. of

ECE, PESU 77
 Remedies for the latch-up problems

 an increase in substrate doping levels with a
consequent drop in the value of Rs
 reducing RP by control of fabrication parameters and
by ensuring a low contact resistance to Vss
 other more elaborate measures such as the
introduction of guard rings.

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Delay-Time Definitions

 The propagation delay times PHL and PLH determine
the input-to-output signal delay during the high-to-
low and low-to-high transitions of the output,
respectively.

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Delay-Time Definitions
 is the time delay
PHL:
between the V 50%

transition of the
rising input voltage
and V50% transition
of the falling output
voltage.
Similarly PLH

Rekha S S, Assistant Professor, Dept. of

80
ECE, PESU
 Delay-Time Definitions

 the input voltage
waveform is usually
assumed to be an
ideal step pulse with
zero rise and fall times.
 PHL becomes the time
required for the output
voltage to fall from VOH to the
V50% level, and
 PLH becomes the time required for the output voltage to rise
from VOL to the V50% level.

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Delay-Time Definitions
V = V + 1/2 (V - V
 The voltage point V50% is defined as follows.
50% OL ) = 1/2( V + V )
OH OL OL OH

PHL = t1 – t0
PLH = t3 – t2

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Components of Energy and Power Switching
Power dissipation in
CMOS circuits 
Dynamic Static
 Dynamic power dissipation is caused by switching
activities of the circuits.
 A higher operating frequency leads to more frequent
switching activities in the circuits and results in increased
power dissipation.
 Static power dissipation is related to the logical states of
the circuits rather than switching activities.
 In CMOS logic, leakage current is the only source of static
power dissipation
Rekha S S, Assistant Professor, Dept. of
83
ECE, PESU
 Dynamic power dissipation

 The most significant source of dynamic power dissipation
in CMOS circuits is Charging and Discharging of
capacitance.
 Sometimes, capacitors are intentionally fabricated to
achieve some non-digital operations like charge sharing
and signal delay.
 But, most of the digital CMOS circuits do not require for
their intended operations.
 The capacitance forms due to parasitic effects of
interconnection wires and transistors.
 Parasitic capacitance cannot be avoided and it has a
significant impact on the power dissipation of the circuits.

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 Charging and discharging 
Output capacitance of a CMOS
Logic gate.
 Switch is used to flip up and down to model the
charging and discharging cycles.
 V is an ideal constant voltage source and Rc (Rd) is
charging (discharging) circuitry, either intentional or
parasitic capacitance.
 According to the laws of physics, the voltage vc(t)
and the current ic(t) of a capacitance CL at time t is
given by
Rekha S S, Assistant Professor, Dept. of
85
ECE, PESU
 During charging cycle from time t0 to t1, energy drawn
from the voltage source is


 Initial capacitor voltage is 0 and assume the capacitor is
fully charged to V.

 Part of the electrical energy Es drawn from the source is

stored in capacitor and rest is dissipated as heat energy in
the resistor Rc.
 The energy stored in the capacitor at the end of the
charging cycle is

 The energy Ec dissipated at Rc during charging is

Rekha S S, Assistant Professor, Dept. of
86
ECE, PESU
 Discharging cycle from t1 to t2
 Assume capacitor is fully discharged to 0.
 Vc(t1) = V , vc(t2) = 0
 The energy Ed dissipated in the discharge resistor Rd
is 
 If capacitor is charged and discharged at the
frequency f cycles per seconds, the power dissipation
of the system is
 The above equation is only the power dissipation
caused by a single capacitor.
 In general, the total power is summed over each
capacitance Ci in a circuit yielding
 Vi is the voltage swing across the capacitor Ci
switching at frequency fi
Rekha S S, Assistant Professor, Dept. of
87
ECE, PESU
 Short-circuit Current in CMOS Circuit


 When the input signal level is above Vtn the N-transistor
is turned ON.
 Similarly, when the signal level is below Vtp the P-
transistor is turned ON.
 When the input signal Vi switches, there is a short
duration in which the input level is between Vtn and Vtp
and both transistors are turned on.
 This causes a short-circuit current from Vdd to ground
and dissipates power.
 The electrical energy drawn from the source is dissipated
as heat in the P and N -transistors.
Rekha S S, Assistant Professor, Dept. of
88
ECE, PESU
Short-circuit Current in CMOS Circuit

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 
 The shape of the short-circuit current curve is
dependent on several factors:
1. The duration and slope of the input signal.
2. The I-V curves of the P and N transistors, which
depend on their sizes, process technology,
temperature, etc.
3. The output loading capacitance of the inverter.

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU
 CMOS Leakage Current

 Leakage current exists as a natural phenomenon of
the semiconductor device operation.
 Leakage is a form of current that is generally not
intended for the normal operation of a digital circuit.
 In circuits that use MOS transistors, there are two
major sources of leakage current:
 1. reverse biased PN-junction current and,
 2. sub-threshold channel conduction current.

Rekha S S, Assistant Professor, Dept. of

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ECE, PESU