TDC_64ps_res2.

vhd Sun Aug 06 10:55:38 2017

1 ----------------------------------------------------------------------------------
2 -- Company: CIEMAT
3 -- Engineer: Jesús Marín
4 --
5 -- Create Date: 15:57:28 04/21/2014
6 -- Design Name: TDC_64ps_res1.vhd
7 -- Module Name: TDC_64ps_res1.vhd - Behavioral
8 -- Project Name: USB_INTERFACE_TDC
9 -- Target Devices: XC6SLX25-CGS324-3C
10 -- Tool versions: ISE 14.5 (64 bits)
11 -- Description: Calculate the time arrival of a signal with aprox. 64ps
resolution.
12 --
13 -- Dependencies: USB_INTERFACE_TDC.vhd
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use ieee.std_logic_unsigned.all;
24
25 -- Uncomment the following library declaration if using
26 -- arithmetic functions with Signed or Unsigned values
27 --use IEEE.NUMERIC_STD.ALL;
28
29 -- Uncomment the following library declaration if instantiating
30 -- any Xilinx primitives in this code.
31
32 library UNISIM;
33 use UNISIM.VComponents.all;
34
35 entity TDC_64ps_res2 is
36 Port ( CH : in STD_LOGIC;
37 CH_test : in STD_LOGIC;
38 RST : in STD_LOGIC;
39 RD_EN : in STD_LOGIC;
40 OSC_SLOW_i : out STD_LOGIC;
41 OSC_FAST_i : in STD_LOGIC;
42 sel_add : in STD_LOGIC_VECTOR(7 downto 0);
43 test : in STD_LOGIC_VECTOR(7 downto 0);
44 ena_test : in STD_LOGIC;
45 TIME_MSB_COUNT : out STD_LOGIC_VECTOR(7 downto 0));
46 end TDC_64ps_res2;
47
48 architecture Behavioral of TDC_64ps_res2 is
49
50 signal carry_in: std_logic_vector(63 downto 0);
51 signal carry_out: std_logic_vector(63 downto 0);
52 signal xor_out: std_logic_vector(63 downto 0);
53 signal phase: std_logic_vector(1 downto 0);
54 signal stop: std_logic;
55 signal pulse_present_slow: std_logic;
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56 signal pulse_present_fast: std_logic;
57 signal count0: std_logic_vector(15 downto 0);
58 signal count1: std_logic_vector(15 downto 0);
59 signal OSC_SLOW: std_logic;
60 --signal OSC_FAST: std_logic;
61
62 --signal carry_out_fast_clk: std_logic_vector(11 downto 0);
63 --signal xor_out_fast_clk: std_logic_vector(11 downto 0);
64 --signal carry_in_fast_clk: std_logic_vector(2 downto 0);
65 --signal CH_i_d: std_logic_vector(7 downto 0);
66 --signal CH_i_dd: std_logic_vector(7 downto 0);
67 --signal CH_i_ddd: std_logic_vector(7 downto 0);
68 --signal ENA_r: std_logic;
69
70 COMPONENT MUX421_GENERIC is
71 generic( width : integer := 8);
72 Port (
73 A : in STD_LOGIC_VECTOR (width-1 downto 0);
74 B : in STD_LOGIC_VECTOR (width-1 downto 0);
75 C : in STD_LOGIC_VECTOR (width-1 downto 0);
76 D : in STD_LOGIC_VECTOR (width-1 downto 0);
77 SEL : in STD_LOGIC_VECTOR (1 downto 0);
78 O : out STD_LOGIC_VECTOR (width-1 downto 0)
79 );
80 END COMPONENT;
81
82 COMPONENT MUX221_GENERIC is
83 generic( width : integer := 8);
84 Port (
85 A : in STD_LOGIC_VECTOR (width-1 downto 0);
86 B : in STD_LOGIC_VECTOR (width-1 downto 0);
87 SEL : in STD_LOGIC_VECTOR (0 downto 0);
88 O : out STD_LOGIC_VECTOR (width-1 downto 0)
89 );
90 END COMPONENT;
91
92 COMPONENT MUX821_GENERIC is
93 generic( width : integer := 8);
94 Port (
95 A : in STD_LOGIC_VECTOR (width-1 downto 0);
96 B : in STD_LOGIC_VECTOR (width-1 downto 0);
97 C : in STD_LOGIC_VECTOR (width-1 downto 0);
98 D : in STD_LOGIC_VECTOR (width-1 downto 0);
99 E : in STD_LOGIC_VECTOR (width-1 downto 0);
100 F : in STD_LOGIC_VECTOR (width-1 downto 0);
101 G : in STD_LOGIC_VECTOR (width-1 downto 0);
102 H : in STD_LOGIC_VECTOR (width-1 downto 0);
103 SEL : in STD_LOGIC_VECTOR (2 downto 0);
104 O : out STD_LOGIC_VECTOR (width-1 downto 0)
105 );
106 END COMPONENT;
107
108 COMPONENT MUX1621_GENERIC is
109 generic( width : integer := 8);
110 Port (
111 A : in STD_LOGIC_VECTOR (width-1 downto 0);
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112 B : in STD_LOGIC_VECTOR (width-1 downto 0);
113 C : in STD_LOGIC_VECTOR (width-1 downto 0);
114 D : in STD_LOGIC_VECTOR (width-1 downto 0);
115 E : in STD_LOGIC_VECTOR (width-1 downto 0);
116 F : in STD_LOGIC_VECTOR (width-1 downto 0);
117 G : in STD_LOGIC_VECTOR (width-1 downto 0);
118 H : in STD_LOGIC_VECTOR (width-1 downto 0);
119 J : in STD_LOGIC_VECTOR (width-1 downto 0);
120 K : in STD_LOGIC_VECTOR (width-1 downto 0);
121 L : in STD_LOGIC_VECTOR (width-1 downto 0);
122 M : in STD_LOGIC_VECTOR (width-1 downto 0);
123 N : in STD_LOGIC_VECTOR (width-1 downto 0);
124 O : in STD_LOGIC_VECTOR (width-1 downto 0);
125 P : in STD_LOGIC_VECTOR (width-1 downto 0);
126 Q : in STD_LOGIC_VECTOR (width-1 downto 0);
127 SEL : in STD_LOGIC_VECTOR (3 downto 0);
128 OUT_MUX : out STD_LOGIC_VECTOR (width-1 downto 0)
129 );
130 END COMPONENT;
131
132 COMPONENT ADDER
133 PORT (
134 a : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
135 c_in : IN STD_LOGIC;
136 c_out : OUT STD_LOGIC;
137 s : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
138 );
139 END COMPONENT;
140
141
142 begin
143
144 --------------
145 -- TDC 64ps --
146 --------------
147
148 --OSC_SLOW
149
150 carry_in(0) <= CH when ena_test = '0' else CH_test;
151
152 FC_U0_delay_01 : CARRY4
153 port map (
154 CO => carry_out(3 downto 0), -- 4-bit carry out
155 O => xor_out(3 downto 0), -- 4-bit carry chain XOR data out
156 CI => carry_in(0), -- 1-bit carry cascade input
157 CYINIT => '0', -- 1-bit carry
initialization
158 DI => "0000", -- 4-bit carry-MUX data in
159 S => "111" & xor_out(55) --(63) -- 4-bit
carry-MUX select input
160 );
161
162 LOOP_01:
163 for i in 1 to 15 generate -- was 15
164 begin
165 carry_in(i) <= carry_out(4*i-1);
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TDC_64ps_res2.vhd Sun Aug 06 10:55:38 2017
166 end generate;
167
168 CARRY_DELAY_00:
169 for i in 1 to 15 generate -- was 15
170 begin
171 FC_U0_delay_11 : CARRY4
172 port map (
173 CO => carry_out(4*i + 3 downto 4*i + 0), -- 4-bit carry out
174 O => xor_out(4*i + 3 downto 4*i + 0), -- 4-bit carry chain XOR
data out
175 CI => carry_in(i), -- 1-bit carry cascade input
176 CYINIT => '0', -- 1-bit carry
initialization
177 DI => "0000", -- 4-bit carry-MUX data in
178 S => "1111" -- 4-bit carry-MUX select
input
179 );
180 end generate;
181
182 OSC_SLOW_i <= carry_out(0); --(31)
183 OSC_SLOW <= carry_out(0); --(31)
184
185 process(OSC_SLOW, RST)
186 begin
187 if RST = '1' then
188 pulse_present_slow <= '0';
189 elsif OSC_SLOW'event and OSC_SLOW = '1' then
190 pulse_present_slow <= '1';
191 end if;
192 end process;
193
194 process (OSC_FAST_i, RST)
195 begin
196 if RST = '1' then
197 phase(1 downto 0) <= "00";
198 stop <= '0';
199 elsif OSC_FAST_i'event and OSC_FAST_i = '1' then
200 if pulse_present_slow = '1' then
201 phase(0) <= OSC_SLOW;
202 phase(1) <= phase(0);
203 else
204 phase(1 downto 0) <= phase(1 downto 0);
205 end if;
206 if phase(1 downto 0) = "10" then
207 stop <= '1';
208 else
209 stop <= stop;
210 end if;
211 end if;
212 end process;
213
214 process(OSC_SLOW, RST)
215 begin
216 if RST = '1' then
217 count0(15 downto 0) <= (others => '0');
218 elsif OSC_SLOW'event and OSC_SLOW = '1' then
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219 if stop = '0' then
220 count0(15 downto 0) <= count0(15 downto 0) + 1;
221 else
222 count0(15 downto 0) <= count0(15 downto 0);
223 end if;
224 end if;
225 end process;
226
227 process(OSC_FAST_i, RST)
228 begin
229 if RST = '1' then
230 count1(15 downto 0) <= (others => '0');
231 elsif OSC_FAST_i'event and OSC_FAST_i = '1' then
232 if pulse_present_slow = '1' and stop = '0' then
233 count1(15 downto 0) <= count1(15 downto 0) + 1;
234 else
235 count1(15 downto 0) <= count1(15 downto 0);
236 end if;
237 end if;
238 end process;
239
240
241 MUX_OF_TIME_1 : MUX421_GENERIC
242 generic map( width => 8)
243 port map (
244 A => count0(7 downto 0),
245 B => count0(15 downto 8),
246 C => count1(7 downto 0),
247 D => count1(15 downto 8),
248 -- E => CH_i_ddd(39 downto 32),
249 -- F => CH_i_ddd(47 downto 40),
250 -- G => CH_i_ddd(55 downto 48),
251 -- H => CH_i_ddd(63 downto 56),
252 ---- J => CH_i_ddd(71 downto 64),
253 ---- K => CH_i_ddd(79 downto 72),
254 ---- L => CH_i_ddd(87 downto 80),
255 ---- M => CH_i_ddd(95 downto 88),
256 ---- N => CH_i_ddd(103 downto 96),
257 ---- O => CH_i_ddd(111 downto 104),
258 ---- P => CH_i_ddd(119 downto 112),
259 ---- Q => CH_i_ddd(127 downto 120),
260 SEL => sel_add(1 downto 0),
261 O => TIME_MSB_COUNT(7 downto 0) --OUT_MUX => TIME_MSB_COUNT(7 downto 0)
262 );
263
264 end Behavioral;
265
266

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