STA518

40 V, 3.5 A quad power half-bridge

Datasheet - production data

Description
The STA518 is a monolithic quad half-bridge
stage in multipower BCD technology. The device
can be used also as dual bridge or reconfigured,
by connecting the CONFIG pin to the Vdd pin, as
a single bridge with double current capacity.
The device is particularly designed to make the
output stage of a stereo all-digital high-efficiency
(DDX™) amplifier capable of delivering an output
power of 24 W x 4 channels @ THD = 10% at
PowerSSO36 VCC 30 V into a 4  load in single-ended
with exposed pad (or slug) up configuration.
It can also deliver 50 + 50 W @ THD = 10% at
VCC 29 V as output power into an 8 load in BTL
configuration and 70 W @ THD = 10% at VCC
Features 34 V into 8 in a single paralleled BTL
 Multipower BCD technology configuration.

 Minimum input output pulse width distortion The input pins have a threshold proportional to
the VL pin voltage.
 200 m RdsON complementary DMOS output
stage
 CMOS-compatible logic inputs
 Thermal protection
 Thermal warning output
 Undervoltage protection
 Short-circuit protection

Table 1. Device summary

Order code Temperature range °C Package Packaging

STA51813TR -40 to 90 PowerSSO36 (slug up) Tape & reel

September 2014 DocID010708 Rev 6 1/21

This is information on a product in full production. www.st.com
Contents STA518

Contents

1 Audio application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Technical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Logic interface and decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Parallel output / high current operation . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/21 DocID010708 Rev 6

STA518 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. VLOW, VHIGH variation with Ibias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Logic truth table (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. PowerSO36 exposed pad up dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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21
List of figures STA518

List of figures

Figure 1. Audio application circuit (quad single-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Low-current dead time for single-ended application: test circuit. . . . . . . . . . . . . . . . . . . . . 11
Figure 4. High-current dead time for bridge application: block diagram. . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. High-current dead time for bridge application: test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. STA518 block diagralm full-bridge DDX® or binary modes . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. STA518 bock diagram binary half-bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Typical stereo full-bridge configuration to obtain 50 + 50 W @ THD = 10%, RL = 8 ,
VCC = 29 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Typical single BTL configuration to obtain 70 W @ THD 10%, RL = 8 , VCC = 34 V . . . 14
Figure 10. Power dissipation vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. THD+N vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. THD+N vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. Power dissipation vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 18. THD+N vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 19. PSSO36 (slug up) mechanical outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4/21 DocID010708 Rev 6

 1
STA518

VCC1P +VCC

15
IN1A 29 M3 R61 C21
IN1A 5K C31 820μF 2200μF
17 L11 22μH
VL 23
+3.3V OUTPL
CONFIG 24 16 R41 C71
20 100nF
OUTPL C91 4Ω
PWRDN PWRDN 25 M2 1μF
14 PGND1P R51 C81 R62
PROTECTIONS C41 100nF
6 5K
R57 R59 FAULT 27 & 330pF
10K 10K LOGIC
26 12 VCC1N
TRI-STATE
C58 M5 C51 C61
100nF 11 1μF 100nF
R63
TH_WAR 28 OUTNL 5K C32 820μF
TH_WAR 10 L12 22μH
IN1B 30 OUTNL
IN1B R42 C72
M4 20 100nF
VDD 21 13 PGND1N C92 4Ω
1μF
Audio application circuit

VDD 22 R52 C82 R64

C42 100nF
6 5K
VSS 33 REGULATORS 330pF
7 VCC2P
VSS 34

DocID010708 Rev 6
M17 R65
C58 C53 C33 820μF
L13 22μH 5K
100nF 100nF VCCSIGN 8
35
OUTPR
C60 9 R43 C73
100nF VCCSIGN 20 100nF
36 OUTPR C93 4Ω
M15 1μF
IN2A 6 PGND2P R53 C83 R66
IN2A 31 C43 100nF
6 5K
330pF
GND-Reg
20 4 VCC2N
GND-Clean
19 M16 C52 C62
3 1μF 100nF
R67
OUTNR 5K C34 820μF
IN2B 2 L14 22μH
Figure 1. Audio application circuit (quad single-ended)

IN2B 32
OUTNR
R44 C74
GNDSUB M14 20 100nF
1 5 PGND2N C94 4Ω
1μF
R54 C84 R68
C44 100nF
6 5K
330pF
D03AU1474

5/21
Audio application circuit

21
Pin description STA518

2 Pin description

Figure 2. Pin connections (top view)

VCCSign 36 1 GND-SUB
VCCSign 35 2 OUT2B
VSS 34 3 OUT2B
VSS 33 4 VCC2B
IN2B 32 5 GND2B
IN2A 31 6 GND2A
IN1B 30 7 VCC2A
IN1A 29 8 OUT2A
TH_WAR 28 9 OUT2A
FAULT 27 10 OUT1B
TRI-STATE 26 11 OUT1B
PWRDN 25 12 VCC1B
CONFIG 24 13 GND1B
VL 23 14 GND1A
VDD 22 15 VCC1A
VDD 21 16 OUT1A
GND-Reg 20 17 OUT1A
GND-Clean 19 18 N.C.

D01AU1273

Table 2. Pin function

Pin n° Name Description

1 GND-SUB Substrate ground

2, 3 OUT2B Output half-bridge 2B
4 Vcc2B Positive supply
5 GND2B Negative supply
6 GND2A Negative supply
7 Vcc2A Positive supply
8, 9 OUT2A Output half-bridge 2A
10, 11 OUT1B Output half-bridge 1B
12 Vcc1B Positive supply
13 GND1B Negative supply
14 GND1A Negative supply
15 Vcc1A Positive supply
16, 17 OUT1A Output half-bridge 1A
18 NC Not connected

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STA518 Pin description

Table 2. Pin function (continued)

Pin n° Name Description

19 GND-clean Logical ground

20 GND-Reg Ground for regulator Vdd
21, 22 Vdd 5 V regulator referred to ground
23 VL Logic reference voltage
24 CONFIG Configuration pin
25 PWRDN Short-circuit pin
26 TRI-STATE Hi-Z pin
27 FAULT Fault pin advisor
28 TH_WAR Thermal warning advisor
29 IN1A Input of half-bridge 1A
30 IN1B Input of half-bridge 1B
31 IN2A Input of half-bridge 2A
32 IN2B Input of half-bridge 2B
33, 34 Vss 5 V regulator referred to +VCC
35, 36 VCC Sign Signal positive supply

Table 3. Functional pin status

Pin name Pin n° Logical value IC - status

FAULT 27 0 Fault detected (short-circuit, or thermal)

FAULT * 27 1 Normal operation
TRI-STATE 26 0 All powers in Hi-Z state
TRI-STATE 26 1 Normal operation
PWRDN 25 0 Low consumption
PWRDN 25 1 Normal operation
TH_WAR 28 0 Temperature of the IC = 130 °C
(1)
TH_WAR 28 1 Normal operation
1. The pin is an open collector. To have a high logic value, it needs to be pulled up by a resistor.

DocID010708 Rev 6 7/21

21
Electrical specifications STA518

3 Electrical specifications

3.1 Absolute maximum ratings

Table 4. Absolute maximum ratings
Symbol Parameter Value Unit

VCC DC supply voltage (pin 4, 7, 12, 15) 40 V

Vmax Maximum voltage on pins 23 to 32 5.5 V
Top Operating temperature range -40 to 90 °C
Ptot Power dissipation (Tcase = 70 °C) 21 W
Tstg, Tj Storage and junction temperature -40 to 150 °C

3.2 Recommended operating conditions

Table 5. Recommended operating conditions (1)
Symbol Parameter Min. Typ. Max. Unit

VCC DC supply voltage 10 36.0 V

VL Input logic reference 2.7 3.3 5.0 V
Tamb Ambient temperature 0 70 °C
1. Performance not guaranteed beyond recommended operating conditions

3.3 Thermal data

Table 6. Thermal data (1)
Symbol Parameter Min. Typ. Max. Unit

Tj-case Thermal resistance junction to case (thermal pad) 1.5 °C/W

TjSD Thermal shut-down junction temperature 150 °C
Twarn Thermal warning temperature 130 °C
thSD Thermal shut-down hysteresis 25 °C
1. See thermal information

3.4 Thermal information

The power dissipated within the device depends primarily on the supply voltage, load
impedance and output modulation level. The PSSO36 package of the STA518 includes an
exposed thermal slug on the top of the device to provide a direct thermal path from the IC to
the heatsink. For the quad single-ended application the dissipated power vs. output power is
shown in Figure 10.

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STA518 Electrical specifications

Considering that for the STA518 the thermal resistance junction to slug is 1.5 °C/W and the
estimated thermal resistance due to the grease placed between slug and heat sink is
2.3 °C/W (the use of thermal pads for this package is not recommended), the suitable heat
sink Rth to be used can be drawn from the following graph Figure 11, where is shown the
derating power vs. tamb for different heat sinks.

3.5 Electrical characteristics

Refer to the circuit in Figure 3 (VL = 3.3 V; VCC = 30 V; RL = 8 ; fsw = 384 kHz; Tamb = 25
°C unless otherwise specified)

Table 7. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

Power P-channel / N-channel

RdsON Id = 1 A 200 270 m
MOSFET RdsON
Power P-channel / N-channel
Idss VCC = 35 V 50 μA
leakage Idss
Power P-channel RdsON
gN Id = 1 A 95 %
matching
Power N-channel RdsON
gP Id = 1 A 95 %
matching
Dt_s Low current dead time (static) see test circuit Figure 3 10 20 ns
L = 22 μH; C = 470 nF; RL = 8 
Dt_d High current dead time (dynamic) 50 ns
Id = 3 A; seeFigure 5
td ON Turn-on delay time Resistive load; VCC = 30 V 100 ns
td OFF Turn-off delay time Resistive load; VCC = 30 V 100 ns
tr Rise time 25 ns
Resistive load; as Figure 3
tf Fall time 25 ns
VCC Supply voltage operating voltage 10 36 V
VL/2
VIN-H High-level input voltage V
+300mV
VL/2 -
VIN-L Low-level input voltage V
300mV
IIN-H High-level input current Pin voltage = VL 1 A
IIN-L Low-level input current Pin voltage = 0.3 V 1 A
High-level PWRDN pin input
IPWRDN-H VL = 3.3 V 35 A
current
Low logical state voltage VLOW
VLOW VL = 3.3 V 0.8 V
(pin PWRDN, TRISTATE) (1)
High logical state voltage VHIGH
VHIGH VL = 3.3 V 1.7 V
(pin PWRDN, TRISTATE) (1)
IVCC- Supply current from VCC in power
PWRDN = 0 3 mA
PWRDN down

DocID010708 Rev 6 9/21

21
Electrical specifications STA518

Table 7. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Output current pins

IFAULT FAULT, TH_WAR when Vpin = 3.3 V 1 mA
fault conditions
Supply current from VCC in Tri-
IVCC-hiz VCC = 30 V; Tri-state = 0 22 mA
state
VCC = 30V;
Supply current from VCC in
Input pulse width = 50% Duty;
IVCC operation 50 mA
Switching frequency = 384 kHz;
(both channels switching)
No LC filters;
IVCC-q Isc (short-circuit current limit) (2) VCC = 30 V 3.5 6 A
Undervoltage protection
VUV 7 V
threshold
tpw_min Output minimum pulse width No load 70 150 ns
1. Table 8 explains the VLOW, VHIGH variation with Ibias.
2. See relevant Application Note AN1994

Table 8. VLOW, VHIGH variation with Ibias

VL VLow min VHigh max Unit

2.7 0.7 1.5 V

3.3 0.8 1.7 V
5 0.85 1.85 V

Table 9. Logic truth table (see Figure 4)

Output
TRI-STATE INxA INxB Q1 Q2 Q3 Q4
mode

0 x x OFF OFF OFF OFF Hi-Z

1 0 0 OFF OFF ON ON DUMP
1 0 1 OFF ON ON OFF NEGATIVE
1 1 0 ON OFF OFF ON POSITIVE
1 1 1 ON ON OFF OFF Not used

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STA518 Electrical specifications

Figure 3. Low-current dead time for single-ended application: test circuit

OUTxY
Vcc

(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc

(1/4)Vcc
+Vcc

t
Duty cycle = 50% DTr DTf
M58
OUTxY R 8Ω
INxY

M57 +
-
V67 =
vdc = Vcc/2
gnd
D03AU1458

Figure 4. High-current dead time for bridge application: block diagram

+VCC

Q1 Q2
OUTxA OUTxB
INxA INxB

Q3 Q4

GND
D00AU1134

Figure 5. High-current dead time for bridge application: test circuit

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

+VCC

Duty cycle=A Duty cycle=B

DTout(A)

M58 Q1 Q2 M64
DTin(A) DTout(B) DTin(B)
OUTA Rload=8Ω OUTB
INA INB
L67 22μ L68 22μ
Iout=4.5A Iout=4.5A
M57 Q3 C69 C70 Q4 M63
470nF C71 470nF 470nF

Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure D03AU1517

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21
Technical information STA518

4 Technical information

The STA518 is a high-efficiency dual-channel H-Bridge that is able to deliver 50 W per

channel (@ THD = 10% RL = 8 , VCC = 29 V) of audio output power.
The STA518 converts both DDX and binary-controlled PWM signals into audio power at the
load. It includes a logic interface, integrated bridge drivers, high-efficiency MOSFET outputs
and thermal and short-circuit protection circuitry.
In DDX mode, two logic level signals per channel are used to control high-speed MOSFET
switches to connect the speaker load to the input supply or to ground in a bridge
configuration, according to the damped ternary modulation operation.
In binary mode operation, both full-bridge and half-bridge modes are supported. The
STA518 includes overcurrent and thermal protection as well as an undervoltage lockout with
automatic recovery. A thermal warning status is also provided.

Figure 6. STA518 block diagram full-bridge DDX® or binary modes

INL 1:2 OUTPL

INR 1:2 Left
Logic I/F
VL
and Decode H-Bridge
PWRDN OUTNL
TRI-STATE

FAULT Protection OUTPR

TWARN Circuitry
Right
H-Bridge
Regulators OUTNR

Figure 7. STA518 block diagram binary half-bridge mode

INL 1:2 LeftA OUTPL
INR 1:2 Logic I/F -Bridge
VL and Decode
PWRDN LeftB OUTNL
TRI-STATE -Bridge

FAULT Protection RightA OUTPR

TWARN Circuitry -Bridge

RightB
Regulators OUTNR
-Bridge

4.1 Logic interface and decode

The STA518 power outputs are controlled using one or two logic level timing signals. In
order to provide a proper logic interface, the Vbias input must operate at the same voltage as
the DDX control logic supply.
Protection circuitry:
The STA518 includes protection circuitry for overcurrent and thermal overload conditions. A
thermal warning pin (pin 28) is activated low (open-drain MOSFET) when the IC

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STA518 Technical information

temperature exceeds 130 °C, in advance of the thermal shutdown protection. When a fault
condition is detected, an internal fault signal acts to immediately disable the output power
MOSFETs, placing both H-Bridges in high impedance state. At the same time an open-drain
MOSFET connected to the FAULT pin (pin 27) is switched on.
There are two possible modes subsequent to activating a fault:
1. SHUTDOWN mode: with FAULT (pull-up resistor) and TRI-STATE pins independent,
an activated fault will disable the device, signaling low at the FAULT output.
The device may subsequently be reset to normal operation by toggling the TRI-STATE
pin from high to low to high using an external logic signal.
2. AUTOMATIC recovery mode: This is shown in the audio application circuit of quad
single-ended. The FAULT and TRI-STATE pins are shorted together and connected to
a time constant circuit comprising R59 and C58.
An activated FAULT will force a reset on the TRI-STATE pin causing normal operation
to resume following a delay determined by the time constant of the circuit.
If the fault condition is still present, the circuit operation will continue repeating until the
fault condition is removed.
An increase in the time constant of the circuit will produce a longer recovery interval.
Care must be taken in the overall system design as not to exceed the protection
thresholds under normal operation.

4.2 Power outputs

The STA518 power and output pins are duplicated to provide a low impedance path for the
device's bridged outputs. All duplicate power, ground and output pins must be connected for
proper operation.
The PWRDN or TRI-STATE pins should be used to set all MOSFETS to the Hi-Z state
during power-up until the logic power supply, VL, is settled.

4.3 Parallel output / high current operation

When using DDX mode output, the STA518 outputs can be connected in parallel in order to
increase the output current capability to a load. In this configuration the STA518 can provide
70 W into 8 ohm.
This mode of operation is enabled with the CONFIG pin (pin 24) connected to VREG1 and
the inputs combined INLA=INLB, INRA=INRB and the outputs combined OUTLA=OTLB,
OUTRA=OUTRB.

4.4 Additional information

Output Filter: A passive 2nd order passive filter is used on the STA518 power outputs to
reconstruct an analog audio signal. System performance can be significantly affected by the
output filter design and choice of passive components. A filter design for 6 ohm / 8 ohm
loads is shown in the typical application circuit of Figure 9.
Quad single-ended circuit (Figure 1) shows a filter for half-bridge mode, 4 ohm loads.

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21
Technical information STA518

Figure 8. Typical stereo full-bridge configuration to obtain 50 + 50 W @ THD = 10%,

RL = 8 , VCC = 29 V
VCC1A +VCC

15
IN1A 29 M3 C30 C55
IN1A 1μF 1000μF
17 L18 22μH
VL 23
+3.3V OUT1A
CONFIG 24 16 C20
100nF
OUT1A
PWRDN PWRDN 25 M2 C52
14 GND1A 330pF R98 C99
PROTECTIONS 6 100nF
R57 R59 FAULT 27 & C23 8Ω
10K 10K LOGIC
26 12 VCC1B 470nF
R63 R100 C101
TRI-STATE
C58 M5 C31 20 6 100nF
100nF 11 1μF
C21
TH_WAR 28 OUT1B 100nF
TH_WAR 10
IN1B 30 OUT1B L19 22μH
IN1B
M4
VDD 21 13 GND1B
VDD 22
VSS 33 REGULATORS
7 VCC2A
VSS 34
M17 C32
C58 C53 1μF
100nF 100nF VCCSIGN 8 L113 22μH
35
OUT2A
C60 9 C110
100nF VCCSIGN 100nF
36 OUT2A
M15 C109
IN2A 6 GND2A 330pF R103 C107
IN2A 31 6 100nF
GND-Reg C108 8Ω
20 4 VCC2B 470nF
R104 R102
GND-Clean C106
C33 20 6
19 M16 100nF
3 1μF
C111
OUT2B 100nF
IN2B 2
IN2B 32
OUT2B L112 22μH
GNDSUB M14
1 5 GND2B

D00AU1148B

Figure 9. Typical single BTL configuration to obtain 70 W @ THD 10%, RL = 8 ,

VCC = 34 V(a)
VL
+3.3V 23 18 N.C.
100nF 22μH
GND-Clean 17
19 OUT1A
16 100nF
GND-Reg OUT1A FILM
20
10K 100nF 11
OUT1B 22Ω 6.2 100nF
X7R VDD 10 X7R
1/2W 1/2W
21 OUT1B
VDD 470nF 8Ω
22 OUT2A FILM
CONFIG 9 6.2
24 OUT2A 330pF 100nF
1/2W
8 X7R
TH_WAR
TH_WAR 28 OUT2B 100nF
3 FILM
PWRDN OUT2B
nPWRDN 25 2
22μH
10K FAULT
27 VCC1A
15 32V
26
TRI-STATE 1μF 2200μF
100nF X7R 63V
IN1A VCC1B
29 12
IN1B
IN1A 30
IN2A VCC2A
31 7 32V
IN2B
IN1B 32 1μF
X7R
VSS VCC2B
33 4
VSS
34 GND1A
100nF 14
X7R VCCSIGN GND1B
35 13

100nF VCCSIGN GND2A

X7R 36 6
Add. GNDSUB GND2B
1 5
D04AU1549

a. A PWM modulator as driver is needed. In particular, this result is achieved using the STA308 + STA518 +
STA50X demo board. Peak Power for t  1sec.

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STA518 Characterization curves

5 Characterization curves

The following characterization curves are obtained using the quad single-ended
configuration (Figure 1) with an STA308A controller.

Figure 10. Power dissipation vs. output power Figure 11. Power derating curve

Figure 12. THD+N vs. output power Figure 13. Output power vs. supply voltage

Figure 14. THD vs. frequency

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Characterization curves STA518

The following characterizations are obtained using the stereo full-bridge configuration
(Figure 8) with STA308A controller.

Figure 15. Output power vs. supply voltage Figure 16. THD+N vs. output power

Figure 17. Power dissipation vs. output power

The following characterization is obtained using a single BTL configuration (Figure 9) with
the STA308A controller.

Figure 18. THD+N vs. output power

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STA518 Package information

6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

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 Figure 19. PSSO36 (slug up) mechanical outline

STA518
DocID010708 Rev 6

Package information
7618147_F
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STA518 Package information

Table 10. PowerSO36 exposed pad up dimensions

Dimensions in mm. Dimensions in inch.
Symbol
Min. Typ. Max. Min. Typ. Max.

A 2.15 - 2.45 0.085 - 0.096

A2 2.15 - 2.35 0.085 - 0.092
a1 0 - 0.1 0.00 - 0.004
b 0.18 - 0.36 0.007 - 0.014
c 0.23 - 0.32 0.009 - 0.013
D 10.10 - 10.50 0.398 - 0.413
E 7.4 - 7.6 0.291 - 0.299
e - 0.5 - - 0.020 -
e3 - 8.5 - - 0.335 -
F - 2.3 - - 0.091 -
G - - 0.1 - - 0.004
H 10.1 - 10.5 - - 0.413
h - - 0.4 - - 0.016
k 0 deg - 8 deg 0 deg - 8 deg
L 0.55 - 0.85 0.022 0.033
M - 4.3 - - 0.169 -
N - - 10 deg - - 10 deg
O - 1.2 - - 0.047 -
Q - 0.8 - - 0.031 -
S - 2.9 - - 0.114 -
T - 3.65 - - 0.114 -
U - 1.0 - - 0.039 -

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Revision history STA518

7 Revision history

Table 11. Document revision history

Date Revision Changes

19-Aug-2004 1 Initial release.

11-Nov-2004 2 Changed symbol in “Electrical Characteristics”.
Changed operating temperature range value to -40 to 90°C
18-May-2006 3
(seeTable 4).
26-Feb-2014 4 Updated order code Table 1 on page 1.
11-Jul-2014 5 Updated figure in cover page.
Updated package information (Figure 19, Table 10, and cover page)
16-Sep-2014 6
Minor textual updates

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STA518

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© 2014 STMicroelectronics – All rights reserved

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