Integrated System Design: UEC749

Topic: Basic Digital Circuits

Dr. Sujit K Patel

Assistant Professor, ECED
Lecture : 1
 VHDL: Very High Speed Integrated Circuit
Hardware Description Language
• Industry standard language to describe hardware

• Originated from work in 70’s & 80’s by the U.S. DoD.

• In 1986, VHDL was proposed as an IEEE standard, and in

1987, it was adopted as the IEEE 1076 standard
VHDL Lexical Elements
Cont’d…
VHDL Lexical Elements
VHDL reserved words: They are identifiers reserved in the VHDL language for a special
purpose. They cannot be used as explicitly declared identifiers.

•access •else •new •return

•after •elsif •next •select
•alias •end •nor •severity
•all •entity •not •signal
•and •exit •null •subtype
•architecture •file •of •then
•array •for •on •to
•assert •function •open •tansport
•attribute •generate •or •type
•begin •generic •others •units
•abs •guarded •out •until
•block •if •package •use
•body •in •port •variable
•buffer •inout •procedure •wait
•bus •is •process •when
•case •label •range •with
•component •library •record •xor
•configuration •linkage •register •downto
•constant •loop •rem •Mod
•disconnect •map •report
VHDL Lexical Elements
VHDL Lexical Elements
VHDL Lexical Elements
VHDL Lexical Elements
VHDL Lexical Elements
VHDL Lexical Elements
VHDL Lexical Elements
 List of reserved operators in VHDL

= Equality operator
/= Inequality operator
:= The assignment operator for variables
< The “less than” operator
<= “less than or equal to” when used in an expression on scalar types & array
The assignment operator
> The “greater than” operator
>= The “greater than or equal to” operator
+ The addition operator
- The subtraction operator
* The multiplication operator
/ The division operator
** The exponentiation operator
& The concatenation operator
Operator Precedence
Some
The Interface keywords (reserved words)

entity OR_2 is the header

comment line -- Input/output ports name of the

design (identifier)

port Port declaration

type
(A, B : in BIT; type

Z : out BIT);
identifier

end OR_2 ; optional

entity declaration terminates statements

The Body
Name of the architecture any legal identifier
Association of
architecture

header architecture DATA_FLOW of OR_2 is

header
begin declaration part

Statement Part
Z <= A or B ;

end DATA_FLOW ;

Closes Body declaration (architecture)

architecture
optional
 The operators
Logical operator

Z <= A or B ; End of assignment

Assignment do not forget the ;

operator
Signal assignment statement

and
Other operators:
or *** “Anytime the input signal A and or B changes value the
xor signal assignment statement executes and computes a new
value for the output signal. ” This is called “ Signal
xnor Transformation.”
nand
nor
not
 VHDL Program Skelton
library ieee; use ieee.std_logic_1164.all;
entity XOR_2 is
Port (A,B : in BIT; Z : out BIT);

end XOR_2;

-- Body
architecture DATA_FLOW of XOR_2 is

Reserved word signal Sig 1, Sig 2: BIT ;

Signal Declaration
begin
Sig 1 <= A and not B;
Sig 2 <= B and not A;
Z <=Sig1 or Sig 2;

end DATA_FLOW;
 Libraries (Predefined)

There are two pre-defined libraries in VHDL:

STD
The standard IEEE library that holds many predefined types
such as BIT. Many of these types are used almost like a
reserved word because they are already predefined in the STD
library.

WORK
The working library into which design units are presently
being analyzed are stored. (ie. design entities).
 Libraries (Predefined)

Analysis means checking the syntax and symantic of a design

entity statically.
Simulate means checking the behaviour of the modelled entity
dynamically.
 Library

• Library files have commonly used packages and entities in

your design.

• A VHDL package file contains common design elements that

you can use in the VHDL file source files that make up design.

• IEEE created the IEEE VHDL library and std_logic type in

standard 1164.

• Parts of the IEEE library can be included in an entity by

inserting lines like these before your entity declaration
 Library

Ex. library ieee;

use ieee.std_logic_1164.all; most case
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;
 VHDL Format : Library

• std_logic_1164: defines the basic std_logic data type and a

few functions

• std_logic data types

‘0’ : logic 0 ‘1’ : logic 1
‘-’ : Don’t care 'U': uninitialized,
'X': unknown
'Z': High Impedance
'W': Weak signal, can't tell if it should be 0 or 1.
'L': Weak signal that should probably go to 0
‘H': Weak signal that should probably go to 1

• Logic function
– and, nand, or, nor, xor, xnor, not
 VHDL Format : Library

Ex. signal s1, s2 : std_logic;

•••
variable v1, v2 : std_logic;
•••
s1 <= ‘0’;
v1 := ‘1’;
s2 <= ‘X’;
wait for 10 ns;
s2 <= s1 and v1; -- ‘0’
v2 := s1 or v1; -- ‘1’
 Library
• std_logic_arith: defines some types and basic arithmetic
operations for representing integers in standard ways a
few functions

Arithmetic functions : +, -, *
Comparison functions : <, >, <=, >=, =, /= and etc.

Example: signal u1, u2 : unsigned (3 downto 0);

signal s1 : signed (3 downto 0);
signal s2 : signed (4 downto 0);
•••
signal v2 : std_logic_vector (4 downto 0);
u1 <= “1001”; -- = 9
s1 <= “1001”; -- = -7
•••
wait for 10 ns;
s2 <= u1 + s1; -- = 2
v2 := u1 + s1; -- = “0010”
 Library
• std_logic_unsigned: defines all of the same arithmatic (+, -, *),
compaison (<, <=, >, >=, =, /=) and shift (shl, shr) operations
as the std_logic_arith library.

• Difference is that the extensions will std_logic_vector values

as arguments and them as unsigned integers.

↔ std_logic_signed

Ex. signal u1, u2 : unsigned (3 downto 0);

signal s1 : signed (3 downto 0);
signal s2 : signed (4 downto 0);
•••
signal v2 : std_logic_vector (4 downto 0);
u1 <= “1001”; -- = 9
s1 <= “1001”; -- = -7
•••
Lecture : 2
 Entity
• Specifies the name of entity, the port of the entity and entity-
related information.

Entity name Port names Port type

Semicolon

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
No Semicolon
z : OUT STD_LOGIC after last port
);
END nand_gate;

Port modes (data flow directions)

Reserved words
 Architecture
• Architecture describes functionality of the system

• Architecture is used to define the interconnections and relations

between inputs and outputs of the system

Ex. ARCHITECTURE dataflow of mux4 IS

SIGNAL select : INTEGER;
BEGIN
select <= 0 WHEN A = ‘0’ AND B = ‘0’ ELSE
1 WHEN A = ‘1’ AND B = ‘0’ ELSE
2 WHEN A = ‘0’ AND B = ‘1’ ELSE
3;
Q <= i0 AFTER 0.5 NS WHEN select = 0 ELSE
i1 AFTER 0.5 NS WHEN select = 1 ELSE
i2 AFTER 0.5 NS WHEN select = 2 ELSE
i3 ;
END dataflow
 VHDL Design Styles

VHDL Design
Styles

BEHAVIORAL

DATAFLOW STRUCTURAL NON-

SYTHESIZABLE
SYNTHESIZABLE

“concurrent” components and “sequential” statements

statements interconnects • State machines • Test Benches
• Registers • Modeling IP

VHDL subset most suitable for synthesis

Example: 3-Input XOR Gate
 Entity Declaration of XOR3

• Same for all architectures

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY xor3 IS
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
C : IN STD_LOGIC;
Result : OUT STD_LOGIC
);
END xor3;
 1. Data Flow Description

• Describes how data moves through the system and the various
processing steps.
– Dataflow uses series of concurrent statements to realize logic.
– Dataflow is most useful style when series of Boolean equations
can represent a logic  used to implement simple
combinational logic

• Concurrent statements are evaluated at the same time; thus, the

order of these statements doesn’t matter
– This is not true for sequential/behavioral statements
This order…
U1_out <= A XOR B;
Result <= U1_out XOR C;
Is the same as this order…
Result <= U1_out XOR C;
U1_out <= A XOR B;
 2. Structural Description

ARCHITECTURE structural OF xor3 IS

SIGNAL U1_OUT: STD_LOGIC;
A
COMPONENT xor2 IS
PORT( B XOR3 Result
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC; C
Y : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
I1
U1: xor2 PORT MAP ( I1 => A, Y
I2 => B, I2
Y =>
U1_OUT);
U2: xor2 PORT MAP ( I1 => U1_OUT,
XOR2
I2 => C,
Y => U1_OUT
Result); A
END structural; B RESULT
C

XOR3
 Cont’d…

• Structural design is the simplest to understand. This style is the closest to

schematic capture and utilizes simple building blocks to compose logic
functions.

• Components are interconnected in a hierarchical manner.

• Structural descriptions may connect simple gates or complex, abstract

components.

• Structural style is useful when expressing a design that is naturally

composed of sub-blocks.
 3. Behavioral Architecture

ARCHITECTURE behavioral OF xor3 IS

BEGIN

PROCESS (A,B,C)
BEGIN
IF ((A XOR B XOR C) = '1') THEN
Result <= '1';
ELSE
Result <= '0';
END IF;
END PROCESS;
END behavioral;
 Test Bench your Model

• Testing a design by simulation

• Use a test bench model

– a Model that uses your Model
– apply test sequences to your inputs
– monitors values on output signals using simulator
 Simulation Algorithm

• Initialization phase
– each signal is given its initial value
– for each process
• activate
• execute until a wait statement, then suspend
 Simulation Model for Half Adder
VHDL Model of HA VHDL Test bench Model for HA
Lecture : 3
 VHDL Data Types

• All declaration of VHDL ports, signals, and variables must

specify their corresponding type or subtype

• Example: signal A,B: std_logic;

 VHDL Data Types

Types

Composite
Access
Scalar
Array Record

Integer Real Enumerated Physical

 VHDL Data Types: Integer data type

• Variables and signals of type integer can only be assigned integers

within a simulator-specific range.

• In the above example, the first two variable assignments are valid
since they assign integers to variables of type integer.

• The last variable assignment is illegal because it attempts to assign a

real number value to a variable of type integer.
 VHDL Data Types: Real data type

• Minimum range for any implementation as defined by standard:

-1.0E38 to 1.0E38

• Example assignment to a variable of type real:

 VHDL Data Types: Enumerated data type

• The basic enumerated data types accepted by Xilinx Synthesis

Tool (XST) are:
– BIT ('0','1')
– BOOLEAN (false, true)
– STD_LOGIC ('U','X','0','1','Z','W','L','H','-')

‘0’ : logic 0
‘1’ : logic 1
‘-’ : Don’t care
'U': uninitialized,
'X': unknown
'Z': High Impedance
'W': Weak signal, can't tell if it should be 0 or 1.
'L': Weak signal that should probably go to 0
‘H': Weak signal that should probably go to 1
 VHDL Data Types: Enumerated data type

• User specific list of possible values

• Example declaration and usage of enumerated data type:

• The enumerated data type allows a user to specify the list of legal
values that a variable or signal of the defined type may be assigned.
 VHDL Data Types: Physical data type
• Example of physical type declaration:

• The physical data type is used for values which have associated units.
• The designer first declares the name and range of the data type and then
specifies the units of the type.

• Notice there is no semicolon separating the end of the TYPE statement and the
UNITS statement.

• The line after the UNITS line states the base unit of the type. The units after the
base unit statement may be in terms of the base unit or another already
defined unit.

• The only predefined physical type in VHDL is time.

 VHDL Data Types: Array

• Used to group elements of same type into a single VHDL object.

• Range may be unconstrained in declaration
– Range would then be constrained when array is used
• Example declaration of one dimensional array (vector)
 Cont’d...

• The array is declared in a TYPE statement. There are

numerous items in an array declaration
– The first item is the name of the array.
– Second, the range of the array is declared.
• The keywords TO and DOWNTO designate ascending or descending indices,
respectively, within the specified range.
– The third item in the array declaration is the specification of the data
type for each element of the array.

• Example one-dimensional array using DOWNTO

 VHDL Data Types: Record
• Used to group elements of possibly different types into a single VHDL
object
• Elements are indexed via field names
• Example of record declaration and usage:
 VHDL Data Types: Access

• In brief, the access type is similar to a pointer in other programming

languages in that it dynamically allocates and deallocates storage space
to the object.

• This capability is useful for implementing abstract data structures

(such as queues and first-in-first-out buffers) where the size of the
structure may not be known at compile time.

• The VHDL access type will not be discussed in detail in this module.
 VHDL Data Types: Subtype

• VHDL subtype allows for user defined constraints on a data type.

– e.g. a subtype based on an unconstrained VHDL type

• May include entire range of base type

• Assignments that are out of the subtype range are illegal

– Range violation detected at run time rather than compile time because only base
type is checked at compile time

• The syntax and an example of a subtype declaration are shown above.

 VHDL Objects

• There are four types of objects in VHDL

– Constants
– Variables
– Signals
– Files
• The scope of an objects is as follows
– Objects declared in a package are available to all VHDL description
that use the package
– Objects declared in an entity are available to all architecture
associated with that entity.
– Objects declared in architecture are available to all statements in
that architecture
– Object declared in a process are available only within that process
VHDL Objects: Constant
 VHDL Objects: Variable

• Provide convenient mechanism for local storage

– E.g. loop counter, intermediate values

• Scope is process in which they are declared

• All variable assignment take place immediately

– No delta or user defined delay is incurred
• Declaration Syntax:

• Declaration example:
 VHDL Objects: Signal
• Used for communication between components

• All VHDL signal assignments require either delta delay

or user defined delay before new value is assumed.

• Declaration Syntax:

• Declaration example:
 VHDL Objects: Variable vs. Signal
• A key difference between variables and signal is the
assignment delay
 VHDL Objects: Variable vs. Signal
• In this example, variables are used to achieve the same functionality as
the example in the previous slide

• However, that in this example, the order in which the statements

appear within the process is important because the two statements
are executed sequentially, and the process will only be executed once as
a result of the single change in a.
 VHDL Objects: File

• Files provide the way for a VHDL design to communicate with host
environment

• File declaration make a file available for use to a design.

• File can be opened for reading and writing

• The package TEXTIO defines powerful routine handling I/O of test files