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    Design Unit-I: Choose The Correct Option From Following C

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    Urstruly Sri
    The document discusses key concepts in VLSI design including Moore's Law, CMOS technology, transistor operation modes, and fabrication processes. Some main points are: - Moore's Law describes the trend of increasing the number of transistors on an integrated circuit over time. - CMOS uses a combination of nMOS and pMOS transistors and is widely used in microprocessors, memory, and other applications. - There are different modes of transistor operation including cut-off, linear, and saturation that depend on voltage thresholds. - Fabrication involves growing oxide layers, doping substrate regions, and other processes to form transistors on a silicon wafer.

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    Design Unit-I: Choose The Correct Option From Following C

    Uploaded by

    Urstruly Sri
    41 views4 pages
    The document discusses key concepts in VLSI design including Moore's Law, CMOS technology, transistor operation modes, and fabrication processes. Some main points are: - Moore's Law describes the trend of increasing the number of transistors on an integrated circuit over time. - CMOS uses a combination of nMOS and pMOS transistors and is widely used in microprocessors, memory, and other applications. - There are different modes of transistor operation including cut-off, linear, and saturation that depend on voltage thresholds. - Fabrication involves growing oxide layers, doping substrate regions, and other processes to form transistors on a silicon wafer.

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    vlsi unit-I

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    The document discusses key concepts in VLSI design including Moore's Law, CMOS technology, transistor operation modes, and fabrication processes. Some main points are: - Moore's Law describes the trend of increasing the number of transistors on an integrated circuit over time. - CMOS uses a combination of nMOS and pMOS transistors and is widely used in microprocessors, memory, and other applications. - There are different modes of transistor operation including cut-off, linear, and saturation that depend on voltage thresholds. - Fabrication involves growing oxide layers, doping substrate regions, and other processes to form transistors on a silicon wafer.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    41 views4 pages

    Design Unit-I: Choose The Correct Option From Following C

    Uploaded by

    Urstruly Sri
    The document discusses key concepts in VLSI design including Moore's Law, CMOS technology, transistor operation modes, and fabrication processes. Some main points are: - Moore's Law describes the trend of increasing the number of transistors on an integrated circuit over time. - CMOS uses a combination of nMOS and pMOS transistors and is widely used in microprocessors, memory, and other applications. - There are different modes of transistor operation including cut-off, linear, and saturation that depend on voltage thresholds. - Fabrication involves growing oxide layers, doping substrate regions, and other processes to form transistors on a silicon wafer.

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    VLSI DESIGN

    Unit- I
    Bits
    1. The relationship between the numbers of transistors per chip versus the year has become
    known as Moores First Law.
    2. VLSI is used in the technologies of Microprocessors, DRAM/SRAM and special processors.
    3. CMOS (complementary metal oxide semiconductor) is combination of nMOS & cMOS
    transistor.
    4. The process of shrinking the layout in which every dimension is reduced by a factor is called
    scaling.
    5. The nMOS fabrication process takes place on a p doped silicon crystal wafer on which is
    grown a thick layer of sio2.
    6. CMOS fabrication process has 4 approaches namely P-well, N-well, tin tub and silicon on
    insulator process.
    7. To achieve low threshold voltage we need either deep well diffusion or high well resistivity.
    8. N-well CMOS circuits are also superior to P-well because of lower substrate bias effects on
    transistor threshold voltage & lower parasitic capacitance are associated with source and drain
    regions.
    9. The n transistor operation in cut off region makes the transistor cut off at the condition where
    vgs<<vt.
    10. There must be the capability for establishing and controlling a current between source and
    drain and this is commonly achieved in one of the two ways giving rise to the enhancement
    mode and depletion mode transistors.
    11. In enhancement mode if gate to the source then electric field is established between gate and
    substrate gives rise to charge region in substrate under gate insulation.
    12. pMOS transistor are inherently slower than nMOS, since hole mobility µp is less by a factor of
    approximately 25 than electron mobility µn.
    13. By the use of chemical vapor deposition technique and hydrogen reduction method Electronic
    grade silicon is obtained.
    14. Encapsulation is required for an IC to protect it against it against mechanical and chemical
    change.
    15. Bipolar transistors provide higher gain and have better noise and high frequency
    characteristics than MOS transistors.
    16. The two approaches to design E-beam machines are raster scanning & vector scanning.
    17. The starting material of E-beam mask consists of chrome plated glass plated coated with E
    beam sensitive resist.
    18. Twin tube process allows separate optimization of NAND p-transistors.
    19. In fabrication process substrate regions are doped with the p-type and n-type impurities.
    20. In N-transistor operation of saturation mode the channel is pinched off and current still flows
    due to the electron drift and current flows depends on VGS.

    Choose the correct option from following


    21. The CMOS P-well process has a high temperature P-well diffusion process ranging from___
    a. 1100-1250C
    b. 1200-15000C
    c. 1400-16000C
    d. 900-11000C
    VLSI DESIGN
    Unit- I
    Bits
    22. The length of the Pentium chip is _______
    a. 0.6µm
    b. 1.5 µm
    c. 0.18 µm
    d. 0.8 µm
    23. Speed power product can be measured in _____
    a. Pico joules
    b. Newton/second
    c. Km/Hr
    d. Joules/meter
    24. n-MOS devices are formed in a ______ substrate of modulate doping level.
    a. n-type
    b. p-type
    c. both n-type & p-type
    d. none
    25. Trance conductance of CMOS when gm α vin
    a. 0
    b. high
    c. ∞
    d. low
    26. Delay sensitivity of load of bipolar is
    a. High
    b. zero
    c. low
    d. ∞
    27. N-transistor operation in linear mode have to satisfy the condition
    a. Vgs > Vt
    b. VDS<Vgs-Vt
    c. both a and b
    d. none
    28. N-transistor operation in saturation mode have condition
    a. Vgs
    b. 0> Vgs> Vt
    c. Vgs =0
    d. vds>Vgs -Vt
    29. In p-transistor operation the transistor becomes off at _______ condition
    a. Vgs < Vt
    b. Vds <Vgs -Vt
    c. vgs>>Vt
    d. Vgs =0
    30. In p- transistor operation at the depletion region it satisfies the condition where___
    a. 0>Vgs>Vt
    b. Vgs>>Vt
    c. Vgs>Vt
    d. Vgs<Vt
    VLSI DESIGN
    Unit- I
    Bits
    31. In p- transistor operation the transistor is on at the condition where___
    a. Vgs<Vt
    b. VDS=0
    c. Both a & b
    d. None
    32. Logic capacity of processor increasing per year
    a. 10%
    b. 20%
    c. 80%
    d. 30%
    33. Mismatch in scaling of transistors and interconnects the interconnect delay has increased
    from5-10% of overall delay to
    a. 20-30%
    b. 40-50%
    c. 50-70%
    d. 80%
    34. The voltage at which device starts conduction is
    a. Offset voltage
    b. Threshold voltage
    c. Threshold current
    d. None of above
    35. Gate oxide and field oxide fall are grown by _____ technique
    a. Encapsulation
    b. Photolithography
    c. Thermal oxidation
    d. None
    36. Oxidation temperature generally lies in between
    a. 600-8000C
    b. 900-12000C
    c. 1200-15000C
    d. 1600-18000C
    37. Field oxide provides isolation in between
    a. Substrate & gate
    b. Gate and drain
    c. Source and gate
    d. None
    38. _______ means growing a single crystal silicon structure upon a original silicon substrate such
    that new substrate is essentially a molecular extension of original substrate
    a. Epitaxial growth
    b. Diffusion
    c. Thermal oxidation
    d. Metallization
    39. The source and drain regions are formed by diffusion ______ impurities
    a. P-type
    b. N-type
    VLSI DESIGN
    Unit- I
    Bits
    c. Both a and b
    d. None
    40. P-transistor mode of operation in linear mode have a condition where
    a. Vgs>Vt
    b. Vgs=0
    c. VDS>Vgs-Vt
    d. VDS <Vgs-Vt

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