Using Differential I/O

(LVDS, Sub-LVDS)
in iCE40 LP/HX Devices
January 2015 Technical Note TN1253

Introduction
Differential I/O standards are popular in a variety of consumer applications, especially those that require high-
speed data transfers such as graphic display drivers and camera interfaces. In these systems, multiple signals are
typically combined onto a smaller number of time-division-multiplexed high-speed, differential serial channels.

Differential signals require two Programmable I/O (PIO) pins, working as a pair or a channel, as shown in Figure 1.
One side of the pair represents the true polarity of the signal while the other side of the pair represents the opposite
polarity. The resulting logic value is the difference between the two sides of the signal pair.

Figure 1. Differential Signaling Electrical Parameters

VCCIO_x
VCCIO_3
Differential
RS Common mode voltage voltage DPxxB
50% of
differential voltage VID

RT
100
RP
RS VOD
VICM DPxxA
VOCM
GND

The key electrical parameters are the common mode voltage and the differential voltage. For iCE40™ applications,
the common mode voltage is essentially half the I/O Bank supply voltage. The differential voltage depends on the
values of the external compensation resistors, discussed in LVDS and Sub-LVDS Termination.

Differential signaling provides many advantages. In the examples discussed here, all the differential I/O standards
have reduced voltage swing, which allows faster switching speeds and potentially higher bandwidth. Reduced volt-
age swings also mean less dynamic power consumption and reduced electromagnetic interference (EMI).

Differential switching provides improved noise immunity and reduces duty-cycle distortion caused the differ-
ences in rise- and fall-time by the output driver.

The higher potential switching speeds of differential I/O allows data to be multiplexed onto a reduced number of
wires at a much higher data rate per line. The reduced number of wires reduces system cost and in some cases
simplifies the system design. The internal phase-locked loop (PLL) available in iCE40 FPGAs provides convenient
on-chip clock multiplication or division to support such applications.

Differential Outputs
For some differential I/O standards, such as LVDS, the output driver is actually a current source. On iCE40 FPGAs,
however, differential outputs are constructed using a pair of single-ended PIO pins as shown in Figure 3, and an
external resistor network consisting of three resistors. Because differential outputs are built from two single-ended
LVCMOS outputs, differential outputs are available in any I/O bank.

The two FPGA outputs must be part of the same I/O tile as indicated in the iCE40 data sheet. The pair choice also
depends on the chosen device package as not all I/O tile pairs are bonded out in all packages. Consult the package
pinout sections of the iCE40 device data sheets for additional information.

© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com 1 TN1253_1.5
 Using Differential I/O (LVDS, Sub-LVDS)
in iCE40 LP/HX Devices

Each differential I/O output pair requires a three-resistor termination network to adjust output characteristics to
match those for the specific differential I/O standard. The output characteristics depend on the values of the parallel
resistor (RP) and series resistors (RS). These resistors should be surface mounted as close as possible to the
FPGA output pins.

Figure 2. Differential Output Pair

External output
compensation Impedance-matched
resistor network signal traces
VCCIO_x
IOL_1A
RS
50
RP
RS
50
IOL_1B
iCE40 Differential Output Pair

1 0 1 0

Noise pulse affects both traces

similarly. Difference is signals
remains nearly constant.

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 Using Differential I/O (LVDS, Sub-LVDS)
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Differential Inputs
Differential inputs are only supported in I/O Bank 3. The maximum number of differential input pairs per device is
shown in Table 1 but the actual number available depends on the specific package used.

Table 1. Maximum Differential Input Pairs Available on iCE40 FPGAs

iCE40HX1K iCE40LP1K iCE40HX4K iCE40LP4K iCE40LP8K iCE40HX8K
Maximum Differential Input Pairs 11 12 12 20 23 26

Differential inputs require specific PIO pin pairs as listed in the iCE40 data sheet. Each differential input pair con-
sists of one pin labeled DPxxA and another labeled DPxxB, where “xx” represents the differential pair number. Both
pins must be in the same differential pair.

Connect the positive or true polarity side of the differential pair to the DPxxA input and the negative or complemen-
tary side of the pair to the DPxxB input. If it is easier to route the differential pair, the input pins can be swapped,
which produces an inverted input value. The inverted input value can subsequently be inverted by logic within the
FPGA.

An input termination resistor must be connected between the DPxxA and DPxxB pins to generate the differential
signal. The resistor’s value must be twice the trace impedance, as described in the following section.

Typically, the resulting signal pair is routed on the printed circuit board (PCB) using controlled impedance and delay
matching.

LVDS and Sub-LVDS Termination

LVDS and Sub-LVDS inputs require external compensation and termination resistors for proper operation, as
shown in Figure 4. A termination resistor, RT, between the positive and negative inputs at the receiver forms a cur-
rent loop. The current across this resistor generates the voltage detected by the receiver’s differential input compar-
ator.

Similarly, iCE40 LVDS and Sub-VLDS outputs require an external resistor network, consisting of two series resis-
tors, RS, and a parallel resistor, RP. This resistor network adjusts the FPGA’s output driver to provide the necessary
current and voltage characteristic s required by the specification.

The signals are routed with matched trace impedance, Z0, on the printed circuit board, typically with 50  imped-
ance.

Figure 3. iCE40 LVDS or Sub-LVDS Differential I/O Channel

VCCIO_x Impedance-matched
signal traces VCCIO_3
RS DPxxB
50
RT
100

RP
RS
50
DPxxA
Single I/O tile

The resistor values for the compensation network are described below. These equations are also provided in the
Differential I/O spreadsheet. The variables are defined and described in Table 2.

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 Using Differential I/O (LVDS, Sub-LVDS)
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Input Termination Resistor (RT)

RT = 2  Z0 (1)

Output Parallel Resistor (RP)

Z 0  VCCIO
R P = 2   -------------------------------------------------- (2)
VCCIO –  2  V OD 
Output Series Resistor (RS)  Z  ----- R P
-
 0 2
R S =  ------------------- – R OUTPUT (3)
RP
 ----- 
 2- – Z 0

Table 2. Compensation Resistor Equation Variables

Variable Description
Z0 Characteristic impedance of the printed circuit board trace; data sheet values assume 50  traces
VCCIO I/O Bank supply voltage, nominal, volts
VOD Differential output voltage swing, nominal, volts
ROUTPUT iCE40 output source resistance, 30 
RP LVDS/Sub-LVDS output source compensation parallel resistor
RS LVDS/Sub-LVDS output source compensation series resistor
RT LVDS/Sub-LVDS input termination resistor

Using the Companion iCE40 Differential I/O Calculator Spreadsheet

The iCE40 data sheet recommends specific values for LVDS and Sub-LVDS differential outputs but also assumes
that the differential signals are routed with 50  characteristic impedance (Z0). This may not be possible in all appli-
cations. Likewise, the system may require some other slightly different I/O standard.

This technical note includes a companion spreadsheet, available for download from the Lattice website and shown
in Figure 4, to calculate resistor values for non-standard conditions. The values in Figure 4 are the default condi-
tions for the LVDS I/O standard. For other standards, simply modify the VCCIO voltage, the differential output volt-
age, VOD, and the characteristic impedance of the printed circuit board traces, Z0.

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 Using Differential I/O (LVDS, Sub-LVDS)
in iCE40 LP/HX Devices

Figure 4. iCE40 Differential I/O Calculator Spreadsheet

iCE40™ Differential Output Calculator (Version 2.3, 28-AUG-2012)

Diff. Trace Source Source Resistor Actual
I/O Bank Output Impedanc Common Mode Series Parallel Terminatio Network Termination Differential
Supply Voltage e Output Voltage Resistor Resistor n Resistor Current Current Voltage
Symbol VCCIO VOD Z0 VOCM RS RP RT IRES IRT VDIFF
Value 2.5 0.35 50 1.25 150 140 100 6.0 3.5 0.349
Units volts volts ohm volts ohm ohm ohm mA mA volts
Companion to Technical Note TN1253: Using Differential I/O (LVDS, SubLVDS) in iCE40 mobileFPGAs

D irections: Enter the values for VCCIO, VOD, and Z0. The resulting resistor values appear under RS, RP, and RT. The VOCM voltage is aslo calculated.

VCCIO iCE40 I/O

Bank Supply Device with
Voltage Characteristic trace Differential Receiver
Differential impedance
RS voltage Common mode voltage
≈ 50% of
Z0
differential voltage

RT
RP VOD VDIFF
RS
Z0
VOCM

GND

1.) The RS and RP resistors should be surface mounted as close to the iCE40 mobileFPGA output balls/pins as possible.
2.) The termination resistor, RT, should be as close to the recieving device's differential inputs as possible.
3.) The actual differential voltage, VDIFF, may vary slightly from differential output voltage due to rounding of resistor values.

The spreadsheet automatically calculates the common mode output voltage, VOCM, which is half of the VCCIO sup-
ply voltage. The spreadsheet also automatically calculates the values for the resistor network.

Finally, the spreadsheet also calculates the current draw through the resistor network and for the termination resis-
tor. The spreadsheet rounds the resistor values to the nearest 10 . Consequently, the spreadsheet also calculates
the actual differential voltage based on the specified resistor values.

Differential Clock Input

iCE40 FPGAs have eight global buffers for distributing clocks or other high fanout signals. Global buffer GBUF7,
shown in Figure 5, is specifically designed to accept a differential clock input on the associated GBIN7/DPxxB,
DPxxA differential input pair, which is part of I/O Bank 3. Connect an external 100  termination resistor across the
input pair. When VCCIO_3 is 2.5V, this global buffer input accepts either LVDS or LVPECL clock inputs.

Figure 5. LVDS or LVPECL Clock Input

GBIN7/DP##B
LVDS/
LVPECL
100

Clock
Driver GBUF7
DP##A

iCE40 Differential Signaling Board Layout Requirements

Figure 6 depicts several transmission line structures commonly used in printed circuit boards (PCBs). Each struc-
ture consists of a signal line and a return path with uniform cross-section along its length. The structure’s dimen-
sions along with the dielectric material properties determine the characteristic impedance of the transmission line.
Figure 6 shows examples of edge-coupled microstrips, and edge-coupled or broad-side-coupled striplines.

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 Using Differential I/O (LVDS, Sub-LVDS)
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To maintain constant differential impedance along the length, maintain uniform trace width and spacing, including
good symmetry between the two lines.

For differential outputs, place the surface-mounted RP and RS resistors as close to the package balls as possible.
Similarly, place the 100  termination resistor, RT, as close as possible to the differential input pair.

Figure 6. Controlled Impedance Transmission Lines

Single-Ended Microstrip Single-Ended Stripline

W W
T

H
H T
H

87 5.98H 60 1.9 ( 2H + T)
Z 0 = --------------------------- ln ----------------------- Z 0 = --------- ln -------------------------------
εr + 1.41 0.8W + T ε ( 0.8W + T)
r

Edge-Coupled Edge-Coupled
S S

H H

Differential Microstrip Differential Stripline

S S
– 0.96 x ---- – 2.9 x ----
H H
Z diff = 2 x Z 0 x 1 – 0.48 x e Z diff = 2 x Z 0 x 1 – 0.347 x e

Typical PC board trace impedance is Z0 = 50 Ohms. For a single-ended microstrip, the trace impedance is calcu-
lated by using the following equation:

Single-ended microstrip trace impedance

87 5.98H
Z 0 = -------------------------- ln ----------------------- (4)
 r + 1.41 0.8W + T
Single-ended stripline trace impedance
60 1.9  2H + T 
Z 0 = -------- ln ------------------------------- (5)
r  0.8W + T 
For an LVDS pair, differential impedance can be determined by using the following equations for differential
microstrip and differential stripline:

Differential impedance for differential microstrip

S
– 0.96  ----
H
Z diff = 2  Z 0  1 – 0.48  e (6)

Differential impedance for differential stripline

S
– 2.9  ----
H
Z diff = 2  Z 0  1 – 0.347  e (7)

Because the coupling of two traces can lower the effective impedance, use 60  design rules to achieve a differen-
tial impedance of approximately 100 ohms.

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 Using Differential I/O (LVDS, Sub-LVDS)
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Layout Recommendations to Minimize Reflection

Skew delay is introduced if the trace lengths between the signals in the differential pair are not similar. With differing
trace lengths, the signals on each side of the differential pair arrive at slightly different times and reflect off the
receiver termination, creating a common-mode noise source on the transmission line.

Common-mode noise degrades the receiver’s eye diagram, reduces signal integrity, and creates crosstalk between
neighboring signals on the board. To minimize reflections due to unmatched trace lengths, consider the following
guidelines:

• Match the length of each signal within the differential signal pair to within 20 mils.
• Minimize turns and vias or feed-throughs. Route differential pairs as straight as possible from point-to-point. Do
not use 90-degree turns when routing differential pairs. Instead, use 45-degree bevels or rounded curves.
• Minimize vias on or near differential trace lines as these may create additional impedance discontinuities that will
increase reflections at the receiver. If vias are required, place them as close to the receiver as possible.
• Use controlled impedance PCB traces. That is, control trace spacing, width, and thickness using stripline or
microstrip layout techniques.

EMI and Noise Cancellation

Differential signaling offers tremendous advantages over single-ended signaling because it is less susceptible to
noise. In differential signaling, two current carrying conductors are routed together, with the current in one conduc-
tor always equal in magnitude but opposite in direction to the other conductor. The result is that both electromag-
netic fields cancel each other.

Common-mode noise rejection is another advantage of differential signaling. The receiver ignores any noise that
couples equally on both sides of the differential signal, as shown in Figure 8.

Figure 7. Single-ended Input Retains Signal Noise

noise Signal to noise
single-ended Output
input retains noise
Input

noise
noise

Figure 8. Differential Input Eliminates Common-Mode Noise

noise Signal to Output with

LVDS Receiver no noise
350 mV
Receiver
350 mV

noise

Reducing EMI Noise

Any skew between differential signals can generate EMI noise on the board. The following are some guidelines to
reduce EMI emission onboard:

• Match edge rates and signal skew between differential signals as closely as possible. Different signal rise and fall
times and skew between signal pairs create common-mode noise, which generates EMI noise.
• Maintain spacing between differential signal pairs that is less than twice the PCB trace width.

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 Using Differential I/O (LVDS, Sub-LVDS)
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Defining Differential I/O

Single-ended I/O connections are automatically inferred from the top-level VHDL or Verilog circuit description dur-
ing logic synthesis. However, differential I/O connections must be specifically instantiated using design primitives
from the Lattice technology library for iCE40 FPGAs. Table 3 lists the specific I/O primitive required by differential
I/O type. Documentation on the design primitives is located under the iCEcube2™ installation directory:

C:\SbtTools\doc\SBT_ICE_Technology_Library.pdf

Table 3. Differential I/O Types and Required SiliconBlue I/O Primitive

Differential I/O Type iCE40 Design Primitive PIN_TYPE IO_STANDARD
Differential clock input SB_GB_IO SB_LVDS_INPUT
Differential input SB_IO See PIN_TYPE Parameter. SB_LVDS_INPUT
Differential output SB_IO SB_LVCMOS

The SB_IO and SB_GB_IO primitives also require specific parameter settings. Differential inputs always require
that IO_STANDARD be set to SB_LVDS_INPUT. Differential outputs typically require that the IO_STANDARD
parameter be set to SB_LVCMOS.

SB_IO Primitive
Table 4 lists the signal ports for the SB_IO primitive, which describes one of the Programmable I/O (PIO) pins on an
iCE40 FPGA. The table also shows the signal direction for each port, relative to the PIO pin (the SB_IO primitive).
These same signals also appear on the SB_GB_IO primitive, which describes a global buffer input.

Table 4. Port Names, Signal Direction, and Description for SB_IO (SB_GB_IO) Primitive
Port Name Direction Description
PACKAGE_PIN I/O Connection to top-level input, output, or bidirectional signal port.
iCEgate latch input. When High, hold the last pad value. Used for power reduction in
some PIN_TYPE modes. There is one control input per I/O Bank.
LATCH_INPUT_VALUE Input
0 = Input data flows freely
1 = Last data value on pad held constant to save power
Clock enable input, shared connection to all flip-flops within the SB_IO primitive. If this
port is left unconnected, automatically tied High.
CLOCK_ENABLE Input
0 = Flip-flops hold their current value
1 = Flip-flops accept new data on the active clock edge
INPUT_CLOCK Input Clock for all input flip-flops. If this port is left unconnected, it is automatically tied Low.
OUTPUT_CLOCK Input Clock for all output flip-flops. If this port is left unconnected, it is automatically tied Low.
Enables the output buffer.
OUTPUT_ENABLE Input 0 = Output disabled, pad is high-impedance (Hi-Z)
1 = Output enabled, actively driving
Data output. For DDR output modes, this is the value clocked out on the rising edge of
D_OUT_0 Input
the OUTPUT_CLOCK.
Data output used in DDR output modes. This is the value clocked out on the falling
D_OUT_1 Input
edge of the OUTPUT_CLOCK.
Data input. For DDR input modes, this is the value clocked into the device on the rising
D_IN_0 Output
edge of the INPUT_CLOCK.
For DDR input modes, this is the value clocked into the device on the falling edge of
D_IN_1 Output
the INPUT_CLOCK.

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 Using Differential I/O (LVDS, Sub-LVDS)
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SB_GB_IO Primitive
Global buffer inputs provide a direct connection from a PIO pin to an associated global buffer. This connection can
be instantiated using an SB_GB_IO primitive. An SB_GB_IO primitive has all the ports for an SB_IO primitive,
shown in Table 4, plus the additional connection shown in Table 5. Global Buffer Input 7 (GBIN7) is the only one
that supports differential clock inputs. See Differential Clock Input for more information.

Table 5. Additional Port Names on SB_GB_IO Primitive

Port Name Direction Description
Output from associated Global Buffer. This output is controlled by the iCE-
GLOBAL_BUFFER_OUTPUT Output gate latch if a control signal is connected to the iCEgate latch input
(LATCH_INPUT_VALUE).

PIN_TYPE Parameter
The PIN_TYPE parameter defines the structure and the functionality of any instantiated SB_IO primitive.
PIN_TYPE is a six-bit binary value. The upper four bits, PIN_TYPE[5:2], define the output structure while the lower
two bits, PIN_TYPE[1:0] define the input structure. Both fields are required, but operate independently.

Global buffer inputs, defined using the SB_GB_IO primitive, are also full-featured PIO pins. However, if only the
GLOBAL_BUFFER_OUTPUT is connected on the SB_GB_IO primitive, then the PIN_TYPE parameter has no real
effect.

Output Field (PIN_TYPE[5:2])

Table 6 shows the various PIN_TYPE definitions for the output side an SB_IO or SB_GB_IO primitive.
Table 6. Output Structures and PIN_TYPE Values
Style Mnemonic (Diagram) PIN_TYPE[5:2]
PIN_NO_OUTPUT
None (output disabled) PAD 0 0 0 0
Hi-Z PACKAGE_PIN

PIN_OUTPUT
PAD
0 1 1 0
D_OUT_0 PACKAGE_PIN

Non-registered Output PIN_OUTPUT_TRISTATE

OUTPUT_ENABLE
1=Output
0=Hi-Z PAD 1 0 1 0
D_OUT_0 PACKAGE_PIN

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Table 6. Output Structures and PIN_TYPE Values (Continued)

Style Mnemonic (Diagram) PIN_TYPE[5:2]
PIN_OUTPUT_REGISTERED
PAD
D_OUT_0 D Q PACKAGE_PIN
0 1 0 1
CLOCK_ENABLE ENA
1=Enabled
0=Hold value
OUTPUT_CLK

PIN_OUTPUT_REGISTERED_ENABLE
OUTPUT_ENABLE
1=Output
0=Hi-Z PAD
D_OUT_0 D Q PACKAGE_PIN 1 0 0 1
CLOCK_ENABLE ENA
1=Enabled
0=Hold value
OUTPUT_CLK

PIN_OUTPUT_ENABLE_REGISTERED
Registered Outputs OUTPUT_ENABLE
1=Output D Q
0=Hi-Z
CLOCK_ENABLE ENA
1=Enabled 1 1 1 0
0=Hold value
OUTPUT_CLK
PAD
D_OUT_0 PACKAGE_PIN

PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED

OUTPUT_ENABLE D Q
1=Output
0=Hi-Z ENA

PAD 1 1 0 1
D_OUT_0 D Q PACKAGE_PIN
CLOCK_ENABLE ENA
1=Enabled
0=Hold value
OUTPUT_CLK

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 Using Differential I/O (LVDS, Sub-LVDS)
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Table 6. Output Structures and PIN_TYPE Values (Continued)

Style Mnemonic (Diagram) PIN_TYPE[5:2]
PIN_OUTPUT_DDR

D_OUT_0 D Q DDR
MUX
ENA
PAD
PACKAGE_PIN
DDR
0 1 0 0
D_OUT_1 D Q

CLOCK_ENABLE ENA
1=Enabled
0=Hold value DDR
OUTPUT_CLK

PIN_OUTPUT_DDR_ENABLE
OUTPUT_ENABLE
1=Output
0=Hi-Z
D_OUT_0 D Q DDR
MUX
ENA
PAD
PACKAGE_PIN
DDR 1 0 0 0
Double Data Rage (DDR) D_OUT_1 D Q
Output
CLOCK_ENABLE ENA
1=Enabled
0=Hold value DDR
OUTPUT_CLK

PIN_OUTPUT_DDR_ENABLE_REGISTERED

OUTPUT_ENABLE D Q
1=Output
0=Hi-Z ENA

D_OUT_0 D Q DDR
MUX
PAD
ENA 1 1 0 0
PACKAGE_PIN
DDR

D_OUT_1 D Q

CLOCK_ENABLE ENA
1=Enabled
0=Hold value DDR
OUTPUT_CLK

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 Using Differential I/O (LVDS, Sub-LVDS)
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Table 6. Output Structures and PIN_TYPE Values (Continued)

Style Mnemonic (Diagram) PIN_TYPE[5:2]
PIN_OUTPUT_REGISTERED_INVERTED
PAD
D_OUT_0 D Q PACKAGE_PIN
INV 0 1 1 1
CLOCK_ENABLE ENA
1=Enabled
0=Hold value
OUTPUT_CLK

PIN_OUTPUT_REGISTERED_ENABLE_INVERTED
OUTPUT_ENABLE
1=Output
0=Hi-Z PAD
D_OUT_0 D Q PACKAGE_PIN 1 0 1 1
INV
CLOCK_ENABLE ENA
Registered Output, Inverted 1=Enabled
0=Hold value
OUTPUT_CLK

PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED_INVERTED
OUTPUT_ENABLE D Q
1=Output
0=Hi-Z ENA

PAD 1 1 1 1
D_OUT_0 D Q PACKAGE_PIN
INV
CLOCK_ENABLE ENA
1=Enabled
0=Hold value
OUTPUT_CLK

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Input Field (PIN_TYPE[1:0])

Table 7 shows the various PIN_TYPE definitions for the input side of an SB_IO or SB_GB_IO primitive.

Table 7. Input Structures and PIN_TYPE Values

Style Mnemonic (Diagram) PIN_TYPE[1:0]
PIN_INPUT
Direct PAD 0 1
D_IN_0 PACKAGE_PIN

PIN_INPUT_REGISTERED
PAD
D_IN_0 Q D PACKAGE_PIN
Registered CLOCK_ENABLE ENA 0 0
1=Enabled
0=Hold value
INPUT_CLK

PIN_INPUT_DDR
PAD
D_IN_0 Q D PACKAGE_PIN
ENA

Double Data Rage (DDR) DDR

0 0
Output
D_IN_1 Q D

CLOCK_ENABLE ENA
1=Enabled
0=Hold value DDR
INPUT_CLK

PIN_INPUT_LATCH
LATCH_INPUT_VALUE
1=Latch current value
0=Flow through iCEgate PAD 1 1
D_IN_0 Q D PACKAGE_PIN
LE

PIN_INPUT_REGISTERED_LATCH
iCEgate Low-Power Latch
LATCH_INPUT_VALUE
1=Latch current value
0=Flow through iCEgate PAD
D_IN_0 Q D Q D PACKAGE_PIN 1 0
CLOCK_ENABLE ENA LE
1=Enabled
0=Hold value
INPUT_CLK

IO_STANDARD Parameter
Differential inputs or outputs require specific settings for the IO_STANDARD parameter, as summarized in Table 8.
Regardless of actual electrical requirements (LVDS, Sub-LVDS), the IO_STANDARD parameter on differential
inputs must be set to SB_LVDS_INPUT. Again, differential inputs are only available in I/O bank 3. For differential
outputs, set IO_STANDARD to SB_LVCMOS. Differential outputs are available in I/O banks 0, 1, 2, or 3.

Table 8. IO_STANDARD Settings for Differential I/O

Differential Inputs Differential Outputs
(I/O Bank 3 Only) (I/O Banks 0, 1, 2, 3)
IO_STANDARD Setting SB_LVDS_INPUT SB_LVCMOS

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 Using Differential I/O (LVDS, Sub-LVDS)
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NEG_TRIGGER Parameter
The optional NEG_TRIGGER parameter, when set to ‘1’, inverts the clock polarity within the PIO pin.

HDL Implementation Example

Most applications that use differential I/O do so because they require very high data bandwidth. Consequently,
most of these applications use also Double Data Rate (DDR) flip-flops to double the effective data rate at the PIO
pin.

The design example shown in Figure 9 uses the DDR flip-flops embedded in every PIO pin.

Figure 9. Differential I/O Design Example

Differential input
Differential output pair
SB_IO
diff_input input_0
D Q D Q
Non-inverting, P-side
DDR DDR diff_out_b
input_180
D Q D Q
D Q D Q Differential output is
DDR DDR built from two SB_IO
primitives using
SB_IO standard LVCMOS
outputs. One side
IO_STANDARD=”SB_LVDS_INPUT” IO_STANDARD=”SB_LVCMOS” transmits inverted
logic values.
PIN_TYPE=6'b000000 PIN_TYPE=6'b010000
A single SB_IO primitive defines a
differential pair when IO_STANDARD D Q
is set to SB_LVDS_INPUT. The Inverting, N-side
second package pin is reserved
automatically by the iCEcube DDR diff_out_a
software.
Differential clock input D Q
D Q
SB_GB_IO DDR
diff_clock_input global_clock
SB_IO
GBUF7 IO_STANDARD=”SB_LVCMOS”
PIN_TYPE=6'b010000
IO_STANDARD=”SB_LVDS_INPUT” External output compensation resistors
PIN_TYPE=6'b000000 and input termination resistors are
required but not shown in this diagram.

VHDL Component Declaration

For VHDL implementations, the SB_IO and SB_GB_IO primitives must be declared as components before they are
first used. Verilog does not require this declaration.

Differential Clock Input

The following Verilog code snippets demonstrate how to instantiate a differential clock input using an SB_GB_IO
primitive. The differential clock input is always connected to Global Buffer GBIN7 and always in I/O Bank. In this
example, shown in Figure 9, the PIO pin only connects an external differential clock signal to the FPGA’s GBUF7
global buffer. The only ports connected on the primitive are the PACKAGE_PIN and the
GLOBAL_BUFFER_OUTPUT ports. Consequently, the PIN_TYPE setting for this SB_GB_IO primitive does not
actually matter.

Set the IO_STANDARD parameter to “SB_LVDS_INPUT”. Doing so also causes the iCEcube2 software to reserve
a second pin for the other side of the differential input pair.

An external 100  termination resistor must be connected between the two inputs. The resistor must be physically
placed as close as possible to the two package balls.

For VHDL implementations, the SB_GB_IO component must be declared.

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 Using Differential I/O (LVDS, Sub-LVDS)
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The PIN_TYPE for this primitive may be different, depending on whether only the global buffer input is used, or if
the data input paths are used, or both. The example shown here is for a dedicated differential clock input.

Verilog
// Differential clock input example: Verilog
// IMPORTANT: The PIN_TYPE is different for a regular LVDS input used as a clock.
// This example is specifically for the differential clock input.
defparam differential_clock_input.PIN_TYPE = 6'b000000 ; // {NO_OUTPUT, PIN_INPUT_REGISTERED}
defparam differential_clock_input.IO_STANDARD = "SB_LVDS_INPUT" ;
SB_GB_IO differential_clock_input (
.PACKAGE_PIN(diff_clock_input),
.LATCH_INPUT_VALUE ( ),
.CLOCK_ENABLE ( ),
.INPUT_CLK ( ),
.OUTPUT_CLK ( ),
.OUTPUT_ENABLE ( ),
.D_OUT_0 ( ),
.D_OUT_1 ( ),
.D_IN_0 ( ),
.D_IN_1 ( ),
.GLOBAL_BUFFER_OUTPUT(global_clock) // Global buffer output
);

VHDL
Under development.

Differential Input
The following Verilog and VHDL code snippets demonstrate how to instantiate a differential input using an SB_ IO
primitive. Differential inputs are always implemented in I/O Bank 3. In this example, shown in Figure 9, the differen-
tial input also connects to Double Data Rate (DDR) input flip-flops. There is no output connected. Consequently,
set the PIN_TYPE parameter to the binary value “000000”, which defines no output (see Table 6) and DDR input
(see Table 7).

Set the IO_STANDARD parameter to “SB_LVDS_INPUT”. Doing so also causes the iCEcube2 software to reserve
a second pin for the other side of the differential input pair.

An external 100  termination resistor must be connected between the two inputs. The resistor must be physically
placed as close as possible to the two package balls.

For VHDL implementations, the SB_ IO component must be declared.

Verilog
// Differential input, DDR data
defparam differential_input.PIN_TYPE = 6'b000000 ; // {NO_OUTPUT, PIN_INPUT_DDR}
defparam differential_input.IO_STANDARD = "SB_LVDS_INPUT" ;
SB_IO differential_input (
.PACKAGE_PIN(diff_input),
.LATCH_INPUT_VALUE ( ),
.CLOCK_ENABLE ( ),
.INPUT_CLK (global_clock),
.OUTPUT_CLK ( ),
.OUTPUT_ENABLE ( ),
.D_OUT_0 ( ),
.D_OUT_1 ( ),
.D_IN_0 (input_0),
.D_IN_1 (input_180)
);

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 Using Differential I/O (LVDS, Sub-LVDS)
in iCE40 LP/HX Devices

VHDL
Under development.

Differential Output Pair

The following Verilog and VHDL code snippets demonstrate how to instantiate a differential output pair using an
SB_ IO primitive. Differential outputs are specified as two separate single-ended outputs. One output provides the
non-inverted or P-side of the pair while the other output provides the inverted or N-side of the pair. In this example,
shown in Figure 9, the differential output also connects to Double Data Rate (DDR) input flip-flops for higher output
performance. There is no input connected. Consequently, set the PIN_TYPE parameter to the binary value
“010000”, which defines DDR output (see Table ) and a benign input (see Table 7).

Differential outputs can be placed in any I/O bank, although the pair must be part of an I/O tile, as shown in the
iCE40 or iCE40 data sheet. Because of better slew rate control, place lower-speed differential outputs in I/O Banks
0, 1, or 2. Differential I/Os in I/O Bank 3 have the best performance, but also have faster, noisier switching edges.
Set the IO_STANDARD parameter to “SB_LVCMOS”.

An external compensation resistor network must be connected between the two inputs. The resistors must be
physically placed as close as possible to the two package balls.

For VHDL implementations, the SB_ IO component must be declared.

Verilog
// Differential output pair, DDR data
// Non-inverting, P-side of pair
defparam differential_output_b.PIN_TYPE = 6'b010000 ; // {PIN_OUTPUT_DDR,
PIN_INPUT_REGISTER }
defparam differential_output_b.IO_STANDARD = "SB_LVCMOS" ;
SB_IO differential_output_b (
.PACKAGE_PIN(diff_output_b),
.LATCH_INPUT_VALUE ( ),
.CLOCK_ENABLE ( ),
.INPUT_CLK ( ),
.OUTPUT_CLK (global_clock),
.OUTPUT_ENABLE ( ),
.D_OUT_0 (input_0), // Non-inverted
.D_OUT_1 (input_180), // Non-inverted
.D_IN_0 ( ),
.D_IN_1 ( )
);

// Inverting, N-side of pair

defparam differential_output_a.PIN_TYPE = 6'b010000 ; // {PIN_OUTPUT_DDR,
PIN_INPUT_REGISTER }
defparam differential_output_a.IO_STANDARD = "SB_LVCMOS" ;
SB_IO differential_output_a (
.PACKAGE_PIN(diff_output_a),
.LATCH_INPUT_VALUE ( ),
.CLOCK_ENABLE ( ),
.INPUT_CLK ( ),
.OUTPUT_CLK (global_clock),
.OUTPUT_ENABLE ( ),
.D_OUT_0 (~input_0), // Inverted
.D_OUT_1 (~input_180), // Inverted
.D_IN_0 ( ),
.D_IN_1 ( )
);
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 Using Differential I/O (LVDS, Sub-LVDS)
in iCE40 LP/HX Devices

VHDL
Under development.

Applications
Applications that benefit most from differential I/O are those with high bandwidth communication requirements such
as graphic displays, cameras and imagers, or chip-to-chip interfaces.

While driving such displays using single-ended LVCMOS I/O is possible, portable or hand-held applications place
additional physical constraints on a design, as shown in Figure 10. Typically, the high bandwidth device—the
graphic display or camera—is separate from the main body that holds the majority of the system electronics. The
main body and the high-bandwidth device are often mechanically connected by some sort of hinge mechanism. In
other applications, the display and camera or cameras are folded into a compact phone, camera, or tablet body.
Sending a wide, LVCMOS signal cable bundle across the hinge to the display is simply impractical. Likewise, a cus-
tom, wide, flex-cable is prohibitively expensive.

The higher bandwidth possible with differential signaling allows the same data to be transported over fewer electri-
cal connections. Few connections results in a smaller, lower-cost flexible cable. Likewise, the smaller voltage swing
results in lower electromagnetic interference (EMI).

Figure 10. Portable Devices Benefit from Differential I/O

Camera
(bandwidth
requirement)

Display
(bandwidth
requirement)

Hinge
(physical
constraint)

Main Body
of Electronics

Laptop, Notebook, Mobile Internet Device (MID) Mobile Phone, Smart Phone

iCE40 FPGAs offer a broad range of possible solutions for handheld applications, primarily in bridging and format
conversion applications.

• Covert RGB data to high-speed differential data and back.

• Connect a processor without an integrated differential interface to a differential display or camera.
• Convert from one high-speed differential interface to another.
• Scale, rotate, and rebroadcast one stream onto another display format or another differential I/O format.

Graphic Displays
Graphic displays demand high data rates, especially high-resolution displays that support a broad color range. In
portable or handheld applications, the challenge is to provide a high-bandwidth communications path between the
graphics controller and the display that fits with the physical constraints of the hinge or the package body. There are
a variety of standard interfaces that leverage differential switching. Perhaps the most widely-used example is Flat
Panel Display Link (FDP-Link), shown in Figure 11. The example shows a 24-bit per pixel design, although there
are other implementations that use fewer colors and differential pairs. A standard 24-bit RGB interface requires up

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 Using Differential I/O (LVDS, Sub-LVDS)
in iCE40 LP/HX Devices

to 28 single-ended signals. Instead of sending a cable bundle with 24 wires across the hinge, FPD-Link serializes
the 28 data/control lines onto four differential I/O pairs, plus a clock differential pair resulting in 64% fewer wires.
FPD-Link uses the Low-Voltage Differential Swing (LVDS) I/O standard.

Dividing 28 lines by four differential pairs also means that the data rate across the interface is seven times higher
than the output clock rate.

Figure 11. Example Differential I/O Solution: Flat Panel Display Interface
28 lines at 1X clock rate = 4 differential channels at 7X clock rate

28 data/control lines Four differential

data channels (8 traces) at
7X the clock rate
RED[7:0] RED[7:0]

GREEN[7:0] GREEN[7:0]

BLUE[7:0] BLUE[7:0]

HSYNC Display HSYNC

Graphics Timing
VSYNC VSYNC
Controller Controller
DATA ENABLE (Display) DATA ENABLE

CONTROL Regenerated clock, CONTROL

same frequency,
different duty cycle

CLOCK CLOCK

Low-voltage,
differential swing
(LVDS) channel

Clock
Previous cycle Current cycle Next cycle
PAIR3 RED1 RED0 CTRL BLU1 BLU0 GRN1 GRN0 RED1 RED0 CTRL BLU1

PAIR2 BLU5 BLU4 DEN VSYNC HSYNC BLU7 BLU6 BLU5 BLU4 DEN VSYNC

PAIR1 GRN4 GRN3 BLU3 BLU2 GRN7 GRN6 GRN5 GRN4 GRN3 BLU3 BLU2

PAIR0 RED3 RED2 GRN2 RED7 RED6 RED5 RED4 RED3 RED2 GRN2 RED7

At the receiving end, the differential data is de-serialized and converted back into a wider bundle of single-ended
signals.

The integrated PLL in iCE40-family FPGAs simplifies this style of interface. An iCE40 FPGA can be at either end of
the serial interface, either to allow a processor without an FPD-Link interface to communicate with an FPD-Link dis-
play, or to allow a processor with only an FPD-Link display interface to communicate to an RGB display or a display
that uses a different format.

Figure 12 shows an example application running on an iCEman40 evaluation board. A 5-Megapixel camera cap-
tures live video images and provides the data to the iCE40 FPGA in RGGB format on a parallel LVTLL interface.

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 Using Differential I/O (LVDS, Sub-LVDS)
in iCE40 LP/HX Devices

Figure 12. 5-Megapixel CMOS Camera to LVDS Display on iCEman40 Evaluation Board

Cameras and Imagers

Differential interfaces are also popular for high-resolution and high-speed cameras and imagers.

Summary
This technical note provides an overview of iCE LVDS technology, focusing on its advantages, implementation,
application, and its various electrical and timing characteristics. It also includes detailed recommendations for
instantiating LVDS transmitter and receivers in your design and calculating the required external terminations to
guarantee optimum performance.

References
• IEEE 1596.3 Standards
• Texas Instruments, “LVDS Owner’s Manual”, 2008
• Jimmy Ma, “A Closer Look at LVDS Technology”, Pericom, 2001
• Texas Instruments, “Application Note 1032: An Introduction to FPD-Link”
• Texas Instruments, “Application Note 1127: LVDS Display Interface (LDI) TFT Data Mapping for Interoperability
with FPD-Link”

Technical Support Assistance

e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com

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 Using Differential I/O (LVDS, Sub-LVDS)
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Revision History
Date Version Change Summary
January 2015 1.5 Updated Differential Outputs section. Updated Figure 2, Differential
Output Pair. Added IOL_1A and IOL_1B.
July 2014 1.4 Updated Figure 1, Differential Signaling Electrical Parameters and
Figure 3, iCE40 LVDS or Sub-LVDS Differential I/O Channel. Changed
DPxxA and DPxxB differential input pair connections.
October 2013 01.3 Changed document title to “Using Differential I/O (LVDS, Sub-LVDS)
in iCE40 LP/HX Devices”.
June 2013 01.2 Updated the Differential Signaling Electrical Parameters and the iCE40
LVDS or Sub-LVDS Differential I/O Channel figures.
Updated the descriptions of the INPUT_CLOCK and the
OUTPUT_CLOCK ports in the Port Names, Signal Direction, and
Description for SB_IO (SB_GB_IO) Primitive table.
Updated Technical Support Assistance information.
March 2013 01.1 Removed the Representative Electrical Characteristics of Various Dif-
ferential I/O Standards table.
Updated information in Differential Outputs.
Updated description of figure showing 5-Megapixel CMOS Camera to
LVDS Display on iCEman40 Evaluation Board.
Removed the Example FPD-Link Transmitter on iCEman40 Evaluation
Board figure and description.
September 2012 01.0 Initial release.

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