Performance Analysis of New Adaptive decision based median

filter on FPGA for Impulsive Noise Filtering

Mohammad Ismaeil1, Keisham Pritamdas2, Kh. Jilen Kumari Devi3 and Samarth Goyal4

Department of Electronics and Communication Engineering

National Institute of Technology Manipur, Imphal 795001, INDIA
Email-ismaeil.karimganj@gmail.com1,das1948@gmail.com2,jilenkumari@gmail.com3,samarthrishikesh@gmail.com4

Abstract- Noise detection and its removal is very important in weighted median filter (CWMF) [3], multi-state median filter
digital image processing. In this paper an Adaptive Decision (MSF) [4], the rank order filter etc. These filters applied
based filtering method is proposed for removing impulse noise uniformly over the whole window without detecting the noisy
mainly salt & pepper noise. The proposed algorithm first detect and noise free pixels which leads to blurring of the image and
the noisy pixel, then filtering is done using decision based
loss of fine details. In order to overcome those problems,
algorithm. The filter works very well on removing fixed valued
impulse noise. With little increase in computational complexity switching median filter has been introduced where the noisy
over basic median filter, these algorithms works well on different pixels are detected and filtered, whereas uncorrupted pixels
noise ratios. This paper also proposes hardware implementation are left behind. In our proposed method of noise detection we
of the proposed algorithm for real time execution. have implemented a concept of fixed threshold value and
Implementations are checked on Artix-7 FPGA development neighborhood operation for filtering. It results in efficient
board of XC7A100T-1csg324c device family using VHDL filtering and better image quality.
programming language in vivado 2015 design tools. The results
show that the FPGA implementation of the filter has a good With advancement in the VLSI design technology, hardware
trade-off between resource consumption and noise removal
implementation become an attractive area for research. By
efficiency.
hardware implementation method we can calculate the
Keywords— Threshold; Median Filter; Salt-and-pepper resource utilization report, area required to implement the
noise; VHDL; and Field programmable gate array (FPGA). filter. Two types of hardware design technologies are there
namely, full custom hardware design called as Application
I. INTRODUCTION specific Integrated circuit (ASIC) and reconfigurable
hardware design also called as Field programmable gate array
DIGITAL image processing is an ever expanding and dynamic (FPGA). Due to reconfigurable nature, cost effective criteria,
area with applications used in many fields like medical and parallelism and pipelining technique, FPGAs are widely
science, surveillance, satellite communication, authentication, used in image processing field.
automated industry inspection and many more areas.
Applications of such fields requires a good quality of image The performance of the filter investigated in two phases. In
for processing. During transmission and acquisition images first phase the image quality, Peak signal to noise ratio
often get affected with noise, due to which quality of the (PSNR) and Mean squared error (MSE) is calculated for
image degrades leads to loss of fine details with other features different amount of noise using MATLAB application, in next
like sharpness, edges etc. Noise are of different types namely phase the filter performance such as area, number of slice
Additive noise (Gaussian noise), Impulse noise etc. additive register, number of LUT, Flip-flops pairs, number of bonded
noise affects the every pixel of the image, where impulse noise IOBs, number of buffers calculated using Xilinx vivado 2015
affect the random pixel with fixed magnitude or with random design tools. The programming language we used for the
magnitude. Pixel affected with random magnitude noise called design is VHDL.
as random valued impulse noise (RVIN), on the other hand
pixel affected with fixed magnitude such as salt and pepper This paper organized as follows: Section I gives a brief
noise is called as Fixed valued impulse noise (FVIN). Image introduction of evolution and importance of noise detection
filtering/smoothing is an efficient solution for removing noise. and noise removal mechanisms in digital image processing.
Nonlinear filters works very well on removing impulse noise Section II describes the proposed method, Section III
without affecting the pixel. Median filter is a widely used hardware implementation method. Section IV describes the
nonlinear filter due to its effectiveness in removing noise. filter evaluation, noise model and Performance measuring
Median filter works on the principle of changing the center parameters. In section V results and resource utilization report
pixel with median of the window irrespective of are summarized and concluded in section VI
existence/absence of noise.
Recently, many image de-noising methods have been
proposed for impulse noise suppression [3]-[6]. Some of them
II. PROPOSED METHOD
employ the simple median filter [2] or its modifications [3],
[4] to make a balance between edge preservation and In proposed algorithm a noisy pixel is detected by passing
complexity. Some of the modified median filter are, the center center pixel of each window through the fixed threshold value

978-1-5386-1703-8/17/$31.00 ©2017 IEEE

‘0’ and ‘255’, which is preset before start of the process. If the
center pixel value lies in between the threshold value then it is
noise free and kept as it is, otherwise the median value of the
corresponding window is checked for the threshold. If the
median is noise free then it will replace the center pixel else
using decision based algorithm it will replace the center pixel
by the fourth or sixth number pixel of the sorting list. If the
fourth and sixth pixel are also noisy then mean of the first
three pixel of the sorted list replace the center pixel. Sorting
will be done in ascending order as shown in Fig. 1. Fig. 3. 3x3 filtering window.

Median filter is one of the most important non-linear filter for III. HARDWARE IMPLEMENTATION
removal of the impulse noise. In median filter the noisy pixel
value is replaced with the median value of the respective The hardware implementation of the proposed algorithm is
window. For odd window median value is calculated by done using VHDL programming language in Xilinx vivado
arranging all the pixel of the window in ascending order and 2015.2, the proposed architectures are designed in pipeline
after arrangement middle value will be the median of the manner to minimize computational time. Parallel processing
corresponding window. has also been done for process acceleration. A 3x3 filtering
window has been selected for computation of the filter output.
­n +1 The design of the threshold median filter consists of different
Median ( M x ) = ® , if n is odd (1) operational stages which are described in the following
¯ 2 paragraphs.

17 19 25 Sorting= 0, 3, 17, 19, 25, 65, 82, 165, 255.

82 255 0
3 165 65 Here n=3
Fig. 1. 3×3 window

17 19 25
82 25 0 Median ( M x ) = 25
Fig. 4. FPGA design flow architecture.
3 165 65
The pixel values of the input image are imported into
module serially for filtering. In order to obtain the 3 x 3
Fig. 2. Median value replace noisy center pixel. window, a set of Delay Blocks are used to generate the row of
Proposed algorithm the window. For generation of this window, two delay blocks
are required for each row in which the first pixel processed
i) Select a 3×3 window in a noisy image. zero latency and the other two take one latency individually. A
ii) Set the fixed threshold value to ‘0’ and ‘255’ as 3x3 window creation module is depicted in Figure 5.
first threshold value and check noisy image pixel
value.
iii) If the pixel value is greater than the ‘0’ and less
and less than ‘255’ then the pixel is noise free
and kept as it is.
iv) If the pixel value is equal to ‘0’ or ‘255’ then
replace the centre pixel with median of the
corresponding window if it is noise free.
v) If the median is noisy then replace the centre
pixel with neighbour pixel value of the median.
Neighbour pixels are fourth and sixth pixel of the
sorting list.
vi) Replace the centre pixel with the mean of first,
second and third pixel value of the sorted list if
neighbour pixels are also noisy.

A generalized filtering window is ‘w’ is formed after partition

of the image consists of ‘r’ rows, ‘c’ columns and ‘D’ Fig. 5. 3x3 window creation module.
diagonals.
The median value is calculated by sorting/arranging the odd
window pixel value in ascending or descending order and
choose the middle value as a median for replacement of the
center pixel. Hardware implementation module of the median
filter is shown in fig 6.
(2)

Where yij denotes the pixel of the corrupted image, φij denote
the pixel, Ps and Pp are the probability of pixel corrupted with
salt and pepper noise respectively.

LENA 10% Noise 30% Noise

Fig. 6. Architecture of the sorting algorithm.

IV. FILTER EVALUATION PEPPERS

The filter is evaluated in this section on a set of commonly
used gray images. Fig 7 (a), (b), (c) shows the Lena, mandrill
and peppers images on which the performance of the new filter
is analyzed by considering a 3×3 window size.

MANDRILL

(a)

Fig. 8. Corrupted images of Lena, Peppers and mandrill.

B. Filter Performance parameters

Filtering performance is evaluated using parameters like
mean squared error (MSE) [10] and peak signal to noise
ratio (PSNR) [12]. MSE measures the noise suppression
capability of the filter.
(b)

M N
1
MSE =
MN
¦¦ [a(i, j ) − a(i, j)]
i =1 j =1
2
(3)

255 2
PSNR = 10 * log10 (4)
MSE
(c)
Fig. 7. Images of Lena, peppers and Mandrill. Where M & N denotes the size of the gray image. a is

A. Noise Model original image and a is filtered image.

The noise model for an impulse noise can be expressed as
 V. IMPLEMENTATION AND RESULTS PEPPERS 10 13.8685 1.9731
The proposed filter is simulated in MATLAB 2012.2 and 20 22.6618 5.2652
hardware implementation is done on Artix-7 XC7A100t- 30 40.5508 10.1032
1csg324c family FPGA board using Xilinx vivado 2015 design 40 62.5087 18.3011
tool. The performance and resource utilization report of the 50 142.1575 29.8993
proposed filter is given on table I (a), I (b) and II. 60 291.0694 56.2237
70 711.6742 87.1914
MANDRILL 10 123.2387 27.6509
Table I. (a). Comparison of PSNR values at different noise 20 136.7330 44.4494
ratio on LENA, PEPPERS and MANDRILL images (256×256 30 157.7602 63.6474
pixels)
40 191.8136 89.1118
50 273.7089 123.2717
IMAGE NOISE Median PROPOSED 60 418.7360 165.7586
LENA 10 34.1752 42.7221 70 20.8362 232.4166

20 32.7006 38.5276
30 31.3819 36.3085
40 29.6204 33.9374
Table II. Results of resources used by filters implemented
50 26.7377 32.0375 in FPGA (3×3 window size).
60 23.9854 29.7243 FILTERS RESOURCES ARTIX-7
70 21.0491 27.8728
MEDIAN FILTER Slice register 285
PEPPERS 10 38.4738 46.9402
LUT 366
20 36.3388 42.6776
Flip-flop 231
30 33.8117 39.8471
40 31.9323 37.2669 BUFG 1
50 28.3640 35.1351 PROPOSED Slice register 533
ADAPTIVE
60 25.2518 32.3925 LUT 610
DECISION BASED
70 21.3689 30.4870 MEDIAN FILTER Flip-flop 334
MANDRILL 10 28.9342 35.4746
BUFG 1
20 28.5330 33.4131
30 27.9117 31.8539
40 27.0629 30.3924
50 25.5188 28.9831 VI. CONCLUSION
This paper presented an adaptive decision based median
60 23.6723 27.6970
filter with an efficient hardware implementation method.
70 20.8362 26.2290 Experiments on three images show that the filter outperforms
the simple median filter in all the noise ratio in preserving the
signal content. The filter providing better PSNR values in
higher noise ratios. The proposed hardware design is
implemented on Artix-7 FPGA board. Future works will be
implementing a modified threshold based median filter with
Table I. (b). Comparison of MSE values at different noise better signal to noise ratio with less hardware resources.
ratio on LENA, PEPPERS and MANDRILL images (256×256
pixels).
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