Lenovo Ideacentre b520 Compal La-7811p Rev.0.1 Qla01 SCH

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A B C D E

ZZZ2 ZZZ1 ZZZ3 ZZZ4 ZZZ5 ZZZ6 ZZZ7 ZZZ8 http://adf.ly/3o8pJ


PCB LA-7811P LS-6951P LS-6953P LS-6955P LS-6956P LS-6957P LS-6958P
DAZ@ DA2@ DA2@ DA2@ DA2@ DA2@ DA2@ DA2@

1 1

Compal Confidential
2

QLA01 LA7811P Schematics Document 2

Intel Sandy Bridge Processor with DDRIII + Cougar Point


AIO M/B

3 3

2011-06-02
REV:0.1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 09, 2011 Sheet 1 of 63
A B C D E
5 4 3 2 1

Compal Confidential http://adf.ly/3o8pJ


VRAM 512MB *1* :2D Display
Model Name : QLAO1 VRAM 1 GB
File Name : LA7811P
DDR3 x4 *2* :3D Display
P.28~30 DDR3-SO-DIMM DDR3-SO-DIMM
Intel CPU BANK 0, 1 BANK 0, 1
P.10 P.11
D Sandy Bridge D

23 LCD VGA 1066/1333MHz 1.5V 1066/1333MHz 1.5V


PEGx16 Desktop Channel A Channel B
NVdia N12P-GV
17W HDMI
OUT
65W F B-CAS
LVDS conn SPI ROM
W25X40BVSNIG 29mm x 29mm B LGA1155
RF IN
P.34 SOIC 8P 37.5mm x 37.5mm
P.21~27
P.33 P.4~9
Option
DVI from dGPU
DTV
FDIx8 DMIx4 USB USB2.0 x2 Touch BT Recorder TV Tuner
HDMI OUT
100 MHz 100 MHz WebCAM Side port A Screen
P.34 P.46
Conn
P.46
On Mini Card
P.34 P.44 P.42

G
DVI from UMA PCH USB2.0 x11
Port 11
Port 5

Scalar Cougar Point 3.3V 48MHz Port 5 Port 0,1 Port 2,3,8,9 Port 4 Port 10 Port 11
DVI
C
Realtek H61 PCIEx4 100MHz 2.5/5.0 GT/S
C

RTD2667 Port 2 Port 6 Port 1


HD_Audio
3.3V 24MHz
FCBGA-942 SATAx3 SATA 1.5/3.0 GT/S
Port 4

P.33 HP conn 27mm x 27mm Port 0 SATA2.0 Port 1 SATA2.0


P.41
P.12~20
HP_SCA_LEFT HP_RIGHT
3.5" SATA ODD Realtek Card Reader WLAN
HP_SCA_RIGHT HP_LEFT SATA HDD Conn LAN RT5209 On Mini Card
Conn RTL8111E-VL 7 in 1 or better
P.35 P.35 P.38 P.37 P.42
HP_2932_LEFT HP AMP Audio Codec SPI ROM
HP_2932_RIGHT APA2176A MX25L3206 Slim BD support 3D GIGA
I2S P.41 ALC663-GR EM2I-12G LAN
P.39 (4MB) P.13
SPI ROM
LPC MX25L1005
33MHz AMC-12G
P.44
A E F
B
IO Board P.36 B

AMP x1 INT EXT KBC


APA_106
P.40
MIC
P.36
MIC
P.41
E PS/2
ENE KB930-A1
P.43
RJ45 USB3.0 x2
NEC uPD720200A HDMI IN Antenna Jack
Conn
P.38 P.38

SPK 3W x2 USB2.0 AV-IN


USB3.0 PS/2
P.40
JPWR1
ATV & HTV Board USB2.0 x2 USB2.0/3.0 HDMI OUT
CVBS AIN-L AIN-R
Conn x2 Conn P.38
DVI
G
HDMI
IN SW1
4 ch. LVDS Scalar Control C B C D-1 D-2
Power ENE Touch D AV
IN
CVBS
A
D-1 Button SB3534 Button AIN SW AIN
A

TS5A23157
P.32 P.48 P.46 H P.47

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 2011/07/20 Title
23.6" LCD Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
120Hz LCD AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom QLA01 M/B LA-7811P Schematic
1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 09, 2011 Sheet 2 of 63
5 4 3 2 1
5 4 3 2 1

DMI_PTX_HRX_N[0..3] 14
http://adf.ly/3o8pJ PEG_GTX_C_HRX_P[0..15] 22
DMI_PTX_HRX_P[0..3] 14 PEG_GTX_C_HRX_N[0..15] 22

DMI_HTX_PRX_N[0..3] 14 PEG_HTX_C_GRX_P[0..15] 22
DMI_HTX_PRX_P[0..3] 14 PEG_HTX_C_GRX_N[0..15] 22
SKT_H2
JCPU1C Note:Use 0.1uF now; If need to support to Gen3, need change C1~C32 to 0.22uF.
<REV>
PEG_GTX_C_HRX_P15 B11 C13 PEG_HTX_GRX_P15 C1 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P15
PEG_GTX_C_HRX_N15 PEG_RX[0] PEG_TX[0] PEG_HTX_GRX_N15 C2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N15
B12 PEG_RX#[0] PEG_TX#[0] C14 1 2
D PEG_GTX_C_HRX_P14 D12 E14 PEG_HTX_GRX_P14 C3 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P14 D
PEG_GTX_C_HRX_N14 PEG_RX[1] PEG_TX[1] PEG_HTX_GRX_N14 C4 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N14
D11 PEG_RX#[1] PEG_TX#[1] E13 1 2
PEG_GTX_C_HRX_P13 C10 G14 PEG_HTX_GRX_P13 C5 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P13
PEG_GTX_C_HRX_N13 PEG_RX[2] PEG_TX[2] PEG_HTX_GRX_N13 C6 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N13
C9 PEG_RX#[2] PEG_TX#[2] G13 1 2
PEG_GTX_C_HRX_P12 E10 F12 PEG_HTX_GRX_P12 C7 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P12
PEG_GTX_C_HRX_N12 PEG_RX[3] PEG_TX[3] PEG_HTX_GRX_N12 C8 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N12
E9 PEG_RX#[3] PEG_TX#[3] F11 1 2
PEG_GTX_C_HRX_P11 B8 J14 PEG_HTX_GRX_P11 C9 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P11
PEG_GTX_C_HRX_N11 PEG_RX[4] PEG_TX[4] PEG_HTX_GRX_N11 C10 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N11
B7 PEG_RX#[4] PEG_TX#[4] J13 1 2
PEG_GTX_C_HRX_P10 C6 D8 PEG_HTX_GRX_P10 C11 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P10
PEG_GTX_C_HRX_N10 PEG_RX[5] PEG_TX[5] PEG_HTX_GRX_N10 C12 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N10
C5 PEG_RX#[5] PEG_TX#[5] D7 1 2
PEG_GTX_C_HRX_P9 A5 D3 PEG_HTX_GRX_P9 C13 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P9
PEG_GTX_C_HRX_N9 PEG_RX[6] PEG_TX[6] PEG_HTX_GRX_N9 C14 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N9
A6 PEG_RX#[6] PEG_TX#[6] C3 1 2

PEG
PEG_GTX_C_HRX_P8 E2 E6 PEG_HTX_GRX_P8 C15 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P8
PEG_GTX_C_HRX_N8 PEG_RX[7] PEG_TX[7] PEG_HTX_GRX_N8 C16 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N8
E1 PEG_RX#[7] PEG_TX#[7] E5 1 2
PEG_GTX_C_HRX_P7 F4 F8 PEG_HTX_GRX_P7 C17 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P7
PEG_GTX_C_HRX_N7 PEG_RX[8] PEG_TX[8] PEG_HTX_GRX_N7 C18 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N7
F3 PEG_RX#[8] PEG_TX#[8] F7 1 2
PEG_GTX_C_HRX_P6 G2 G10 PEG_HTX_GRX_P6 C19 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P6
PEG_GTX_C_HRX_N6 PEG_RX[9] PEG_TX[9] PEG_HTX_GRX_N6 C20 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N6
G1 PEG_RX#[9] PEG_TX#[9] G9 1 2
PEG_GTX_C_HRX_P5 H3 G5 PEG_HTX_GRX_P5 C21 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P5
PEG_GTX_C_HRX_N5 PEG_RX[10] PEG_TX[10] PEG_HTX_GRX_N5 C22 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N5
H4 PEG_RX#[10] PEG_TX#[10] G6 1 2
PEG_GTX_C_HRX_P4 J1 K7 PEG_HTX_GRX_P4 C23 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P4
PEG_GTX_C_HRX_N4 PEG_RX[11] PEG_TX[11] PEG_HTX_GRX_N4 C24 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N4
J2 PEG_RX#[11] PEG_TX#[11] K8 1 2
PEG_GTX_C_HRX_P3 K3 J5 PEG_HTX_GRX_P3 C25 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P3
PEG_GTX_C_HRX_N3 PEG_RX[12] PEG_TX[12] PEG_HTX_GRX_N3 C26 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N3
K4 PEG_RX#[12] PEG_TX#[12] J6 1 2
PEG_GTX_C_HRX_P2 L1 M8 PEG_HTX_GRX_P2 C27 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P2
PEG_GTX_C_HRX_N2 PEG_RX[13] PEG_TX[13] PEG_HTX_GRX_N2 C28 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N2
L2 PEG_RX#[13] PEG_TX#[13] M7 1 2
PEG_GTX_C_HRX_P1 M3 L6 PEG_HTX_GRX_P1 C29 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P1
PEG_GTX_C_HRX_N1 PEG_RX[14] PEG_TX[14] PEG_HTX_GRX_N1 C30 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N1
M4 PEG_RX#[14] PEG_TX#[14] L5 1 2
PEG_GTX_C_HRX_P0 N1 N5 PEG_HTX_GRX_P0 C31 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P0
C PEG_GTX_C_HRX_N0 PEG_RX[15] PEG_TX[15] PEG_HTX_GRX_N0 C32 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N0 C
N2 PEG_RX#[15] PEG_TX#[15] N6 1 2

DMI_PTX_HRX_P0 W5 V7 DMI_HTX_PRX_P0
DMI_PTX_HRX_N0 DMI_RX[0] DMI_TX[0] DMI_HTX_PRX_N0
W4 DMI_RX#[0] DMI_TX#[0] V6
DMI_PTX_HRX_P1 V3 W7 DMI_HTX_PRX_P1
DMI_PTX_HRX_N1 DMI_RX[1] DMI_TX[1] DMI_HTX_PRX_N1
V4 DMI_RX#[1] DMI_TX#[1] W8
DMI_PTX_HRX_P2 Y3 Y6 DMI_HTX_PRX_P2
DMI_PTX_HRX_N2 DMI_RX[2] DMI_TX[2] DMI_HTX_PRX_N2
DMI

Y4 DMI_RX#[2] DMI_TX#[2] Y7
DMI_PTX_HRX_P3 AA4 AA7 DMI_HTX_PRX_P3
DMI_PTX_HRX_N3 DMI_RX_3 DMI_TX[3] DMI_HTX_PRX_N3
AA5 DMI_RX#[3] DMI_TX#[3] AA8

P3 PE_RX[0] PE_TX[0] P8
P4 PE_RX#[0] PE_TX#[0] P7
R2 PE_RX[1] PE_TX[1] T7
R1 PE_RX#[1] PE_TX#[1] T8 7/20 PE_TX[0~3]/PE_TX#[0~3] only use on
7/20 PE_RX[0~3]/PE_RX#[0~3] only use on T4 PE_RX[2] PE_TX[2] R6 Workstation.
GEN

Workstation. T3 PE_RX#[2] PE_TX#[2] R5


U2 PE_RX[3] PE_TX[3] U5
U1 PE_RX#[3] PE_TX#[3] U6
+1.05VCCIO

24.9_0402_1% 2 1 R1 PEG_IRCOMP B5 PEG_ICOMPO H_FDI_TXN[0..7] 16


C4 PEG_RCOMPO H_FDI_TXP[0..7] 16
B4 PEG_ICOMPI SKT_H2
JCPU1D

LOTES_ACAZIF096P01_SANDYBRIDGE 3 OF 11
PEG_ICOMPI and RCOMPO signals should be shorted and CONN@ AC8 H_FDI_TXP0
FDI_TX[0] H_FDI_TXN0
FDI_TX#[0] AC7
B routed 16 H_FDI_FSYNC0 AC5 AC2 H_FDI_TXP1 B
FDI_FSYNC_0 FDI_TX[1] H_FDI_TXN1
with - max length = 500 mils - ;Width/Space= (4 mils/15mils) 16 H_FDI_LSYNC0 AC4 FDI_LSYNC_0 FDI_TX#[1] AC3
FDI_TX[0] AD2 H_FDI_TXP2
PEG_ICOMPO signals should be routed with - max length = FDI_TX[2] H_FDI_TXN2
FDI_TX#[2] AD1
AD4 H_FDI_TXP3
500 mils FDI_TX[3]
AD3 H_FDI_TXN3
FDI_TX#[3]
- Width/Space (12 mils/15mils)
AD7 H_FDI_TXP4
FDI_TX[4] H_FDI_TXN4
FDI_TX#[4] AD6
AE5 AE7 H_FDI_TXP5
16 H_FDI_FSYNC1 FDI_FSYNC_1 FDI_TX[5]
AE4 AE8 H_FDI_TXN5
16 H_FDI_LSYNC1 FDI_LSYNC_1 FDI_TX#[5]
AF3 H_FDI_TXP6
FDI_TX[6] H_FDI_TXN6
FDI_TX#[6] AF2
AG2 H_FDI_TXP7
FDI_TX[7] H_FDI_TXN7
FDI_TX#[7] AG1
1000P_0402_50V7K @ 2 1 C1007 H_FDI_FSYNC0
+1.05VCCIO 16 H_FDI_INT AG3 FDI_INT
1000P_0402_50V7K @ 2 1 C1008 H_FDI_LSYNC0 FDI
24.9_0402_1% 2 1 R2 FDI_ICOMP AE2 LINK
1000P_0402_50V7K @ FDI_COMPIO
2 1 C1009 H_FDI_FSYNC1 AE1 FDI_ICOMPO
1000P_0402_50V7K @ 2 1 C1010 H_FDI_LSYNC1
4 OF 11
LOTES_ACAZIF096P01_SANDYBRIDGE
1000P_0402_50V7K @ 2 1 C1011 H_FDI_INT CONN@

8/23 Add
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (1/6) DMI,FDI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 16, 2011 Sheet 4 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ +1.05VCCIO

SKT_H2
JCPU1E
H_CATERR# 1K_0402_5% 2 @ 1 R6
H_PECI 1K_0402_5% 2 @ 1 R7
XDP_TDO_R 51_0402_5% 2 1 R8
0_0402_5% 1 R656 CLK_CPU_DMI_R XDP_TDI_R 51_0402_5% R9
17 CLK_CPU_DMI 2 W2 BCLK[0] VCCIO_SELECT P33 2 1
0_0402_5% 1 R657 2 CLK_CPU_DMI#_R W1 P34 VCCSA_VID VCCSA_VID 53 XDP_TMS_R 51_0402_5% 2 1 R10
17 CLK_CPU_DMI# BCLK#[0] VCCSA_VID_0
D T2 VCCSA_SENSE VCCSA_SENSE 53 H_VIDALERT# 75_0402_1% 2 1 R11 D
H_VIDSCLK VCCSA_SENSE H_VIDSCLK 90.9_0402_1% @
57 H_VIDSCLK C37 VIDSCLK 2 1 R12
H_VIDSOUT B37 A36 VCCSENSE H_VIDSOUT 110_0402_1% 2 1 R13
57 H_VIDSOUT H_VIDALERT# R300 1 VIDSOUT VCC_SENSE VCCSENSE 57
57 H_VIDALERT# 2 43_0402_1% H_VIDALERT#_R A37
VIDALERT# VSS_SENSE B36 VSSSENSE
VSSSENSE 57
H_THERMTRIP#_R 51_0402_5% 2 @ 1 R501
H_PROCHOT# 51_0402_5% 2 1 R521
AB4 VCCIO_SENSE VCCIO_SENSE 54 H_THERMTRIP# 51_0402_5% 2 @ 1 R715
13 H_CPUPW RGD VCCIO_SENSE
H_CPUPW RGD J40 AB3
PM_SYS_PW RGD_BUF 2 R644 1 PM_SYS_PW RGD_R AJ19 UNCOREPWRGOOD VSSIO_SENSE
120_0402_5% H_RESET# SM_DRAMPWROK VGFX_VCCSENSE
F36 RESET# VCCAXG_SENSE L32 VGFX_VCCSENSE 57
M32 VGFX_VSSSENSE VGFX_VSSSENSE 57
H_PM_SYNC VSSAXG_SENSE XDP_TRST#_R 51_0402_5% 2 R14
12 H_PM_SYNC E38 PM_SYNC 1
H_PECI J35 L39 XDP_TDO_R XDP_TCLK_R 51_0402_5% 2 1 R15
12,43 H_PECI H_CATERR# PECI TDO XDP_TDI_R H_CPUPW RGD 1K_0402_5% 2
E37 L40 1 R579
H_PROCHOT# CATERR# TDI XDP_TCLK_R
43 H_PROCHOT# H34 PROCHOT# TCK M40
0_0402_5% 2 R500 1 H_THERMTRIP#_R G35 L38 XDP_TMS_R
12 H_THERMTRIP# THERMTRIP# TMS
J39 XDP_TRST#_R
+1.5V TRST#
AJ33 SKTOCC# PRDY# K38
H_SNB_IVB# K32 K40
15 H_SNB_IVB# PROC_SEL PREQ#
E39 XDP_DBR#_R R5 1 2 0_0402_5% XDP_DBRETSET#
DBR# XDP_DBRETSET# 13
1

DDR_VREF AJ22 C40 CLK_CPU_ITP_R T80


SM_VREF BCLK_ITP CLK_CPU_ITP#_R
BCLK_ITP# D40 T81
R638
100_0402_1%
T73 CFG0 H36 H40
2

DDR_VREF CFG1 CFG[0] BPM#[0]


T74 J36 CFG[1] BPM#[1] H38
CFG2 J37 G38
CFG[2] BPM#[2]
1

1 CFG3 K36 G40


CFG4 CFG[3] BPM#[3]
T75 L36 CFG[4] BPM#[4] G39 9/29 Del NET:XDP_BPM#[0..7]_R
R639 C777 CFG5 N35 F38
C 100_0402_1% 0.1U_0402_16V4Z CFG6 CFG[5] BPM#[5] C
L37 CFG[6] BPM#[6] E40
2 CFG7 +1.5V
T62 M36 F40
2

CFG8 CFG[7] BPM#[7]


T63 J38 CFG[8]
T64 CFG9 L35 B39
CFG[9] RSVD

1
T65 CFG10 M38 J33
CFG11 CFG[10] RSVD R643
T66 N36 CFG[11] RSVD L34
T67 CFG12 N38 L33 200_0402_5%
CFG13 CFG[12] RSVD
T68 N39 CFG[13] RSVD K34
T69 CFG14 N37

2
CFG15 CFG[14]
T70 N40 CFG[15]
9/29 Del R557/R558/R561/R564~R574 T71 CFG16 G37 N33 R641 1 2 0_0402_5% PM_SYS_PW RGD_BUF
CFG[16] RSVD 13 DRAMPW ROK
T72 CFG17 G36 M34
1K_0402_5% R559 CFG2 CFG[17] RSVD
2 1

1
1K_0402_5% 2 @ 1 R560 CFG3
1K_0402_5% 2 @ 1 R562 CFG5 AT14 AV1 R642
1K_0402_5% @ R563 CFG6 RSVD RSVD 39_0402_5%
2 1 RSVD AW2
AY3 @
RSVD
L9

1 2
RSVD
H7 RSVD RSVD J9 D
H8 RSVD RSVD K9
PEG Static x16 Lane Numbering Reversal. SUSP 2
47,48,55 SUSP
G Q17
1: Normal Operation L31 S SSM3K7002FU_SC70-3

3
RSVD @
CFG2
0:Lane numbers Reversed J31 @
* RSVD
RSVD K31 H_CPUPW RGD C1030 1 2 1000P_0402_50V7K

PEG Static x4 Lane Numbering Reversal. AD34 @


RSVD PM_SYS_PW RGD_R C997 1 1000P_0402_50V7K
RSVD AD35 2
B B
1: Normal Operation
CFG3 * 0:Lane numbers Reversed MISC

PCIE Port Bifurcation Straps


LOTES_ACAZIF096P01_SANDYBRIDGE 5 OF 11
CONN@
11: 1x16 PCI Express (Default)
*10: 2x8 PCI Express
CFG[6:5]
01: Reserved
00: 1 x 8, 2 x 4 : PCI Express

+3VS

0.1U_0402_16V4Z
1
+1.05VCCIO
C748
1

R325
A
U19 1.2K_0402_1% A
5

74AHC1G09GW _TSSOP5 R294


2

1 43_0402_1%
P

B
O 4H_RESET#_R 1 2 H_RESET#
PCH_PLT_RST# 2
13,38,43 PCH_PLT_RST# A
G

R577
Security Classification Compal Secret Data Compal Electronics, Inc.
3

0_0402_5%
@ 2010/07/20 2011/07/20 Title
Issued Date Deciphered Date
PROCESSOR (2/6) CLK,JTAG
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 5 of 63
5 4 3 2 1
5 4 3 2 1

10 DDR_A_D[0..63]
http://adf.ly/3o8pJ 11 DDR_B_D[0..63]
11 DDR_B_DQS#[0..7]
10 DDR_A_DQS#[0..7] 11 DDR_B_DQS[0..7]
10 DDR_A_DQS[0..7] 11 DDR_B_MA[0..15]
10 DDR_A_MA[0..15]
SKT_H2 SKT_H2
JCPU1A JCPU1B

DDR_A_MA0 AV27 AJ3 DDR_A_D0 <REV>


DDR_A_MA1 SA_MA[0] SA_DQ[0] DDR_A_D1 DDR_B_MA0 <BALLMAP_REV> DDR_B_D0
AY24 SA_MA[1] SA_DQ[1] AJ4 AK24 SB_MA[0] SB_DQ[0] AG7
DDR_A_MA2 AW24 AL3 DDR_A_D2 DDR_B_MA1 AM20 AG8 DDR_B_D1
DDR_A_MA3 AW23 SA_MA[2] SA_DQ[2] DDR_A_D3 DDR_B_MA2 SB_MA[1] SB_DQ[1] DDR_B_D2
SA_MA[3] SA_DQ[3] AL4 AM19 SB_MA[2] SB_DQ[2] AJ9
D DDR_A_MA4 AV23 AJ2 DDR_A_D4 DDR_B_MA3 AK18 AJ8 DDR_B_D3 D
DDR_A_MA5 SA_MA[4] SA_DQ[4] DDR_A_D5 DDR_B_MA4 SB_MA[3] SB_DQ[3] DDR_B_D4
AT24 SA_MA[5] SA_DQ[5] AJ1 AP19 SB_MA[4] SB_DQ[4] AG5
DDR_A_MA6 AT23 AL2 DDR_A_D6 DDR_B_MA5 AP18 AG6 DDR_B_D5
DDR_A_MA7 SA_MA[6] SA_DQ[6] DDR_A_D7 DDR_B_MA6 SB_MA[5] SB_DQ[5] DDR_B_D6
AU22 SA_MA[7] SA_DQ[7] AL1 AM18 SB_MA[6] SB_DQ[6] AJ6
DDR_A_MA8 AV22 AN1 DDR_A_D8 DDR_B_MA7 AL18 AJ7 DDR_B_D7
DDR_A_MA9 SA_MA[8] SA_DQ[8] DDR_A_D9 DDR_B_MA8 SB_MA[7] SB_DQ[7] DDR_B_D8
AT22 SA_MA[9] SA_DQ[9] AN4 AN18 SB_MA[8] SB_DQ[8] AL7
DDR_A_MA10 AV28 AR3 DDR_A_D10 DDR_B_MA9 AY17 AM7 DDR_B_D9
DDR_A_MA11 AU21 SA_MA[10] SA_DQ[10] DDR_A_D11 DDR_B_MA10 SB_MA[9] SB_DQ[9] DDR_B_D10
SA_MA[11] SA_DQ[11] AR4 AN23 SB_MA[10] SB_DQ[10] AM10
DDR_A_MA12 AT21 AN2 DDR_A_D12 DDR_B_MA11 AU17 AL10 DDR_B_D11
DDR_A_MA13 AW32 SA_MA[12] SA_DQ[12] DDR_A_D13 DDR_B_MA12 SB_MA[11] SB_DQ[11] DDR_B_D12
SA_MA[13] SA_DQ[13] AN3 AT18 SB_MA[12] SB_DQ[12] AL6
DDR_A_MA14 AU20 AR2 DDR_A_D14 DDR_B_MA13 AR26 AM6 DDR_B_D13
DDR_A_MA15 AT20 SA_MA[14] SA_DQ[14] DDR_A_D15 DDR_B_MA14 SB_MA[13] SB_DQ[13] DDR_B_D14
SA_MA[15] SA_DQ[15] AR1 AY16 SB_MA[14] SB_DQ[14] AL9
AV2 DDR_A_D16 DDR_B_MA15 AV16 AM9 DDR_B_D15
DDR_A_W E# AW29 SA_DQ[16] DDR_A_D17 SB_MA[15] SB_DQ[15] DDR_B_D16
10 DDR_A_W E# SA_WE# SA_DQ[17] AW3 SB_DQ[16] AP7
DDR_A_CAS# AV30 AV5 DDR_A_D18 DDR_B_W E# AR25 AR7 DDR_B_D17
10 DDR_A_CAS# SA_CAS# SA_DQ[18] 11 DDR_B_W E# SB_WE# SB_DQ[17]
DDR_A_RAS# AU28 AW5 DDR_A_D19 DDR_B_CAS# AK25 AP10 DDR_B_D18
10 DDR_A_RAS# SA_RAS# SA_DQ[19] 11 DDR_B_CAS# SB_CAS# SB_DQ[18]
AU2 DDR_A_D20 DDR_B_RAS# AP24 AR10 DDR_B_D19
SA_DQ[20] 11 DDR_B_RAS# SB_RAS# SB_DQ[19]
AU3 DDR_A_D21 AP6 DDR_B_D20
DDR_A_BS0 SA_DQ[21] DDR_A_D22 DDR_B_BS0 SB_DQ[20] DDR_B_D21
10 DDR_A_BS0 AY29 SA_BS_0 SA_DQ[22] AU5 11 DDR_B_BS0 AP23 SB_BS[0] SB_DQ[21] AR6
DDR_A_BS1 AW28 AY5 DDR_A_D23 DDR_B_BS1 AM24 AP9 DDR_B_D22
10 DDR_A_BS1 SA_BS[1] SA_DQ[23] 11 DDR_B_BS1 SB_BS[1] SB_DQ[22]
DDR_A_BS2 AV20 AY7 DDR_A_D24 DDR_B_BS2 AW17 AR9 DDR_B_D23
10 DDR_A_BS2 SA_BS[2] SA_DQ[24] 11 DDR_B_BS2 SB_BS[2] SB_DQ[23]
AU7 DDR_A_D25 AM12 DDR_B_D24
SA_DQ[25] DDR_A_D26 SB_DQ[24] DDR_B_D25
SA_DQ[26] AV9 SB_DQ[25] AM13
AU29 AU9 DDR_A_D27 AN25 AR13 DDR_B_D26
10 DDR_A_CS0# SA_CS#[0] SA_DQ[27] 11 DDR_B_CS0# SB_CS#[0] SB_DQ[26]
AV32 AV7 DDR_A_D28 AN26 AP13 DDR_B_D27
10 DDR_A_CS1# SA_CS#[1] SA_DQ[28] 11 DDR_B_CS1# SB_CS#[1] SB_DQ[27]
AW30 AW7 DDR_A_D29 AL25 AL12 DDR_B_D28
SA_CS#[2] SA_DQ[29] DDR_A_D30 SB_CS#[2] SB_DQ[28] DDR_B_D29
AU33 SA_CS#[3] SA_DQ[30] AW9 AT26 SB_CS#[3] SB_DQ[29] AL13
AY9 DDR_A_D31 AR12 DDR_B_D30
SA_DQ[31] DDR_A_D32 SB_DQ[30] DDR_B_D31
10 DDR_A_CKE0 AV19 SA_CKE[0] SA_DQ[32] AU35 11 DDR_B_CKE0 AU16 SB_CKE[0] SB_DQ[31] AP12
C AT19 AW37 DDR_A_D33 AY15 AR28 DDR_B_D32 C
10 DDR_A_CKE1 SA_CKE[1] SA_DQ[33] 11 DDR_B_CKE1 SB_CKE[1] SB_DQ[32]
AU18 AU39 DDR_A_D34 AW15 AR29 DDR_B_D33
SA_CKE[2] SA_DQ[34] DDR_A_D35 SB_CKE[2] SB_DQ[33] DDR_B_D34
AV18 SA_CKE[3] SA_DQ[35] AU36 AV15 SB_CKE[3] SB_DQ[34] AL28
AW35 DDR_A_D36 AL29 DDR_B_D35
SA_DQ[36] DDR_A_D37 SB_DQ[35] DDR_B_D36
10 DDR_A_ODT0 AV31 SA_ODT[0] SA_DQ[37] AY36 11 DDR_B_ODT0 AL26 SB_ODT[0] SB_DQ[36] AP28
AU32 AU38 DDR_A_D38 AP26 AP29 DDR_B_D37
10 DDR_A_ODT1 SA_ODT[1] SA_DQ[38] 11 DDR_B_ODT1 SB_ODT[1] SB_DQ[37]
AU30 AU37 DDR_A_D39 AM26 AM28 DDR_B_D38
SA_ODT[2] SA_DQ[39] DDR_A_D40 SB_ODT[2] SB_DQ[38] DDR_B_D39
AW33 SA_ODT[3] SA_DQ[40] AR40 AK26 SB_ODT[3] SB_DQ[39] AM29
AR37 DDR_A_D41 AP32 DDR_B_D40
SA_DQ[41] DDR_A_D42 SB_DQ[40] DDR_B_D41
SA_DQ[42] AN38 SB_DQ[41] AP31
AN37 DDR_A_D43 SB_CK[0] AP35 DDR_B_D42
SA_DQ[43] DDR_A_D44 SB_DQ[42] DDR_B_D43
SA_DQ[44] AR39 SB_DQ[43] AP34
AY25 AR38 DDR_A_D45 AL21 AR32 DDR_B_D44
10 DDR_A_CLK0 SA_CK[0] SA_DQ[45] 11 DDR_B_CLK0 SB_CK[0] SB_DQ[44]
AW25 AN39 DDR_A_D46 AL22 AR31 DDR_B_D45
10 DDR_A_CLK0# SA_CK#[0] SA_DQ[46] 11 DDR_B_CLK0# SB_CK#[0] SB_DQ[45]
AU24 AN40 DDR_A_D47 AL20 AR35 DDR_B_D46
10 DDR_A_CLK1 SA_CK[1] SA_DQ[47] 11 DDR_B_CLK1 SB_CK[1] SB_DQ[46]
AU25 AL40 DDR_A_D48 AK20 AR34 DDR_B_D47
10 DDR_A_CLK1# SA_CK#[1] SA_DQ[48] 11 DDR_B_CLK1# SB_CK#[1] SB_DQ[47]
AW27 AL37 DDR_A_D49 AL23 AM32 DDR_B_D48
SA_CK[2] SA_DQ[49] DDR_A_D50 SB_CK[2] SB_DQ[48] DDR_B_D49
AY27 SA_CK#[2] SA_DQ[50] AJ38 AM22 SB_CK#[2] SB_DQ[49] AM31
AV26 AJ37 DDR_A_D51 AP21 AL35 DDR_B_D50
SA_CK[3] SA_DQ[51] DDR_A_D52 SB_CK[3] SB_DQ[50] DDR_B_D51
AW26 SA_CK#[3] SA_DQ[52] AL39 AN21 SB_CK#[3] SB_DQ[51] AL32
AL38 DDR_A_D53 AM34 DDR_B_D52
SA_DQ[53] DDR_A_D54 SB_DQ[52] DDR_B_D53
R16 SA_DQ[54] AJ39 SB_DQ[53] AL31
10,11 SM_DRAMRST# 2 1DRAMRST# AW18 SM_DRAMRST# SA_DQ[55] AJ40 DDR_A_D55 +V_DDR_REFB AH1 FC_AH1 SB_DQ[54] AM35 DDR_B_D54
AG40 DDR_A_D56 +V_DDR_REFA AH4 AL34 DDR_B_D55
0_0402_5% SA_DQ[56] FC_AH4 SB_DQ[55]
1 AG37 DDR_A_D57 1 1 AH35 DDR_B_D56
SA_DQ[57] DDR_A_D58 SB_DQ[56] DDR_B_D57
SA_DQ[58] AE38 SB_DQ[57] AH34
C33 AE37 DDR_A_D59 C614 C613 AE34 DDR_B_D58
SA_DQ[59] DDR_A_D60 SB_DQ[58] DDR_B_D59
.1U_0402_16V7K SA_DQ[60] AG39 .1U_0402_16V7K .1U_0402_16V7K SB_DQ[59] AE35
2 DDR_A_D61 2 2 DDR_B_D60
@ SA_DQ[61] AG38 SB_DQ[60] AJ35
B DDR_A_D62 DDR_B_D61 B
SA_DQ[62] AE39 SB_DQ[61] AJ34
AE40 DDR_A_D63 AF33 DDR_B_D62
SA_DQ[63] SB_DQ[62] DDR_B_D63
7/20 Intel-Need to add RC filter SB_DQ[63] AF35

AV13 AK3 DDR_A_DQS0 AN16 AH7 DDR_B_DQS0


SA_DQS[8] SA_DQS[0] DDR_A_DQS1 SB_DQS[8] SB_DQS[0] DDR_B_DQS1
AV12 SA_DQS#[8] SA_DQS[1] AP3 AN15 SB_DQS#[8] SB_DQS[1] AM8
AW4 DDR_A_DQS2 AR8 DDR_B_DQS2
SA_DQS[2] DDR_A_DQS3 SB_DQS[2] DDR_B_DQS3
AU12 SA_ECC_CB[0] SA_DQS[3] AV8 AL16 SB_ECC_CB[0] SB_DQS[3] AN13
AU14 AV37 DDR_A_DQS4 AM16 AN29 DDR_B_DQS4
SA_ECC_CB[1] SA_DQS[4] DDR_A_DQS5 SB_ECC_CB[1] SB_DQS[4] DDR_B_DQS5
AW13 SA_ECC_CB[2] SA_DQS[5] AP38 AP16 SB_ECC_CB[2] SB_DQS[5] AP33
AY13 AK38 DDR_A_DQS6 AR16 AL33 DDR_B_DQS6
SA_ECC_CB[3] SA_DQS[6] DDR_A_DQS7 SB_ECC_CB[3] SB_DQS[6] DDR_B_DQS7
AU13 SA_ECC_CB[4] SA_DQS[7] AF38 AL15 SB_ECC_CB[4] SB_DQS[7] AG35
AU11 SA_ECC_CB[5] AM15 SB_ECC_CB[5]
AY12 AK2 DDR_A_DQS#0 AR15 AH6 DDR_B_DQS#0
SA_ECC_CB[6] SA_DQS#[0] DDR_A_DQS#1 SB_ECC_CB[6] SB_DQS#[0] DDR_B_DQS#1
AW12 SA_ECC_CB[7] SA_DQS#[1] AP2 AP15 SB_ECC_CB[7] SB_DQS#[1] AL8
AV4 DDR_A_DQS#2 AP8 DDR_B_DQS#2
SA_DQS#[2] DDR_A_DQS#3 SB_DQS#[2] DDR_B_DQS#3
SA_DQS#[3] AW8 SB_DQS#[3] AN12
AV36 DDR_A_DQS#4 AN28 DDR_B_DQS#4
DDR_A SA_DQS#[4] DDR_A_DQS#5 SB_DQS#[4] DDR_B_DQS#5
SA_DQS#[5] AP39 DDR_B SB_DQS#[5] AR33
AK39 DDR_A_DQS#6 AM33 DDR_B_DQS#6
SA_DQS#[6] DDR_A_DQS#7 2 OF 11 SB_DQS#[6] DDR_B_DQS#7
SA_DQS#[7] AF39 SB_DQS#7] AG34

LOTES_ACAZIF096P01_SANDYBRIDGE 1 OF 11 LOTES_ACAZIF096P01_SANDYBRIDGE CONN@


CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (3/6) DDRIII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 16, 2011 Sheet 6 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ

+CPU_CORE:112A
+VGFX_CORE:35A
+CPU_CORE +CPU_CORE
SKT_H2 +VGFX_CORE
JCPU1F
D SKT_H2 D
JCPU1G

A12
VCC VCC
F32 +VGFX_CORE
A13 F33 AB33
A14
VCC
VCC
VCC
VCC
F34
+CPU_CORE
+CPU_CORE AB34
VCCAXG
VCCAXG +VGFX_CORE
A15 G15 AB35
VCC VCC VCCAXG
A16 G16 AB36
VCC VCC VCCAXG
A18 G18 AB37
VCC VCC 22U_0805_6.3V6M 22U_0805_6.3V6M VCCAXG 22U_0805_6.3V6M 22U_0805_6.3V6M
A24 G19 AB38
VCC VCC VCCAXG
A25 G21 AB39
VCC VCC VCCAXG
A27 G22 1 1 1 1 AB40 1 1 1 1
VCC VCC C34 C37 C35 C36 VCCAXG C38 C39 C40 C41
A28 VCC VCC G24 AC33 VCCAXG
B15 G25 AC34 UMA@ UMA@ UMA@ UMA@
VCC VCC VCCAXG
B16 VCC VCC G27 AC35 VCCAXG
B18 G28 2 2 2 2 AC36 2 2 2 2
VCC VCC 22U_0805_6.3V6M 22U_0805_6.3V6M VCCAXG 22U_0805_6.3V6M 22U_0805_6.3V6M
B24 VCC VCC G30 AC37 VCCAXG
B25 VCC VCC G31 AC38 VCCAXG
B27 VCC VCC G32 (Place these capacitors inside CPU socket cavity, top layer) AC39 VCCAXG (Place these capacitors inside CPU socket cavity, top layer)
B28 VCC VCC G33 AC40 VCCAXG
B30 VCC VCC H13 T33 VCCAXG
B31 VCC VCC H14 T34 VCCAXG
B33 H15 +CPU_CORE T35 +VGFX_CORE
VCC VCC VCCAXG
B34 VCC VCC H16 T36 VCCAXG
C15 VCC VCC H18 T37 VCCAXG
C16 H19 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M T38 22U_0805_6.3V6M
VCC VCC VCCAXG
C18 VCC VCC H21 T39 VCCAXG
C19 VCC VCC H22 1 1 1 1 1 1 1 T40 VCCAXG 1 1
C21 H24 C42 C43 C44 C45 C46 C47 C48 U33 C49 C50
VCC VCC VCCAXG UMA@ UMA@
C22 VCC VCC H25 U34 VCCAXG
C24 VCC VCC H27 U35 VCCAXG
2 2 2 2 2 2 2 2 2
C25 VCC VCC H28 U36 VCCAXG
C27 H30 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M U37 22U_0805_6.3V6M
C VCC VCC VCCAXG C
C28 VCC VCC H31 U38 VCCAXG
C30 VCC VCC H32 U39 VCCAXG (Place these capacitors under CPU socket, Bottom layer)
C31 J12 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M U40
VCC VCC VCCAXG
C33 VCC VCC J15 W33 VCCAXG
C34 VCC VCC J16 1
C51
1
C52
1
C53
1
C54
1
C55
1
C56
1
C57
W34 VCCAXG E-CAP package
C36 VCC VCC J18 W35 VCCAXG
D13 J19 W36 +VGFX_CORE
VCC VCC VCCAXG
D14 J21 W37
VCC VCC 2 2 2 2 2 2 2 VCCAXG 560U_2.5V_M_R10
D15 J22 W38
VCC VCC 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VCCAXG
D16 J24 Y33 1
VCC VCC VCCAXG

1
D18 J25 Y34
VCC VCC VCCAXG + + +
D19
VCC VCC
J27 (Place these capacitors under CPU socket, Bottom layer) Y35
VCCAXG
D21 J28 Y36 C58 C59 C60
VCC VCC VCCAXG 560U_2.5V_M UMA@ 560U_2.5V_M_R10
D22 J30 Y37

2
VCC VCC +CPU_CORE VCCAXG UMA@ 2 UMA@
D24 K15 Y38
VCC VCC VCCAXG
D25 K16
VCC VCC +CPU_CORE GFX POWER
D27
VCC VCC
K18 E-CAP package Near C64/C67
D28
VCC VCC
K19 1 1 (Place C58 capacitors under CPU socket, Top layer)
D30 K21 560U_2.5V_M 560U_2.5V_M 7 OF 11 (Place C59/C60 capacitors under CPU socket, Bottom layer)
VCC VCC C807 C808 LOTES_ACAZIF096P01_SANDYBRIDGE
D31 K22 1 1 1 1
VCC VCC @ @ CONN@
D33
VCC VCC
K24 8/24Change symbol of C58 from SF000001P00 to SF000001K00
D34 K25 + + + + 0.1U_0402_16V4Z 2 20.1U_0402_16V4Z
10/23 Change symbol of C59/C60 from SGA20331E10 to SF000002M00
VCC VCC C62 C63 C64 C67
D35
VCC VCC
K27 11/2 Change PN of C59/C60 from SF000002M00 to SF000001K00
D36 K28 560U_2.5V_M
VCC VCC 2 2 2 2
E15
VCC VCC
K30 10/27 Add C807/C808(ESD request)
E16 L13
VCC VCC 560U_2.5V_M
E18 L14
VCC VCC +VGFX_CORE
E19 L15
VCC VCC
E21
VCC VCC
L16 8/24Change symbol of C62~C63 from SF000001P00 to SF000001K00
E22
VCC VCC
L18 Near C58
E24
VCC VCC
L19 (Place C62~C64 capacitors under CPU socket, Top layer) 1
E25 L21
B VCC VCC C809 B
E27 L22
VCC VCC +CPU_CORE @
E28
VCC VCC
L24 Polymer package
E30 L25 10/8 Change symbol of C69 from SGA20331E10 to 0.1U_0402_16V4Z 2
VCC VCC
E31 L27
E33
VCC VCC
L28 SGA00005R00
VCC VCC 330U_2.5V_M_R15
E34
VCC VCC
L30 10/27 Add C809(ESD request)
E35 M14 1
VCC VCC
1

F15 M15
VCC VCC + + + +
F16 M16
VCC VCC C65 C66 C68 C69
F18 M18
VCC VCC 330U_2.5V_M_R15 @ 330U_D2_2VM_R6M
F19 M19
2

VCC VCC @ 2 3
F21 M21
VCC VCC
F22 M22
VCC VCC 560U_2.5V_M_R10
F24 M24
VCC VCC
F25 M25
VCC VCC
F27 M27
VCC VCC
F28
VCC VCC
M28 10/23 Change symbol of C65/C66/C68 from SGA20331E10 to SF000002M00
F30
VCC VCC
M30 (Place C65~C69 capacitors under CPU socket, Bottom layer)
F31
VCC
11/2 Change PN of C68 from SF000002M00 to SF000001K00
CPU POWER
6 OF 11
LOTES_ACAZIF096P01_SANDYBRIDGE
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (4/6) PWR,Bypass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 09, 2011 Sheet 7 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ

+1.05VCCIO SKT_H2
JCPU1H
8.5A
D 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M M13 +1.5V D
VCCIO
1 1 1 1 1 1 1 1 1 A11 AJ13
4.5A22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCCIO VDDQ
A7 AJ14 1 1

560U_2.5V_M_R10

560U_2.5V_M_R10
C70 C71 C72 C73 C74 C75 C76 C77 C78 VCCIO VDDQ
AA3 VCCIO VDDQ AJ23 1 1 1 1 1 1 1
+ +

C984

C985
@ @ @ @ AB8 AJ24 C79 C80 C81 C82 C83 C84 C85
2 2 2 2 2 2 2 2 2 VCCIO VDDQ @ @ @
AF8 VCCIO VDDQ AR20
AG33 AR21 @
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VCCIO VDDQ 2 2 2 2 2 2 2 2 2
AJ16 VCCIO VDDQ AR22
(Place these capacitors inside CPU socket cavity, top layer) AJ17 AR23 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCCIO VDDQ
AJ26 VCCIO VDDQ AR24
AJ28 VCCIO VDDQ AU19
AJ32 VCCIO VDDQ AU23
+1.05VCCIO AK15 AU27
VCCIO VDDQ
AK17 VCCIO VDDQ AU31 11/2 Change PN of C984/C985 from SF000002000 to SF000001K00
560U_2.5V_M_R10 AK19 AV21
VCCIO VDDQ
1 1 1 AK21 VCCIO VDDQ AV24
AK23 VCCIO VDDQ AV25
+ + + AK27 AV29
C86 C87 C88 VCCIO VDDQ
AK29 VCCIO VDDQ AV33
@ AK30 AW31
560U 2.5V M 2 2 2 VCCIO VDDQ
B9 VCCIO VDDQ AY23
D10 VCCIO VDDQ AY26
560U_2.5V_M_R10 D6 AY28
VCCIO VDDQ
E3 VCCIO
E4 VCCIO
G3 VCCIO
11/2 Change PN of C87/C88 from SF000001P00 to SF000001K00 G4 VCCIO VDDQ AJ20
J3 VCCIO
C J4 C
VCCIO
J7 VCCIO
J8 VCCIO
L3 VCCIO
L4 VCCIO
L7 VCCIO
N3 VCCIO
N4 VCCIO
N7 VCCIO
R3 VCCIO
R4 VCCIO
R7 VCCIO
U3 VCCIO
U4 VCCIO
11/4 Change PN of C91 from SF000001P00 to SF000001K00 U7 VCCIO
V8 VCCIO
W3 VCCIO
+VCCSA

10U_0805_6.3V6M 8.8A H10 VCCSA


1 H11 VCCSA
1 1 560U_2.5V_M_R10 H12
+ VCCSA
J10 VCCSA
C89 C90 C91 K10
10U_0805_6.3V6M VCCSA
K11 VCCSA
2 2 2
(Place these capacitors inside CPU socket cavity, top layer) L11 VCCSA
L12 VCCSA
M10 VCCSA
M11 VCCSA
B +1.8VS B
M12 VCCSA
1A AK11
VCCPLL
AK12 VCCPLL
1

1
+ C93 IO/SA/PLL
C92 330U_6.3V_M_R14 POWER
10U_0805_6.3V6M
2

2
8 OF 11
LOTES_ACAZIF096P01_SANDYBRIDGE
10/23 Change symbol of C93 from SGA00000Y80 to SF000002N00 CONN@
11/4 Change PN of C93 from SF000002N00 to SF000001G00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (5/6) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 09, 2011 Sheet 8 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ
JCPU1K
SKT_H2
JCPU1I AV11 G8
VSS VSS
A17 VSS VSS AM27 AV14 VSS VSS H1
A23 VSS VSS AM3 AV17 VSS VSS H17
A26 VSS VSS AM30 AV3 VSS VSS H2
A29 VSS VSS AM36 AV35 VSS VSS H20
A35 VSS VSS AM37 AV38 VSS VSS H23
AA33 VSS VSS AM38 AV6 VSS VSS H26
D AA34 VSS VSS AM39 AW10 VSS VSS H29 D
AA35 VSS VSS AM4 AW11 VSS VSS H33
AA36 VSS VSS AM40 AW14 VSS VSS H35
AA37 VSS VSS AM5 AW16 VSS VSS H37
AA38 VSS VSS AN10 AW36 VSS VSS H39
AA6 VSS VSS AN11 AW6 VSS VSS H5
AB5 VSS VSS AN14 AY11 VSS VSS H6
AC1 VSS VSS AN17 AY14 VSS VSS H9
AC6 VSS VSS AN19 AY18 VSS VSS J11
SKT_H2
AD33 AN22 AY35 J17 JCPU1J
VSS VSS VSS VSS
AD36 VSS VSS AN24 AY4 VSS VSS J20
AD38 VSS VSS AN27 AY6 VSS VSS J23
AD39 VSS VSS AN30 AY8 VSS VSS J26
AD40 VSS VSS AN31 B10 VSS VSS J29 AB7 RSVD
AD5 VSS VSS AN32 B13 VSS VSS J32 AD37 RSVD
AD8 VSS VSS AN33 B14 VSS VSS K1 AG4 RSVD
AE3 VSS VSS AN34 B17 VSS VSS K12 AJ29 RSVD RSVD AT11
AE33 VSS VSS AN35 B23 VSS VSS K13 AJ30 RSVD RSVD AP20
AE36 VSS VSS AN36 B26 VSS VSS K14 AJ31 RSVD RSVD AN20
AF1 VSS VSS AN5 B29 VSS VSS K17 AV34 RSVD RSVD AU10
AF34 VSS VSS AN6 B32 VSS VSS K2 AW34 RSVD RSVD AY10
AF36 VSS VSS AN7 B35 VSS VSS K20
AF37 VSS VSS AN8 B38 VSS VSS K23 P35 RSVD
AF40 VSS VSS AN9 B6 VSS VSS K26 P37 RSVD
AF5 VSS VSS AP1 C11 VSS VSS K29 P39 RSVD
AF6 VSS VSS AP11 C12 VSS VSS K33 R34 RSVD
AF7 VSS VSS AP14 C17 VSS VSS K35 R36 RSVD
AG36 VSS VSS AP17 C20 VSS VSS K37 R38 RSVD RSVD AF4
AH2 VSS VSS AP22 C23 VSS VSS K39 R40 RSVD RSVD AB6
C AH3 AP25 C26 K5 AE6 C
VSS VSS VSS VSS RSVD
AH33 VSS VSS AP27 C29 VSS VSS K6 RSVD AJ11
AH36 VSS VSS AP30 C32 VSS VSS L10
AH37 VSS VSS AP36 C35 VSS VSS L17
AH38 VSS VSS AP37 C7 VSS VSS L20 A38 NCTF RSVD D38
AH39 VSS VSS AP4 C8 VSS VSS L23 AU40 NCTF RSVD C39
AH40 VSS VSS AP40 D17 VSS VSS L26 AW38 NCTF RSVD C38
AH5 VSS VSS AP5 D2 VSS VSS L29 C2 NCTF RSVD J34
AH8 VSS VSS AR11 D20 VSS VSS L8 D1 NCTF RSVD N34
AJ12 VSS VSS AR14 D23 VSS VSS M1
AJ15 AR17 D26 M17 SPARES
VSS VSS VSS VSS
AJ18 VSS VSS AR18 D29 VSS VSS M2
AJ21 AR19 D32 M20 10 OF 11
VSS VSS VSS VSS LOTES_ACAZIF096P01_SANDYBRIDGE
AJ25 VSS VSS AR27 D37 VSS VSS M23
AJ27 AR30 D39 M26 CONN@
VSS VSS VSS VSS
AJ36 VSS VSS AR36 D4 VSS VSS M29
AJ5 VSS VSS AR5 D5 VSS VSS M33
AK1 VSS VSS AT1 D9 VSS VSS M35
AK10 VSS_AK10 VSS AT10 E11 VSS VSS M37
AK13 VSS VSS AT12 E12 VSS VSS M39
AK14 VSS VSS AT13 E17 VSS VSS M5
AK16 VSS VSS AT15 E20 VSS VSS M6
AK22 VSS VSS AT16 E23 VSS VSS M9
AK28 VSS VSS AT17 E26 VSS VSS N8
AK31 VSS VSS AT2 E29 VSS VSS P1
AK32 VSS VSS AT25 E32 VSS VSS P2
AK33 VSS VSS AT27 E36 VSS VSS P36
AK34 VSS VSS AT28 E7 VSS VSS P38
AK35 VSS VSS AT29 E8 VSS VSS P40
B B
AK36 VSS VSS AT3 F1 VSS VSS P5
AK37 VSS VSS AT30 F10 VSS VSS P6
AK4 VSS VSS AT31 F13 VSS VSS R33
AK40 VSS VSS AT32 F14 VSS VSS R35
AK5 VSS VSS AT33 F17 VSS VSS R37
AK6 VSS VSS AT34 F2 VSS VSS R39
AK7 VSS VSS AT35 F20 VSS VSS R8
AK8 VSS VSS AT36 F23 VSS VSS T1
AK9 VSS VSS AT37 F26 VSS VSS T5
AL11 VSS VSS AT38 F29 VSS VSS T6
AL14 VSS VSS AT39 F35 VSS VSS U8
AL17 VSS VSS AT4 F37 VSS VSS V1
AL19 VSS VSS AT40 F39 VSS VSS V2
AL24 VSS VSS AT5 F5 VSS VSS V33
AL27 VSS VSS AT6 F6 VSS VSS V34
AL30 VSS VSS AT7 F9 VSS VSS V35
AL36 VSS VSS AT8 G11 VSS VSS V36
AL5 VSS VSS AT9 G12 VSS VSS V37
AM1 VSS VSS AU1 G17 VSS VSS V38
AM11 VSS VSS AU15 G20 VSS VSS V39
AM14 VSS VSS AU26 G23 VSS VSS V40
AM17 VSS VSS AU34 G26 VSS VSS V5
AM2 VSS VSS AU4 G29 VSS VSS W6
AM21 VSS VSS AU6 G34 VSS VSS Y5
AM23 VSS VSS AU8 G7 VSS VSS Y8
AM25 VSS VSS AV10 AY37 VSS_NCTF
A4 VSS_NCTF B3 VSS_NCTF
AV39 VSS_NCTF
A A
LOTES_ACAZIF096P01_SANDYBRIDGE
9 OF 11 CONN@
LOTES_ACAZIF096P01_SANDYBRIDGE
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (6/6) VSS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 09, 2011 Sheet 9 of 63
5 4 3 2 1
5 4 3 2 1

Layout Note:Place C94 on Bottom Layer at DIMM


close to CPU
R17 +1.5V +1.5V Layout Note:
http://adf.ly/3o8pJ
0_0402_5% JDIMM2
+1.5V Place near JDIMMA
+V_DDR_REFA 1 2 +DIMM0_VREF 1 VREF_DQ VSS1 2
3 4 DDR_A_D4
VSS2 DQ4

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

C94

C96

1U_0402_6.3V6K
C95

1U_0402_6.3V6K
C97

1U_0402_6.3V6K
C98

1U_0402_6.3V6K
C99
All VREF traces should DDR_A_D1 7 8
DQ1 VSS3 DDR_A_DQS#0
have 10 mil trace width 1 1 9 VSS4 DQS#0 10 1 1 1 1
DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0 @ @
13 VSS5 VSS6 14
DDR_A_D2 15 16 DDR_A_D6
2 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7 2 2 2 2
17 18
DQ3 DQ7
19 20
D DDR_A_D8 VSS7 VSS8 DDR_A_D12 D
21 22
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24
DQ9 DQ13
25 26
DDR_A_DQS#1 VSS9 VSS10 DDR_A_DM1
27 28
DDR_A_DQS1 DQS#1 DM1 SM_DRAMRST#
29 30 SM_DRAMRST# 6,11
0.1U_0402_16V4Z DQS1 RESET#
31 32
+1.5V DDR_A_D10 VSS11 VSS12 DDR_A_D14
33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
DQ11 DQ15
37
VSS13 VSS14
38
+1.5V
Layout Note: Place near JDIMMA
DDR_A_D16 39 40 DDR_A_D20
DQ16 DQ20
1

DDR_A_D17 41 42 DDR_A_D21
R18 DQ17 DQ21
1 43 VSS15 VSS16 44
+DIMM0_VREF 1K_0402_1% DDR_A_DQS#2 45 46 DDR_A_DM2
DQS#2 DM2

10U_0603_6.3V6M
C100

10U_0603_6.3V6M
C101

10U_0603_6.3V6M
C102

10U_0603_6.3V6M
C103

10U_0603_6.3V6M
C104

10U_0603_6.3V6M
C105

10U_0603_6.3V6M
C294 DDR_A_DQS2 47 48
DQS2 VSS17

1
49 50 DDR_A_D22 1 1 1 1 1 1 1
2

2 VSS18 DQ22

C106
DDR_A_D18 51 52 DDR_A_D23 +
+DIMM0_VREF DDR_A_D19 DQ18 DQ23 @ @ @ C107
53 DQ19 VSS19 54
55 56 DDR_A_D28 330U_2.5V_M_R15

2
DDR_A_D24 VSS20 DQ28 DDR_A_D29 2 2 2 2 2 2 2 @
57 DQ24 DQ29 58
1

DDR_A_D25 59 60
R19 DQ25 VSS21 DDR_A_DQS#3
61 VSS22 DQS#3 62
1K_0402_1% DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30 10/23 Change symbol of C107 from SGA20331E10 to
2

DDR_A_D27 DQ26 DQ30 DDR_A_D31


69 70
71
DQ27 DQ31
72
SF000002M00
VSS25 VSS26

6 DDR_A_CKE0 DDR_A_CKE0 73 74 DDR_A_CKE1


CKE0 CKE1 DDR_A_CKE1 6
75 VDD1 VDD2 76
77 78 DDR_A_MA15
C DDR_A_BS2 NC1 A15 DDR_A_MA14 C
6 DDR_A_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_A_MA12 DDR_A_MA11 DDR_A_DQS#[0..7] 6
83 A12/BC# A11 84
DDR_A_MA9 85 86 DDR_A_MA7
A9 A7 DDR_A_DQS[0..7] 6
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4 DDR_A_D[0..63] 6
91 A5 A4 92
93 94
DDR_A_MA3 VDD7 VDD8 DDR_A_MA2 DDR_A_MA[0..15] 6
95 96
DDR_A_MA1 A3 A2 DDR_A_MA0
97 98
A1 A0
99 100
DDR_A_CLK0 VDD9 VDD10 DDR_A_CLK1
6 DDR_A_CLK0 101 102 DDR_A_CLK1 6
DDR_A_CLK0# CK0 CK1 DDR_A_CLK1#
103 104 DDR_A_CLK1# 6
6 DDR_A_CLK0# CK0# CK1# +1.5V
105 106
DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
107 108 DDR_A_BS1 6
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
6 DDR_A_BS0 109 110 DDR_A_RAS# 6
BA0 RAS#
111 112
VDD13 VDD14

1
DDR_A_WE# 113 114 DDR_A_CS0#
6 DDR_A_WE# WE# S0# DDR_A_CS0# 6
DDR_A_CAS# 115 116 DDR_A_ODT0 R20
6 DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 6
117 118 1K_0402_1%
DDR_A_MA13 VDD15 VDD16 DDR_A_ODT1
119 120 DDR_A_ODT1 6
DDR_A_CS1# A13 ODT1
121 122

2
6 DDR_A_CS1# S1# NC2
123 124
VDD17 VDD18 +VREF_CA
125 126
NCTEST VREF_CA
127
VSS27 VSS28
128 2.2U_0603_6.3V6K
C110

0.1U_0402_16V4Z
C111
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

1
DDR_A_D33 131 132 DDR_A_D37 1 1
DQ33 DQ37 R21
133 134
DDR_A_DQS#4 VSS29 VSS30 DDR_A_DM4 1K_0402_1%
135 136
DDR_A_DQS4 DQS#4 DM4
137 138
DQS4 VSS31 DDR_A_D38 2 2
139 140

2
DDR_A_D34 VSS32 DQ38 DDR_A_D39
141 142
B DDR_A_D35 DQ34 DQ39 B
143 144
DQ35 VSS33 DDR_A_D44
145 146
DDR_A_D40 VSS34 DQ44 DDR_A_D45
147 148
DDR_A_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_A_DQS#5
151 152
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 154
DM5 DQS5
155 156
DDR_A_D42 VSS37 VSS38 DDR_A_D46
157 158
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
161 162
DDR_A_D48 VSS39 VSS40 DDR_A_D52
Layout Note:Place near JDIMM1.203/204 163 164
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 166
DQ49 DQ53
167 168
+0.75VS DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6
169 170
DDR_A_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_A_D54
173 174
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 176
DQ50 DQ55
0.1U_0402_16V4Z

4.7U_0603_6.3V6K

DDR_A_D51 177 178


DQ51 VSS45 DDR_A_D60
1 1 179 180
DDR_A_D56 VSS46 DQ60 DDR_A_D61
181 182
DQ56 DQ61
C116

C112 DDR_A_D57 183 184


DQ57 VSS47 DDR_A_DQS#7
185 186
2 2 DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 188
DM7 DQS7
189 190
DDR_A_D58 VSS49 VSS50 DDR_A_D62
191 192
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 194
DQ59 DQ63
195 196
VSS51 VSS52
197 198
SA0 EVENT# D_CK_SDATA
+3VS 199 200
VDDSPD SDA D_CK_SCLK D_CK_SDATA 11,13
201 202
SA1 SCL D_CK_SCLK 11,13
+0.75VS 203 204 +0.75VS
VTT1 VTT2
1
0.1U_0402_16V4Z
C118

2.2U_0603_6.3V6K
C119

10K_0402_5%
R30

10K_0402_5%
R33

A A
205 G1 G2 206
2

1 1
FOX_AS0A626-U2SN-7F
CONN@
DDR_A_DM0 R22 1 2 0_0402_5%
2

2 2 DDR_A_DM1 R23 1 2 0_0402_5%


STANDARD:5.2mm
1

DDR_A_DM2 R24 1 2 0_0402_5%


DDR_A_DM3 R25 1 2 0_0402_5%
DDR_A_DM4
DDR_A_DM5
R26
R27
1 2 0_0402_5%
0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
DDR_A_DM6 R28 1 2 0_0402_5%
DDR_A_DM7 R29 1 2 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII CHANNELA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 16, 2011 Sheet 10 of 63
5 4 3 2 1
5 4 3 2 1

Layout Note:Place C124 on Bottom Layer at DIMM


close to CPU
R34 +1.5V +1.5V +1.5V
http://adf.ly/3o8pJ
Layout Note:
Place near JDIMMB
0_0402_5% JDIMM1
+V_DDR_REFB 1 2 +DIMM1_VREF 1 VREF_DQ VSS1 2

0.1U_0402_16V4Z
C124
3 4 DDR_B_D4
VSS2 DQ4

0.1U_0402_16V4Z
C125

1U_0402_6.3V6K
C120

1U_0402_6.3V6K
C121

1U_0402_6.3V6K
C122

1U_0402_6.3V6K
C126
All VREF traces should 1 1 DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5
have 10 mil trace width 7 DQ1 VSS3 8 1 1 1 1
9 10 DDR_B_DQS#0
DDR_B_DM0 VSS4 DQS#0 DDR_B_DQS0 @ @
11 DM0 DQS0 12
2 2 13 14
DDR_B_D2 VSS5 VSS6 DDR_B_D6 2 2 2 2
15 16
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 18
DQ3 DQ7 DDR_B_DQS#[0..7] 6
19 20
D DDR_B_D8 VSS7 VSS8 DDR_B_D12 D
21 22
DDR_B_D9 DQ8 DQ12 DDR_B_D13 DDR_B_DQS[0..7] 6
23 24
DQ9 DQ13
25 26
DDR_B_DQS#1 VSS9 VSS10 DDR_B_DM1 DDR_B_D[0..63] 6
27 28
DQS#1 DM1

0.1U_0402_16V4Z
DDR_B_DQS1 29 30 SM_DRAMRST#
+1.5V DQS1 RESET# SM_DRAMRST# 6,10 DDR_B_MA[0..15] 6
31 32
DDR_B_D10 VSS11 VSS12 DDR_B_D14
33 34
+DIMM1_VREF DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 36
DQ11 DQ15
37
VSS13 VSS14
38 Layout Note: Place near JDIMMB
1

DDR_B_D16 39 40 DDR_B_D20 +1.5V


R35 DDR_B_D17 DQ16 DQ20 DDR_B_D21
1 41 42
1K_0402_1% DQ17 DQ21
43 VSS15 VSS16 44
C295 DDR_B_DQS#2 45 46 DDR_B_DM2
DQS#2 DM2

10U_0603_6.3V6M
C130

10U_0603_6.3V6M
C123

10U_0603_6.3V6M
C127

10U_0603_6.3V6M
C131

10U_0603_6.3V6M
C132

10U_0603_6.3V6M
C128

10U_0603_6.3V6M
DDR_B_DQS2 47 48
2

DQS2 VSS17

1
2

C133
+DIMM1_VREF 49 50 DDR_B_D22 1 1 1 1 1 1 1
DDR_B_D18 VSS18 DQ22 DDR_B_D23 +
51 DQ18 DQ23 52
1

DDR_B_D19 53 54 @ @ @ @ C129
R36 DQ19 VSS19 DDR_B_D28 560U_2.5V_M_R10
55 56

2
1K_0402_1% DDR_B_D24 VSS20 DQ28 DDR_B_D29 2 2 2 2 2 2 2
57 DQ24 DQ29 58
DDR_B_D25 59 60
DQ25 VSS21 DDR_B_DQS#3
61 62
2

DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3


63 DM3 DQS3 64
65 VSS23 VSS24 66 10/23 Change symbol of C129 from SGA20331E10 to SF000002M00
DDR_B_D26 67 68 DDR_B_D30 11/2 Change PN of C129 from SF000002M00 to SF000001K00
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

6 DDR_B_CKE0 DDR_B_CKE0 73 74 DDR_B_CKE1


CKE0 CKE1 DDR_B_CKE1 6
75 VDD1 VDD2 76
77 78 DDR_B_MA15
C DDR_B_BS2 NC1 A15 DDR_B_MA14 DDR_B_DM0 R37 0_0402_5% C
6 DDR_B_BS2 79 BA2 A14 80 1 2
81 82 DDR_B_DM1 R38 1 2 0_0402_5%
DDR_B_MA12 VDD3 VDD4 DDR_B_MA11 DDR_B_DM2 R39 0_0402_5%
83 A12/BC# A11 84 1 2
DDR_B_MA9 85 86 DDR_B_MA7 DDR_B_DM3 R40 1 2 0_0402_5%
A9 A7 DDR_B_DM4 R41 0_0402_5%
87 VDD5 VDD6 88 1 2
DDR_B_MA8 89 90 DDR_B_MA6 DDR_B_DM5 R42 1 2 0_0402_5%
DDR_B_MA5 A8 A6 DDR_B_MA4 DDR_B_DM6 R43 0_0402_5%
91 A5 A4 92 1 2
93 94 DDR_B_DM7 R44 1 2 0_0402_5%
DDR_B_MA3 VDD7 VDD8 DDR_B_MA2
95 96
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0
99 100
DDR_B_CLK0 VDD9 VDD10 DDR_B_CLK1
6 DDR_B_CLK0 101 102 DDR_B_CLK1 6
DDR_B_CLK0# CK0 CK1 DDR_B_CLK1#
103 104 DDR_B_CLK1# 6
6 DDR_B_CLK0# CK0# CK1# +1.5V
105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 108 DDR_B_BS1 6
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
6 DDR_B_BS0 109 110 DDR_B_RAS# 6
BA0 RAS#
111 112
VDD13 VDD14

1
DDR_B_WE# 113 114 DDR_B_CS0#
6 DDR_B_WE# WE# S0# DDR_B_CS0# 6
DDR_B_CAS# 115 116 DDR_B_ODT0 R45
6 DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 6
117 118 1K_0402_1%
DDR_B_MA13 VDD15 VDD16 DDR_B_ODT1
119 120 DDR_B_ODT1 6
DDR_B_CS1# A13 ODT1
121 122

2
6 DDR_B_CS1# S1# NC2
123 124
VDD17 VDD18 +VREF_CB
125 126
NCTEST VREF_CA
127 128
DDR_B_D32 VSS27 VSS28 DDR_B_D36
129 130
DQ32 DQ36

1
2.2U_0603_6.3V6K
C134

0.1U_0402_16V4Z
C135
DDR_B_D33 131 132 DDR_B_D37
DQ33 DQ37 R46
133 134 1 1
DDR_B_DQS#4 VSS29 VSS30 DDR_B_DM4 1K_0402_1%
135 136
DDR_B_DQS4 DQS#4 DM4
137 138
DQS4 VSS31 DDR_B_D38
139 140

2
DDR_B_D34 VSS32 DQ38 DDR_B_D39 2 2
141 142
B DDR_B_D35 DQ34 DQ39 B
143 144
DQ35 VSS33 DDR_B_D44
145 146
DDR_B_D40 VSS34 DQ44 DDR_B_D45
147 148
DDR_B_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_B_DQS#5
151 152
DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
153 154
DM5 DQS5
155 156
DDR_B_D42 VSS37 VSS38 DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
DQ43 DQ47
161 162 Layout Note:Place near JDIMM4.203/204
DDR_B_D48 VSS39 VSS40 DDR_B_D52
163 164
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 166
DQ49 DQ53 +0.75VS
167 168
DDR_B_DQS#6 VSS41 VSS42 DDR_B_DM6
169 170
DDR_B_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_B_D54
173 174
VSS44 DQ54
4.7U_0603_6.3V6K
0.1U_0402_16V4Z

DDR_B_D50 175 176 DDR_B_D55


+3VS +3VS DDR_B_D51 DQ50 DQ55
177 178 1 1
DQ51 VSS45
C138

C140

179 180 DDR_B_D60


DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 182
DDR_B_D57 DQ56 DQ61
183 184
DQ57 VSS47
1

2 2
0.1U_0402_16V4Z
C142

2.2U_0603_6.3V6K
C143

1 1 185 186 DDR_B_DQS#7


R47 DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7
187 188
10K_0402_5% DM7 DQS7
189 190
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 192
2 2 DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
2

DQ59 DQ63
195 196
VSS51 VSS52
197 198
SA0 EVENT# D_CK_SDATA
199 200
VDDSPD SDA D_CK_SCLK D_CK_SDATA 10,13
201 202
SA1 SCL D_CK_SCLK 10,13
+0.75VS 203 204 +0.75VS
VTT1 VTT2
1

A A
205 G1 G2 206
R49
10K_0402_5% SUYIN_600023HB204G208ZL
CONN@
2

STANDARD:9.2mm
<Address: 01> Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII CHANNELB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 16, 2011 Sheet 11 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ

U1C CPT_CRB

AC56 SATA_DTX_C_PRX_N0
SATA0RXN SATA_DTX_C_PRX_N0 35
AB55 SATA_DTX_C_PRX_P0

CLINK
SATA0RXP SATA_DTX_C_PRX_P0 35
AE46 SATA_PTX_DRX_N0 SATA for HDD
SATA0TXN SATA_PTX_DRX_N0 35
D AE44 SATA_PTX_DRX_P0 D
SATA0TXP SATA_PTX_DRX_P0 35

SATA3
BA50 AA53 SATA_DTX_C_PRX_N1
CL_CLK1 SATA1RXN SATA_DTX_C_PRX_N1 35
BF50 AA56 SATA_DTX_C_PRX_P1
CL_DATA1 SATA1RXP SATA_DTX_C_PRX_P1 35
43 EC_REVPW ROK
@ 1 R891 2 0_0402_5% BF49 CL_RST1# SATA1TXN AG49 SATA_PTX_DRX_N1
SATA_PTX_DRX_N1 35 SATA for ODD
AG47 SATA_PTX_DRX_P1
SATA1TXP SATA_PTX_DRX_P1 35
13 PCH_PW ROK_R 1 R892 2 0_0402_5% BC46 APWROK
SATA2RXN AL50
BN21 PWM0 SATA2RXP AL49
BT21 PWM1 SATA2TXN AL56
BM20 PWM2 SATA2TXP AL53
BN19 PWM3 SATA3RXN AN46

FAN

SATA2
SATA3RXP AN44
SATA3TXN AN56
PCH_GPIO17 BT17 AM55
CAM_OFF TACH0_GPIO17 SATA3TXP
34 CAM_OFF BR19 TACH1_GPIO1 SATA4RXN AN49
PCH_GPIO6 BA22 AN50
EC_SCI# TACH2_GPIO6 SATA4RXP
43 EC_SCI# BR16 TACH3_GPIO7 SATA4TXN AT50
PCH_GPIO68 BU16 AT49
PCH_GPIO69 TACH4_GPIO68 SATA4TXP
BM18 TACH5_GPIO69 SATA5RXN AT46
PCH_GPIO70 BN17 AT44
PCH_GPIO71 TACH6_GPIO70 SATA5RXP
BP15 TACH7_GPIO71 SATA5TXN AV50
SATA5TXP AV49
BC43 SST
AF55 CLK_BUF_PCIE_SATA# T54
PCH_GPIO22 CLKIN_SATA_N CLK_BUF_PCIE_SATA
BA53 SCLOCK_GPIO22 CLKIN_SATA_P AG56 T57
PROJECT_ID2 BE54
PCH_GPIO39 SLOAD_GPIO38 PCH_SATALED# +1.05VS_PCH
BF55 SDATAOUT0_GPIO39 SATALED# BF57 PCH_SATALED# 46
PCH_GPIO48 AW53 AJ55 Layout Note:SATA_COMP WITH LENGTH NO MORE THAN 500 MILS TO
SDATAOUT1_GPIO48 SATAICOMPI SATA_COMP R51
SATAICOMPO AJ53 1 2 37.4_0402_1%
C RESISTOR. C

GPIO
BC54 PCH_GPIO21
SATA0GP_GPIO21 PCH_GPIO19
AY52
SATA1GP_GPIO19
BB55 PROJECT_ID0 Boot BIOS Strap Bit 0(GPIO19)
SATA2GP_GPIO36 PROJECT_ID1
AY20 NC SATA3GP_GPIO37 BG53
AU56 PCH_GPIO16 SERIRQ C963 @ 1 2 1000P_0402_50V7K
SATA4GP_GPIO16 PCH_GPIO49 SATA3_COMP C996 @ 1
SATA5GP_GPIO49 BA56 2 1000P_0402_50V7K
+1.05VS_PCH

SATA3COMPI AE54 R52


PROJECT ID TABLE AE52 SATA3_COMP 2 1 49.9_0402_1%
+3VS SATA3RCOMPO

TP16 AE50
CONFIG2@ R53
10K_0402_5% 2 1 R680 AC52 SATA3RBIAS 1 2
10K_0402_5% 2 SATA3RBIAS
1 R61 PROJECT_ID0
CONFIG4@ 750_0402_1%
CONFIG1@
10K_0402_5% 2 1 R681 BB57 EC_GA20
A20GATE EC_GA20 43
10K_0402_5% 2 1 R62 PROJECT_ID1 BN56
CONFIG5@
HOST INIT3_3V# EC_KBRST#
RCIN# BG56 EC_KBRST# 43
AV52 SERIRQ
10K_0402_5% 2 CONFIG3@
CONFIG3@R511 SERIRQ SERIRQ 43
1 R511 THRMTRIP# E56 H_THERMTRIP#
H_THERMTRIP# 5
10K_0402_5% 2 1 R209 PROJECT_ID2 H48 PCH_PECI_R 0_0402_5% 1 @ 2 R111
CONFIG6@ PECI H_PM_SYNC H_PECI 5,43
PMSYNCH F55 H_PM_SYNC 5 +3VS

PCH_SATALED# R54 1 2 10K_0402_5%


3 OF 10 EC_GA20 R55 1 2 10K_0402_5%
BD82H67-SLJ49-B3_FCBGA942 EC_KBRST# R56 1 2 10K_0402_5%
B SERIRQ R57 10K_0402_5% B
1 2
PCH_GPIO21 R58 1 2 10K_0402_5%
PCH_GPIO19 R59 1 2 10K_0402_5%
PCH_GPIO16 R60 1 2 10K_0402_5%
PCH_GPIO49 R499 1 2 10K_0402_5%
PCH_GPIO17 R502 1 2 10K_0402_5%
CAM_OFF R503 1 @ 2 10K_0402_5%
PCH_GPIO6 R504 1 2 10K_0402_5%
EC_SCI# R505 1 @ 2 10K_0402_5%
PCH_GPIO68 R506 1 2 10K_0402_5%
PCH_GPIO69 R507 1 2 10K_0402_5%
PCH_GPIO70 R508 1 2 10K_0402_5%
PCH_GPIO71 R509 1 2 10K_0402_5%
7/30 R510--- CRB:1K ohm;EDS:10K ohm PCH_GPIO22 R510 1 2 10K_0402_5%

7/30 R512--- CRB:10K ohm PD to PCH_GPIO39 R512 1 2 10K_0402_5%


PCH_GPIO48 R513 1 2 10K_0402_5%
GND;EDS:10K ohm PU to +3VS

+3VSB CLK_BUF_PCIE_SATA# R361 1 2 10K_0402_5%


+RTCVCC CLK_BUF_PCIE_SATA R362 1 2 10K_0402_5%
+RTCBATT PCH_GPIO19 R347 1 @ 2 1K_0402_1%
D3
2 W=20mils
W=20mils 1 R299
1 3 +RTCBATT_R 1 2
C293 W=20mils
A A
1U_0402_6.3V6K DAN202UT106_SC70 1K_0402_5%
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/9) SATA,FAN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 12 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ EC_SMI# R324 10K_0402_5%


+3VALW

HDA for AUDIO EC_SW I# R74


2 1
10K_0402_5%
2 1
1 2 HDA_BITCLK_PCH PCH_GPIO74 R75 2 1 10K_0402_5%
39 HDA_BITCLK_AUDIO
R69 33_0402_5% U1D PCH_SML1CLK R63 2 1 4.7K_0402_5%
AW55 PCH_GPIO0 PCH_SML1DAT R76 2 1 4.7K_0402_5%
BMBUSY#_GPIO0 CLKRUN# LAN_SMBCLK R64 2.2K_0402_5%
BA20 LDRQ1#_GPIO23 CLKRUN#_GPIO32 BC56 CLKRUN# 43 2 1
1 2 HDA_RST#_PCH LPC_AD0 BK15 BC25 PCH_GPIO33 LAN_SMBDATA R65 2 1 2.2K_0402_5%
39 HDA_RST#_AUDIO 43 LPC_AD0 FWH0_LAD0 HDA_DOCK_EN#_GPIO33
R72 33_0402_5% LPC_AD1 BJ17 BL56 PCH_GPIO34 PCH_GPIO60 R77 2 1 2.2K_0402_5%
HDA_SDOUT_PCH 43 LPC_AD1 LPC_AD2 FWH1_LAD1 STP_PCI#_GPIO34 PCH_GPIO35 PM_LANPHY_ENABLE R66 @ 10K_0402_5%
39 HDA_SDOUT_AUDIO 1 2 43 LPC_AD2 BJ20 FWH2_LAD2 GPIO35 BJ57 2 1
R73 33_0402_5% LPC_AD3 BG20 SMIB R67 2 1 10K_0402_5%
43 LPC_AD3 FWH3_LAD3 EC_SMI# PCH_GPIO28 R68 1K_0402_1%
D BK17 LDRQ0# GPIO8 BP51 EC_SMI# 36,43 2 1 D
HDA_SDO LPC_FRAME# BG17 BK50 PM_LANPHY_ENABLE PM_LANPHY_ENABLE PCH_GPIO13 R896 2 1 10K_0402_5%
43 LPC_FRAME# FWH4_LFRAME# LAN_PHY_PWR_CTRL_GPIO12
BA25 PCH_GPIO13 SUSW ARN#_R R448 2 1 10K_0402_5%
HDA_BITCLK_PCH HDA_DOCK_RST#_GPIO13 SMIB PCH_GPIO57 R71 10K_0402_5%
ME debug mode, BU22 HDA_BCLK GPIO15 BM55 SMIB 36 2 1
HDA_RST#_PCH BC22 BP53 PCH_GPIO27 R78 2 1 10K_0402_5%
this signal has a weak internal pull down HDA_SDIN0 HDA_RST# GPIO24_MEM_LED PCH_GPIO28
T1
W LAN_CLKREQ# R530 10K_0402_5%
39 HDA_SDIN0 BD22 HDA_SDIN0 GPIO28 BJ55 2 1
Low = Disable (default) BF22 BH49 SLP_LAN# CLKREQ_USB30# R531 2 1 10K_0402_5%
*
High = Enable (flash descriptor security overide) +3VALW R338 2 @ 1 1K_0402_1% BK22
HDA_SDIN1
HDA_SDIN2
SLP_LAN#_GPIO29
PCIECLKRQ2#_GPIO20 AV43 LAN_CLKREQ#
SLP_LAN# 38
LAN_CLKREQ# 38
TV_CLKREQ# R532 2 1 10K_0402_5%
BJ22 BL54 W LAN_CLKREQ# DRAMPW ROK R646 2 @ 1 200_0402_5%
HDA_SDIN3 PCIECLKRQ5#_GPIO44 W LAN_CLKREQ# 42
R890 1 2 HDA_SDOUT_PCH BT23 AV44 CLKREQ_USB30# PCH_GPIO31 R675 2 1 10K_0402_5%
43 ME_FLASH HDA_SDO PCIECLKRQ6#_GPIO45 CLKREQ_USB30# 36
0_0402_5% HDA_SYNC_AUDIO_R BP23 BP55 TV_CLKREQ# PCH_GPIO72 R676 2 1 200_0402_5%
HDA_SYNC PCIECLKRQ7#_GPIO46 TV_CLKREQ# 42
HDA_SYNC BT53 PCH_GPIO57 PCH_PCIE_W AKE#_R R203 2 1 1K_0402_1%
PCH_SPI_MOSI_1 R79 0_0402_5% PCH_SPI_MOSI GPIO57 SYS_PW ROK_R PCH_GPIO11 R716 10K_0402_5%
This signal has a weak internal pull down 1 2 AU53 SPI_MOSI SYS_PWROK BJ53 EC_SW I# 43 2 1
PCH_SPI_MISO_1 R80 1 2 0_0402_5% PCH_SPI_MISO AT55 BJ48 EC_SW I#
H=>On Die PLL is supplied by 1.5V PCH_SPI_CS0# R81 0_0402_5% PCH_SPI_CS0#_R SPI_MISO RI# PCH_PLT_RST#
PCH_PLT_RST# 5,38,43
1 2 AT57 SPI_CS0# PLTRST# BK48
L=>On Die PLL is supplied by 1.8V PCH_SPI_CLK_1 R83 1 2 0_0402_5% PCH_SPI_CLK AR54 BC44 PCH_PCIE_W AKE#_R R364 1 2 0_0402_5%
SPI_CLK WAKE# PCH_PCIE_W AKE# 36,38,42
Need to pull high for Huron River platform AR56 BC41
* +3VALW SPI_CS1# SLP_A#
SLP_S3# BM53 PM_SLP_S3# PM_SLP_S3# 43
BN52 PM_SLP_S4# PM_SLP_S4# 43
SLP_S4# SUS_PW R_ACK_R R391 1 2 0_0402_5% SUSW ARN#_R
2.2K_0402_5% 1 2 R945 PCH_SMBCLK BH50 PM_SLP_S5# PM_SLP_S5# 43
2.2K_0402_5% 1 SLP_S5#_GPIO63
2 R946 PCH_SMBDATA
SUS_STAT#_GPIO61 BN54 T2
1 R70 2 HDA_SYNC_AUDIO_R BA47 PCH_SUSCLK_R R363 1 2 0_0402_5%
39 HDA_SYNC_AUDIO SUSCLK_GPIO62 PCH_SUSCLK 43
33_0402_5% AV46 PCH_GPIO72
BATLOW#_GPIO72 SUS_PW R_ACK_R R365 1 @
SUSACK# BP45 2 0_0402_5% SUS_PW R_ACK 43
1

PCH_RTCX1 BR39 BU46 SUSW ARN#_R R390 1 2 0_0402_5%


RTCX1 SUSWARN#-SUS_PWR_DN_ACK-GPIO30 SUSW ARN# 43
@ PCH_RTCX2 BN39 BG46 DRAMPW ROK DRAMPW ROK 5
R356 PCH_RTCRST# RTCX2 DRAMPWROK
BT41 RTCRST# Stuff R391 if EC don't want to
1M_0402_5% PCH_SRTCRST# BN37

PM_GPIO(DSW)
C SM_INTRUDER# SRTCRST# PCH_GPIO27
involve in the handshake mechanism +3VS C
BM38 BJ43
2

PCH_PW ROK_R INTRUDER# GPIO27 for the DeepSX state entry and exit
12 PCH_PW ROK_R BJ38 PWROK
PCH_RSMRST# BK38 BG43 PCH_GPIO31
PCH_INTVRMEN RSMRST# GPIO31 PCH_GPIO33 R894 10K_0402_5%
BN41 INTVRMEN SLP_SUS# BD43 T51 2 1
PCH_DPW ROK BT37 BT43 PBTN_OUT# PCH_GPIO0 R82 2 1 10K_0402_5%
DPWROK PWRBTN# PBTN_OUT# 43
PCH_DSW VRMEN BR42 PCH_GPIO34 R84 2 1 10K_0402_5%
DSWVRMEN XDP_DBRETSET# LAN_CLKREQ# R529 10K_0402_5%
SYS_RESET# BE52 XDP_DBRETSET# 5 2 1
PCH_RSMRST# R303 1 2 0_0402_5% PCH_DPW ROK BE56 PCH_SPKR PCH_SPKR 39 XDP_DBRETSET# R581 2 1 10K_0402_5%
PCH_GPIO11 SPKR PCH_SPKR R583 @ 1K_0402_5%
BN49 SMBALERT#_GPIO11 2 1
Stuff R303 if do not support DeepSX state PCH_SMBCLK BT47 PCH_SPKR:HIGH= Enable ( No Reboot);
42 PCH_SMBCLK PCH_SMBDATA SMBCLK
BR49
EC_PW ROK R3441 2 0_0402_5% PCH_PW ROK_R 42 PCH_SMBDATA PCH_GPIO60 BU49
SMBDATA
SML0ALERT#_GPIO60 PROCPWRGD D53 H_CPUPW RGD H_CPUPW RGD 5 * LOW= Disable(Default)
LAN_SMBCLK BT51
LAN_SMBDATA SML0CLK CLKRUN# R926 @
BM50 SML0DATA 2 1 10K_0402_5%
PCH_GPIO74 BR46 SLP_LAN# R897 2 @ 1 1K_0402_1%
EC_SMB_CK2_M R88 SML1ALERT#_PCHHOT#_GPIO74
43 EC_SMB_CK2_M 1 2 0_0402_5% PCH_SML1CLK BJ46 SML1CLK_GPIO58
PCH_GPIO33 R895 2 @ 1 1K_0402_1%
EC_SMB_DA2_M R89 1 2 0_0402_5% PCH_SML1DAT BK46 SYS_PW ROK R719 2 1 10K_0402_5%
43 EC_SMB_DA2_M SML1DATA_GPIO75 PCH_GPIO35 R85 2.2K_0402_5%
2 1

JTAG(SUS)
C146 8/20 Add BC49 PCH_JTAG_RST# EC_SMI# R86 2 @ 1 1K_0402_1%
18P_0402_50V8J TP12 PCH_JTAG_TCK SUSW ARN#_R R207 @ 1K_0402_1%
JTAG_TCK BA43 2 1
2 1 PCH_RTCX1 1000P_0402_50V7K 2 1 @ C987 LAN_CLKREQ# BC52 PCH_JTAG_TDI EC_PW ROK R718 2 1 10K_0402_5%
1000P_0402_50V7K 2 JTAG_TDI
1 @ C988 PCH_JTAG_TDO
JTAG_TDO BF47 PCH_JTAG_TDO PCH_GPIO28 R340 2 @ 1 1K_0402_1%
X1
JTAG_TMS BC50 PCH_JTAG_TMS * On-Die PLL Voltage Regulator
1

3 4 4 OF 10
NC OSC R87 BD82H67-SLJ49-B3_FCBGA942
H: Enable
2 1 +RTCVCC R99 1 2 20K_0402_1% PCH_SRTCRST# L: Disable
NC OSC 10M_0402_5% @
close to RAM door
32.768KHZ_12.5PF_Q13MC14610002 1 @ 2 RC Delay 18~25mS 8/19 Change footprint of U2 to XDP_DBRETSET# C676 1 2 0.1U_0402_16V4Z
2

C147 J2 R342 2 @ 1 0_0402_5%


B PCH_RTCX2 10K_0603_5%
WIESO_G6179-100000_8P Q18 <EMI> B
2 1
C149 SA000041P00 4MB MMBT3906_SOT23-3 8/13 Add C676 close to U1(EMI request)
18P_0402_50V8J 1U_0402_6.3V6K +3VS PCH_RSMRST# 1 3

C
EC_RSMRST# 43
1 2

E
+3VS +3VS U2 +3VALW

1
R655 PCH_SPI_CS0# 1 8

B
2
4.7K_0402_5% R94 CS# VCC
1 2 4.7K_0402_5% SPI_W P1# 3 WP# SCLK 6 PCH_SPI_CLK_1 R717 1 2 +3VALW
2

R96 2 4.7K_0402_5% SPI_HOLD1# PCH_SPI_MOSI_1 10K_0402_5% R319 4.7K_0402_5%


G

1 2 +3VS 1 7 HOLD# SI 5
4 2 PCH_SPI_MISO_1 R91 1 2 200_0402_5%
PCH_SMBCLK D_CK_SCLK GND SO D38A PCH_JTAG_TMS R92
1 3 D_CK_SCLK 10,11 1 2 100_0402_5%

2
S IC FL 32M MX25L3206EM2I-12G SOP 8P 1
D

Q32 +RTCVCC R90 1 2 20K_0402_1% PCH_RTCRST# SPI ROM Footprint 200mil 6


SSM3K7002FU_SC70-3 close to RAM door 2 R93 1 2 200_0402_5%
1 @ 2 RC Delay 18~25mS PCH_JTAG_TDO R95 1 2 100_0402_5%
J1 R348 1 @ 2 0_0402_5% BAV99DW -7-F_SOT363~N
10K_0603_5%
+3VS C148 +3VS D38B R97 1 2 200_0402_5%
R654 1U_0402_6.3V6K 4 PCH_JTAG_TDI R98 1 2 100_0402_5%
4.7K_0402_5% 1 2 3
2

U20
G

1 2 +3VS 5

1
EC_PW ROK R100 1 2 20K_0402_5%
B 2
P

EC_PW ROK 43
PCH_SMBDATA 1 3 D_CK_SDATA SYS_PW ROK 4 BAV99DW -7-F_SOT363~N R343 PCH_JTAG_RST# R101 1 2 10K_0402_5%
D_CK_SDATA 10,11 Y VGATE 2.2K_0402_5%
1
D

A VGATE 43,57
G

Q31
SSM3K7002FU_SC70-3 R943 1 2 0_0402_5% NC7SZ08P5X_NL_SC70-5
3

2
PCH_JTAG_TCK R102 1 2 51_0402_5%
+3VS
+RTCVCC
A
@ SYS_PW ROK_R R349 1 2 0_0402_5% SYS_PW ROK A
5

U25
1M_0402_5% 2 1 R103 SM_INTRUDER# PCH_PLT_RST# 2 B R350 1 @ 2 0_0402_5% VGATE
P

4 PLT_RST# PLT_RST# 22,36,37,42


390K_0402_5% 2 Y
1 R104 PCH_DSW VRMEN 1 A
G

390K_0402_5% 2 1 R105 PCH_INTVRMEN


1

NC7SZ08P5X_NL_SC70-5
Security Classification Compal Secret Data Compal Electronics, Inc.
3
1

R944
R106 2010/07/20 2011/07/20 Title
Issued Date Deciphered Date
100K_0402_5%
1K_0402_5%
@
PCH (2/9) LPC, HDA, SMBUS
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 13 of 63
5 4 3 2 1
5 4 3 2 1

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DMI_HTX_PRX_N[0..3]
4 DMI_HTX_PRX_N[0..3]
D DMI_HTX_PRX_P[0..3] D
4 DMI_HTX_PRX_P[0..3]
DMI_PTX_HRX_N[0..3]
4 DMI_PTX_HRX_N[0..3]
DMI_PTX_HRX_P[0..3]
4 DMI_PTX_HRX_P[0..3] CPT_CRB
U1B

DMI_HTX_PRX_N0 D33 BF36 USB20_N0


DMI_HTX_PRX_P0 DMI0RXN USBP0N USB20_P0 USB20_N0 44
DMI_PTX_HRX_N0
B33 DMI0RXP USBP0P BD36
USB20_N1 USB20_P0 44 USB Conn OC[0..3] use for EHCI 1
J36 DMI0TXN USBP1N BC33 USB20_N1 44
DMI_PTX_HRX_P0 H36 BA33 USB20_P1 USB Conn OC[4..7] use for EHCI 2
DMI_HTX_PRX_N1 DMI0TXP USBP1P USB20_N2 USB20_P1 44
A36 DMI1RXN USBP2N BM33 USB20_N2 36
DMI_HTX_PRX_P1 B35 BM35 USB20_P2 USB Conn
DMI_PTX_HRX_N1 DMI1RXP USBP2P USB20_N3 USB20_P2 36
P38 DMI1TXN USBP3N BT33 USB20_N3 36

DMI
DMI_PTX_HRX_P1 R38 BU32 USB20_P3 USB Conn EHCI 1
DMI_HTX_PRX_N2 DMI1TXP USBP3P USB20_N4 USB20_P3 36
B37 DMI2RXN USBP4N BR32 USB20_N4 34
DMI_HTX_PRX_P2 C36 BT31 USB20_P4 Touch Screen
DMI_PTX_HRX_N2 DMI2RXP USBP4P USB20_N5 USB20_P4 34
H38 DMI2TXN USBP5N BN29 USB20_N5 34
DMI_PTX_HRX_P2 J38 BM30 USB20_P5 Web Camera
DMI_HTX_PRX_N3 DMI2TXP USBP5P USB20_P5 34
E37 DMI3RXN USBP6N BK33
+1.05VS_PCH DMI_HTX_PRX_P3 F38 BJ33
DMI_PTX_HRX_N3 DMI3RXP USBP6P
M41 DMI3TXN USBP7N BF31
R107 DMI_PTX_HRX_P3 P41 BD31
49.9_0402_1% DMI3TXP USBP7P USB20_N8
B31 DMI_IRCOMP USBP8N BN27 USB20_N8 36
1 2 DMI_COMP E31 BR29 USB20_P8 USB 2.0
DMI_ZCOMP USBP8P USB20_N9 USB20_P8 36
USBP9N BR26 USB20_N9 36

USB
T77 CLK_BUF_CPU_DMI# P33 BT27 USB20_P9 USB 2.0
CLK_BUF_CPU_DMI CLKIN_DMI_N USBP9P USB20_N10 USB20_P9 36
T78 R33 CLKIN_DMI_P USBP10N BK25 USB20_N10 46
BJ25 USB20_P10 Bluetooth
C PCIE_DTX_C_PRX_N1 USBP10P USB20_N11 USB20_P10 46 C
37 PCIE_DTX_C_PRX_N1 J20 PERN1 USBP11N BJ31
For CardReader 37 PCIE_DTX_C_PRX_P1
PCIE_DTX_C_PRX_P1 L20 BK31 USB20_P11 R1205
1 SW TV@ 2 0_0402_5% EHCI 2
PCIE_PTX_DRX_N1 PERP1 USBP11P R1206 USB20_N_TV 42
37 PCIE_PTX_DRX_N1 F25 PETN1 USBP12P BD27 1 SW TV@ 2 0_0402_5% USB20_P_TV 42 Mini Card(TV Tuner)
PCIE_PTX_DRX_P1 F23 BF27
37 PCIE_PTX_DRX_P1 PETP1 USBP12N
PCIE_DTX_C_PRX_N2 P20 BK27 R1207
1 HTV@ 2 0_0402_5%
38 PCIE_DTX_C_PRX_N2 PERN2 USBP13P USB20_N_DTV 46
For PCIE LAN PCIE_DTX_C_PRX_P2 R20 BJ27 R1208
1 HTV@ 2 0_0402_5% HDTV recorder
38 PCIE_DTX_C_PRX_P2 PERP2 USBP13N USB20_P_DTV 46
C9077 2 1 .1U_0402_16V7K PCIE_PTX_DRX_N2 C22
38 PCIE_PTX_C_DRX_N2 PETN2
C9078 2 1 .1U_0402_16V7K PCIE_PTX_DRX_P2 A22 BM43 USB_OC#0
38 PCIE_PTX_C_DRX_P2 PETP2 OC0#_GPIO59 USB_OC#0 44

PCI-E
H17 BD41 USB_OC#1
PERN3 OC1#_GPIO40 USB_OC#1 36
J17 BG41 USB_OC#2_R
PERP3 OC2#_GPIO41 USB_OC#34
E21 PETN3 OC3#_GPIO42 BK43 USB_OC#34 36
B21 PETP3 OC4#_GPIO43 BP43
PCIE_DTX_C_PRX_N4 P17 BJ41 USB_OC#5_R
42 PCIE_DTX_C_PRX_N4 PERN4 OC5#_GPIO9
PCIE_DTX_C_PRX_P4 M17 BT45 USB_OC#6_R
42 PCIE_DTX_C_PRX_P4 PERP4 OC6#_GPIO10
For WiFi LAN PCIE_PTX_DRX_N4 F18 BM45 USB_OC#7_R
42 PCIE_PTX_DRX_N4 PETN4 OC7#_GPIO14
PCIE_PTX_DRX_P4 E17 Layout Note:USB_BIAS WITH LENGTH NO MORE THAN 500 MILS TO
42 PCIE_PTX_DRX_P4 PETP4 R108
PCIE_DTX_C_PRX_N5 N15 BP25 USB_BIAS 1 2
42 PCIE_DTX_C_PRX_N5 PERN5 USBRBIAS# RESISTOR.
For TV Tuner PCIE_DTX_C_PRX_P5 M15 BM25
42 PCIE_DTX_C_PRX_P5 PERP5 USBRBIAS 22.6_0402_1%
PCIE_PTX_DRX_N5 B17
42 PCIE_PTX_DRX_N5 PETN5
PCIE_PTX_DRX_P5 C16 BD38 CLK_BUF_DREF_96M# T58
42 PCIE_PTX_DRX_P5 PETP5 CLKIN_DOT_96N
PCIE_DTX_C_PRX_N6 J15 BF38 CLK_BUF_DREF_96M T76
36 PCIE_DTX_C_PRX_N6 PERN6 CLKIN_DOT_96P
PCIE_DTX_C_PRX_P6 L15
36 PCIE_DTX_C_PRX_P6 PERP6 R109
For USB3.0 PCIE_PTX_DRX_N6 A16 A32 DMI2RBIAS 1 2
36 PCIE_PTX_DRX_N6 PETN6 DMI2RBIAS
PCIE_PTX_DRX_P6 B15
36 PCIE_PTX_DRX_P6 PETP6
J12 750_0402_1%
PERN7
H12 PERP7
F15 PETN7
F13 PETP7
H10 USB_OC#2_R R110 1 2 10K_0402_5% +3VALW
B PERN8 USB_OC#7_R R113 10K_0402_5% B
J10 PERP8 1 2
B13 USB_OC#6_R R114 1 2 10K_0402_5%
PETN8 USB_OC#5_R R115 10K_0402_5%
D13 PETP8 1 2
USB_OC#34 R296 1 @ 2 10K_0402_5%

2 OF 10
BD82H67-SLJ49-B3_FCBGA942 CLK_BUF_DREF_96M# R357 1 2 10K_0402_5%
CLK_BUF_DREF_96M R358 1 2 10K_0402_5%
CLK_BUF_CPU_DMI# R359 1 2 10K_0402_5%
CLK_BUF_CPU_DMI R360 1 2 10K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/9) DMI, USB, PCIE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 14 of 63
5 4 3 2 1
5 4 3 2 1

CPT_CRB

U1F CPT_CRB
http://adf.ly/3o8pJ PLACE RGB RESISTORS CLOSE TO
PCH:<250 MILS TO MCH BALL
NV_CLE
M48
R47
U1E

RESERVED_29 RESERVED_22 AB50


Y50
PCH_CRT_B @ DF_TVS RESERVED_21
2 1 Y41 RESERVED_6 RESERVED_14 AB49
150_0402_1% R116 M50 AB44
1M_0402_5% 2 RESERVED_4 RESERVED_13
+3VS 1 R514 PCH_CRT_G 2 @ 1 M49 RESERVED_3 RESERVED_12 U49
1M_0402_5% 2 1 R882 150_0402_1% R117 U43 R44
PCH_CRT_R @ RESERVED_2 RESERVED_11
2 1 J57 RESERVED_1 RESERVED_10 U50
PCH_HDMI_DET T1 AR4 PCH_CRT_HSYNC 150_0402_1% R118 U46
31 PCH_HDMI_DET DDPB_HPD CRT_HSYNC PCH_CRT_HSYNC RESERVED_9
PCH_HDMIOUT_DET N2 AR2 PCH_CRT_VSYNC U44
36 PCH_HDMIOUT_DET DDPC_HPD CRT_VSYNC PCH_CRT_VSYNC RESERVED_8
M1 DDPD_HPD RESERVED_7 H50
AN6 PCH_CRT_R K46
CRT_RED PCH_CRT_R RESERVED_20
D R8 AN2 PCH_CRT_G L56 D
DDPB_AUXP CRT_GREEN PCH_CRT_G RESERVED_19
R9 AM1 PCH_CRT_B J55
DDPB_AUXN CRT_BLUE PCH_CRT_B RESERVED_18
U14 DDPC_AUXP RESERVED_17 F53
U12 DDPC_AUXN CRT_IRTN AM6 RESERVED_16 H52
N6 DDPD_AUXP RESERVED_15 E52
R6 DDPD_AUXN
RESERVED_28 K50
PCH_HDMI_TXD2+ R14 AW1 PCH_CRT_DATA K49
31 PCH_HDMI_TXD2+ DDPB_0P CRT_DDC_DATA PCH_CRT_DATA RESERVED_27
PCH_HDMI_TXD2- R12 AW3 PCH_CRT_CLK AB46
31 PCH_HDMI_TXD2- DDPB_0N CRT_DDC_CLK PCH_CRT_CLK RESERVED_26
PCH_HDMI_TXD1+ M11 G56
31 PCH_HDMI_TXD1+ DDPB_1P RESERVED_25
PCH_HDMI_TXD1- M12 AT3 DAN_IREF
31 PCH_HDMI_TXD1- DDPB_1N DAC_IREF
PCH_HDMI_TXD0+ H8 Y44
31 PCH_HDMI_TXD0+ DDPB_2P RESERVED_24

1
PCH_HDMI_TXD0- K8 L53
31 PCH_HDMI_TXD0- DDPB_2N RESERVED_23
PCH_HDMI_TXC+ L5 R121
31 PCH_HDMI_TXC+ DDPB_3P
PCH_HDMI_TXC- M3 1K_0402_0.5% R50
31 PCH_HDMI_TXC- DDPB_3N RESERVED_5
PCH_HDMI_CTXD2+ L2
36 PCH_HDMI_CTXD2+ DDPC_0P
PCH_HDMI_CTXD2- J3 Y18 @ T3 PLACE DACREFSET RES(R121) CLOSE TO NVRAM
36 PCH_HDMI_CTXD2-

2
PCH_HDMI_CTXD1+ G2 DDPC_0N TP6 @ T4 5 OF 10
36 PCH_HDMI_CTXD1+ DDPC_1P TP7 Y17 PCH:<500 MILS TO MCH BALL
PCH_HDMI_CTXD1- G4 AB18 @ T5 BD82H67-SLJ49-B3_FCBGA942
36 PCH_HDMI_CTXD1- DDPC_1N TP8
PCH_HDMI_CTXD0+ F3 AB17 @ T6
36 PCH_HDMI_CTXD0+ DDPC_2P TP9
PCH_HDMI_CTXD0- F5
36 PCH_HDMI_CTXD0- DDPC_2N
PCH_HDMI_CTXC+ E4
36 PCH_HDMI_CTXC+ DDPC_3P
PCH_HDMI_CTXC- E2
36 PCH_HDMI_CTXC- DDPC_3N +3VS
D5 DDPD_0P
B5 DDPD_0N
C6 DDPD_1P DMI & FDI Termination Voltage
D7 DDPD_1N

1
B7 DDPD_2P Set to VCC when HIGH
C9 DDPD_2N NV_CLE
C E11
B11
DDPD_3P
R482
2.2K_0402_5%
R483
2.2K_0402_5% )RU+'0,287 Set to VSS when LOW C

DDPD_3N UMA@ UMA@

2
U2 AL12 +1.8VS
SDVO_INTP DDPC_CTRLCLK PCH_HDMI_CCLK_R 36
T3 SDVO_INTN DDPC_CTRLDATA AL14 PCH_HDMI_CDATA_R 36

1
W3 AL9 +3VS
SDVO_STALLP DDPD_CTRLCLK R636
U5 SDVO_STALLN DDPD_CTRLDATA AL8
2.2K_0402_5%
U8 SDVO_TVCLKINP SDVO_CTRLCLK AL15

1
U9 AL17

2
SDVO_TVCLKINN SDVO_CTRLDATA NV_CLE R637 2
1 H_SNB_IVB# 5
R394 R395 4.7K_0402_5% 1
6 OF 10 2.2K_0402_5% 2.2K_0402_5%
BD82H67-SLJ49-B3_FCBGA942 UMA@ UMA@ Note:Place R637 close to U1.R47 C782

2
PCH_HDMI_CLK 31,32 and <=100 mils 0.1U_0402_16V4Z
2 @
+5VS PCH_HDMI_DATA 31,32
+CRT_VCC
D31
2 1
@ 1
RB491D_SOT23-3 C718 +CRT_VCC
W=40mils 2
0.1U_0402_16V4Z
@ JCRT1
1 1
RED 2 2
3 3
GREEN 4
B 4 B
5 5
BLUE 6 6
7 7
R671 1 @ 2 0_0402_5% JRGB_VS 8
32,33,43 UART_TX 8
R672 1 @ 2 0_0402_5% 9
32,33,43 UART_RX 9
JRGB_HS 10
RGB_DDC_DAT 10
11 11
RGB_DDC_CLK 12 12

13 GND1
14 GND2
ACES_87213-1200G +CRT_VCC +3VS
CONN@

R515 1 @ 2 0_0402_5% RED 2.2K_0402_5%


PCH_CRT_R
1

1
R516 1 @ 2 0_0402_5% GREEN
PCH_CRT_G
@ R525
R526 4.7K_0402_5% R120 R119
R517 1 @ 2 0_0402_5% BLUE 4.7K_0402_5% @ CRT@ 2.2K_0402_5%
PCH_CRT_B

2
CRT@
2

2
R527
R518 1 @ 2 0_0402_5% JRGB_HS RGB_DDC_DAT 1 @ 2 6 1 PCH_CRT_DATA
PCH_CRT_HSYNC PCH_CRT_DATA
0_0402_5%

5
R519 1 @ 2 0_0402_5% JRGB_VS @ Q15A
PCH_CRT_VSYNC
A
R528 DMN66D0LDW -7_SOT363-6 A
RGB_DDC_CLK 1 @ 2 3 4 PCH_CRT_CLK
PCH_CRT_CLK
0_0402_5%
11/4 Change PN of Q15 from SB00000AR00 to SB00000DH00 @ Q15B
BLUE 2 @ 1 DMN66D0LDW -7_SOT363-6
150_0402_1% R523
GREEN 2 @ 1
150_0402_1% R524 Security Classification Compal Secret Data Compal Electronics, Inc.
RED 2 @ 1 2010/07/20 2011/07/20 Title
Issued Date Deciphered Date
150_0402_1% R522
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) CRT, DPI, VRAM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 15 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ

D D

4 H_FDI_TXN[0..7]
4 H_FDI_TXP[0..7]

U1A CPT_CRB

+3VS CPT_CRB
BH8 BF15 U1G
PCI_DEVSEL# PAR AD0
BH9 DEVSEL# AD1 BF17
17 CLK_PCH_33M_FB BD15 CLKIN_PCILOOPBACK AD2 BT7
AV14 PCIRST# AD3 BT13
R122 1 2 8.2K_0402_5% PCI_DEVSEL# PCI_IRDY# BF11 BG12
R123 8.2K_0402_5% PCI_IRDY# IRDY# AD4
1 2 AV15 PME# AD5 BN11
R124 1 2 8.2K_0402_5% PCI_SERR# PCI_SERR# BR6 BJ12 FDILINK
R125 8.2K_0402_5% PCI_STOP# PCI_STOP# SERR# AD6
1 2 BC12 STOP# AD7 BU9
PCI_PLOCK# BA17 BR12 H31 C42 H_FDI_TXN0
PCI_TRDY# PLOCK# AD8 44 USB30_RN1 TP21 FDI_RXN0 H_FDI_TXP0
BC8 TRDY# AD9 BJ3 44 USB30_RP1 J31 TP25 FDI_RXP0 B43
PCI_PERR# BM3 BR9 C29 F45 H_FDI_TXN1
PERR# AD10 44 USB30_TN1 TP29 FDI_RXN1
R126 1 2 8.2K_0402_5% PCI_PLOCK# PCI_FRAME# BC11 BJ10 E29 F43 H_FDI_TXP1
PCI_TRDY# FRAME# AD11 44 USB30_TP1 TP33 FDI_RXP1 H_FDI_TXN2
R127 1 2 8.2K_0402_5% BM8 H41
R128 8.2K_0402_5% PCI_PERR# AD12 FDI_RXN2 H_FDI_TXP2
1 2 BF3 44 USB30_RN2 J27 J41
R129 8.2K_0402_5% PCI_FRAME# AD13 TP22 FDI_RXP2 H_FDI_TXN3
1 2 AD14 BN2 44 USB30_RP2 L27 TP26 FDI_RXN3 C46
C PCI_GNT0# H_FDI_TXP3 C
BA15 GNT0# AD15 BE4 44 USB30_TN2 F28 TP30 FDI_RXP3 D47
PCI_GNT1# AV8 BE6 E27 B45 H_FDI_TXN4
Boot BIOS Strap Bit 0(GNT1#) PCI_GNT2# GNT1#_GPIO51 AD16 44 USB30_TP2 TP34 FDI_RXN4 H_FDI_TXP4
BU12 GNT2#_GPIO53 AD17 BG15 FDI_RXP4 A46
R130 1 2 8.2K_0402_5% PCI_REQ0# PCI_GNT3# BE2 BC6 T15 @ J25 B47 H_FDI_TXN5
R131 8.2K_0402_5% PCI_REQ1# GNT3#_GPIO55 AD18 T16 @ TP23 FDI_RXN5 H_FDI_TXP5
1 2 BT11 L25 C49
R132 8.2K_0402_5% PCI_REQ2# AD19 T17 @ TP27 FDI_RXP5 H_FDI_TXN6
1 2 AD20 BA14 C26 TP31 FDI_RXN6 J43
R133 1 2 8.2K_0402_5% PCI_REQ3# BL2 T18 @ B27 H43 H_FDI_TXP6
PCI_REQ0# AD21 TP35 FDI_RXP6 H_FDI_TXN7
BG5 BC4 M43
PCI_REQ1# REQ0# AD22 T19 @ FDI_RXN7 H_FDI_TXP7
BT5 BL4 L22 P43
PCI_REQ2# REQ1#_GPIO50 AD23 T20 @ TP24 FDI_RXP7
BK8 BC2 J22
PCI_REQ3# REQ2#_GPIO52 AD24 T21 @ TP28 H_FDI_FSYNC0
AV11 BM13 B25 B51 H_FDI_FSYNC0 4
R134 8.2K_0402_5% PCI_PIRQA# REQ3#_GPIO54 AD25 T22 @ TP32 FDI_FSYNC0 H_FDI_LSYNC0
1 2 BA9 D25 E49 H_FDI_LSYNC0 4
R135 8.2K_0402_5% PCI_PIRQB# AD26 TP36 FDI_LSYNC0 H_FDI_FSYNC1
1 2 BF9 C52 H_FDI_FSYNC1 4
R136 8.2K_0402_5% PCI_PIRQC# AD27 FDI_FSYNC1 H_FDI_LSYNC1
1 2 BA8 D51 H_FDI_LSYNC1 4
R137 8.2K_0402_5% PCI_PIRQD# PCI_PIRQA# AD28 FDI_LSYNC1
1 2 BK10 BF8
PCI_PIRQB# PIRQA# AD29 H_FDI_INT
BJ5 AV17 H46 H_FDI_INT 4
PCI_PIRQC# PIRQB# AD30 FDI_INT
BM15 BK12
PCI_PIRQD# PIRQC# AD31
BP5
PCI_PIRQE# PIRQD#
BN9
R138 8.2K_0402_5% PCI_PIRQE# PCI_PIRQF# PIRQE#_GPIO2
1 2 AV9
PIRQF#_GPIO3
R139 1 2 8.2K_0402_5% PCI_PIRQF# PCI_PIRQG# BT15 BN4
R140 8.2K_0402_5% PCI_PIRQG# CARD_HPLUG PIRQG#_GPIO4 C_BE0#
1 2 37 CARD_HPLUG BR4 BP7
R141 8.2K_0402_5% CARD_HPLUG PIRQH#_GPIO5 C_BE1#
1 2 BG2
C_BE2# 7 OF 10
BP13
C_BE3# BD82H67-SLJ49-B3_FCBGA942
PCI

1 OF 10
BD82H67-SLJ49-B3_FCBGA942

B B

1000P_0402_50V7K 2 1 @ C989 CLK_PCH_33M_FB

8/23 Add

Boot BIOS Strap PCI_GNT0# R142 1 @ 2 1K_0402_5%


PCH_GNT1# PCH_GPIO19 Boot BIOS Loaction Have internal PU
PCI_GNT1# R143 1 @ 2 1K_0402_5%
0 0 LPC Have internal PU
PCI_GNT2# R144 1 @ 2 1K_0402_5%
0 1 Reserved Have internal PU
PCI_GNT3# R145 1 @ 2 1K_0402_5%
1 0 PCI Have internal PU

1 1 SPI *
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI,FDI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 16 of 63
5 4 3 2 1
5 4 3 2 1

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CPT_CRB
U1H

R27 CLKIN_GND1_N_R
CLKIN_GND1_N CLKIN_GND1_P_R CLKIN_GND1_N_R R146 10K_0402_5%
CLKIN_GND1_P P27 1 2
CLKIN_GND1_P_R R147 1 2 10K_0402_5%
W53 CLKIN_GND0_N_R CLKIN_GND0_N_R R148 1 2 10K_0402_5%
T23 @ CLKIN_GND0_N CLKIN_GND0_P_R CLKIN_GND0_P_R R149 10K_0402_5%
D AT11 CLKOUT_PCI0 CLKIN_GND0_P V52 1 2 D
CLK_BUF_ICH_14M R292 1 2 10K_0402_5%
T24 @ AN14 R52 CLK_CPU_XDP# T82
CLKOUT_PCI1 CLKOUT_ITPXDP_N CLK_CPU_XDP
CLKOUT_ITPXDP_P N52 T83
2 1 CLK_PCH_33M_FB_R AT12
16 CLK_PCH_33M_FB CLKOUT_PCI2
R150 22_0402_5% AE2 CLK_PCIE_TV#
CLKOUT_PCIE7N CLK_PCIE_TV# 42
2 1 CLK_PCI_LPC_R AT17 AF1 CLK_PCIE_TV For PCIE WLAN
43 CLK_PCI_LPC CLKOUT_PCI3 CLKOUT_PCIE7P CLK_PCIE_TV 42
R151 22_0402_5%
T25 @ AT14 P31 CLK_CPU_DMI#
CLKOUT_PCI4 CLKOUT_DMI_N CLK_CPU_DMI# 5
R31 CLK_CPU_DMI
CLKOUT_DMI_P CLK_CPU_DMI 5

CLKOUT_DP_N N56
T26 @ AT9 M55
T27 @ CLKOUTFLEX0_GPIO64 CLKOUT_DP_P
BA5 CLKOUTFLEX1_GPIO65
T28 @ AW5 AE6 CLK_PCIE_READER#
CLKOUTFLEX2_GPIO66 CLKOUT_PCIE0N CLK_PCIE_READER# 37
T29 @ BA2 AC6 CLK_PCIE_READER For CardReader
CLKOUTFLEX3_GPIO67 CLKOUT_PCIE0P CLK_PCIE_READER 37

CLKOUT_PCIE1N AA5
+1.05VS_PCH R152 1 2 90.9_0402_1% XCLK_RCOMP AL2 W5
XCLK_RCOMP CLKOUT_PCIE1P

T79 CLK_BUF_ICH_14M AN8 AB12 CLK_PCIE_LAN#


REFCLK14IN CLKOUT_PCIE2N CLK_PCIE_LAN# 38
AB14 CLK_PCIE_LAN For PCIE LAN
CLKOUT_PCIE2P CLK_PCIE_LAN 38

CLKOUT_PCIE3N AB9
CLKOUT_PCIE3P AB8

CLKOUT_PCIE4N Y9
CLKOUT_PCIE4P Y8
C AF3 CLK_PCIE_W LAN# C
CLKOUT_PCIE5N CLK_PCIE_W LAN# 42
AG2 CLK_PCIE_W LAN For TV Tuner
CLKOUT_PCIE5P CLK_PCIE_W LAN 42
C156
2 1 AB3 CLK_USB30#
CLKOUT_PCIE6N CLK_USB30# 36
AA2 CLK_USB30 For USB 3.0
CLKOUT_PCIE6P CLK_USB30 36
2

27P_0402_50V8J R153
1

AG8 CLK_PCIE_VGA#
CLKOUT_PEG_A_N CLK_PCIE_VGA# 22
Y1 1M_0402_5% AG9 CLK_PCIE_VGA
CLKOUT_PEG_A_P CLK_PCIE_VGA 22
XTAL25_OUT AJ5
C157 XTAL25_OUT
AE12
2

XTAL25_IN CLKOUT_PEG_B_N
2 1 AJ3 XTAL25_IN CLKOUT_PEG_B_P AE11

27P_0402_50V8J 25MHZ_20PF_7A25000012

1000P_0402_50V7K 2 1 @ C999 XCLK_RCOMP

B B
8/23 Add

8 OF 10
BD82H67-SLJ49-B3_FCBGA942

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) CLOCK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 17 of 63
5 4 3 2 1
5 4 3 2 1

+1.05VS_PCH
U1I CPT_CRB http://adf.ly/3o8pJ +1.05VS_PCH

1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0805_10V6K F20 AC24 10U_0805_10V6K 1U_0402_6.3V6K


VCCIO_24 VCCCORE_1
F30 VCCIO_25 VCCCORE_2 AC26
1 1 1 1 1 1 V25 VCCIO_26 VCCCORE_3 AC28
V27 VCCIO_27 VCCCORE_4 AC30 1 1 1 1
C439 C438 C437 C436 C440 C441 V31 AC32
1U_0402_6.3V6K VCCIO_28 VCCCORE_5 C158 C159 C442 C489
V33 VCCIO_29 VCCCORE_6 AE24
2 2 2 2 2 2 @ 1U_0402_6.3V6K
Y24 VCCIO_30 VCCCORE_7 AE28
2 2 2 2
1U_0402_6.3V6K 10U_0805_10V6K
Y26 VCCIO_31 PCIe CORE VCCCORE_8 AE30
Y30 VCCIO_32 VCCCORE_9 AE32
D Y32 AE34 1U_0402_6.3V6K D
VCCIO_33 VCCCORE_10
Y34 VCCIO_34 VCCCORE_11 AE36
VCCCORE_12 AG32
VCCCORE_13 AG34
VCCCORE_14 AJ32
VCCCORE_15 AJ34
AJ36 +3VALW +3VSB +3VSB
VCCCORE_16
VCCCORE_17 AL32
VCCCORE_18 AL34

2
VCCCORE_19 AN32 1
AN34 R371 R368
VCCCORE_20 220_0402_5% 390K_0402_5% C562
VCCCORE_21 AR32
AR34 4.7U_0805_10V4Z
VCCCORE_22 2
AA34

6 2

1
VCCIO_22
AA36 VCCIO_23 PCIe
Q88A

3
V22 DMN66D0LDW -7_SOT363-6 R367
VCCIO_35 Q19
Y20 VCCIO_36 2 1 2 2
Y22 1M_0402_5%
VCCIO_37 SI2305CDS-T1-GE3_SOT23-3
1

3
C611

1
3300P_0402_50V7-K
+VCCDMI 2
43 PCH_ENABLE 5 +3VALW
Near B41/E41 Q88B

2
DMN66D0LDW -7_SOT363-6

4
0.1U_0402_16V4Z 4.7U_0603_6.3V6K 1 1
1 1 1 1 R370
C C564 C563 C
C749 C750 C751 C752 47K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z

1
2 2
0.1U_0402_16V4Z
2 2 2 2
1U_0402_6.3V6K

Note:Trace need to be at least 20 mils width with full VSS/VCC reference plane)
AG24 +VCCASW 1U_0402_6.3V6K R537 1 2 0_0805_5% +1.05VS_PCH
R584 1 +VCCDMI VCCASW_4
+1.05VCCIO 2 B41 VCCDMI_2 VCCASW_5 AG26
0_0805_5% DMI AG28 1 1 1 1
VCCASW_6
E41 VCCDMI_1 VCCASW_7 AJ24
AJ26 C735 C736 C739 C737
VCCASW_8 1U_0402_6.3V6K 10U_0805_6.3V6M
VCCASW_9 AJ28
1U_0402_6.3V6K 2 2 2 2
+1.05VS_PCH AL40 VCCIO_8 VCCASW_10 AL24
+VCCAPLLSATA AN40 VCCIO_9 SATA VCCASW_11 AL28
1 1 AN41 AN22 1U_0402_6.3V6K
VCCIO_10 VCCASW_12
VCCASW_13 AN24
1 1 C753 C754 AG38 AN26
1U_0402_6.3V6K VCCIO_20 VCCASW_14
AG40 VCCIO_21 VCCASW_15 AN28
C771 C772 2 2
SATA3 VCCASW_16 AR24
1U_0402_6.3V6K 10U_0805_6.3V6M AG41 AR26
@ 2 2 @ VCCIO_7 VCCASW_17
VCCASW_18 AR28
VCCASW_19 AR30
VCCASW_20 AR36
VCCASW_21 AR38
VCCASW_22 AU30
VCCASW_23 AU36
B +VCCSSC B

AU34 +VCCDIFFCLK
VCCASW_3
VCCASW_2 AV36
+VCCAPLLEXP AU32
VCCASW_1 1 1

AE15 +VCCDIFFCLK R374 1 2 0_0603_5% +1.05VS_PCH C755 C757


VCCDIFFCLKN_1 1U_0402_6.3V6K 1U_0402_6.3V6K
1 1 AE17
DIFFCLKN VCCDIFFCLKN_2 AG15
2 2
C740 C741 VCCDIFFCLKN_3 +VCC_DMICLK R536 1
AJ20 2 0_0805_5% Near AE15 Near AC20
1U_0402_6.3V6K 10U_0805_6.3V6M DMI VCCCLKDMI
AE40 +VCCUSB
+1.05VS_PCH
@ 2 2 @ VCCIO_18 +VCCSSC R375 1
VCCSSC_1 AC20 2 0_0603_5% +1.05VS_PCH
SSC VCCSSC_2 AE20
+1.05VS_PCH R631 1 @ 2 0_0805_5% +VCCAPLLSATA U56 VCCAPLLSATA +VCCUSB R376 1 +VCC_DMICLK
VCCIO_1 AV24 2 0_0805_5% +1.05VS_PCH
Need change to 1uH +1.05VS_PCH BA38 VCCIO_19 PLL VCCIO_2 AV26
USB VCCIO_3 AY25 1
+1.05VS_PCH L27 1 @ 2 +VCCAPLLEXP B53 AY27 1 1
+VCCAPLLDMI2 10UH_LB2012T100MR_20% VCCAPLLEXP VCCIO_4 C758
+1.05VS_PCH R632 1 @ 2 0_0603_5% +VCCAFDIPLL C54 V36 1U_0402_6.3V6K C738 C756
VCCAFDIPLL VCCIO_13 2 1U_0402_6.3V6K 10U_0805_6.3V6M
1 1
PCIe Y36
2 2 @
VCCIO_12
C773 C774 +1.05VS_PCH R633 1 @ 2 0_0603_5% +VCCACLK_PCH AL5 SATA3 AJ38 Near AJ20
1U_0402_6.3V6K 10U_0805_6.3V6M VCCACLK VCCIO_11
@ 2 2 @ R634 1 @
+1.05VS_PCH 2 0_0805_5% +VCCAPLLDMI2 A19 VCCAPLLDMI2 PCIe VCCIO_14 Y28

9 OF 10

A
BD82H67-SLJ49-B3_FCBGA942 A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 18 of 63
5 4 3 2 1
5 4 3 2 1

+3VS http://adf.ly/3o8pJ

2
U1K
D13 +VCCVRM
RB751V-40_SOD323-2 +VCC5REF BF1
+5VS V5REF
+VCC5REFSUS BT25 AJ1 R535 1 2 0_0402_5% +1.8VS

1
V5REF_SUS VCCVRM_1
VCCVRM_4 R2 1 1
R533 1 2 10_0402_5% +VCC5REF +3VALW AV28 R54
VCCSUSHDA VCCVRM_3 C775 C734
VCCVRM_2 R56
D 1 1 Near BF1 +3VS AU20 10U_0805_6.3V6M 0.1U_0402_16V4Z D
VCC3_3_9 2 2
AV20 VCC3_3_10
C728 C729 +3VALW R898 1 @ 2 AU22
0.1U_0402_16V4Z 1U_0402_6.3V6K 0_0805_5% VCC3_3_7
VCCPNAND_01 T55 +1.8VS
2 2 R899 1
+3VS 2 AN52 VCCSPI VCCPNAND_02 T57
0_0805_5% +1.8VS Near T55
1 Near AN52
+3VALW
1
C727 AL38 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS
1U_0402_6.3V6K VCC3_3_5 C726
PCI VCC3_3_6 AN38
2
2 0.1U_0402_16V4Z
1 1 1 1 2
D14
RB751V-40_SOD323-2 C722 C723 C724 C725
+5VALW BC17 1U_0402_6.3V6K
VCC3_3_2 2 2 2 2
BD17
1

HVCMOS VCC3_3_3
BD20 Near AL38
R534 1 VCC3_3_4
2 10_0402_5% +VCC5REFSUS
0.1U_0402_16V4Z
Near BF1 +3VS
1 1
C731 C730 A12
0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCIe VCC3_3_8
AF57
2 2 VCC3_3_1
SATA 1 1
C160 C161
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
+3VS +3VALW Near AF57
C 1 1 C

C733 C732
1U_0402_6.3V6K 0.1U_0402_16V4Z Place C706/C720/C721 close to PCH BALL(D55)
2 2

Near AU20 Near AV28 +1.05VS_PCH


+3VALW

BT35 1U_0402_6.3V6K
VCCSUS3_3_11

VCCSUS3_3_2 AV30 1 1 1 1
VCCSUS3_3_3 AV32 1 1
AY31 C706 C719 C720 C721
VCCSUS3_3_4 C162 C163
VCCSUS3_3_5 AY33 0.1U_0402_16V4Z
0.1U_0402_16V4Z 2 2 2 2
VCCSUS3_3_6 BJ36 0.1U_0402_16V4Z
9/7 Add BK36
2 2
VCCSUS3_3_7 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
VCCSUS3_3_8 BM36 Near BT35
R154
VCCSUS3_3_9 AT40
VCCSUS3_3_10 AU38

VCCSUS3_3_1 U31
+VCCDPW ROK
FBM-11-160808-601-T_0603 AV40 +VCCDPW ROK R635 1 2 0_0603_5% +3VALW
UMA@ VCCDSW3_3

V_PROC_IO D55 +1.05VCCIO 1


V_PROC_IO_NCTF B56
C167
B +VCCSUS B
Layout Note: +3VS DCPSUS_3 A39
2
0.1U_0402_16V4Z
AA32
Close to AT1,AB1,AC2 < 100 mil DCPSUS_1
Near AV40
BU42 +RTCVCC
DIS@ <1mA VCCRTC +RTCVCC
2

BR54 +VCCRTCEXT
1_0603_5% DCPRTC
DCPRTC_NCTF BT56
R154 AT41 +VCCSUS
+VCCDAC DCPSUS_2
11/4 Change PN of C170/C172 from SF000002Y00 to AV41 +VCCDCPSUS
1

DCPSUSBYP
SF000001G00 +VCCSST
AT1 VCCADAC DCPSST BA46
1 1 1 1
+1.05VS_PCH +VCCADPLLA AB1 @
1 VCCADPLLA
1 C164 C410 C165 C166
C169 + C168 AC2 Near BA46 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ VCCADPLLB 2 2 2 2
L1 1 2 220U_6.3V_M
10UH_LB2012T100MR_20% 1U_0402_6.3V6K 2 2
10uH inductor, 120mA
1 1
C171 R155 BD82H67-SLJ49-B3_FCBGA942
1

+ 0_0402_5% +RTCVCC
C170 1U_0402_6.3V6K @
330U_6.3V_M_R14 2
2
1 1
2

+VCCADPLLB C776 C630


1U_0402_6.3V6K 0.1U_0402_16V4Z
2 2
A +VCCADPLLA A
L2 1 2
10UH_LB2012T100MR_20% Near BU42
10uH inductor, 120mA 1 1 +VCCADPLLB
C173
+
C172 1U_0402_6.3V6K
330U_6.3V_M_R14 2 Security Classification Compal Secret Data Compal Electronics, Inc.
2
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (8/9) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 19 of 63
5 4 3 2 1
5 4 3 2 1
CPT_CRB
U1J
BC15 A26
BC20
BC27
BC31
VSS_125
VSS_126
VSS_127
VSS_128
VSS_5
VSS_6
VSS_7
VSS_8
A29
A42
A49
http://adf.ly/3o8pJ
BC36 VSS_129 VSS_9 A9
BC38 VSS_130 VSS_10 AA20 U1L
BC47 VSS_131 VSS_11 AA22
BC9 VSS_132 VSS_12 AA24
BD25 VSS_133 VSS_13 AA26 L12 VSS_231 TP3 L33
BD33 VSS_134 VSS_14 AA28 L17 VSS_232 TP13 AE49
BF12 VSS_135 VSS_15 AA30 L38 VSS_233 TP17 BA36
BF20 VSS_136 VSS_16 AA38 L41 VSS_234 TP18 AY36
BF25 AB11 L43 Y14
VSS_137 VSS_17 VSS_235 TP19
BF33 AB15 M20 Y12
VSS_138 VSS_18 VSS_236 TP20
BF41 AB40 M22 P22
D VSS_139 VSS_19 VSS_237 TP1 D
BF43 AB41 M25 M38
VSS_140 VSS_20 VSS_238 TP4
BF46 AB43 M27 P25
VSS_141 VSS_21 VSS_239 VSS_296
BF52 AB47 M31 R25
VSS_142 VSS_22 VSS_240 VSS_295
BF6 AB52 T52 P36
VSS_143 VSS_23 VSS_260 VSS_294
BG22 AB57 T6 R36
VSS_144 VSS_24 VSS_261 VSS_293
BG25 AB6 U11 L31
VSS_145 VSS_25 VSS_262 TP2
BG27 AC22 U15 L36
VSS_146 VSS_26 VSS_263 TP5
BG31 AC34 U17 AL44
VSS_147 VSS_27 VSS_264 VSS_292
BG33 AC36 U20 AL43
VSS_148 VSS_28 VSS_265 VSS_291
BG36 AC38 U22
VSS_149 VSS_29 VSS_266
BG38 AC4 U25 AE41
VSS_150 VSS_30 VSS_267 TP14
BH52 VSS_151 VSS_31 AC54 U27 VSS_268 TP15 AE43
BH6 VSS_152 VSS_32 AE14 U33 VSS_269
BJ1 VSS_153 VSS_33 AE18 U36 VSS_270 TP11 BA27
BJ15 VSS_154 VSS_34 AE22 U38 VSS_271
BK20 VSS_155 VSS_35 AE26 U41 VSS_272
BK41 VSS_156 VSS_36 AE38 U47 VSS_273
BK52 VSS_157 VSS_37 AE4 U53 VSS_274
BK6 VSS_158 VSS_38 AE47 V20 VSS_275
BM10 VSS_159 VSS_39 AE8 V38 VSS_276
BM12 VSS_160 VSS_40 AE9 V6 VSS_277
BM16 VSS_161 VSS_41 AF52 W1 VSS_278
BM22 VSS_162 VSS_42 AF6 W55 VSS_279 TP10 BM46
BM23 VSS_163 VSS_43 AG11 W57 VSS_280
BM26 VSS_164 VSS_44 AG14 Y11 VSS_281
BM28 VSS_165 VSS_45 AG20 Y15 VSS_282 L_BKLTCTL AG12 NOTE:PCH adds support for panel power sequencing required for
BM32 VSS_166 VSS_46 AG22 Y38 VSS_283 L_BKLTEN AG18 embedded DisplayPort support. L_VDDEN, L_BKLTEN and L_BKLTCTL pins are
BM40 VSS_167 VSS_47 AG30 Y40 VSS_284 L_VDD_EN AG17
BM42 AG36 Y43 added on the PCH for panel power sequencing. It is important to note that a 6
VSS_168 VSS_48 VSS_285 layer board design may be required to access these pins on the PCH package
BM48 VSS_169 VSS_49 AG43 Y46 VSS_286
BM5 VSS_170 VSS_50 AG44 Y47 VSS_287 in a fully featured platform design.
BN31 VSS_171 VSS_51 AG46 Y49 VSS_288
C C
BN47 VSS_172 VSS_52 AG5 Y52 VSS_289
BN6 VSS_173 VSS_53 AG50 Y6 VSS_290
BP3 VSS_174 VSS_54 AG53
BP33 VSS_175 VSS_55 AH52
BP35 VSS_176 VSS_56 AH6
BR22 VSS_177 VSS_57 AJ22
BR52 VSS_178 VSS_58 AJ30 A4 VSS_NCTF_1
BU19 AJ57 A6
VSS_179 VSS_59 VSS_NCTF_2
BU26 AK52 B2
VSS_180 VSS_60 VSS_NCTF_3
BU29 AK6 BM1
VSS_181 VSS_61 VSS_NCTF_4
BU36 AL11 BM57
VSS_182 VSS_62 VSS_NCTF_5
BU39 AL18 BP1
VSS_183 VSS_63 VSS_NCTF_6
C19 AL20 BP57
VSS_184 VSS_64 VSS_NCTF_7
C32 AL22 BT2
VSS_185 VSS_65 VSS_NCTF_8
C39 AL26 BU4
VSS_186 VSS_66 VSS_NCTF_9
C4 AL30 BU52
VSS_187 VSS_67 VSS_NCTF_10
D15 AL36 BU54
VSS_188 VSS_68 VSS_NCTF_11
D23 AL41 BU6
VSS_189 VSS_69 VSS_NCTF_12
D3 AL46 D1
VSS_190 VSS_70 VSS_NCTF_13
D35 AL47 F1
VSS_191 VSS_71 VSS_NCTF_14
D43 AM52
VSS_192 VSS_73
D45 AM3
VSS_193 VSS_72
E19 AM57
VSS_194 VSS_74
E39 AN11
VSS_195 VSS_75
E54 AN12
VSS_196 VSS_76
E6 AN15
VSS_197 VSS_77
E9 AN17
VSS_198 VSS_78
F10 AN18
VSS_199 VSS_79
F12 AN20
VSS_200 VSS_80
F16 AN30
VSS_201 VSS_81
F22 AN36
VSS_202 VSS_82
F26 AN4
B VSS_203 VSS_83 B
F32 AN43
VSS_204 VSS_84
F33 AN47
VSS_205 VSS_85
F35 AN54
VSS_206 VSS_86
F36 AN9
VSS_207 VSS_87
F40 AR20
VSS_208 VSS_88
F42 AR22
VSS_209 VSS_89
F46 AR52
VSS_210 VSS_90
F48 AR6
VSS_211 VSS_91
F50 AT15
VSS_212 VSS_92
F8 AT18 AY22
VSS_213 VSS_93 VSS_4
AV18 AT43 C12
VSS_104 VSS_94 VSS_3
AV22 AT47 AE56
VSS_105 VSS_95 VSS_1
AV34 AT52 BR36
VSS_106 VSS_96 VSS_2
AV38 AT6 AU2
VSS_107 VSS_97 VSSADAC
AV47 AT8
VSS_108 VSS_98
AV6 AU24 A54
VSS_109 VSS_99 TS_VSS1
AW57 AU26 A52
VSS_110 VSS_100 TS_VSS2
AY38 AU28 F57
VSS_111 VSS_101 TS_VSS3
AY6 AU5 D57
VSS_112 VSS_102 TS_VSS4
B23 AV12
VSS_113 VSS_103
BA11 BA49
VSS_114 VSS_119
BA12 BB1
VSS_115 VSS_120
BA31 BB3
VSS_116 VSS_121
BA41 BB52
VSS_117 VSS_122
BA44 BB6
VSS_118 VSS_123
G54 BC14
VSS_214 VSS_124
H15 M33
VSS_215 VSS_241
H20 M36
VSS_216 VSS_242
H22 M46
VSS_217 VSS_243 BD82H67-SLJ49-B3_FCBGA942
H25 M52
VSS_218 VSS_244
H27 M57
VSS_219 VSS_245
H33 VSS_220 VSS_246 M6
A A
H6 VSS_221 VSS_247 M8
J1 VSS_222 VSS_248 M9
J33 VSS_223 VSS_249 N4
J46 VSS_224 VSS_250 N54
J48 VSS_225 VSS_251 R11
J5 VSS_226 VSS_252 R15
J53 VSS_227 VSS_253 R17
K52 R22
K6
VSS_228 VSS_254
R4
Security Classification Compal Secret Data Compal Electronics, Inc.
VSS_229 VSS_255
K9 VSS_230 VSS_256 R41 Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
R43
VSS_257
VSS_258 R46 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH(9/9)VSS
R49 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
10 OF 10 VSS_259 Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
BD82H67-SLJ49-B3_FCBGA942 Date: Thursday, June 16, 2011 Sheet 20 of 63
5 4 3 2 1
5 4 3 2 1

U8D
http://adf.ly/3o8pJ
Part 4 of 7
For GB2-128 & GB2b-128 colayout....
AM11 IFPA_TXC NC_0 A2
AM12 IFPA_TXC_N NC_1 A7
AM8 IFPA_TXD0 NC_2 B7
AL8 IFPA_TXD0_N NC_3 C5
AM10 C7 STRAP4 STRAP4 30
IFPA_TXD1 NC_4
AM9 IFPA_TXD1_N NC_5 D5
AK10 IFPA_TXD2 NC_6 D6
AL10 D7 STRAP3 STRAP3 30
IFPA_TXD2_N NC_7
AK11 IFPA_TXD3 NC_8 E5
AL11 E7 VPGOOD 1 2
D IFPA_TXD3_N NC_9 R1187 10K_0402_5% D
NC_10 F4
G5 GV@
NC_11
AP13 IFPB_TXC NC_12 H32
AN13 IFPB_TXC_N NC_13 J25
AN8 IFPB_TXD4 NC_14 J26
AP8 P6 STRAP_REF2 1 2
IFPB_TXD4_N NC_15 R1188 40.2K_0402_1%
AP10 IFPB_TXD5 NC_16 U7
AN10 V6 GV@
IFPB_TXD5_N NC_17
AR11 IFPB_TXD6 NC_18 Y4
AR10 IFPB_TXD6_N NC_19 AA4
AN11 IFPB_TXD7 NC_20 AB4
AP11 IFPB_TXD7_N NC_21 AB7
NC_22 AC5

NC
NC_23 AD6 Internal Thermal Sensor
VGA_HDMI_CTXD2+ AM7 AF6
36
36
VGA_HDMI_CTXD2+
VGA_HDMI_CTXD2-
VGA_HDMI_CTXD2-
VGA_HDMI_CTXD1+
AM6
AL5
IFPC_L0
IFPC_L0_N
NC_24
NC_25 AG6
AG20
External VGA Thermal Sensor SMB_CLK_GPU 22
36 VGA_HDMI_CTXD1+ VGA_HDMI_CTXD1- IFPC_L1 NC_26
AM5 AJ5 SMB_DATA_GPU 22
36 VGA_HDMI_CTXD1- VGA_HDMI_CTXD0+ IFPC_L1_N NC_27 Address: 0x9A H
To HDMI-out 36 VGA_HDMI_CTXD0+
AM3 IFPC_L2 NC_28 AK15

1
VGA_HDMI_CTXD0- AM4 AL7 R186 R187
36 VGA_HDMI_CTXD0- VGA_HDMI_CTXC+ IFPC_L2_N NC_29
AP1 IFPC_L3 VGA@ VGA@
36 VGA_HDMI_CTXC+ VGA_HDMI_CTXC- AR2 IFPC_L3_N 0_0402_5% 0_0402_5%
36 VGA_HDMI_CTXC-

Address: 0x9E H

2
AR8 +3VS_DGPU
IFPD_L0
AR7 IFPD_L0_N @ U9
AP7 IFPD_L1 C213 2 1 1 8 VGA_SMB_CK2
AN7 0.1U_0402_16V4Z VDD SCLK
IFPD_L1_N
AN5 IFPD_L2 THERM_D+ 2 7 VGA_SMB_DA2
C AP5 D+ SDATA C

LVDS/TMDS
IFPD_L2_N C214
AR5 IFPD_L3 1 2 2200P_0402_50V7K 3 6 THERM#_VGA
AR4 D- ALERT# THERM#_VGA 22
IFPD_L3_N @
THERM_D- 4 5
THERM# GND
VGA_DVI_ETXD2+ AH6 VGA_SMB_CK2 C980 @ 1
31 VGA_DVI_ETXD2+ IFPE_L0 2 1000P_0402_50V7K
VGA_DVI_ETXD2- AH5 ADM1032ARMZ-2REEL_MSOP8 VGA_SMB_DA2 C981 @ 1
31 VGA_DVI_ETXD2- IFPE_L0_N 2 1000P_0402_50V7K
VGA_DVI_ETXD1+ AH4 @
31 VGA_DVI_ETXD1+ VGA_DVI_ETXD1- IFPE_L1
AG4
31 VGA_DVI_ETXD1- VGA_DVI_ETXD0+ IFPE_L1_N
To 2D/3D Vision 31
31
VGA_DVI_ETXD0+
VGA_DVI_ETXD0-
VGA_DVI_ETXD0-
AF4
AF5
IFPE_L2
IFPE_L2_N
VGA_DVI_ETXC+ AE6
31 VGA_DVI_ETXC+ VGA_DVI_ETXC- IFPE_L3 +3VS_DGPU
AE5
31 VGA_DVI_ETXC- IFPE_L3_N
D35 VGA_SENSE +3VS_DGPU
VDD_SENSE_0 VGA_SENSE 59
AL2 P7
IFPF_L0 VDD_SENSE_1

2
AL3 AD20 VGA@ 11/4 Change PN of Q1 from
IFPF_L0_N VDD_SENSE_2
AJ3 VGA@ R188 R189
IFPF_L1
2.2K_0402_5% 2.2K_0402_5%
SB00000EO00 to SB00000DH00
AJ2
IFPF_L1_N
AJ1
IFPF_L2

5
AH1 AD19 GND_SENSE VGA@
IFPF_L2_N GND_SENSE_0

1
AH2 E35 GND_SENSE 59 Q1B
+3VS_DGPU IFPF_L3 GND_SENSE_1
AH3 R7 VGA_SMB_CK2 4 3
IFPF_L3_N GND_SENSE_2
1
1

EC_SMB_CK2 43

2
R192 R193 VGA@ DMN66D0LDW-7_SOT363-6
2.2K_0402_5% 2.2K_0402_5% Q1A
VGA@ VGA@ AP2 VGA_SMB_DA2 1 6
IFPC_AUX_I2CW_SCL EC_SMB_DA2 43
AN3
TEST
2
2

VGA_HDMI_CCLK_R IFPC_AUX_I2CW_SDA_N
36 VGA_HDMI_CCLK_R DMN66D0LDW-7_SOT363-6
VGA_HDMI_CDATA_R PU AT EC SIDE, +3VS AND 4.7K
B HDMI-OUT 36 VGA_HDMI_CDATA_R
+3VS_DGPU AP4 AP35 TESTMODE @
B
IFPD_AUX_I2CX_SCL TESTMODE
AN4 AP14 T31 VGA_SMB_CK2 1 2 EC_SMB_CK2
IFPD_AUX_I2CX_SDA_N JTAG_TCK

1
AN14 @ R190 0_0402_5%
JTAG_TDI T32
1
1

AN16 @ VGA_SMB_DA2 1 2 EC_SMB_DA2


JTAG_TDO T33 10K_0402_5%
R682 R683 AE4 AR14 @ R191 @ 0_0402_5%
IFPE_AUX_I2CY_SCL JTAG_TMS T34
2.2K_0402_5% 2.2K_0402_5% AD4 @ 2 10K_0402_5%
AP16 R195 1 VGA@ VGA@ R194
VGA@ VGA@ IFPE_AUX_I2CY_SDA_N JTAG_TRST_N

2
2
2

31,32 VGA_HDMI_ECLK_R VGA_HDMI_ECLK_R AF3


VGA_HDMI_EDATA_R IFPF_AUX_I2CZ_SCL
Scalar 31,32 VGA_HDMI_EDATA_R AF2
IFPF_AUX_I2CZ_SDA_N SERIAL
C3
ROM_CS_N ROM_SI
D3
ROM_SI ROM_SO ROM_SI 30
C4
ROM_SO ROM_SCLK ROM_SO 30
D4
ROM_SCLK ROM_SCLK 30
if unuse this pin , pull down 36k
+3VS_DGPU
GENERAL A5 R1189 2 VGA@ 1 36K_0402_1%
NC/SPDIF_NC
R196 A4
BUFRST_N R197 1 VGA@
MULTI_STRAP_REF0_GND
N9 2 40.2K_0402_1%
2 1 AB5
CEC
VGA@ 10K_0402_5% M9 R198 1 VGA@ 2 40.2K_0402_1%
STRAP0 MULTI_STRAP_REF1_GND
W5
30 STRAP0 STRAP1 STRAP0 THERM_D+
W7 B5
30 STRAP1 STRAP2 STRAP1 THERMDP THERM_D-
V7 B4
30 STRAP2 STRAP2 THERMDN

A N12P-GV1-A1_BGA973 VGA@ A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(1/12)-LVDS/HDMI/DP/THM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 16, 2011 Sheet 21 of 63
5 4 3 2 1
5 4 3 2 1

U8A

PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0
AP17
AN17
http://adf.ly/3o8pJ
PEX_RX0
PEX_RX0_N
Part 1 of 7
GPIO0
GPIO1
K1
K2 VGA_HDMI_DET
VGA_HDMI_DET 36
4 PEG_HTX_C_GRX_P[0..15]
PEG_HTX_C_GRX_P[0..15]

PEG_HTX_C_GRX_P1 AN19 K3 VGA_BL_PWM PEG_HTX_C_GRX_N[0..15]


PEG_HTX_C_GRX_N1 PEX_RX1 GPIO2 VGA_ENVDD VGA_BL_PWM 34 4 PEG_HTX_C_GRX_N[0..15]
AP19 PEX_RX1_N GPIO3 H3 VGA_ENVDD 34
PEG_HTX_C_GRX_P2 AR19 H2 VGA_ENBKL
PEG_HTX_C_GRX_N2 PEX_RX2 GPIO4 GPU_VID0 VGA_ENBKL 33 PEG_GTX_C_HRX_P[0..15]
AR20 PEX_RX2_N GPIO5 H1 GPU_VID0 59
PEG_HTX_C_GRX_P3 AP20 H4 GPU_VID1 4 PEG_GTX_C_HRX_P[0..15]
PEX_RX3 GPIO6 GPU_VID1 59
PEG_HTX_C_GRX_N3 AN20 H5
PEG_HTX_C_GRX_P4 PEX_RX3_N GPIO7 GPIO8 PEG_GTX_C_HRX_N[0..15]
AN22 PEX_RX4 GPIO8 H6
PEG_HTX_C_GRX_N4 AP22 J7 THERM#_VGA 4 PEG_GTX_C_HRX_N[0..15]
PEG_HTX_C_GRX_P5 PEX_RX4_N GPIO9 THERM#_VGA 21
AR22 K4
PEG_HTX_C_GRX_N5 PEX_RX5 GPIO10
AR23 K5
PEG_HTX_C_GRX_P6 PEX_RX5_N GPIO11 GPIO12
AP23 H7

GPIO
D PEG_HTX_C_GRX_N6 PEX_RX6 GPIO12 +3VS_DGPU D
AN23 J4 T30
PEG_HTX_C_GRX_P7 PEX_RX6_N GPIO13 @
AN25 J6
PEG_HTX_C_GRX_N7 PEX_RX7 GPIO14 VGA_IFPE_DET_R R156 1 VGA@2
AP25 L1
PEG_HTX_C_GRX_P8 PEX_RX7_N GPIO15 10K_0402_5%
AR25 L2
PEG_HTX_C_GRX_N8 PEX_RX8 GPIO16
Under GPU(below 150mils) AR26
PEX_RX8_N GPIO17
L4

2
G
150mA PEG_HTX_C_GRX_P9 AP26 M4
BLM18PG330SN1D_0603 PEG_HTX_C_GRX_N9 PEX_RX9 GPIO18
AN26 L7
0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M +PLLVDD PEG_HTX_C_GRX_P10 PEX_RX9_N GPIO19 VGA_IFPE_DET_R
+1.05VS_DGPU 1 2 AN28 L5 3 1
L3 PEG_HTX_C_GRX_N10 PEX_RX10 GPIO20 VGA_IFPE_DET 31,32

D
AP28 K6
VGA@ PEG_HTX_C_GRX_P11 PEX_RX10_N GPIO21
1 1 1 1 2 AR28 L6
C177 C174 C175 C178 C176 PEG_HTX_C_GRX_N11 PEX_RX11 GPIO22 Q58
AR29 M6
PEG_HTX_C_GRX_P12 PEX_RX11_N GPIO23 SSM3K7002FU_SC70-3
AP29 PEX_RX12 GPIO24 M7
PEG_HTX_C_GRX_N12 AN29 @
VGA@ 2 VGA@ 2 VGA@ 2 VGA@ 2 VGA@ 1 PEG_HTX_C_GRX_P13 PEX_RX12_N +3VS_DGPU
AN31 PEX_RX13 MIOA_D0_NC N1
PEG_HTX_C_GRX_N13 AP31 P4 R850 1 @ 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z PEG_HTX_C_GRX_P14 PEX_RX13_N MIOA_D1_NC 0_0402_5%
AR31 PEX_RX14 MIOA_D2_NC P1
PEG_HTX_C_GRX_N14 AR32 P2
PEG_HTX_C_GRX_P15 PEX_RX14_N MIOA_D3_NC
AR34 PEX_RX15 MIOA_D4_NC P3
PEG_HTX_C_GRX_N15 AP34 T3 GPIO8 R157 1 VGA@ 2 10K_0402_5%
PEX_RX15_N MIOA_D5_NC
MIOA_D6_NC T2
T1 GPIO12 R158 1 VGA@ 2 10K_0402_5%
PEG_GTX_C_HRX_P0 C179 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P0 MIOA_D7_NC
1 2 AL17 PEX_TX0 MIOA_D8_NC U4
PEG_GTX_C_HRX_N0 C180 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N0 AM17 U1 I2CC_SCL R159 1 VGA@ 2 2.2K_0402_5%

PCI EXPRESS
PEG_GTX_C_HRX_P1 C181 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P1 PEX_TX0_N MIOA_D9_NC
1 2 AM18 PEX_TX1 MIOA_D10_NC U2
PEG_GTX_C_HRX_N1 C182 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N1 AM19 U3 I2CC_SDA R160 1 VGA@ 2 2.2K_0402_5%
PEG_GTX_C_HRX_P2 C183 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P2 PEX_TX1_N MIOA_D11_NC
1 2 AL19 R6
PEG_GTX_C_HRX_N2 C184 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N2 PEX_TX2 MIOA_D12_NC SMB_CLK_GPU R161 1 VGA@ 2 2.2K_0402_5%
1 2 AK19 T6

DVO
PEG_GTX_C_HRX_P3 C185 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P3 PEX_TX2_N MIOA_D13_NC
1 2 AL20 N6
PEG_GTX_C_HRX_N3 C186 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N3 PEX_TX3 MIOA_D14_NC SMB_DATA_GPU R162 1 VGA@ 2 2.2K_0402_5%
1 2 AM20 PEX_TX3_N
PEG_GTX_C_HRX_P4 C187 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P4 AM21 Y1
PEG_GTX_C_HRX_N4 C188 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N4 PEX_TX4 MIOB_D0_NC THERM#_VGA R163 1 VGA@ 2 10K_0402_5%
1 2 AM22 Y2
PEG_GTX_C_HRX_P5 C189 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P5 PEX_TX4_N MIOB_D1_NC
1 2 AL22 PEX_TX5 MIOB_D2_NC Y3
C PEG_GTX_C_HRX_N5 C190 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N5 HDCP_SCL R164 1 VGA@ 2 2.2K_0402_5% C
1 2 AK22 AB3
PEG_GTX_C_HRX_P6 C191 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P6 PEX_TX5_N MIOB_D3_NC
1 2 AL23 PEX_TX6 MIOB_D4_NC AB2
PEG_GTX_C_HRX_N6 C192 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N6 AM23 AB1 HDCP_SDA R165 1 VGA@ 2 2.2K_0402_5%
PEG_GTX_C_HRX_P7 C193 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P7 PEX_TX6_N MIOB_D5_NC
1 2 AM24 PEX_TX7 MIOB_D6_NC AC4
PEG_GTX_C_HRX_N7 C194 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N7 AM25 AC1 I2CA_SCL R166 1 VGA@ 2 2.2K_0402_5%
PEG_GTX_C_HRX_P8 C195 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P8 PEX_TX7_N MIOB_D7_NC
1 2 AL25 PEX_TX8 MIOB_D8_NC AC2
PEG_GTX_C_HRX_N8 C196 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N8 AK25 AC3 I2CA_SDA R167 1 VGA@ 2 2.2K_0402_5%
PEG_GTX_C_HRX_P9 C197 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P9 PEX_TX8_N MIOB_D9_NC
1 2 AL26 AE3
PEG_GTX_C_HRX_N9 C198 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N9 PEX_TX9 MIOBD_10_NC I2CB_SCL R168 1 VGA@ 2 2.2K_0402_5%
1 2 AM26
PEX_TX9_N MIOB_D11_NC
AE2
PEG_GTX_C_HRX_P10 C199 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P10 AM27 U6
PEG_GTX_C_HRX_N10 C200 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N10 PEX_TX10 MIOB_D12_NC I2CB_SDA R169 1 VGA@ 2 2.2K_0402_5%
1 2 AM28
PEX_TX10_N MIOB_D13_NC
W6
PEG_GTX_C_HRX_P11 C201 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P11 AL28 Y6
PEG_GTX_C_HRX_N11 C202 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N11 PEX_TX11 MIOB_D14_NC
1 2 AK28
PEG_GTX_C_HRX_P12 C203 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P12 PEX_TX11_N
1 2 AK29 N3
PEG_GTX_C_HRX_N12 C204 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N12 PEX_TX12 MIOA_HSYNC_NC
1 2 AL29 L3
PEG_GTX_C_HRX_P13 C205 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P13 PEX_TX12_N MIOA_VSYNC_NC VGA_ENVDD R170 1 VGA@ 2 10K_0402_5%
1 2 AM29
PEG_GTX_C_HRX_N13 C206 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N13 PEX_TX13
1 2 AM30
PEX_TX13_N MIOB_HSYNC_NC
W1
PEG_GTX_C_HRX_P14 C207 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P14 AM31 W2 VGA_ENBKL R171 2 VGA@ 1 10K_0402_5%
PEG_GTX_C_HRX_N14 C208 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N14 PEX_TX14 MIOB_VSYNC_NC
1 2 AM32
PEG_GTX_C_HRX_P15 C209 VGA@ .1U_0402_16V7K PEG_GTX_HRX_P15 PEX_TX14_N VGA_BL_PWM R172 2 @
1 2 AN32
PEX_TX15 MIOA_DE_NC
N2 1 10K_0402_5%
PEG_GTX_C_HRX_N15 C210 1 2 VGA@ .1U_0402_16V7K PEG_GTX_HRX_N15 AP32 P5
PEX_TX15_N MIOA_CTL3_NC
N5
MIOA_VREF_NC VGA_HDMI_DET R754 1 VGA@ 2 100K_0402_5%
Y5
CLK_PCIE_VGA MIOB_DE_NC
17 CLK_PCIE_VGA AR16 W3
CLK_PCIE_VGA# PEX_REFCLK MIOB_CTL3_NC
AR17 AF1
17 CLK_PCIE_VGA# CLK_REQ_GPU# PEX_REFCLK_N MIOB_VREF_NC
AR13 VGA@
PEX_CLKREQ_N R173 1
N4 2 10K_0402_5%
PEX_TSTCLK_OUT MIOA_CLKIN_NC
Differential signal 1 VGA@ 2 AJ17
PEX_TSTCLK_OUT MIOA_CLKOUT_NC
R4
R174 200_0402_1% PEX_TSTCLK_OUT# AJ18 VGA@
PEX_TSTCLK_OUT_N R175 1
MIOB_CLKIN_NC
AE1 2 10K_0402_5%
V4
B R176 1 VGA@ 2 PLTRST_VGA_R# MIOB_CLKOUT_NC B
AM16
13,36,37,42 PLT_RST# 0_0402_5% PEX_RST_N +3VS_DGPU
AG21 T4
R177 1 VGA@ 2 2.49K_0402_1% PEX_TERMP MIOA_CLKOUT_NC_N
W4
MIOB_CLKOUT_NC_N
R178 1 @ 2 10M_0402_5% 60mA U5
+PLLVDD MIOACAL_PD_VDDQ_NC
AE9 T5 1
PLLVDD MIOACAL_PU_GND_NC @
45mA

1
Y2 PLTRST_VGA_R# AF9 AA7 C805
SP_PLLVDD MIOBCAL_PD_VDDQ_NC @ 0.1U_0402_16V4Z
XTALIN XTAL_OUT
45mA MIOBCAL_PU_GND_NC
AA6
2
1 2 AD9 R685
VID_PLLVDD
2

10K_0402_5% U6
CLK

27MHZ_16PF_X5H027000FG1H R179 XTALIN B1 8 1

2
VGA@ 10K_0402_5% XTAL_OUT XTAL_IN VCC NC
1 1 B2 AM15 7 2
C211 C212 @ XTAL_OUT DACA_RED HDCP_SCL NC NC
AM14 6 3
18P_0402_50V8J 18P_0402_50V8J 10K_0402_5%2 R180 XTALOUT DACA_GREEN HDCP_SDA SCL NC
1 VGA@ D1 AL14 5 4
1

VGA@ VGA@ XTALSSIN XTAL_OUTBUFF DACA_BLUE SDA GND


2 R181 1 VGA@ D2
XTAL_SSIN

1
2 2 10K_0402_5% AM13 AT88SC0808C-SU-2.7_SO8
DACA_HSYNC @ @ @
AL13
DACA_VSYNC R684 R686
Internal Thermal Sensor R182
SMB_CLK_GPU E2 AJ12 +DACA_VDD 2 1 2.2K_0402_5% 100K_0402_1%
21 SMB_CLK_GPU I2CS_SCL DACA_VDD
SMB_DATA_GPU E1 AK12 10K_0402_5%VGA@

2
21 SMB_DATA_GPU I2CS_SDA DACA_VREF
AK13
I2CC_SCL DACA_RSET
E3
I2CC_SDA I2CC_SCL
DACs

E4 AK4
I2CC_SDA DACB_RED
DACB_GREEN
AL4 8/19 Change symbol and footprint of U6 to SA000017Y00
+3VS_DGPU I2CB_SCL G3 AJ4
I2CB_SDA I2CB_SCL DACB_BLUE
I2C

G2
I2CB_SDA
AM1
I2CA_SCL DACB_HSYNC
G1 AM2
I2CA_SDA I2CA_SCL DACB_VSYNC
G4
I2CA_SDA
2

AG7 +DACB_VDD 2 R183 1 VGA@


R184 HDCP_SCL DACB_VDD 10K_0402_5%
F6 I2CH_SCL DACB_VREF AK6
A VGA@ 10K_0402_5% HDCP_SDA A
G6 I2CH_SDA DACB_RSET AH7
1

N12P-GV1-A1_BGA973 VGA@
CLK_REQ_GPU#
2

@ R185
@R185
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
VGA(2/12)-PCIE/DAC/GPIO
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 22 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ

D D

+VGA_CORE +VGA_CORE
U8G

AB11 VDD_0 VDD_56 P21


AB13 Part 7 of 7 P23
VDD_1 VDD_57
AB15 VDD_2 VDD_58 P25
AB17 R11
AB19
VDD_3
VDD_4
VDD_59
VDD_60 R12 Under GPU
AB21 VDD_5 VDD_61 R13
AB23 VDD_6 VDD_62 R14
AB25 R15 +VGA_CORE
VDD_7 VDD_63
AC11 VDD_8 VDD_64 R16
AC12 R17 4700P_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K 0.047U_0402_25V6K
VDD_9 VDD_65
AC13 VDD_10 VDD_66 R18
AC14 VDD_11 VDD_67 R19
AC15 VDD_12 VDD_68 R20 1 1 1 1 1 1 1 1 1
AC16 R21 C215 C216 C217 C218 C219 C220 C221 C222 C224 C225
VDD_13 VDD_69 C223
AC17 VDD_14 VDD_70 R22
AC18 R23 VGA@
VDD_15 VDD_71 VGA@ VGA@ VGA@ 2 VGA@ 2 VGA@ 2 VGA@ 2 VGA@ 2 VGA@ 2 2 VGA@ 2 VGA@ 2
AC19 VDD_16 VDD_72 R24
AC20 VDD_17 VDD_73 R25
AC21 VDD_18 VDD_74 T12
C AC22 T14 4700P_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K 0.047U_0402_25V6K 0.047U_0402_25V6K C
VDD_19 VDD_75
AC23 VDD_20 VDD_76 T16

POWER
AC24 VDD_21 VDD_77 T18
AC25 VDD_22 VDD_78 T20
AD12 VDD_23 VDD_79 T22
AD14 T24 4700P X2
VDD_24 VDD_80 +VGA_CORE 0.01U X 6
AD16 VDD_25 VDD_81 V11
AD18 V13 0.047U X3
VDD_26 VDD_82 0.022U_0402_25V7K 0.1U_0402_16V4Z 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.022U X3
AD22 VDD_27 VDD_83 V15 0.1U X2
AD24 VDD_28 VDD_84 V17 0.22U X3
L11 VDD_29 VDD_85 V19 1U X1
L12 VDD_30 VDD_86 V21 1 1 1 1 1 1

1
L13 V23 C226 C227 C228 C229 C230 C231 C232 C233 C234
VDD_31 VDD_87
L14 VDD_32 VDD_88 V25
L15 W11 VGA@ VGA@ VGA@

2
VDD_33 VDD_89 VGA@ 2 VGA@ 2 VGA@ 2 2 2 VGA@ VGA@ VGA@ 2
L16 VDD_34 VDD_90 W12
L17 VDD_35 VDD_91 W13
L18 VDD_36 VDD_92 W14
L19 W15 0.022U_0402_25V7K 0.022U_0402_25V7K 0.1U_0402_16V4Z 0.22U_0402_6.3V6K 1U_0402_6.3V6K
VDD_37 VDD_93
L20 VDD_38 VDD_94 W16
L21 VDD_39 VDD_95 W17
L22 VDD_40 VDD_96 W18
L23 VDD_41 VDD_97 W19
L24 W20
L25
VDD_42
VDD_43
VDD_98
VDD_99 W21
+VGA_CORE
Near GPU
M12 VDD_44 VDD_100 W22
M14 W23 +VGA_CORE
VDD_45 VDD_101 22U_0805_6.3V6M 10U_0603_6.3V6M
B M16 VDD_46 VDD_102 W24 B
M18 W25 330U_D2_2V_Y
VDD_47 VDD_103
M20 VDD_48 VDD_104 Y12
M22 VDD_49 VDD_105 Y14 1 2 2 1 1 1
M24 Y16 C235 C236 C237 C238
VDD_50 VDD_106 + C240 + C1018
P11 VDD_51 VDD_107 Y18
P13 Y20 VGA@ VGA@ VGA@
VDD_52 VDD_108 2 VGA@ 1 VGA@ 1 VGA@ 2
P15 VDD_53 VDD_109 Y22
2 2
P17 VDD_54 VDD_110 Y24
P19 560U_2.5V_M_R10
VDD_55 10U_0603_6.3V6M 4.7U_0603_6.3V6K

10/23 Change symbol of C239 from SGA20331E10 to SF000002M00


11/2 Change PN of C1018 from SF000002000 to SF000001K00
N12P-GV1-A1_BGA973 VGA@ +VGA_CORE

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10/7 Add C819~C825

1 1 1 1 1 1 1
C819 C820 C821 C822 C823 C824 C825
@ @ @ @ @ @ @
0.1U_0402_16V4Z 2 2 2 2 2 2 2

A 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(3/12)-VGA CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic1.A
Date: Thursday, June 09, 2011 Sheet 23 of 63
5 4 3 2 1
5 4 3 2 1

+VRAM_1.5VS

3.5A
U8E
http://adf.ly/3o8pJ
2200mA Under GPU
Part 5 of 7
Close to Pin

4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K J23 AG11 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K 10U_0603_6.3V6M +1.05VS_DGPU
FBVDDQ_0 PEX_IOVDDQ_0
J24 FBVDDQ_1 PEX_IOVDDQ_1 AG12
1 1 1 1 1 1 1 1 J29 FBVDDQ_2 PEX_IOVDDQ_2 AG13 1 1 1 1 1 1 1 1
C241 C242 C243 C244 C245 C246 C247 C248 AA27 AG15 C249 C256
@ @ @ FBVDDQ_3 PEX_IOVDDQ_3 C250 C251 C252 C253 C254 C255
AA29 FBVDDQ_4 PEX_IOVDDQ_4 AG16
VGA@ VGA@ VGA@ VGA@ VGA@ AA31 AG17 VGA@ VGA@ VGA@ VGA@ VGA@ @ VGA@ VGA@ 22U_0805_6.3V6M
2 2 2 2 2 2 2 2 FBVDDQ_5 PEX_IOVDDQ_5 2 2 2 2 2 2 2 2
AB27 FBVDDQ_6 PEX_IOVDDQ_6 AG18
AB29 FBVDDQ_7 PEX_IOVDDQ_7 AG22
4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K AC27 AG23 0.1U_0402_16V4Z 1U_0402_6.3V6K 4.7U_0603_6.3V6K
FBVDDQ_8 PEX_IOVDDQ_8
D AD27 FBVDDQ_9 PEX_IOVDDQ_9 AG24 D
AE27 FBVDDQ_10 PEX_IOVDDQ_10 AG25
AJ28 AG26 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K 10U_0603_6.3V6M +1.05VS_DGPU
FBVDDQ_11 PEX_IOVDDQ_11
B18 FBVDDQ_12 PEX_IOVDDQ_12 AJ14
22U_0805_6.3V6M 22U_0805_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M E21 AJ15 1 1 1 1 1 1 1 1
FBVDDQ_13 PEX_IOVDDQ_13 C257 C264
G17 FBVDDQ_14 PEX_IOVDDQ_14 AJ19
G18 AJ21 C258 C259 C260 C261 C262 C263 @
1 1 1 1 1 1 1 1 FBVDDQ_15 PEX_IOVDDQ_15
G22 AJ22 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ @ 22U_0805_6.3V6M
C265 C266 C267 C268 C269 C270 C271 C272 FBVDDQ_16 PEX_IOVDDQ_16 2 2 2 2 2 2 2 2
G8 FBVDDQ_17 PEX_IOVDDQ_17 AJ24
VGA@ @ @ VGA@ @ VGA@ @ VGA@ G9 AJ25
2 2 2 2 2 2 2 2 FBVDDQ_18 PEX_IOVDDQ_18 0.1U_0402_16V4Z 1U_0402_6.3V6K 4.7U_0603_6.3V6K
H29 FBVDDQ_19 PEX_IOVDDQ_19 AJ27

POWER
J14 FBVDDQ_20 PEX_IOVDDQ_20 AK18
22U_0805_6.3V6M 22U_0805_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M J15 AK20
J16
FBVDDQ_21 PEX_IOVDDQ_21
AK23
Close to Pin
FBVDDQ_22 PEX_IOVDDQ_22 L4 VGA@
J17 FBVDDQ_23 PEX_IOVDDQ_23 AK26
J20 AL16 1U_0402_6.3V6K 1U_0402_6.3V6K 2 1 +1.05VS_DGPU
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K 1U_0402_6.3V6K FBVDDQ_24 PEX_IOVDDQ_24 BLM18PG121SN1D_0603
J21 FBVDDQ_25
J22 FBVDDQ_26 1 1 1 1 1
N27 +1.05VS_DGPU
1 1 1 1 1 1 1 FBVDDQ_27
P27 AK16 C280 C281 C282 C803 C804
C273 C274 C275 C276 C277 C278 C279 FBVDDQ_28 PEX_IOVDD_0 VGA@ @ VGA@ VGA@ @ 1000P_0402_50V7K
R27 FBVDDQ_29 PEX_IOVDD_1 AK17
VGA@ @ VGA@ VGA@ 2 2 2 2 2 1U_0402_6.3V6K
T27 FBVDDQ_30 PEX_IOVDD_2 AK21
VGA@ 2 VGA@ 2 VGA@ 2 2 2 2 2
U27 AK24 1 1 1 1
FBVDDQ_31 PEX_IOVDD_3 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
U29 FBVDDQ_32 PEX_IOVDD_4 AK27
0.1U_0402_16V4Z 1U_0402_6.3V6K 1U_0402_6.3V6K V27 C514 C515 C516 C517
V29
FBVDDQ_33 120mA @ @ @ @
FBVDDQ_34 1000P_0402_50V7K 2 2 2 2 1000P_0402_50V7K
V34 FBVDDQ_35
W27 AG14 +PEX_PLLVDD 1000P_0402_50V7K
FBVDDQ_36 PEX_PLLVDD
Y27 FBVDDQ_37
C C
+VRAM_1.5VS VGA@ 10K_0402_5% +3VS_DGPU
8/9 EMI Suggestion R199 1 +IFPAB_PLLVDD 240mA (120mA each) 1U_0402_6.3V6K
2 AK9 IFPAB_PLLVDD PEX_SVDD_3V3 AG19
1000P_0402_50V7K 1 2 AJ11 F7
R200 @ 1K_0402_1% IFPAB_RSET PEX_SVDD_3V3_NC
1 1 1
+3VS_DGPU
1 1 1 1
2 R201 1 +IFPAB_IOVDD AG9
120mA(12~16mils) C283 C284 C285
C502 C506 C507 C509 VGA@ 10K_0402_5% IFPA_IOVDD 0.1U_0402_16V4Z 1U_0402_6.3V6K VGA@ VGA@ VGA@
AG10 IFPB_IOVDD VDD33_0 J10
VGA@ VGA@ VGA@ VGA@ 2 2 2
VDD33_1 J11
1000P_0402_50V7K 2 2 2 2 1000P_0402_50V7K
J12 1 1 1 1 1
1000P_0402_50V7K +IFPC_PLLVDD VDD33_2 C290 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
AJ9 IFPC_PLLVDD VDD33_3 J13
1 VGA@ 2 AK7 J9 C286 C287 C288 C289
R202 1K_0402_1% IFPC_RSET VDD33_4 VGA@ VGA@ VGA@ VGA@ VGA@ 4.7U_0603_6.3V6K
+IFPC_IOVDD 2 2 2 2 2
AJ8 IFPC_IOVDD
VGA@ P9 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R205 1 +IFPD_PLLVDD MIOA_VDDQ_NC_0 +3VS_DGPU
2 AC6 IFPD_PLLVDD MIOA_VDDQ_NC_1 R9 8/9 EMI Suggestion

2
1 @ 2 10K_0402_5% AB6 T9 Under GPU(below 150mils)
R204 1K_0402_1% IFPD_RSET MIOA_VDDQ_NC_2 R206 1000P_0402_50V7K
MIOA_VDDQ_NC_3 U9
2 R691 1 +IFPD_IOVDD AK8 VGA@ 10K_0402_5%
VGA@ 10K_0402_5% IFPD_IOVDD
1 1 1 1
AA9

1
+IFPEF_PLLVDD MIOB_VDDQ_NC_0 C510 C511 C512 C513
AJ6 IFPEF_PLLVDD MIOB_VDDQ_NC_1 AB9
1 VGA@ 2 AL1 IFPEF_RSET MIOB_VDDQ_NC_2 W9 VGA@ VGA@ VGA@ VGA@
R208 1K_0402_1% Y9 1000P_0402_50V7K 2 2 2 2 1000P_0402_50V7K
+IFPE_IOVDD MIOB_VDDQ_NC_3 1000P_0402_50V7K
AE7 IFPE_IOVDD

2
AD7 IFPF_IOVDD VGA@ R210
10K_0402_5%
B B
+3VS_DGPU
N12P-GV1-A1_BGA973 VGA@

1
L5
2 1 +IFPCDEF_PLLVDD
BLM18PG181SN1D_0603 Under GPU(below 150mils)
VGA@
220mA +1.05VS_DGPU
285mA +3VS to +3VS_DGPU
0_0603_5% L13
+IFPCDEF_PLLVDD 1 2 1U_0402_6.3V6K +IFPC_PLLVDD 2 1 4.7U_0603_6.3V6K 0.1U_0402_16V4Z +IFPE_IOVDD
R688 BLM18PG181SN1D_0603 +3VS_DGPU
VGA@ VGA@ 1 1 1 1
+3VS PJ26
JUMP_43X79
C816 C815 C818 C817 2
1 1
VGA@ VGA@ VGA@ VGA@ 2 1 1
C291 C292 2 2 2 2 VGA@
@ VGA@
2 2 1U_0402_6.3V6K 0.1U_0402_16V4Z

4.7U_0603_6.3V6K
220mA
+IFPCDEF_PLLVDD 1 2 0.1U_0402_16V4Z +IFPEF_PLLVDD
R687 0_0603_5%
Under GPU(below 150mils) VGA@ 1 1 1
+1.05VS_DGPU C814 C813 C812
L6 285mA @ @ VGA@
2 1 0.1U_0402_16V4Z +IFPC_IOVDD
BLM18PG181SN1D_0603 2 2 2
A A
VGA@ 1 1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z
C300 C301 C302
@ VGA@ @
2 2 2

1U_0402_6.3V6K 0.1U_0402_16V4Z Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(4/12)-POWER
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic1.A
Date: Thursday, June 09, 2011 Sheet 24 of 63
5 4 3 2 1
5 4 3 2 1

B3
U8F
http://adf.ly/3o8pJ
Part 6 of 7
GND_0
B6 GND_1 GND_97 V18
B9 GND_2 GND_98 V20
B12 GND_3 GND_99 V22
B15 GND_4 GND_100 V24
B21 GND_5 GND_101 V31
B24 GND_6 GND_102 Y11
B27 GND_7 GND_103 Y13
B30 GND_8 GND_104 Y15
B33 GND_9 GND_105 Y17
D
C2 GND_10 GND_106 Y19 D
C34 GND_11 GND_107 Y21
E6 GND_12 GND_108 Y23
E9 GND_13 GND_109 Y25
E12 GND_14 GND_110 AA2
E15 GND_15 GND_111 AA5
E18 GND_16 GND_112 AA11
E24 GND_17 GND_113 AA12
E27 GND_18 GND_114 AA13
E30 GND_19 GND_115 AA14
F2 GND_20 GND_116 AA15
F31 GND_21 GND_117 AA16
F34 GND_22 GND_118 AA17
F5 GND_23 GND_119 AA18
J2 GND_24 GND_120 AA19
J5 GND_25 GND_121 AA20
J31 GND_26 GND_122 AA21
J34 GND_27 GND_123 AA22
K9 GND_28 GND_124 AA23
L9 GND_29 GND_125 AA24
M2 GND_30 GND_126 AA25
M5 GND_31 GND_127 AA34
M11 GND_32 GND_128 AB12
M13 GND_33 GND_129 AB14
M15 GND_34 GND_130 AB16
M17 GND_35 GND_131 AB18
M19 GND_36 GND_132 AB20
M21 GND_37 GND_133 AB22
M23 GND_38 GND_134 AB24
M25 GND_39 GND_135 AC9
C M31 GND_40 GND_136 AD2 C
M34 GND_41 GND_137 AD5

GND
N11 GND_42 GND_138 AD11
N12 GND_43 GND_139 AD13
N13 GND_44 GND_140 AD15
N14 GND_45 GND_141 AD17
N15 GND_46 GND_142 AD21
N16 GND_47 GND_143 AD23
N17 GND_48 GND_144 AD25
N18 GND_49 GND_145 AD31
N19 GND_50 GND_146 AD34
N20 GND_51 GND_147 AE11
N21 GND_52 GND_148 AE12
N22 GND_53 GND_149 AE13
N23 GND_54 GND_150 AE14
N24 GND_55 GND_151 AE15
N25 GND_56 GND_152 AE16
P12 GND_57 GND_153 AE17
P14 GND_58 GND_154 AE18
P16 GND_59 GND_155 AE19
P18 GND_60 GND_156 AE20
P20 GND_61 GND_157 AE21
P22 GND_62 GND_158 AE22
P24 GND_63 GND_159 AE23
R2 GND_64 GND_160 AE24
R5 GND_65 GND_161 AE25
R31 GND_66 GND_162 AG2
R34 GND_67 GND_163 AG5
T11 GND_68 GND_164 AG31
B
T13 GND_69 GND_165 AG34 B
T15 GND_70 GND_166 AK2
T17 GND_71 GND_167 AK5
T19 GND_72 GND_168 AK14
T21 GND_73 GND_169 AK31
T23 GND_74 GND_170 AK34
T25 GND_75 GND_171 AL6
U11 GND_76 GND_172 AL9
U12 GND_77 GND_173 AL12
U13 GND_78 GND_174 AL15
U14 GND_79 GND_175 AL18
U15 GND_80 GND_176 AL21
U16 GND_81 GND_177 AL24
U17 GND_82 GND_178 AL27
U18 GND_83 GND_179 AL30
U19 GND_84 GND_180 AN2
U20 GND_85 GND_181 AN34
U21 GND_86 GND_182 AP3
U22 GND_87 GND_183 AP6
U23 GND_88 GND_184 AP9
U24 GND_89 GND_185 AP12
U25 GND_90 GND_186 AP15
V2 GND_91 GND_187 AP18
V5 GND_92 GND_188 AP21
V9 GND_93 GND_189 AP24
V12 GND_94 GND_190 AP27
V14 GND_95 GND_191 AP30
V16 GND_96 GND_192 AP33

A A
N12P-GV1-A1_BGA973 VGA@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(5/12)-GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 09, 2011 Sheet 25 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ

U8B

Part 2 of 7 U30 CMDA0


MDA[0..63] FBA_CMD0 CMDA0 28
D MDA0 L32 V30 D
28,29 MDA[0..63] MDA1 FBA_D0 FBA_CMD1 CMDA2
N33 FBA_D1 FBA_CMD2 U31 CMDA2 28
MDA2 L33 V32 CMDA3
FBA_D2 FBA_CMD3 CMDA3 28
MDA3 N34 T35 CMDA4
FBA_D3 FBA_CMD4 CMDA4 28,29
MDA4 N35 U33 CMDA5
FBA_D4 FBA_CMD5 CMDA5 28,29
MDA5 P35 W32 CMDA6
FBA_D5 FBA_CMD6 CMDA6 28,29
MDA6 P33 W33 CMDA7
FBA_D6 FBA_CMD7 CMDA7 28,29
MDA7 P34 W31 CMDA8
FBA_D7 FBA_CMD8 CMDA8 28,29
MDA8 K35 W34 CMDA9
FBA_D8 FBA_CMD9 CMDA9 28,29
MDA9 K33 U34 CMDA10
FBA_D9 FBA_CMD10 CMDA10 28,29
MDA10 K34 U35 CMDA11
FBA_D10 FBA_CMD11 CMDA11 28,29
MDA11 H33 U32 CMDA12
FBA_D11 FBA_CMD12 CMDA12 28,29
MDA12 G34 T34 CMDA13
FBA_D12 FBA_CMD13 CMDA13 28,29
MDA13 G33 T33 CMDA14
FBA_D13 FBA_CMD14 CMDA14 28,29
MDA14 E34 W30 CMDA15
FBA_D14 FBA_CMD15 CMDA15 28,29
MDA15 E33 AB30 CMDA16
FBA_D15 FBA_CMD16 CMDA16 29
MDA16 G31 AA30
MDA17 FBA_D16 FBA_CMD17 CMDA18
F30 FBA_D17 FBA_CMD18 AB31 CMDA18 29
MDA18 G30 AA32 CMDA19
FBA_D18 FBA_CMD19 CMDA19 29
MDA19 G32 AB33 CMDA20
FBA_D19 FBA_CMD20 CMDA20 28,29
MDA20 K30 Y32 CMDA21
FBA_D20 FBA_CMD21 CMDA21 28,29
MDA21 K32 Y33 CMDA22
FBA_D21 FBA_CMD22 CMDA22 28,29
MDA22 H30 AB34 CMDA23
FBA_D22 FBA_CMD23 CMDA23 28,29
MDA23 K31 AB35 CMDA24
FBA_D23 FBA_CMD24 CMDA24 28,29
MDA24 L31 Y35 CMDA25
FBA_D24 FBA_CMD25 CMDA25 28,29
MDA25 L30 W35 CMDA26
FBA_D25 FBA_CMD26 CMDA26 28,29
MDA26 M32 Y34 CMDA27

MEMORY INTERFACE
FBA_D26 FBA_CMD27 CMDA27 28,29
MDA27 N30 Y31 CMDA28
FBA_D27 FBA_CMD28 CMDA28 28,29
MDA28 M30 Y30 CMDA29
FBA_D28 FBA_CMD29 CMDA29 28,29
C MDA29 P31 W29 CMDA30 C
FBA_D29 FBA_CMD30 CMDA30 28,29
MDA30 R32 Y29
MDA31 FBA_D30 FBA_CMD31
R30 FBA_D31
MDA32 AG30 P32 DQMA0
FBA_D32 FBA_DQM0 DQMA0 28
MDA33 AG32 H34 DQMA1
FBA_D33 FBA_DQM1 DQMA1 28
MDA34 AH31 J30 DQMA2
FBA_D34 FBA_DQM2 DQMA2 28
MDA35 AF31 P30 DQMA3
FBA_D35 FBA_DQM3 DQMA3 28
MDA36 AF30 AF32 DQMA4
FBA_D36 FBA_DQM4 DQMA4 29
MDA37 AE30 AL32 DQMA5
FBA_D37 FBA_DQM5 DQMA5 29
MDA38 AC32 AL34 DQMA6
FBA_D38 FBA_DQM6 DQMA6 29
MDA39 AD30 AF35 DQMA7
FBA_D39 FBA_DQM7 DQMA7 29
MDA40 AN33
MDA41 FBA_D40 DQSA#0
AL31 FBA_D41 FBA_DQS_RN0 L35 DQSA#0 28

A
MDA42 AM33 G35 DQSA#1
FBA_D42 FBA_DQS_RN1 DQSA#1 28
MDA43 AL33 H31 DQSA#2
FBA_D43 FBA_DQS_RN2 DQSA#2 28
MDA44 AK30 N32 DQSA#3
FBA_D44 FBA_DQS_RN3 DQSA#3 28
MDA45 AK32 AD32 DQSA#4
FBA_D45 FBA_DQS_RN4 DQSA#4 29
MDA46 AJ30 AJ31 DQSA#5
FBA_D46 FBA_DQS_RN5 DQSA#5 29
MDA47 AH30 AJ35 DQSA#6
FBA_D47 FBA_DQS_RN6 DQSA#6 29
MDA48 AH33 AC34 DQSA#7
FBA_D48 FBA_DQS_RN7 DQSA#7 29
MDA49 AH35
MDA50 FBA_D49 DQSA0
AH34 FBA_D50 FBA_DQS_WP0 L34 DQSA0 28
MDA51 AH32 H35 DQSA1
FBA_D51 FBA_DQS_WP1 DQSA1 28
MDA52 AJ33 J32 DQSA2
FBA_D52 FBA_DQS_WP2 DQSA2 28
MDA53 AL35 N31 DQSA3
FBA_D53 FBA_DQS_WP3 DQSA3 28
MDA54 AM34 AE31 DQSA4
FBA_D54 FBA_DQS_WP4 DQSA4 29
MDA55 AM35 AJ32 DQSA5
FBA_D55 FBA_DQS_WP5 DQSA5 29
MDA56 AF33 AJ34 DQSA6
FBA_D56 FBA_DQS_WP6 DQSA6 29
MDA57 AE32 AC33 DQSA7
B FBA_D57 FBA_DQS_WP7 DQSA7 29 B
MDA58 AF34
MDA59 FBA_D58
AE35 FBA_D59 FBA_WCK0 P29
MDA60 AE34 R29
MDA61 FBA_D60 FBA_WCK0_N
AE33 FBA_D61 FBA_WCK1 L29
+1.05VS_DGPU Under GPU(below 150mils) MDA62 AB32 M29
MDA63 FBA_D62 FBA_WCK1_N
BLM18PG330SN1D_0603
12mil AC35 FBA_D63 FBA_WCK2 AG29
FBA_WCK2_N AH29
1 2 10U_0603_6.3V6M 1U_0402_6.3V6K 0.1U_0402_16V4Z +FB_AVDD_0 AG27 FB_DLLAVDD_0 FBA_WCK3 AD29
L7 AF27 AE29
VGA@ FB_PLLAVDD_0 FBA_WCK3_N
1 1 1 1 1
+FB_AVDD_1 J19
C303 C304 C305 C306 C307 FB_DLLAVDD_1 CLKA0
J18 FB_PLLAVDD_1 FBA_CLK0 T32 CLKA0 28
VGA@ VGA@ VGA@ VGA@ VGA@ T31 CLKA0#
2 2 2 2 2 FBA_CLK0_N CLKA0# 28
J27 FB_VREF_NC
0.1U_0402_16V4Z @ 2R218 60.4_0402_1%
1 T30 AC31 CLKA1
FBA_DEBUG0 FBA_CLK1 CLKA1 29
0.1U_0402_16V4Z 2 1 T29 AC30 CLKA1#
FBA_DEBUG1 FBA_CLK1_N CLKA1# 29
R219 10K_0402_5%
@
+VRAM_1.5VS N12P-GV1-A1_BGA973 VGA@
+1.05VS_DGPU

BLM18PG330SN1D_0603
12mil
1 2 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z +FB_AVDD_1
L8
VGA@ 1 1 1 1 1
C308 C309 C310 C311 C312
A
VGA@ VGA@ VGA@ VGA@ VGA@ A
2 2 2 2 2
1U_0402_6.3V6K
0.1U_0402_16V4Z

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(6/12)-MEM Interface A
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 16, 2011 Sheet 26 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ
U8C

Part 3 of 7 F18
FBC_CMD0
B13 FBC_D0 FBC_CMD1 E19
D13 FBC_D1 FBC_CMD2 D18
A13 FBC_D2 FBC_CMD3 C17
A14 FBC_D3 FBC_CMD4 F19
C16 FBC_D4 FBC_CMD5 C19
B16 FBC_D5 FBC_CMD6 B17
D A17 FBC_D6 FBC_CMD7 E20 D
D16 FBC_D7 FBC_CMD8 B19
C13 FBC_D8 FBC_CMD9 D20
B11 FBC_D9 FBC_CMD10 A19
C11 FBC_D10 FBC_CMD11 D19
A11 FBC_D11 FBC_CMD12 C20
C10 FBC_D12 FBC_CMD13 F20
C8 FBC_D13 FBC_CMD14 B20
B8 FBC_D14 FBC_CMD15 G21
A8 FBC_D15 FBC_CMD16 F22
E8 FBC_D16 FBC_CMD17 F24
F8 FBC_D17 FBC_CMD18 F23
F10 FBC_D18 FBC_CMD19 C25
F9 FBC_D19 FBC_CMD20 C23
F12 FBC_D20 FBC_CMD21 F21
D8 FBC_D21 FBC_CMD22 E22
D11 FBC_D22 FBC_CMD23 D21
E11 FBC_D23 FBC_CMD24 A23
D12 FBC_D24 FBC_CMD25 D22
E13 FBC_D25 FBC_CMD26 B23
F13 C22

MEMORY INTERFACE C
FBC_D26 FBC_CMD27
F14 FBC_D27 FBC_CMD28 B22
F15 FBC_D28 FBC_CMD29 A22
E16 FBC_D29 FBC_CMD30 A20
F16 FBC_D30 FBC_CMD31 G20
F17 FBC_D31
D29 FBC_D32 FBC_DQM0 A16
F27 FBC_D33 FBC_DQM1 D10
F28 FBC_D34 FBC_DQM2 F11
C E28 D15 C
FBC_D35 FBC_DQM3
D26 FBC_D36 FBC_DQM4 D27
F25 FBC_D37 FBC_DQM5 D34
D24 FBC_D38 FBC_DQM6 A34
E25 FBC_D39 FBC_DQM7 D28
E32 FBC_D40
F32 FBC_D41 FBC_DQS_RN0 B14
D33 FBC_D42 FBC_DQS_RN1 B10
E31 FBC_D43 FBC_DQS_RN2 D9
C33 FBC_D44 FBC_DQS_RN3 E14
F29 FBC_D45 FBC_DQS_RN4 F26
D30 FBC_D46 FBC_DQS_RN5 D31
E29 FBC_D47 FBC_DQS_RN6 A31
B29 FBC_D48 FBC_DQS_RN7 A26
C31 FBC_D49
C29 FBC_D50 FBC_DQS_WP0 C14
B31 FBC_D51 FBC_DQS_WP1 A10
C32 FBC_D52 FBC_DQS_WP2 E10
B32 FBC_D53 FBC_DQS_WP3 D14
B35 FBC_D54 FBC_DQS_WP4 E26
B34 FBC_D55 FBC_DQS_WP5 D32
A29 FBC_D56 FBC_DQS_WP6 A32
B28 FBC_D57 FBC_DQS_WP7 B26
A28 FBC_D58
C28 FBC_D59 FBC_WCK0 G14
C26 FBC_D60 FBC_WCK0_N G15
D25 FBC_D61 FBC_WCK1 G11
B25 FBC_D62 FBC_WCK1_N G12
A25 FBC_D63 FBC_WCK2 G27
B B
FBC_WCK2_N G28
FBC_WCK3 G24
+VRAM_1.5VS 1 2 K27 FBCAL_PD_VDDQ FBC_WCK3_N G25
R223 VGA@ 40.2_0402_1%
1 2 L27 FBCAL_PU_GND
R224 VGA@ 40.2_0402_1% E17
FBC_CLK0
1 2 M27 FBCAL_TERM_GND FBC_CLK0_N D17
R225 VGA@ 60.4_0402_1%
+VRAM_1.5VS 60.4_0402_1% 2 1 R226 G19
FBC_DEBUG0 FBC_CLK1 D23
2 @ 1 G16 FBB_DEBUG1 FBC_CLK1_N E23
R227 10K_0402_5%
@
N12P-GV1-A1_BGA973 VGA@

GV sku

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(7/12)-MEM Interface C
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 09, 2011 Sheet 27 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ
Memory Partition A - Lower 32 bits MDA[0..63] 26,29

CMDA[30..0] 26

+VRAM_1.5VS DQMA[7..0] 26,29


U10 U11 DQSA[7..0] 26,29

1
+FBA_VREFCA0 M8 E3 MDA23 +FBA_VREFCA0 M8 E3 MDA26
D VREFCA DQL0 VREFCA DQL0 DQSA#[7..0] 26,29 D
R1175 +FBA_VREFDQ0 H1 F7 MDA19 +FBA_VREFDQ0 H1 F7 MDA29
1.1K_0402_1% VREFDQ DQL1 MDA18 VREFDQ DQL1 MDA27
F2 F2
VGA@ CMDA9 DQL2 MDA22 CMDA9 DQL2 MDA31
N3 F8 N3 F8
CMDA11 A0 DQL3 MDA20 CMDA11 A0 DQL3 MDA24
P7 H3 Group2 P7 H3 Group3
2

+FBA_VREFCA0 CMDA8 A1 DQL4 MDA17 CMDA8 A1 DQL4 MDA28


P3 H8 P3 H8
CMDA25 A2 DQL5 MDA21 CMDA25 A2 DQL5 MDA25
N2 G2 N2 G2
A3 DQL6 A3 DQL6
1

1 CMDA10 P8 H7 MDA16 CMDA10 P8 H7 MDA30


R1176 CMDA24 A4 DQL7 CMDA24 A4 DQL7
P2 P2
1.1K_0402_1% C1257 CMDA22 A5 CMDA22 A5
R8 R8
VGA@ 0.01U_0402_25V7K CMDA7 A6 MDA13 CMDA7 A6 MDA6
R2 D7 R2 D7
2 VGA@ CMDA21 A7 DQU0 MDA11 CMDA21 A7 DQU0 MDA3
T8 C3 T8 C3
2

CMDA6 A8 DQU1 MDA14 CMDA6 A8 DQU1 MDA4


R3 A9 DQU2 C8 R3 A9 DQU2 C8
CMDA29 L7 C2 MDA9 CMDA29 L7 C2 MDA1
CMDA23 A10/AP DQU3 MDA12 Group1 CMDA23 A10/AP DQU3 MDA5
R7 A11 DQU4 A7 R7 A11 DQU4 A7 Group0
CMDA28 N7 A2 MDA8 CMDA28 N7 A2 MDA2
CMDA20 A12 DQU5 MDA15 CMDA20 A12 DQU5 MDA7
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDA4 T7 A3 MDA10 CMDA4 T7 A3 MDA0
+VRAM_1.5VS CMDA14 A14 DQU7 CMDA14 A14 DQU7
M7 A15/BA3 M7 A15/BA3
+VRAM_1.5VS +VRAM_1.5VS
1

CMDA12 M2 B2 CMDA12 M2 B2
R1177 CMDA27 BA0 VDD CMDA27 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
1.1K_0402_1% CMDA26 M3 G7 CMDA26 M3 G7 U10 U11
VGA@ BA2 VDD BA2 VDD
VDD K2 VDD K2
K8 K8
2

+FBA_VREFDQ0 VDD VDD


VDD N1 VDD N1
CLKA0 J7 N9 R1179 CLKA0 J7 N9
26 CLKA0 CK VDD CK VDD
1

1 CLKA0# K7 R1 10K_0402_5% CLKA0# K7 R1


26 CLKA0# CMDA3 CK VDD CMDA3 CK VDD K4W1G1646G-BC11 K4W1G1646G-BC11
R1178 K9 R9 1 VGA@ 2 K9 R9
1.1K_0402_1% C1258 CKE/CKE0 VDD CKE/CKE0 VDD X76_SAM512M@ X76_SAM512M@
VGA@ 0.01U_0402_25V7K
2 VGA@ CMDA2 K1 A1 1 2 CMDA2 K1 A1 U10 U11
2

C ODT/ODT0 VDDQ ODT/ODT0 VDDQ C


CMDA0 L2 A8 R1180 CMDA0 L2 A8
CMDA30 CS/CS0 VDDQ 10K_0402_5% CMDA30 CS/CS0 VDDQ
J3 RAS VDDQ C1 J3 RAS VDDQ C1
CMDA15 K3 C9 VGA@ CMDA15 K3 C9
CMDA13 CAS VDDQ CMDA13 CAS VDDQ
L3 D2 L3 D2
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
F1 F1 H5TQ1G63DFR-11C H5TQ1G63DFR-11C
DQSA2 VDDQ DQSA3 VDDQ X76_HYN512M@ X76_HYN512M@
26 DQSA2 F3 DQSL VDDQ H2 26 DQSA3 F3 DQSL VDDQ H2
DQSA1 C7 H9 DQSA0 C7 H9
26 DQSA1 DQSU VDDQ 26 DQSA0 DQSU VDDQ U10 U11

DQMA2 E7 A9 DQMA3 E7 A9
26 DQMA2 DQMA1 DML VSS 26 DQMA3 DQMA0 DML VSS
26 DQMA1 D3 B3 26 DQMA0 D3 B3
DMU VSS DMU VSS
E1 E1
VSS VSS
G8 G8
DQSA#2 VSS DQSA#3 VSS K4W2G1646C-HC11 K4W2G1646C-HC11
26 DQSA#2 G3 J2 26 DQSA#3 G3 J2
DQSA#1 DQSL VSS DQSA#0 DQSL VSS X76_SAM1G@ X76_SAM1G@
26 DQSA#1 B7 J8 26 DQSA#0 B7 J8
DQSU VSS DQSU VSS
M1 M1
VSS VSS U10 U11
M9 M9
VSS VSS
P1 P1
CMDA5 VSS CMDA5 VSS
T2 RESET VSS
P9 T2 RESET VSS
P9
T1 T1
VSS VSS
L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
H5TQ2G63BFR-11C H5TQ2G63BFR-11C
1

1
J1 B1 J1 B1 X76_HYN1G@ X76_HYN1G@
R1184 R1185 NC/ODT1 VSSQ R1186 NC/ODT1 VSSQ
L1 B9 L1 B9
10K_0402_5% 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ
J9 D1 J9 D1
VGA@ VGA@ NC/CE1 VSSQ VGA@ NC/CE1 VSSQ
L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
E8 E8
VSSQ VSSQ
F9 F9
VSSQ VSSQ
G1 G1
B VSSQ VSSQ B
64Mx16 VSSQ
G9 64Mx16 VSSQ
G9

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96
X76@ X76@

+VRAM_1.5VS +VRAM_1.5VS

CLKA0
1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
VGA@ 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1

VGA@

C1260

VGA@

C1261

VGA@

C1262

VGA@

C1263

1 2 80.6_0402_1%
VGA@

C1264

VGA@

C1265

VGA@

C1266

VGA@

C1267

VGA@

C1268

VGA@

C1269

VGA@

C1270

VGA@

C1271

VGA@

C1272

VGA@

C1273
R1182 R1181
160_0402_1% VGA@
@ 1 2 80.6_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2 2 2
R1183
2

2
CLKA0# C1259
0.01U_0402_25V7K
@
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3/ Channel A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 28 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ
Memory Partition A - Upper 32 bits
MDA[0..63] 26,28

+VRAM_1.5VS CMDA[30..0] 26
U12 U13
DQMA[7..0] 26,28
+FBA_VREFCA1 M8 E3 MDA38 +FBA_VREFCA1 M8 E3 MDA42
VREFCA DQL0 VREFCA DQL0
1

D +FBA_VREFDQ1 MDA33 +FBA_VREFDQ1 MDA41 D


H1 F7 H1 F7 DQSA[7..0] 26,28
R1190 VREFDQ DQL1 MDA37 VREFDQ DQL1 MDA40
F2 F2
1.1K_0402_1% CMDA9 DQL2 MDA34 CMDA9 DQL2 MDA44
N3 F8 N3 F8 DQSA#[7..0] 26,28
VGA@ CMDA11 A0 DQL3 MDA36 CMDA11 A0 DQL3 MDA45
P7
A1 DQL4
H3 Group4 P7
A1 DQL4
H3 Group5
CMDA8 P3 H8 MDA35 CMDA8 P3 H8 MDA47
2

+FBA_VREFCA1 CMDA25 A2 DQL5 MDA39 CMDA25 A2 DQL5 MDA43


N2 G2 N2 G2
CMDA10 A3 DQL6 MDA32 CMDA10 A3 DQL6 MDA46
P8 H7 P8 H7
A4 DQL7 A4 DQL7
1

1 CMDA24 P2 CMDA24 P2
R1192 C1274 CMDA22 A5 CMDA22 A5
R8 R8
1.1K_0402_1% 0.01U_0402_25V7K CMDA7 A6 MDA57 CMDA7 A6 MDA51
R2 D7 R2 D7
VGA@ VGA@ CMDA21 A7 DQU0 MDA62 CMDA21 A7 DQU0 MDA53
T8 C3 T8 C3
2 CMDA6 A8 DQU1 MDA56 CMDA6 A8 DQU1 MDA48
R3 C8 R3 C8
2

CMDA29 A9 DQU2 MDA63 CMDA29 A9 DQU2 MDA54


L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
CMDA23 R7 A7 MDA58 Group7 CMDA23 R7 A7 MDA49 Group6
CMDA28 A11 DQU4 MDA61 CMDA28 A11 DQU4 MDA55
N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDA20 T3 B8 MDA59 CMDA20 T3 B8 MDA50
CMDA4 A13 DQU6 MDA60 CMDA4 A13 DQU6 MDA52
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDA14 M7 CMDA14 M7
+VRAM_1.5VS A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS

CMDA12 M2 B2 CMDA12 M2 B2
BA0 VDD BA0 VDD
1

CMDA27 N8 D9 CMDA27 N8 D9
R1191 CMDA26 BA1 VDD CMDA26 BA1 VDD
M3 G7 M3 G7 U12 U13
1.1K_0402_1% BA2 VDD BA2 VDD
VDD K2 VDD K2
VGA@ K8 K8
VDD VDD
N1 N1
2

+FBA_VREFDQ1 CLKA1 VDD R1200 CLKA1 VDD


26 CLKA1 J7 CK VDD N9 J7 CK VDD N9
CLKA1# K7 R1 10K_0402_5% CLKA1# K7 R1
26 CLKA1# CK VDD CK VDD
1

1 CMDA19 K9 R9 1 VGA@ 2 CMDA19 K9 R9 K4W1G1646G-BC11 K4W1G1646G-BC11


R1197 C1275 CKE/CKE0 VDD CKE/CKE0 VDD
X76_SAM512M@ X76_SAM512M@
1.1K_0402_1% 0.01U_0402_25V7K
VGA@ VGA@ CMDA18 K1 A1 1 2 CMDA18 K1 A1 U12 U13
C 2 CMDA16 ODT/ODT0 VDDQ R1199 CMDA16 ODT/ODT0 VDDQ C
L2 A8 L2 A8
2

CMDA30 CS/CS0 VDDQ 10K_0402_5% CMDA30 CS/CS0 VDDQ


J3 RAS VDDQ C1 J3 RAS VDDQ C1
CMDA15 K3 C9 VGA@ CMDA15 K3 C9
CMDA13 CAS VDDQ CMDA13 CAS VDDQ
L3 WE VDDQ D2 L3 WE VDDQ D2
VDDQ E9 VDDQ E9
F1 F1 H5TQ1G63DFR-11C H5TQ1G63DFR-11C
DQSA4 VDDQ DQSA5 VDDQ
26 DQSA4 F3 H2 26 DQSA5 F3 H2 X76_HYN512M@ X76_HYN512M@
DQSA7 DQSL VDDQ DQSA6 DQSL VDDQ
26 DQSA7 C7 H9 26 DQSA6 C7 H9
DQSU VDDQ DQSU VDDQ
U12 U13

DQMA4 E7 A9 DQMA5 E7 A9
26 DQMA4 DML VSS 26 DQMA5 DML VSS
DQMA7 D3 B3 DQMA6 D3 B3
26 DQMA7 DMU VSS 26 DQMA6 DMU VSS
E1 E1
VSS VSS
G8 G8
DQSA#4 VSS DQSA#5 VSS
26 DQSA#4 G3 J2 26 DQSA#5 G3 J2 K4W2G1646C-HC11 K4W2G1646C-HC11
DQSA#7 DQSL VSS DQSA#6 DQSL VSS
26 DQSA#7 B7 J8 26 DQSA#6 B7 J8 X76_SAM1G@ X76_SAM1G@
DQSU VSS DQSU VSS
M1 M1
VSS VSS
M9 M9 U12 U13
VSS VSS
P1 P1
CMDA5 VSS CMDA5 VSS
T2 RESET VSS
P9 T2 RESET VSS
P9
T1 T1
VSS VSS
L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
H5TQ2G63BFR-11C H5TQ2G63BFR-11C
1

1
J1 B1 J1 B1 X76_HYN1G@ X76_HYN1G@
R1196 NC/ODT1 VSSQ R1198 NC/ODT1 VSSQ
L1 NC/CS1 VSSQ
B9 L1 NC/CS1 VSSQ
B9
243_0402_1% J9 D1 243_0402_1% J9 D1
VGA@ NC/CE1 VSSQ VGA@ NC/CE1 VSSQ
L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
E8 E8
VSSQ VSSQ
F9 F9
VSSQ VSSQ
G1 G1
B VSSQ VSSQ B
64Mx16 VSSQ
G9 64Mx16 VSSQ
G9

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96
X76@ X76@
+VRAM_1.5VS +VRAM_1.5VS

CLKA1
1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
VGA@ 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1

VGA@

C1277

VGA@

C1278

VGA@

C1279

VGA@

C1280

1 2 80.6_0402_1%
VGA@

C1281

VGA@

C1282

VGA@

C1283

VGA@

C1284

VGA@

C1285

VGA@

C1286

VGA@

C1287

VGA@

C1288

VGA@

C1289

VGA@

C1290
R1194 R1193
160_0402_1% VGA@
@ 80.6_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 2
R1195
2

2
CLKA1# C1276
0.01U_0402_25V7K
@
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDDR5 / Channel A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic1.A
Date: Thursday, June 16, 2011 Sheet 29 of 63

5 4 3 2 1
5 4 3 2 1

+3VS_DGPU
Resistor Values
http://adf.ly/3o8pJ
Pull-up to +3VGS
Physical
Pull-down to Gnd
Strapping pin
Power
Rail
Logical
Strapping Bit3
Logical
Strapping Bit2
Logical
Strapping Bit1
Logical
Strapping Bit0
5K 1000 0000 GS XCLK_417 FB_0_BAR_SIZE
SMB_ALT_ADDR VGA_DEVICE
10K 1001 0001 ROM_SO GV +3VGS FB[1] FB[0]

2
R280 R281 R282 15K 1010 0010 GS SLOT_CLK_CFG
45.3K_0402_1% 34.8K_0402_1% 20K_0402_1% ROM_SCLK +3VGS PCI_DEVID[4] SUB_VENDOR PEX_PLL_EN_TERM
VGA@ @ @ 20K 1011 0011 GV PCI_DEVID[5]

1
D 25K 1100 0100 ROM_SI +3VGS RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0] D
21 STRAP0 STRAP0
21 STRAP1 STRAP1 30K 1101 0101 STRAP0 +3VGS USER[3] USER[2] USER[1] USER[0]
21 STRAP2 STRAP2
35K 1110 0110 STRAP1 +3VGS 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
2

2
45K 1111 0111 STRAP2 +3VGS PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
@ R283 R284 R285
45.3K_0402_1% 4.99K_0402_1% 4.99K_0402_1% STRAP3 +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
VGA@ VGA@
GV@4.99K STRAP4 +3VGS RESERVED RESERVED PCIE_MAX_SPEED DP_PLL_VDD33V
1

1
+3VS_DGPU SUB_VENDOR XCLK_417
0 No VBIOS ROM (Default) 0 277MHz (Default)

2
+3VS_DGPU
R1201
10K_0402_5% 1 BIOS ROM is present 1 Reserved
@

1
21 STRAP4 STRAP4
2

2 FB_0_BAR_SIZE User [3:0]

2
R286 R287 R288
C 4.99K_0402_1% 10K_0402_1% 4.99K_0402_1% R1202 EDID is used C
@ VGA@ VGA@ 20K_0402_5% 0 256MB (Default) 1111
GV@10K GV@4.99K GV@ 1920x1080
1

1
1 Reserved 1000-1100 Customer defined
21 ROM_SI ROM_SI
21 ROM_SO ROM_SO
ROM_SCLK
21 ROM_SCLK +3VS_DGPU 3GIO_PADCFG[3:0] PEX_PLL_EN_TERM
2

0000 RESERVED 0 Disable (Default)


2

2
R289
X76 34.8K_0402_1% R290 R291 R1203
X76@ 10K_0402_1% 15K_0402_1% 15K_0402_1% 0110 Notebook Default 1 Enable
@ @ GV@
1

1
21 STRAP3 STRAP3
SLOT_CLOCK_CFG

2
R1204
15K_0402_5% 0 GPU and MCH don't share a common reference clock
@

1
R289 R289 R289 R289
1 GPU and MCH share a common reference clock (Default)

B B
SMBUS_ALT_ADDR VGA_DEVICE
15K_0402_1% 24.9K_0402_1% 34.8K_0402_1% 45.3K_0402_1%
X76_SAM512M@ X76_HYN512M@ X76_SAM1G@ X76_HYN1G@
0 0x9E (Default) 0 3D Device

1 0x9C (Multi-GPU usage) 1 VGA Device (Default)

GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
PCIE_MAX_SPEED DP_PLL_VDD33V
1 Default 0 Default
K4W1G1646G-BC11 1111 0000 0000 1010 0011 0010 1001 1000
N12P-GV 900 MHz 64M* 16* 4 SA00004GS00 R1221 R1235 R1226 R1642 R1644 R289 R1228 R1229
512MB PU 45K PD 5K PD 5K PU 15K PD 20K PD 15K PU 10K PU 5K GPU Package DeviceID PCI_DEVID[5..0]
H5TQ1G63DFR-11C 1111 0000 0000 1010 0011 0100 1001 1000
N12P-GV 900 MHz 64M* 16* 4 SA000041S20 R1221 R1235 R1226 R1642 R1644 R289 R1228 R1229
512MB PU 45K PD 5K PD 5K PU 15K PD 20K PD 25K PU 10K PU 5K N12P-GS GB2-128 0x0DF4 (..1111 0100)
K4W2G1646C-HC11 1111 0000 0000 1010 0011 0110 1001 1000
N12P-GV 900 MHz 128M* 16* 4 SA000047Q00 R1221 R1235 R1226 R1642 R1644 R289 R1228 R1229
1GB PU 45K PD 5K PD 5K PU 15K PD 20K PD 35K PU 10K PU 5K N12P-GV-B GB2b-128 0x1050 (..0101 0000)
H5TQ2G63BFR-11C 1111 0000 0000 1010 0011 0111 1001 1000
N12P-GV 900 MHz 128M* 16* 4 SA00003YO30 R1221 R1235 R1226 R1642 R1644 R289 R1228 R1229
A 1GB PU 45K PD 5K PD 5K PU 15K PD 20K PD 45K PU 10K PU 5K A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(12/12)-MISC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 30 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ

0804 Vendor suggest close to Cap.


0804 Vendor suggest close to Cap.

UMA_3D@ 1 R8584 2 0_0402_5% HDMI_3TX2-


HDMI_3TX2- HDMI_3TX2+ HDMI_3TX2- 32
VGA_3D@ 1 R693 2 0_0402_5% UMA_3D@ 1 R8585 2 0_0402_5%
D HDMI_3TX2- 32 HDMI_3TX2+ 32 D
VGA_3D@ 1 R698 2 0_0402_5% HDMI_3TX2+
HDMI_3TX2+ 32 HDMI_3TX1-
UMA_3D@ 1 R8586 2 0_0402_5%
HDMI_3TX1- HDMI_3TX1+ HDMI_3TX1- 32
VGA_3D@ 1 R694 2 0_0402_5% UMA_3D@ 1 R8587 2 0_0402_5%
HDMI_3TX1- 32 HDMI_3TX1+ 32
VGA_3D@ 1 R699 2 0_0402_5% HDMI_3TX1+
HDMI_3TX1+ 32 HDMI_3TX0-
UMA_3D@ 1 R8588 2 0_0402_5%
HDMI_3TX0- HDMI_3TX0+ HDMI_3TX0- 32
VGA_3D@ 1 R695 2 0_0402_5% UMA_3D@ 1 R8589 2 0_0402_5%
HDMI_3TX0+ HDMI_3TX0- 32 HDMI_3TX0+ 32
VGA_3D@ 1 R697 2 0_0402_5% HDMI_3TX0+ 32 HDMI_3CLK-
UMA_3D@ 1 R8590 2 0_0402_5%
HDMI_3CLK- 32
VGA_3D@ 1 R696 2 0_0402_5% HDMI_3CLK- UMA_3D@ 1 R8591 2 0_0402_5% HDMI_3CLK+
HDMI_3CLK+ HDMI_3CLK- 32 HDMI_3CLK+ 32
VGA_3D@ 1 R692 2 0_0402_5% HDMI_3CLK+ 32

C497 UMA@2 1 .1U_0402_16V7K PCH_HDMI_C_TXD2- UMA_2D@ R429 1 2 0_0402_5% HDMI_TX2-


15 PCH_HDMI_TXD2-
21 VGA_DVI_ETXD2- C397 VGA@2 1 .1U_0402_16V7K VGA_HDMI_C_TXD2- R621 1VGA_2D@2 0_0402_5% HDMI_TX2- C491 UMA@2 1 .1U_0402_16V7K PCH_HDMI_C_TXD2+ UMA_2D@ R614 1 2 0_0402_5% HDMI_TX2+
15 PCH_HDMI_TXD2+
21 VGA_DVI_ETXD2+ C398 VGA@2 1 .1U_0402_16V7K VGA_HDMI_C_TXD2+ R622 1 VGA_2D@2 0_0402_5% HDMI_TX2+
C495 UMA@2 1 .1U_0402_16V7K PCH_HDMI_C_TXD1- UMA_2D@ R615 1 2 0_0402_5% HDMI_TX1-
VGA_HDMI_C_TXD1- 15 PCH_HDMI_TXD1-
21 VGA_DVI_ETXD1- C399 VGA@2 1 .1U_0402_16V7K R623 1 VGA_2D@2 0_0402_5% HDMI_TX1- C492 UMA@2 1 .1U_0402_16V7K PCH_HDMI_C_TXD1+ UMA_2D@ R616 1 2 0_0402_5% HDMI_TX1+
VGA_HDMI_C_TXD1+ 15 PCH_HDMI_TXD1+
21 VGA_DVI_ETXD1+ C400 VGA@2 1 .1U_0402_16V7K R624 1 VGA_2D@2 0_0402_5% HDMI_TX1+
C494 UMA@2 1 .1U_0402_16V7K PCH_HDMI_C_TXD0- UMA_2D@ R617 1 2 0_0402_5% HDMI_TX0-
VGA_HDM_C_TXD0- 15 PCH_HDMI_TXD0-
21 VGA_DVI_ETXD0- C401 VGA@2 1 .1U_0402_16V7K R625 1 VGA_2D@2 0_0402_5% HDMI_TX0- C493 UMA@2 1 .1U_0402_16V7K PCH_HDMI_C_TXD0+ UMA_2D@ R618 1 2 0_0402_5% HDMI_TX0+
VGA_HDMI_C_TXD0+ 15 PCH_HDMI_TXD0+
21 VGA_DVI_ETXD0+ C402 VGA@2 1 .1U_0402_16V7K R626 1 VGA_2D@2 0_0402_5% HDMI_TX0+
C498 UMA@2 1 .1U_0402_16V7K PCH_HDMI_C_TXC- UMA_2D@ R619 1 2 0_0402_5% HDMI_CLK-
VGA_HDMI_C_TXC- 15 PCH_HDMI_TXC-
21 VGA_DVI_ETXC- C403 VGA@2 1 .1U_0402_16V7K R627 1 VGA_2D@2 0_0402_5% HDMI_CLK- C496 UMA@2 1 .1U_0402_16V7K PCH_HDMI_C_TXC+ UMA_2D@ R620 1 2 0_0402_5% HDMI_CLK+
15 PCH_HDMI_TXC+
21 VGA_DVI_ETXC+ C405 VGA@2 1 .1U_0402_16V7K VGA_HDMI_C_TXC+ R628 1 VGA_2D@2 0_0402_5% HDMI_CLK+

S2 S1
(pin33) (pin32) TMDS/DDC output

C
H H PORT1/SCL1,SDA1 C

H L PORT2/SCL2,SDA2

L H All disconnected

+3VS
1

HDMI_TX0-
HDMI_TX0+ HDMI_SC_D0- 33
R851
HDMI_SC_D0+ 33
HDMI_TX1-
10K_0402_5%
PORT 1 HDMI_TX1+ HDMI_SC_D1-
HDMI_SC_D1+
33
33 To Scaler
@ HDMI_TX2-
(PC-mode)
2

VGA_IFPE_DET HDMI_HPD_SW HDMI_TX2+ HDMI_SC_D2- 33


22,32 VGA_IFPE_DET 1 R421 2 HDMI_HPD_SW 33 HDMI_SC_D2+ 33
0_0402_5% HDMI_CLK-
HDMI_SC_CK- 33
HDMI_CLK+
HDMI_SC_CK+ 33
@
15 PCH_HDMI_DET 1 R422 2
0_0402_5% +3VS
B B
1

R538
20K_0402_5%
@
2

2
6 1 R800 1 2 0_0402_5% VGA_2D@ VGA_HDMI_ECLK_R 21,32
32,33 HDMI_SC_SCL
Q8664A R799 1 2 0_0402_5% UMA_2D@ PCH_HDMI_CLK 15,32
DMN66D0LDW-7_SOT363-6

5
3 4 R794 1 2 0_0402_5% VGA_2D@ VGA_HDMI_EDATA_R 21,32
32,33 HDMI_SC_SDA
Q8664B R793 1 2 0_0402_5% UMA_2D@ PCH_HDMI_DATA 15,32
DMN66D0LDW-7_SOT363-6

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Switch
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 31 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ
0810 Vendor suggest to reserve for EDID debug
+HDMI_EDID_5V
D40
+V_5V 2
1
3
D D
DAN202UT106_SC70-3
@

2
1
R786 R787
C917
4.7K_0402_5% 4.7K_0402_5% 0.1U_0402_10V6K
@ @ U52 2 @

1
@ 8 1
@ VCC A0
7 WP A1 2
31,33 HDMI_SC_SCL R788 1 2 100_0402_5% 6 3
R789 1 SCL A2
31,33 HDMI_SC_SDA 2 100_0402_5% 5 SDA GND 4
@
CAT24C02WI-GT3_SO8
1 1
C915 C916
33P_0402_50V8J 33P_0402_50V8J
@ 2 2 @

C C

12/11 3D Scaler Pin define update


J4
1 2
1 2
36 HDMI_IN_D0+ 3 4 HDMI_IN_CK+ 36
3 4
36 HDMI_IN_D0- 5 6 HDMI_IN_CK- 36
5 6
7 8
7 8
36 HDMI_IN_D1+ 9 10 HDMI_IN_D2+ 36
9 10
36 HDMI_IN_D1- 11 12 HDMI_IN_D2- 36
11 12
13 14
13 14
15 16 +V_3.3V
33,40 I2S_WS 15 16
17 18
33 I2S_SCLK 17 18
19 20
33 I2S_MCLK 19 20
21 22
21 22
31 HDMI_3TX1+ 23 24
23 24 I2S_DATA0 33,40
31 HDMI_3TX1- 25 26 I2S_DATA1
25 26 HP_2932_LEFT 41
27 28 I2S_DATA2
27 28 HP_2932_RIGHT 41
31 HDMI_3TX0+ 29 30
29 30
31 HDMI_3TX0- 31 32 HDMI_3TX2+ 31
31 32
33 34 HDMI_3TX2- 31
33 34
40 AUDIO_3D_RIGHT 35 36
35 36
40 AUDIO_3D_LEFT 37 38 HDMI_3CLK+ 31
37 38
39 40 HDMI_3CLK- 31
39 40
45 AIN_TAS_R 41 42
41 42
45 AIN_TAS_L 43 44
43 44 S_BKOFF 33,34,43
45 46
45 46
22,31 VGA_IFPE_DET 47 48
47 48
49 50 3D_PWREN 43
B 49 50 B
33,36 CVBS_L 51 52 HDMI_IN_SDATA 36
51 52
33,36 VIN0N# 53 54 HDMI_IN_SCLK 36
53 54
33,43 LSADC0 55 56 HDMI_IN_HPD 36
55 56
33,43 LSADC1 57 58
57 58
59 60 LSADC2 33,43
59 60
61 62 LSADC3 33,43
15,33,43 UART_TX 61 62
63 64
15,33,43 UART_RX 63 64
65 66
VGA_HDMI_ECLK 65 66 BL_PWM 33,34
67 68
VGA_HDMI_EDATA 67 68 TV_ON_OFF 43
69 70
69 70 HDMI_SYNC_DET 33,43
71 72 MUTE_CODEC 33,39
UMA_3D@ 71 72
73 74 CVBS_SYNC_DET 33,36,43
R8592 1 VGA_HDMI_ECLK 73 74
15,31 PCH_HDMI_CLK 2 0_0402_5% +12V1 75
75 76
76 PANEL_STATE_OFF 33,43
77 78 +V_5V
R8593 1 VGA_HDMI_EDATA 77 78
15,31 PCH_HDMI_DATA 2 0_0402_5% 79 80
79 80
UMA_3D@
81 82
GND GND

ACES_88079-0800A1
CONN@
VGA_3D@
21,31 VGA_HDMI_ECLK_R R939 1 2 0_0402_5% VGA_HDMI_ECLK 12/6 Change symbol of J4 from LTCX002TM00 to SP010011B00(60pin to 80pin)
R940 1 2 0_0402_5% VGA_HDMI_EDATA
21,31 VGA_HDMI_EDATA_R
VGA_3D@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3D Scalar
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 32 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ

120P_0402_50V8

56P_0402_50V8
+1.3VALW +1.3V_SCA_L +3V_SCA_L +3V_SCA_VB +1.3V_SCA_YPP 2D@ +3V_SCL 1 R457 2
+1.3V_SCA_L +3V TO +1.3VALW 1 1 0_0603_5%
+V_3.3V

C908

C907
L51 L52 Pre-MP Scaler power soft start 1
1 R759 2 0_0603_5% 2D@ R297 1 R545 2 +3VSB

10U_0805_10V6K
2D@ FBMA-L11-160808-221LMT 0603 C411 10K_0402_5% 0_0603_5%

10U_0805_10V6K
FBMA-L11-160808-221LMT 0603 2 2

1U_0402_6.3V6K

0.1U_0402_16V4Z
2D@ 1 1 1 0.1U_0402_16V4Z 2D@ @

3
2D@ 2
S

C421

1U_0402_6.3V6K
C423 1 1 1 FBMA-L11-160808-221LMT 0603 2D@

2
+3V_SCA_DELAY +3V_SCA_L 1 2D@ 2
G

C422

C413
2D@ 2 9/29 Add R457/R545
+3V_SCA_PLL +1.3V_SCA_D 43 SCALER_ON#

C412
@ 0.1U_0402_16V4Z C870 2D@ L48 R298 100_0402_1%
2 2 2
1 R760 2 0_0603_5% 2D@ 2D@ Q11
2 2 2 +1.3VALW

0.1U_0402_16V4Z
2D@ SI2305CDS-T1-GE3 1P SOT23-3

56P_0402_50V8
10U_0805_10V6K
+3V_SCA_D

220U_6.3V_M

1U_0402_6.3V6K
D
1 2D@

1
+3V_SCA_L 2D@ +3V_SCA_VD 2D@ 1 1 1 1 1
+3V_SCA_VD +3V_SCA_L

C906

C873

C417

C871

C905
+

2
+1.3V_SCA_D +3V_SCA

C416
D D
L49
+3V_SCA_VD R301 U22
2 @ 2 2 2 2 2
10U_0805_10V6K
+1.3V_SCA_YPP 30_0402_1% 1 8
FBMA-L11-160808-221LMT 0603

1U_0402_6.3V6K
2D@ +3V_SCA_VB 2D@ 2D@ SHDN GND
1 1 1 1 1 1 2 7
+3V_SCA_IF IN GND
C433

C435 120P_0402_50V8 2D@ 2D@ 2D@ 3 6

1
OUT GND
C434
2D@ C910 C909 2D@ C414 4 5
@ 0.1U_0402_16V4Z 2D@ 56P_0402_50V8 +3V_SCA_TMDS 2D@ SET GND
1

2
2 2 2 2 2 2D@ 1U_0603_10V6K 2 G9141P11U_SO8
2D@ 120P_0402_50V8 R302 C415 2D@
2D@ 1U_0805_25V7K
100_0402_1% @ 2

1
0809 EMI suggest 10/30 Change U22 to SOP8 package

115

125

128

111
+3V_SCA_L +3V_SCA_TMDS 10/30 Mount R301=30 ohm;R302=100 ohm

18

20

47

52

59

63

64

75

86

87
2
0.1U_0402_16V4Z

L50 U23
+3V_SCA_TMDS +3V_SCA_L +3V_SCA_D

V3.3IO
V3.3BB1

V3.3BB0

V3.3PLL

V3.3APLL
V1.2CORE

V3.3LVDS

V12CORE

V1.2TMDS

V3.3TMDS

V12CORE
V1.2YPPADC

V3.3VDADC

V3.3VDAC

V3.3IFADC
10U_0805_10V6K

+3V_SCA_PLL
1U_0402_6.3V6K

FBMA-L11-160808-221LMT 0603 FBMA-L11-160808-221LMT 0603


2D@ 1 1 1 L53 L54
C418

C420

C885 2D@ 1 2 0.1U_0402_16V4Z 3 +3V_SCA_PLL 2D@ 2D@ 2D@


BIN1N

120P_0402_50V8

56P_0402_50V8
C419

1U_0402_6.3V6K

0.1U_0402_16V4Z
C886 2D@ 1 2 0.1U_0402_16V4Z 4 102 2D@ FBMA-L11-160808-221LMT 0603
BIN1P SPDIFO I2S_MCLK 32

1U_0402_6.3V6K
@ C887 2D@ 1 2 0.1U_0402_16V4Z 5 101 1 1 1 1
GIN1N SPDIFI I2S_DATA0 32,40

1
2 2 2

C428

C912

C911
C888 2D@ 1 2 0.1U_0402_16V4Z 6 100 I2S_DATA1
2D@ GIN1P I2C_S_SDA I2S_DATA1

C427
C889 2D@ 1 2 0.1U_0402_16V4Z 7 99 I2S_DATA2 1 1 C426
RIN1N I2C_S_SCL I2S_DATA2

1
C890 2D@ 1 2 0.1U_0402_16V4Z 8 98 C431 4.7U_0805_10V6K

2
RIN1P I2C_M0_SDA POWER_KEY 43 2 2 2 2

C430
2D@ +3V_SCA_VD 9 97 C429 2D@ 2D@
C877 2D@ 0.1U_0603_25V7K V3.3YPPADC I2C_M0_SCL S_MUTE# 40 4.7U_0805_10V6K 0.1U_0402_16V4Z
1 2 10 96

2
C862 2D@ 0.1U_0603_25V7K AIN_5R IRRX BL_PWM ENVDD 34 2D@ 2 2 2D@
1 2 11 AIN_5L RF_AGC 95
C891 2D@ 0.1U_0402_16V4Z SCA_RESET BL_PWM 32,34 2D@
1 2 12 94
+3V_SCA_L BIN0N RESET 2D@
C892 2D@ 1 2 0.1U_0402_16V4Z 13 BIN0P TCON13 93
S_BKOFF 32,34,43
0809 EMI suggest
330NH_SWI0805F-R33K_10% +3V_SCA_IF C893 2D@ 1 2 0.1U_0402_16V4Z 14 92
GIN0N LSADC3 LSADC3 32,43
1 2 C894 2D@ 1 2 0.1U_0402_16V4Z 15 91
GIN0P LSADC2 LSADC2 32,43
L47 C895 2D@ 1 2 0.1U_0402_16V4Z 16 90
4.7U_0805_10V6K

C RIN0N LSADC1 LSADC1 32,43 C


2D@ 1 C896 2D@ 1 2 0.1U_0402_16V4Z 17 89
RIN0P LSADC0 LSADC0 32,43
1

1U_0402_6.3V6K 88 1 2D@ 2 C781 +V_3.3V


C858 C859 UART_RX LSADC_REF 10K_0402_1%
107 DDC0_SDA
1 2
2D@ 2D@ 15,32,43 UART_RX UART_TX R708
108 Close to Scaler
2

2 15,32,43 UART_TX DDC0_SCL 1U_0402_6.3V6K


31,32 HDMI_SC_SDA 109 DDC1_SDA TEAN 85
TXE0- 34 +3V_SCA 10K_0402_5%
IF_GND

31,32 HDMI_SC_SCL 110 DDC1_SCL TEAP 84


TXE0+ 34 SCA_RESET
I2S signal to TAS3208 TEBN 83 1 R334 2 2D@
TXE1- 34 10K_0402_5%
112 82
32,40 I2S_WS GPIOA5 TEBP TXE1+ 34 SPI_SC_MOSI
32 I2S_SCLK
113
GPIOA6 TECN
81
TXE2- 34 1 R305 2 2D@

1
114 80
2D@ CEC TECP TXE2+ 34 +1.3VALW
+3V_SCA_TMDS 1 R318 2 TECLKN
79 R710 10K_0402_5%
27K_0402_5% TXEC- 34 20K_0402_5% SI2305CDS-T1-GE3 1P SOT23-3 SPI_SC_SCK
116 31 HDMI_SC_CK- 78 1 R306 2 2D@
RXCN TECLKP TXEC+ 34 2D@
117 31 HDMI_SC_CK+ 77
RXCP TEDN TXE3- 34

3
S
+V_3.3V 118 76 10K_0402_5%

2
31 HDMI_SC_D0- RX0N TEDP TXE3+ 34 G
BL_PWM
119 31 HDMI_SC_D0+ 2 1 R308 2 2D@
RX0P

1
120 31 HDMI_SC_D1- 74
10K_0402_5% RX1N TOAN TXO0- 34 2D@ Q50 10K_0402_5%
121 31 HDMI_SC_D1+ 73
UART_TX RX1P TOAP TXO0+ 34 HDMI_SW_EC
1 R757 2 122 72 R709 2D@ 1 R852 2
123
31 HDMI_SC_D2- RX2N RTD2667/LQFP128 TOBN
71
TXO1- 34 10K_0402_5%
D
@

1
31 HDMI_SC_D2+ RX2P TOBP TXO1+ 34

1
10K_0402_5% 1 2D@ 2 124 70 C
+3V_SCA_DELAY

2
UART_RX REXT TOCN TXO2- 34
1 R758 2 2D@R707 6.2K_0402_1% 69 2 Q51
TOCP TXO2+ 34

2
C863 1 2 0.1U_0603_25V7K126 68 B 2D@
10K_0402_5% HSYNCVIN TOCLKN TXOC- 34 E MMBT3904_SOT23-3
1 2 0.1U_0603_25V7K127 67 1 R309

3
HP_PLUG# VSYNCVIN TOCLKP TXOC+ 34
1 R763 2 C878 2D@
TODN
66
TXO3- 34
C872 10K_0402_5% @
32,36,43 CVBS_SYNC_DET CVBS_SYNC_DET 39 65 1U_0402_6.3V6K
@ 10K_0402_5% CVBS_L_R VIN10P TODP TXO3+ 34 2D@ SPI_SC_CS
40

1 1
VIN01P 2
1 R772 2 I2S_DATA2 32,43 PANEL_STATE_OFF 41
VIN11P
VIN0N 42 106 SPI_SC_CS 0804 Vendor suggest delay circuit.
@ 10K_0402_5% C902 2D@ 1 VIN0N SPI_CS# SPI_SC_SCK
2 0.1U_0603_25V7K
43
VIN02P SPI_SCK
105 (3ms more)
1 R773 2 I2S_DATA1 44 104 SPI_SC_MISO 10K_0402_5%
32,39 MUTE_CODEC VIN12P SPI_DI
1 2 0.1U_0603_25V7K 45 103 SPI_SC_MOSI R310
4.7K_0402_5% 2D@ C861 VIN1N SPI_DO HDMI_SYNC_DET 2D@
46 38

2
B VIN03P VIN00P HDMI_SYNC_DET 32,43 +V_3.3V B
2 R790 1CVBS_SYNC_DET C901 2D@ 1 2 0.1U_0603_25V7K 36 AIN_R
@ AIN_1R +V_3.3V
35 AIN_L
4.7K_0402_5% AIN_1L
36 HDMI_IN_HPD_SC 48
RGBSW0
2 R791 1HDMI_SYNC_DET 39,41,43 HP_PLUG#
HP_PLUG# 49
AIN_2L

1
@ 50 33 C576 1 2 @ 47U_1206_6.3V6M 0.1U_0402_10V6K
4.7K_0402_5% 31 HDMI_HPD_SW R886 0_0402_5% RGBSW1 HPOUT_L C577 1 HP_SCA_LEFT 41
22 VGA_ENBKL 1 2 51
AIN_2R HPOUT_R
32 2 @ 47U_1206_6.3V6M
HP_SCA_RIGHT 41

1
2 R792 1MUTE_CODEC 2D@ 31 C866 1 2 2D@ 0.1U_0603_25V7K R312 1
@ R748 1 2D@ 2 75_0402_5% AIN_3L C867 1
53
AVOUT1 AIN_3R
30 2 2D@ 0.1U_0603_25V7K 10K_0402_5% 2D@
4.7K_0402_5% R749 1 2D@ 2 75_0402_5% 54 29 HDMI_SWOFF_EC 2D@ R313 C424
HDMI_SWOFF_EC

2
AVOUT2 AIO_2L
2 R802 1HDMI_SC_SDA 28 HDMI_SW_EC
HDMI_SW_EC
2D@ 10K_0402_5% 2D@
@ AIO_2R 0_0402_5% U24 2
27

2
4.7K_0402_5% C864 2D@ 1 AIO_1L SPI_SC_CS
2 1U_0402_6.3V6K 57 26 1 R314 2 1 8
IF1N AIO_1R CS# VCC
2 R796 1HDMI_SC_SCL C865 2D@ 1 2 1U_0402_6.3V6K 58
IF1P AOUT_L
25 SPI_SC_MISO 1 R315 2 2 7
DO(IO1) HOLD#(IO3)
47_0402_5%
AMP_SCA_LEFT 40
@ 24 0_0402_5% 3 6 R316 1 2D@ 2 SPI_SC_SCK
AOUT_R C868 2D@ AMP_SCA_RIGHT 40 2D@ WP#(IO2) CLK SPI_SC_MOSI
23 4 5 R317 1 2
G3.3VDADC

AIN_MONO GND DI(IO0)


G3.3IFADC
G3.3VDAC

XI_SC 61 22 1 2 1U_0402_6.3V6K 0_0402_5%


G3.3APLL

XIN AOUT_MONO
G3.3BB1

G3.3BB0

G3.3PLL

XO_SC 62 21 1 2 W25X40BVSNIG SOIC 8P 2D@


XOUT VCM_BB
EPAD

2D@
L41 C869 0.1U_0402_16V4Z
CVBS_L 1 2 2D@ Close to Scaler
1UH_CBC2012T1R0M_20% 2D@ 10/29 Change value of C425/C432 from 22pF to 15pF
1

19

34

37

55

56

60

129

2D@ 1 0804 Vendor suggest close to scaler


2D@
C853 +3V_SCA_L C425
FBM-11-160808-601-T_0603

FBM-11-160808-601-T_0603

330P_0402_50V7K L42 2D@ C856 2 1 XO_SC


2 10K_0402_5% 2 2D@ 1 @
IF_GND

36,45 AIN_IO_L 1 2 1 2 AIN_L

1
2 R307 1 S_MUTE# 4.99K_0402_1% 0_0402_5% R704 15P_0402_50V8J
2

1
2D@ 4.99K_0402_1% 4.7U_0603_6.3V6K 2D@ @
2D@ L43 C857 R323 Y3
1UH_CBC2012T1R0M_20% L45 2D@ 1 2 1 2 2D@ 1 @ 2 1M_0402_5% 27MHZ_12PF_X5H027000IC1H-H
C851 36,45 AIN_IO_R AIN_R
470P_0402_50V8J

470P_0402_50V8J

L40 L55 L44 L46 1 1 2D@ 0_0402_5% R706 2D@

2
2

1
FBM-11-160808-601-T_0603

CVBS_L 1 R700 2 1 2 1 2 CVBS_L_R 2D@ 2D@ C854 4.7U_0603_6.3V6K C432


32,36 CVBS_L
2

FBM-11-160808-601-T_0603

A 0_0402_5% 2D@ C855 XI_SC A


2 1
1

2D@ 1 0.047U_0402_25V8K D36 2D@ 2D@ R328 R326


1

2D@ 2 2 10K_0402_5% 10K_0402_5% 15P_0402_50V8J


SM05_SOT23
R702 C850 @ 2D@ 2D@ 2D@
2

75_0402_5% 270P_0402_50V7K
1

@ 2 2D@
1
2

C852
1 R701 2 VIN0N# 1 2 VIN0N Security Classification Compal Secret Data Compal Electronics, Inc.
0_0402_5% Issued Date 2010/07/20 2011/07/20 Title
@ 0.047U_0402_25V8K
Deciphered Date
2D@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Scalar
0804 Vendor suggest close to scaler Size Document Number Rev
32,36 VIN0N# AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 33 of 63
5 4 3 2 1
A B C D E

WebCam+Digital Mic http://adf.ly/3o8pJ 1


R330
2
0_0402_5%
WCM-2012-900T_0805 JCAM1
USB20_P5 4 4 USB20_P5_R
14 USB20_P5 3 3 USB20_N5_R
1 1
5/18 Change R332 from 100K to 10K ohm R331 1 CAM_PWR
2 2
2 0_0402_5% 3 3
+3VS USB20_N5 1 R965 2 0_0402_5%
135mA 14 USB20_N5
1 1 2 2 4 4
5
40 mils L15 @ L68 INT_MIC 6
5
DMIC_DATA_R 6
1 2 39 DMIC_DATA 1 2 7 7 GND 9

D
3 1 CAM_PWR R333 0_0402_5% FBMA-10-100505-301T_2P DMIC_CLK_R 8 10
8 GND

0.1U_0402_16V4Z
L69 1 2
39 DMIC_CLK

2
R332 2 @ 1 FBMA-10-100505-301T_2P ACES_87213-0800N

C443
1 @ Q12 C444 CONN@ 1

G
2
10K_0402_5% AO3413_SOT23-3 11/30 Del R969/R970
10U_0603_6.3V6M 10/27 Add D49(ESD request) 11/30 Add L68/L69=SM01000CY00
R335 1 2 D49

1
1 @ 2 0_0402_5% 2 DMIC_DATA_R +3VS
12 CAM_OFF
1 11/28 Change symbol of JCAM1 from
1 R942 2 0_0402_5% 3 DMIC_CLK_R
43 EC_CAM_OFF SP02000RQ00 to SP02000S300

2
@
R437
PESD5V0U2BT_SOT23-3 10K_0402_5%
<ESD> @

1
R797 INT_MIC
MIC_INT_VREFO 1 2 1 R810 2 R703 1 2 1K_0402_5% INT_MIC_RIGHT 39
0_0402_5% 2.2K_0402_5%

D41

1
1 2
R809 R742 1
C453 27K_0402_5% 0_0402_5% 3
0.1U_0402_16V4Z @
@ 2

2
PESD5V0U2BT_SOT23-3
<EMI>
R705 1 2 1K_0402_5% INT_MIC_LEFT 39

2
LVDS CONN +V_5V
1150mA 2

JLVDS1
LVDS POWER +LCDVDD +5VSB

33 TXO0+ 2 2 1 1 TXO0- 33 1

2
33 TXO1+ 4 4 3 3 TXO1- 33
6 5 R336 R337 C446
33 TXO2+ 6 5 TXO2- 33 4.7U_0805_10V4Z
8 7 220_0402_5% 390K_0402_5%
33 TXOC- 8 7 2
10 9 2D@ 2D@ 2D@
33 TXO3- 10 9 TXOC+ 33
12 11

6 2

1
33 TXE0- 12 11 TXO3+ 33
14 13 TXE0+ 33
14 13
33 TXE1+ 16
16 15
15 TXE1- 33 120mil
18 17 Q13A
33 TXE2- 18 17

3
20 19 DMN66D0LDW-7_SOT363-6 R339
33 TXEC- 20 19 TXE2+ 33
22 21 2D@ 2 1 2 2 Q14
33 TXE3- 22 21 TXEC+ 33
24 23 1M_0402_5%
+LCDVDD 24 23 TXE3+ 33
26 25 11/4 Change PN of Q13 from SB570025280 to 2D@ 1 SI2305CDS-T1-GE3_SOT23-3

1
26 25

3
+LCDVDD 28 27 SB00000DH00 2D@
28 27 C447
30 29 +LCDVDD

1
30 29 @
1 2
3300P_0402_50V7-K 120mil 1150mA
1 1 C448 32 31 2 1 5 2D@ +LCDVDD
GND GND 22 VGA_ENVDD
2D@ R419 0_0402_5% Q13B

2
C451 C452 680P_0402_50V7K ACES_87242-3001-09 DMN66D0LDW-7_SOT363-6

4
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 CONN@ 2D@ 1 2D@
33 ENVDD 2 1 1
2D@ 2 2 2D@ R420 0_0402_5% R341
2D@ C449 C450
2 @ 1 4.7U_0805_10V4Z 0.1U_0402_16V4Z

1
43 EC_ENVDD 2 2 2D@
R881 0_0402_5% 47K_0402_5% 2D@

3
INVERTER 3

950mA +12V2 INVPWR_B+


ENVDD: scalar->EC-> inverter L17
INVT_PWM: scalar-> inverter 1
1 2
FBMA-L11-201209-221LMA30T_0805

1
BKOFF#: scalar->EC-> inverter 10/20 C456 C457

680P_0402_50V7K 680P_0402_50V7K

2
2

PVT change from alw to vs for EUP.


Touch Panel @ 0_0402_5% @ 2 R747 JINV1
D11 100mA 22 VGA_BL_PWM 1
INVPWR_B+ 1
USB20_P4_R 0_0402_5% @ 1
+5VS 4
VIN IO1
2 +5VS 1 2 43 INVT_PWM 1 2 R352 2
2
C458 0.1U_0402_16V4Z 3
USB20_N4_R 3
3 1 4
IO2 GND 4
5
PRTR5V0U2X_SOT143-4 @ 1 0_0402_5% BL_PWM_R 5
2 32,33 BL_PWM 1 2 R351 6
C459 1U_0603_10V6K 6
7
0_0402_5% S_BKOFF_R 7
32,33,43 S_BKOFF 1 2 R353 8
8
9
9

1
0_0402_5% 1 @ 2 R598 10
43 BKOFF# 10
JTOUCH R354 11
4.7K_0402_5% 11
1 1 12
USB20_N4 0_0402_5% USB20_N4_R 1 12
1 2 R345 2
14 USB20_N4 USB20_P4 0_0402_5% USB20_P4_R 2
1 2 R346 3 C499

2
4 14 USB20_P4 3 4
4 4 13 GND1
5 2 14
5 680P_0402_50V7K GND2
6 GND
7 ACES_87213-1200G
Shield GND GND CONN@
ACES_87213-0500G_5P
CONN@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN. / WebCam
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic1.A
Date: Thursday, June 16, 2011 Sheet 34 of 63
A B C D E
A B C D E F G H

HDD POWER Conn http://adf.ly/3o8pJ


+12VS 8/18 Add C918~C921 HDD SATA HDD Conn.
1 1
C920 C918 JHDD1
0.1U_0402_16V4Z 10U_0805_25V_K +12VS
2 2 1
C470 1 SATA_PTX_C_DRX_P0 GND
12 SATA_PTX_DRX_P0 2 0.01U_0402_16V7K 2
A+
C471 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3
1 12 SATA_PTX_DRX_N0 A- 1
4
JWAF1 C469 1 SATA_DTX_PRX_N0 GND
2 0.01U_0402_16V7K 5
B-
1 12 SATA_DTX_C_PRX_N0 C472 1 2 0.01U_0402_16V7K SATA_DTX_PRX_P0 6
+5VS 1 12 SATA_DTX_C_PRX_P0 B+
+5VS 2 7 8
2 GND GND
3 9
3 GND
4
4 TYCO_4-1775058-8
1 1 5
GND CONN@
6
C921 C919 GND
0.1U_0402_16V4Z 10U_0805_6.3V6M ACES_88290-044G
2 2 CONN@

12/6 Change footprint of JWAF1 from SP02000AO00 to SP02000EB00

Layout Note:Place C918/C919/C920/C921 close to JWAFER1

ODD POWER Conn


+12VS 10/29 Add C930/C931
ODD SATA ODD Conn.
+12VS
1 1
JODD1
2 C930 C931 2
0.1U_0402_16V4Z 10U_0805_25V_K 1
2 2 JWAF2 SATA_PTX_DRX_P1 C461 1 SATA_PTX_C_DRX_P1 GND
12 SATA_PTX_DRX_P1 2 0.01U_0402_16V7K 2
SATA_PTX_DRX_N1 C462 1 SATA_PTX_C_DRX_N1 A+
1 1 12 SATA_PTX_DRX_N1 2 0.01U_0402_16V7K 3 A-
+5VS 2 2 4 GND
3 SATA_DTX_C_PRX_N1 C463 1 2 0.01U_0402_16V7K SATA_DTX_PRX_N1 5
3 12 SATA_DTX_C_PRX_N1 SATA_DTX_C_PRX_P1 C464 1 SATA_DTX_PRX_P1 B-
4 4 2 0.01U_0402_16V7K 6 B+
+5VS 5 12 SATA_DTX_C_PRX_P1 7 8
GND GND GND
6 9
GND GND
1 1 ACES_88290-044G TYCO_4-1775058-5
CONN@ CONN@
C928 C929
0.1U_0402_16V4Z 10U_0805_6.3V6M
2 2
12/6 Change footprint of JWAF1 from SP02000AO00 to SP02000EB00

10/28 Add C928/C929


Layout Note:Place C928/C929 close to JWAFER2

3 3

SSD

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
HDD & ODD & SSD Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 35 of 63
A B C D E F G H
5 4 3 2 1

http://adf.ly/3o8pJ
+V_3.3V 10/22 Add(EMI Request)
+5VSB
+V_5V

1
+USB_VCCB
U37 ACES_88389-1C01-BS
1 8 R439 1 1
GND OUT 100K_0402_5%
2 7 +5VALW 120 119 +5VALW
IN OUT C829 C830 120 119
3 6 118 117

2
IN OUT 82P_0402_50V8J 82P_0402_50V8J 118 117
1 4 5 1 2 USB_OC#1 14 +HDMI_5V_IN 116 115
EN# OC# R440 <EMI> 2 2 <EMI> 116 115
114 113 LAN_MIDI0- 38
C648 APL3510BXI-TRG MSOP8 10K_0402_5% 114 113
+HDMI_5V_OUT 112 111 LAN_MIDI0+ 38
4.7U_0603_6.3V6K 112 111
1 110 109
2 110 109
12/9 Add +1.5V 108
108 107
107 LAN_MIDI1- 38
C649 R498 1 2 0_0402_5% 106 105
+USB_VCCB
0.1U_0402_16V4Z
L31/L35/R498/R520/R553/R554(near 106 105 LAN_MIDI1+ 38
104 103
2 J6) 104 103
1 WCM-2012-900T_4P 102 101

330U_6.3V_M_R14
44,47 SYSON# 102 101 LAN_MIDI2- 38
D 1 14 PCIE_PTX_DRX_N6 4 3 43,46 BT_RESET 100 99 LAN_MIDI2+ 38 D
+ 4 3 100 99

C644
C645 PCIE_PTX_DRX_N6_1 13,22,37,42 PLT_RST# 98 97
@ PCIE_PTX_DRX_P6_1 98 97
96 95 LAN_MIDI3- 38
470P_0402_50V7K @1 96 95
14 PCIE_PTX_DRX_P6 2 43 PS2_CLK 94 93 LAN_MIDI3+ 38
2 2 1 <EMI> 2 94 93
11/2 Change PN of C644 from SF000002Y00 to 43 PS2_DATA 92
92 91
91
L31 90 89 PCIE_DTX_C_PRX_P6_1
SF000001G00 PCIE_PTX_DRX_P6_1 90 89 PCIE_DTX_C_PRX_N6_1
1 2 88 87
R520 0_0402_5% PCIE_PTX_DRX_N6_1 88 87
86 85
86 85
84 83
+HDMI_EDID_5V R553 1 84 83 USB20_N9 14
2 0_0402_5% 82 81
14 USB20_N8 82 81 USB20_P9 14
80 79
+HDMI_EDID_5V 14 USB20_P8 80 79
WCM-2012-900T_4P 78 77
D34 78 77 USB20_N2 14
14 PCIE_DTX_C_PRX_N6 4 3 38 LOM_SPD1000LED_ORG# 76 75
4 3 76 75

2
+3V_SCA_L PCIE_DTX_C_PRX_N6_1 +5VALW 2 74 73 USB20_P2 14
1 13,38,42 PCH_PCIE_WAKE# 74 73
R293 PCIE_DTX_C_PRX_P6_1 1 72 71
@1 72 71 USB20_N3 14
1K_0402_1% C408 2 3 PCH_SMIBMI 70 69
14 PCIE_DTX_C_PRX_P6 1 <EMI> 2 70 69 USB20_P3 14
0.1U_0402_16V4Z 43,47,55 SYSON 68 67
68 67
1

1
2 L35 DAN202UT106_SC-70 66 65 HDMI_CTXC+

1
R630 R647 66 65 HDMI_CTXC-
1 2 64 63
R712 HDMI_IN_HPD R554 0_0402_5% 4.7K_0402_5% 4.7K_0402_5% 64 63
62 61
100K_0402_5% 62 61 HDMI_CTXD2+
60 59
60 59 HDMI_CTXD2-
58 57
2

2
58 57
1

C 12/9 Add R555 1 2 0_0402_5% CLK_USB30_1 56 55


56 55
33 HDMI_IN_HPD_SC 1 R711 2 2 Q52
L36/R555/R556(near J3) CLK_USB30#_1 54 53 HDMI_CTXD1+
B MMBT3904_SOT23-3 54 53 HDMI_CTXD1-
WCM-2012-900T_4P 52 51
1K_0402_1% E 52 51
4 3 50 49
3

17 CLK_USB30# 4 3 50 49
CLK_USB30#_1 HDMI_OUT_DET 48 47 HDMI_CTXD0+
CLK_USB30_1 48 47 HDMI_CTXD0-
43 HDMI_CABLE_DET 46 45
@1 46 45
17 CLK_USB30 2 44 43
1 <EMI> 2 44 43
0804 Vendor suggest. L36
42
40
42 41
41
39
HDMI_IN_D0+ 32
32 HDMI_IN_HPD 40 39 HDMI_IN_D0- 32
1 2 32 HDMI_IN_SDATA 38 37
R556 0_0402_5% 38 37
32 HDMI_IN_SCLK 36 35 HDMI_IN_D1+ 32
36 35
34 33 HDMI_IN_D1- 32
HDMI_CDATA 34 33
32 31
R839 2 UMA@ 1 0_0402_5% HDMI_CCLK 32 31
15 PCH_HDMI_CTXC- +V_5V 30 29 HDMI_IN_D2+ 32
R840 2 UMA@ 1 0_0402_5% 30 29
15 PCH_HDMI_CTXC+ 12/10 Add C797(NV 28
28 27
27 HDMI_IN_D2- 32
R843 2 UMA@ 1 0_0402_5% 26 25
C
PCH_OUT_DET
request) 38 LOM_ACTLED_YEL# 26 25 C
1 38 LOM_SPD100LED_GRN# 24 23 HDMI_IN_CK+ 32
R775 2 0_0402_5% 24 23
32,33 CVBS_L 1 22 21 HDMI_IN_CK- 32
R844 UMA@ 0_0402_5% C797 22 21
15 PCH_HDMI_CTXD0- 2 1 32,33 VIN0N# 20 19
R845 UMA@ 0_0402_5% @ R380 2 0_0402_5% 20 19
15 PCH_HDMI_CTXD0+ 2 1 33,45 AIN_IO_L 1 18 17 CLKREQ_USB30# 13
R846 UMA@ 0_0402_5% 2 330P_0402_50V7K R379 2 0_0402_5% 18 17 R769 2 0_0402_5%
15 PCH_HDMI_CTXD1- 2 1 33,45 AIN_IO_R 1 16 15 1 CVBS_SYNC_DET 32,33,43
R847 UMA@ 0_0402_5% 16 15
15 PCH_HDMI_CTXD1+ 2 1 44,47 SYSON# 14 13 E51TXD_P80DATA 42,43
R848 UMA@ 0_0402_5% 14 13
15 PCH_HDMI_CTXD2- 2 1 14 USB_OC#34 12 11
R849 UMA@ 0_0402_5% 12 11
15 PCH_HDMI_CTXD2+ 2 1 10 9
10 9
+V_5V +1.05VS_PCH 8 7
R829 2 VGA@ 1 0_0402_5% HDMI_CTXC- 8 7
21 VGA_HDMI_CTXC- (Place on Bottom side) 6
6 5
5
R828 2 VGA@ 1 0_0402_5% HDMI_CTXC+ +USB_VCCB 4 3 +USB_VCCB
21 VGA_HDMI_CTXC+ 4 3
0.1U_0402_16V4Z +3VALW 2 1 +3VALW
2 1
R832 1 VGA@ 2 1K_0402_5% HDMI_OUT_DET 1 1 1 1 CONN@ J6
22 VGA_HDMI_DET
R838 2 VGA@ 1 0_0402_5% HDMI_CTXD0- C880 C897 C898 C899
21 VGA_HDMI_CTXD0-
R837 2 VGA@ 1 0_0402_5% HDMI_CTXD0+ 0.1U_0402_16V4Z
21 VGA_HDMI_CTXD0+ 22 2 2
R835 2 VGA@ 1 0_0402_5% HDMI_CTXD1-
21 VGA_HDMI_CTXD1-
R836 2 VGA@ 1 0_0402_5% HDMI_CTXD1+ 0.1U_0402_16V4Z
21 VGA_HDMI_CTXD1+
R834 2 VGA@ 1 0_0402_5% HDMI_CTXD2- 0.1U_0402_16V4Z
21 VGA_HDMI_CTXD2-
R833 2 VGA@ 1 0_0402_5% HDMI_CTXD2+
21 VGA_HDMI_CTXD2+

8/13 Add D46/D47SCA00000T00(EMI Suggest)


8/13 Change symbol of D7/D8 to SCA00000T00(EMI Suggest)
HDMI_CCLK HDMI_OUT_DET

+'0,,1
HDMI_IN_SCLK

HDMI_IN_SDATA
HDMI_IN_HPD

HDMI_CABLE_DET
+'0,287 HDMI_CDATA
+3VS +3VS_DGPU +HDMI_5V_OUT
3

2
3

D45 D44 R807 R808


D7 D8 <EMI> <EMI> 0_0402_5% 0_0402_5%

1
<EMI> <EMI> @ @ UMA@ VGA@
@ @ R751 R750

1
4.7K_0402_5% 4.7K_0402_5%
PESD5V0U2BT_SOT23-3

2
G
B PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3 B

2
PESD5V0U2BT_SOT23-3 15 PCH_HDMI_CCLK_R R803 1 UMA@ 2 0_0402_5%
1

21 VGA_HDMI_CCLK_R R804 1 VGA@ 2 0_0402_5% 3 1 HDMI_CCLK


1

D
2
G
SSM3K7002FU_SC70-3
D46 @ +3VS R805 1 UMA@ 2 0_0402_5% Q8662
D12 15 PCH_HDMI_CDATA_R
@ HDMI_CTXC+ 1 10 HDMI_CTXC+ R806 1 VGA@ 2 0_0402_5% 3 1 HDMI_CDATA
21 VGA_HDMI_CDATA_R
HDMI_IN_CK- HDMI_IN_CK-

D
1 10
2

HDMI_CTXC- HDMI_CTXC-
G

2 9
HDMI_IN_CK+ 2 9 HDMI_IN_CK+ SSM3K7002FU_SC70-3
HDMI_CTXD2+ 4 7 HDMI_CTXD2+ PCH_OUT_DET 1 3 Q8663
PCH_HDMIOUT_DET 15
HDMI_IN_D0- 4 7 HDMI_IN_D0-
D

S
1

HDMI_CTXD2- 5 6 HDMI_CTXD2-
HDMI_IN_D0+ 5 6 HDMI_IN_D0+ R883
Q87
3 20K_0402_5% 10/22 Add(EMI Request)
3 UMA@ 2N7002H_SOT23 +5VSB
9/2 Change PN of D12/D22/D46/D47 from 8 UMA@
2

8
SC300000T00 to SC300000T10 RCLAMP0524PATCT 1 1
RCLAMP0524PATCT
D47 @ C831 C832
D22 @ HDMI_CTXD1+ 1 10 HDMI_CTXD1+ 82P_0402_50V8J 82P_0402_50V8J
HDMI_IN_D1- 1 10 HDMI_IN_D1- PCH_SMIBMI 1 R948 2 0_0402_5% <EMI> 2 2 <EMI>
HDMI_CTXD1- HDMI_CTXD1- @1 R949 0_0402_5% SMIB 13
2 9 2 EC_SMI# 13,43
HDMI_IN_D1+ 2 9 HDMI_IN_D1+
HDMI_CTXD0+ 4 7 HDMI_CTXD0+
HDMI_IN_D2- 4 7 HDMI_IN_D2-
HDMI_CTXD0- 5 6 HDMI_CTXD0-
HDMI_IN_D2+ 5 6 HDMI_IN_D2+
+V_5V +HDMI_EDID_5V
3
3 10/22 Add(EMI Request)
8 +HDMI_5V_OUT
8 D15
1 @ D23 F2
1

RCLAMP0524PATCT +V_5V 2 1 1 2 1 2 +HDMI_5V_IN R714 1 @ 2 0_0603_5%


RCLAMP0524PATCT C716 C715
820P_0402_25V7 330P_0402_50V7K RB491D_SOT23 1.1A_8V_1812L110PR D37 F3 W=40mils
2

2 RB491D_SOT23 +HDMI_5V
A +5VS 2 1 1 2 A
<EMI> <EMI> 1 11/4 Change PN of D15 from 1
C409 RB491D_SC59-3 1.1A_8V_1812L110PR
SCS00003600 to SCS00002000 C874
+V_5V 10/22 Add(EMI Request) 10/22 Add(EMI Request) 10/22 Add(EMI Request) 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+12V1 11/4 Change PN of D37 from
+12V1 Place close to J6 +V_5V 2 2
SC1B491D000 to SCS00002000
330P_0402_50V7K 82P_0402_50V8J
1 1 1 1 1
1

1
1

C793 C794 C795 C833 C828 C834


330P_0402_50V7K <EMI> <EMI> 82P_0402_50V8J 82P_0402_50V8J C717 C778
Security Classification Compal Secret Data Compal Electronics, Inc.
2

<EMI> 2 2 2 <EMI> <EMI> 2 <EMI> 2 820P_0402_25V7 330P_0402_50V7K


2

820P_0402_25V7 2
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
<EMI> <EMI>
Place close to J3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IO BD CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 16, 2011 Sheet 36 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ
+3VS

U29

C521 2 1 .1U_0402_16V7K PCIE_PTX_C_DRX_P1 1 48 RREF 1 2


14 PCIE_PTX_DRX_P1 HSIP RREF R372 6.2K_0402_1% C527 8/19 Add
C520 2 1 .1U_0402_16V7K PCIE_PTX_C_DRX_N1 2 47 2 1 +3VS
14 PCIE_PTX_DRX_N1 HSIN 3V3_IN 0.1U_0402_16V4Z
D CLK_PCIE_READER 3 46 CDCLK_REQ# D
17 CLK_PCIE_READER REFCLKP CLK_REQ#
CLK_PCIE_READER# CDCLK_REQ# R885
17 CLK_PCIE_READER# 4 REFCLKN PERST# 45 PLT_RST# 13,22,36,42 1 2 10K_0402_5%
C526 1 2 AV12 5 44
4.7U_0603_6.3V6K AV12 EEDO
PCIE_DTX_C_PRX_P1 2 1 PCIE_DTX_C_PRX_P1_C 6 43 CARD_HPLUG_R 1 R373 2 CARD_HPLUG
14 PCIE_DTX_C_PRX_P1 HSOP EECS CARD_HPLUG 16
C518 0.1U_0402_16V4Z @ 0_0402_5%
PCIE_DTX_C_PRX_N1 2 1 PCIE_DTX_C_PRX_N1_C 7 42
14 PCIE_DTX_C_PRX_N1 HSON EESK
C519 0.1U_0402_16V4Z
8 41 CARD_HPLUG_R C971 @ 1 2 1000P_0402_50V7K
GND GPIO/EEDI
2 1 DV13 9 40 MS_INS# 8/20 Add
C528 0.1U_0402_16V4Z DV12 MS_INS#
+3VS 10 Card1_3V3 39 SD_CD#
+3VS_CR SD_CD#
11 38 SP15_SDWP_XDD7
3V3_IN SP15
12 37 SP14_MSCLK_XDD6 1 R599 2 0_0402_5%
1 1 Card2_3V3 SP14
10U_0603_6.3V6M 0.1U_0402_16V4Z
C554 C552 XD_CD# 13 36 SP13_MSD7_XDD5 1
XD_CD# SP13
2 2 4.7U_0603_6.3V6K DV33_18 14 35 SP12_MSD3_XDD4 C531
DV33_18 SP12
5P_0402_50V
15 34 SP11_MSD6_XDD3 2
1 1 GND SP11
8/18 Change C531 to 5pF(Vendor suggest)
C956 C556 SP1_SDD7_XDRDY 16 33 SP10_MSD2_XDD2
@ SP1 SP10
2 2 SP2_SDD6_XDRE# 17 32 SP9_MSD0_XDD1
SP2 SP9
C 8/18 Add C956(Vendor suggest) C
0.1U_0402_16V4Z SP3_SDD5_XDCE# 18 31 SP8_MSD4_XDD0
SP3 SP8
8/18 Change C532 to 5pF(Vendor suggest) SP4_SDD4_XDWE# 19 30 SP7_MSD1_XDWP#
33_0402_5% SP4 SP7
1/17 Change C532 to 6.8pF(EMI suggest) L70
SD_D1_R 1 2 SD_D1 20 29 SP6_MSD5_XDALE C557
33_0402_5% SD_D1 SP6
L71 1 2 4.7U_0603_6.3V6K
SD_D0_R 1 2 SD_D0 21 28 SP5_MSBS_XDCLE
C532 SD_D0 SP5
L72 33_0402_5% C533
2 1 SD_CLK_R 1 2 SD_CLK 22 27 DV12_S 1 2 0.1U_0402_16V4Z
33_0402_5% SD_CLK DV12_S
L73
6.8P_0402_50V SD_CMD_R 1 2 SD_CMD 23 26
33_0402_5% SD_CMD GND 33_0402_5%
L74 L75
SD_D3_R 1 2 SD_D3 24 25 SD_D2 1 2 SD_D2_R
SD_D3 SD_D2
11/30 Add L70~L75=SM01000CY00
1/17 Change L70~L75 from SM01000CY00 to RTS5209-GR_LQFP48_7X7
SD028330A80(EMI Suggest)

< 7 in 1 Card Reader > 8/15 Update JREAD1 Pin define +3VS_CR
B +3VS_CR JREAD1 B

+3VS_CR 21
SD_VDD SP15_SDWP_XDD7
38 XD_VCC SD_W /P 41
15 SD_CMD_R
SP15_SDWP_XDD7 SD_CMD SD_CD#
37 XD_D7 SD_C/D 39
0.1U_0402_16V4Z 0.1U_0402_16V4Z SP14_MSCLK_XDD6 36 25 SD_CLK_R 1 R801 2 33_0402_5%
SP13_MSD7_XDD5 XD_D6 SD_CLK SD_D0_R @
35 XD_D5 SD_DAT0 31 1
SP12_MSD3_XDD4 33 34 SD_D1_R
SP11_MSD6_XDD3 XD_D4 SD_DAT1 SD_D2_R @ C796
1 1 1 1 32 XD_D3 SD_DAT2 9
2

SP10_MSD2_XDD2 30 11 SD_D3_R 22P_0402_50V8J


R369 C534 C529 C535 C530 SP9_MSD0_XDD1 XD_D2 SD_CD/DAT3 2
27 XD_D1 SD_GND 40
@ 0.1U_0402_16V4Z SP8_MSD4_XDD0 23 19
10K_0402_5% 2 2 2 2 XD_D0 SD_VSS +3VS_CR
SD_VSS 29
SP7_MSD1_XDWP# 13
1

SP4_SDD4_XDWE# XD_-W P
8 XD_-W E
SP6_MSD5_XDALE 7 12 R798
10U_0603_6.3V6M SP5_MSBS_XDCLE XD_ALE MS_VCC SP14_MSCLK_XDD6 @
6 XD_CLE MSCLK 14 1 2 33_0402_5%
SP3_SDD5_XDCE# 5 22 SP9_MSD0_XDD1 1
SP2_SDD6_XDRE# XD_-CE MS_SDIO/DATA0 SP7_MSD1_XDWP#
4 XD_-RE MS_DATA1 24
SP1_SDD7_XDRDY 3 20 SP10_MSD2_XDD2 C783
XD_CD# XD_R/-B MS_DATA2 SP12_MSD3_XDD4 @
Place C534 close to socket pin 38 2 XD_CARD DECTECT MS_DATA3 16
2
22P_0402_50V8J
26 SP5_MSBS_XDCLE
MS_BS MS_INS#
Place C529 close to socket pin 21 1 XD_GND MS_INS/EXT DET 18
17 XD_GND MS_VSS 28
Place C535 close to socket pin 21 MS_VSS 10

Place C530 close to socket pin 12 42 GND GND 43


A A

Proconn-MXP038-A0-2042_43P
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIE-Card Reader-RTS5209
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic1.A
Date: Thursday, June 16, 2011 Sheet 37 of 63
5 4 3 2 1
5 4 3 2 1

J9
@
JUMP_43X79
http://adf.ly/3o8pJ
2 2 1 1
+3VSB 1 R889 2
0_0603_5% 60mil
Q86 +3.3V_LAN

D
+V_3.3V 1 R888 2 3 1
0_0603_5%
@ @ AO3413_SOT23-3

0.1U_0402_16V4Z

G
1 1 1

2
2
R826 2

C922
C536 C537 C538
D 10K_0402_5%
@ @ 2
4.7U_0603_6.3V6K 2 2
10U_0805_6.3V6M Power ( Decoupling Cap. ) D

1
0.1U_0402_16V4Z

Place C538 close to pin5 40 mils 60 mils


0812 Reserve GLAN_PCIE_WAKE# @ 1

1
R827 @ D +3.3V_LAN +LAN_VDD10
1 2 2 Q47 C555
43 GLAN_PCIE_WAKE#
0_0402_5% G @
S 2 0.1U_0402_16V4Z C9052 2 1 .1U_0402_16V7K C9053 2 1 .1U_0402_16V7K

3
1 R902 2 @
13 SLP_LAN#
0_0402_5% SSM3K7002FU_SC70-3 C9054 2 1 .1U_0402_16V7K C9055 2 1 .1U_0402_16V7K

C9056 2 1 .1U_0402_16V7K C9057 2 1 .1U_0402_16V7K

10/26 Add Q47/C555 C9058 2 1 .1U_0402_16V7K C9059 2 1 .1U_0402_16V7K

C9060 2 1 .1U_0402_16V7K C9061 2 1 .1U_0402_16V7K


1000P_0402_50V7K 2 1 @ C998 SLP_LAN#
C9062 2 1 .1U_0402_16V7K C9063 2 1 .1U_0402_16V7K

C9064 2 1 .1U_0402_16V7K

C625, C610, C617, C626 ,C621 , C604 close to


Pin 12,27,39,42,47,48 , respectively
C615, C614,C622 ,C620, C616,C611,C624 close to
pin 3,6,9,13,29,41,45, respectively

C C

check with RT
U30

C9065 2 1 .1U_0402_16V7K PCIE_DTX_PRX_P6 22 31 LOM_SPD1000LED_ORG# LOM_SPD1000LED_ORG# 36


14 PCIE_DTX_C_PRX_P2 HSOP LED3/EEDO LOM_SPD100LED_GRN#
37 LOM_SPD100LED_GRN# 36
C9066 2 PCIE_DTX_PRX_N6 LED1/EESK LOM_ACTLED_YEL#
1 .1U_0402_16V7K 23
HSON LED0
40 LOM_ACTLED_YEL# 36
14 PCIE_DTX_C_PRX_N2
17 30 10K_0402_5% 1 R8594 2 SPEC:
14 PCIE_PTX_C_DRX_P2 HSIP EECS/SCL
18 32 10K_0402_5% 1 R8595 2 3.3V, 70mA (Max)
14 PCIE_PTX_C_DRX_N2 HSIN EEDI/SDA
R378 1 @ 1.05V, 300mA (Max)
+3.3V_LAN 2 10K_0402_5%
13 LAN_CLKREQ# R572 2 1 0_0402_5% LAN_CLKREQ#_R 16 1 LAN_MIDI0+_R R393 2 1 0_0402_5% LAN_MIDI0+
CLKREQB MDIP0 LAN_MIDI0+ 36
2 LAN_MIDI0-_R R401 2 1 0_0402_5% LAN_MIDI0-
MDIN0 LAN_MIDI0- 36 +3.3V_LAN +LAN_VDDREG
R430 1 2 0_0402_5% PLT_A_RST#_LAN 25 4 LAN_MIDI1+_R R402 2 1 0_0402_5% LAN_MIDI1+
5,13,43 PCH_PLT_RST# PERSTB MDIP1 LAN_MIDI1-_R LAN_MIDI1- LAN_MIDI1+ 36
5 R404 2 1 0_0402_5% 40 mils 40 mils
CLK_PCIE_LAN MDIN1 LAN_MIDI2+_R LAN_MIDI2+ LAN_MIDI1- 36
19 7 R406 2 1 0_0402_5% 1 2
17 CLK_PCIE_LAN CLK_PCIE_LAN# REFCLK_P NC/MDIP2 LAN_MIDI2-_R LAN_MIDI2- LAN_MIDI2+ 36
20 8 R414 2 1 0_0402_5% R8596 0_0603_5%
17 CLK_PCIE_LAN# REFCLK_N NC/MDIN2 LAN_MIDI3+_R LAN_MIDI3+ LAN_MIDI2- 36
10 R415 2 1 0_0402_5% 1 2
NC/MDIP3 LAN_MIDI3+ 36 .1U_0402_16V7K
11 LAN_MIDI3-_R R416 2 1 0_0402_5% LAN_MIDI3- C9067
LAN_X1 NC/MDIN3 LAN_MIDI3- 36 C9068
43
CKXTAL1 4.7U_0603_6.3V6K
LAN_X2 44 13 2 1
+3.3V_LAN CKXTAL2 DVDD10 +LAN_VDD10
R8597 29 Close to Pin 34,35
DVDD10
1 2 10K_0402_5% DVDD10
41
PCH_PCIE2_WAKE# 28
13,36,42 PCH_PCIE_WAKE# LANWAKEB
1 2 ISOLATE# 26 27 <Note>
B +3VS ISOLATEB DVDD33 +3.3V_LAN B
R311 1K_0402_5% 39 C623 is X5R
DVDD33
For Power saving mode, Speed down to 10Mb/s
14 12 +3.3V_LAN
R320 10K_0402_5% 1 R377 NC/SMBCLK AVDD33
2 15
NC/SMBDATA AVDD33
42
15K_0402_5% 1 2 LAN_SMBALERT 38 47
+3.3V_LAN GPO/SMBALERT AVDD33
R477 1K_0402_5% 48
R491 0_0402_5% AVDD33
Pin26 assert Low, Layout Note: L60 must be
RTL8111E will 1 2 ENSWREG 33 within 200mil to Pin36,
+3.3V_LAN ENSWREG
3.3V : Enable switching regulator 21
be isolated with 0V : Disable switching regulator EVDD10 +LAN_EVDD10 C589 & C299 must be within
34
PCIe I/F bus VDDREG 200mil to L60
40 mils +LAN_VDDREG 35
VDDREG AVDD10
3 +LAN_VDD10
6
AVDD10 +LAN_VDD10 +LAN_VDD10 +LAN_EVDD10
9
AVDD10
1 2 46
RSET AVDD10
45 60 mils 60 mils
R476 2.49K_0402_1% 60 mils L109 60 mils 1 2
24 36 +LAN_REGOUT 1 2 R8598 0_0603_5%
GND REGOUT 2.2UH +-5% NLC252018T-2R2J-N
49 1 1 1 2
PGND C9069 .1U_0402_16V7K
C9070 C9071 C9072
RTL8111E-VL-CGT_QFN48_6X6 4.7U_0603_6.3V6K .1U_0402_16V7K 1U_0402_6.3V6K
P/N:SA00004LR00 <Note> 2 2 2 1
Close to Pin 21
Crystal 4.7U is X5R

LAN_X1

Y5
25MHZ_20PF_X5H025000DK1H
A LAN_X2 A
1 2
33P_0402_50V8J

33P_0402_50V8J

1 1
C986

C990

2 2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Intel LAN-82579
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic1.A
Date: Thursday, June 16, 2011 Sheet 38 of 63
5 4 3 2 1
A B C D E F G H

0105 Add L24/L25


http://adf.ly/3o8pJ +5VALW L24 1 2
0_0805_5%
1 2 MONO_IN_1 1 2 MONO_IN
43 BEEP# R397 47K_0402_5% C565 0.1U_0402_16V4Z L25 1 2
0_0805_5%
1 2 +5VAMP
13 PCH_SPKR R398 47K_0402_5% 0.1U_0402_16V4Z U31
1 +5VS L20 1
@
2 60mil 1 IN
40mil

1
0_0805_5% 1 1 OUT 5 +VDDA 4.75V
R399 C566 @ C567 C568 2
L21 GND @
0.1U_0402_16V4Z 1 2
10K_0402_5% 2 0_0805_5% 0.1U_0402_16V4Z 3 SHDN BYP
4 1 2
1 2 2 C569 1

2
7/27 Follow NCQFO G9191-475T1U_SOT23-5 0.01U_0402_25V7K

R795 1 2 0_0402_5%
43 CODEC_CN (output = 300 mA)
1
C639
@
0.1U_0402_16V4Z
2

40mil 1026 DEL MIC_R_VREFO


+AVDD_HDA
MIC_INT_VREFO
L22
10mil
MIC_L_VREFO +V_3.3V
+VDDA 1 2
1 1
FBMA-L11-160808-800LMT_0603 2.2U_0603_16V6K

1
C572 C573 VREF 1 1 HP_PLUG#_CODEC
4.7U_0805_10V4Z 0.1U_0402_16V4Z C571

3
2 2 C570 0.1U_0402_16V4Z R767
(Place next to PIN25)
10K_0402_5%
+AVDD_HDA 2 2 @ Q69B

2
5 DMN66D0LDW-7 2N_SOT363-6
@

6
+3VS_VDD

4
1 1 1 Q69A
HP_PLUG#2 DMN66D0LDW-7 2N_SOT363-6
33,41,43 HP_PLUG#
C574 C575 C595 @
10U_0805_6.3V6M 0.1U_0402_16V4Z 2.2U_0603_16V6K

1
2 2 2
(Place next to PIN38)

25

27

28

19

31

38
1

9
U32
2 2

DVDD-IO

MIC2-VREFO
DVDD1

AVDD1

MIC1-VREFO-L

AVDD2
VREF

CPVEE
HP_PLUG# R783 1 2 0_0402_5% HP_PLUG#_CODEC
SPDIFO2 45
41 HP_LEFT 33 HPOUT-L
LINE1-R 24 0810 vendor suggest
41 HP_RIGHT 32 HPOUT-R
23
LINE1-L
1026 Add digital-MIC for reserve 37
MONO-OUT
22 MIC_C_R 2 1 MIC_R_R R776 1 2 1K_0402_5%
MIC1-R 4.7U_0603_6.3V6K C579 MIC_CEN_R 41
34 DMIC_CLK 46
+3VS_VDD DMIC-CLK1/2 MIC_C_L MIC_R_L R777 1
21 2 1 2 1K_0402_5%
MIC1-L 4.7U_0603_6.3V6K C581 MIC_LFE_L 41
34 DMIC_DATA 2
GPIO0/DMIC-DATA1/2
L23 1026 Change mute_codec to GPIO1 MUTE_CODEC 3 17 INT_MIC_RIGHT_C 1 2 C454
2 1
15mil 32,33 MUTE_CODEC GPIO1 MIC2-R 1U_0402_6.3V6K INT_MIC_RIGHT 34
+3VS
MBK1608121YZF_0603 16 INT_MIC_LEFT_C 1 2 C455
HDA_SDOUT_AUDIO MIC2-L 1U_0402_6.3V6K INT_MIC_LEFT 34
1 1 5
13 HDA_SDOUT_AUDIO SDATA-OUT
15
C578 C580 LINE2-R
6
10U_0805_6.3V6M 0.1U_0402_16V4Z 13 HDA_BITCLK_AUDIO BIT-CLK
14
2 2 LINE2-L
1 13 HDA_SDIN0 1 R413 2 HDA_SDIN0_R 8
33_0402_5% SDATA-IN
(Place next to PIN1)
C586 10 20K_0402_1%
22P_0402_50V8J 13 HDA_SYNC_AUDIO SYNC
13 1 2 R405
2 Sense A MIC_PLUG# 41
11 34 1 2 R400 HP_PLUG#_CODEC
13 HDA_RST#_AUDIO RESET# Sense B 5.1K_0402_1%
MONO_IN 12
PCBEEP
1 1 35 R778 1 2 0_0402_5%
FRONT-OUT-L AMP_FRONT_LEFT 40
18
3 C582 C583 LINE1-VREFO R779 1 0_0402_5% 3
36 2 AMP_FRONT_RIGHT 40
10U_0805_6.3V6M 0.1U_0402_16V4Z FRONT-OUT-R
20
@ 2 2 LINE2-VREFO
(Place next to PIN9) SURR-OUT-L
39

2 R403 1 JDREF 40 41
20K_0402_1% JDREF SURR-OUT-R

43 EAPD_CODEC 47 43
EAPD CEN
48 44
C597 SPDIFO1 LFE
1 2 29
CBP

DVSS1

DVSS2

AVSS2

AVSS1
C584 1 2.2U_0603_16V6K 30 <EMI> C616 1 2 0.1U_0402_16V4Z
@ CBN
ESD 1026 Add C597 <EMI> C615 1 2 0.1U_0402_16V4Z
10P_0402_50V8J ALC663-GR_LQFP48_7X7

42

26
2 <EMI> C460 1 2 1U_0402_6.3V6K
1026 Change U32 from SA00004BR00 to SA00003G300
<EMI> C508 1 2 1U_0402_6.3V6K
+3VS
<EMI> C553 1 2 1U_0402_6.3V6K
10/23 Add C460/C508/C553(EMI suggest)
R407 1 2 0_0805_5%
1

R408 1 2 0_0805_5%
R756
4.7K_0402_5% R409 1 2 0_0805_5%
@ 8/13 Add R756(EMI Suggest)
R410 1 2 0_0805_5%
2

R411 1 2 0_0805_5%
HDA_RST#_AUDIO
4 R412 1 4
2 0_0805_5%
Sense Pin Impedance Codec Signals 1
C585
SENSE A 0.01U_0402_16V7K
2 GND GNDA
20K PORT1 (PIN 21, 22) @

Place close to Codec


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
SENSE B 5.1K PORT-2 (PIN 32, 33) HD Audio Codec ALC663
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B QLA01 M/B LA-7811P Schematic 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 16, 2011 Sheet 39 of 63
A B C D E F G H
A B C D E

http://adf.ly/3o8pJ
C9051 +V_3.3V
1/10 Change U40 to APL5610 R976 9/29 Add Q59/R546/R547
1 2 U40 10K_0402_5%
+12V1 6
VCC EN 1 1 2 +V_5V
4.7UF_0805_16V6 1

4.7K_0402_5%
FDS8884_SO8
5 DRV GND 2

1
8
7
6
5

4.7K_0402_5%
Q49 R983 C799
1 10K_0402_5% 4 POK FB 3 1U_0402_6.3V4Z 11/4 Change PN of Q59 from 1

R546

R548
2
4.7U_0805_10V6K

4.7U_0805_10V6K
1 2 SB00000AR00 to SB00000DH00
2

APL5610CI-TRG_SOT23-6
C674 C661

2
2
4 +3VS R977
12K_0402_1%
1

R557

1
1 2 1 2 +PVDD
0_0402_5% C900 R857 6 1 VOL_SCL_AMP
43 VOL_SCL
1 2 2.4K_0402_1%

5
+V_5V Q59A
1
2
3

C299 22U_0805_6.3V6M 47P_0402_50V8J +V_3.3V DMN66D0LDW-7_SOT363-6

2
1 2 3 4 VOL_SDA_AMP
43 VOL_SDA
@
120 mil L60 1
120 mil 10U_0805_10V4Z 0.1U_0402_16V4Z Q59B
2
FBMA-L11-201209-221LMA30T_0805 DMN66D0LDW-7_SOT363-6
1 1 1 1
L61 1 @ 2 C587 C588 C589 C590 1
FBMA-L11-201209-221LMA30T_0805
C712
0_0402_5% 2 2 2 2
1U_0402_6.3V4Z
@ 1 R418 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z 2
43 EC_MUTE#
@ 1 R417 2 0_0402_5% MUTE_AMP
33 S_MUTE#
R8579 @
1 2 0_0603_5%

16
U43

1
U59 +5CH_AUDIO
3D@

PVDD2

PVDD1

AVDD

I2CVDD
1 2 OUTPL_SW 9 8
32,33 I2S_WS NC1 V+
C1017 1U_0402_6.3V4Z 2
3D@ NO1 OUTPL
COM1 10
32 AUDIO_3D_RIGHT 1 2 OUTNL_SW 7
C1015 1U_0402_6.3V4Z OUTPR NC2
OUT-RP 7 4 NO2
@ @ 9
2 MUTEb OUTNR OUTNL 2
33 AMP_SCA_RIGHT 1 2 1 R953 2 300_0402_5% 6 6
C596 1U_0402_6.3V4Z OUT-RN COM2
1 IN1
1 2 ALC106_R
1 2 ALC106_R_C 12 5 3
39 AMP_FRONT_RIGHT INPUT-R OUTPL 43 AV_AUDIO_SEL# IN2 GND
C598 4.7U_0603_6.3V6K C1022 1U_0402_6.3V4Z 2
OUT-LP G3205P71U_MSOP10
AMP_POWER_DOWN# 10 3 OUTNL
43 AMP_POWER_DOWN# SDb OUT-LN

1 2 ALC106_L 1 2 ALC106_L_C 13 1 2
39 AMP_FRONT_LEFT INPUT-L VOL_SCL_AMP R8580 @ 0_0603_5%
C600 4.7U_0603_6.3V6K C1023 1U_0402_6.3V4Z 14
VOL_SCL
33 AMP_SCA_LEFT 1 2 +PVDD
C602 1U_0402_6.3V4Z 1 R973 2 11 15 VOL_SDA_AMP
@ 5.1K_0402_5% BYPASS SE_BTLb/SDA

32 AUDIO_3D_LEFT 1 2 10_0603_5%2
1

AGND

EPAD
C1016 1U_0402_6.3V4Z @
R8581
3D@ 1
32,33 I2S_DATA0 1 2 R972 +5CH_AUDIO
C1019 1U_0402_6.3V4Z C605 ALC106-GR_ESOP16 U60
5.1K_0402_5%
8

17

3D@ 2.2U_0805_25V6K OUTPR_SW ACES_87212-04G0


9 8
2

2 NC1 V+ JSPK21
2 SPKL+
NO1
1

10 OUTPR 1
COM1 SPKL- 1
R955 OUTNR_SW 7 2
R950 NC2 SPKR+ 2
8/25 Modify to AGND 1 2 4 3
300_0402_5% NO2 SPKR- 3
4
@ 0_0402_5% 4
6 OUTNR 5
GND
2

COM2 6
1 GND
IN1
43 AV_AUDIO_SEL# 5 3
IN2 GND CONN@
G3205P71U_MSOP10

3 1 R8582
@ 2 3
0_0603_5%

L107 L104
FBMA-L11-160808-121LMA30T_0805 FBMA-L11-160808-121LMA30T_0805
OUTPR_SW 1 2 SPKR+ OUTPL_SW SPKL+
1 2
1 3A/120ohm/100MHz 1 3A/120ohm/100MHz
1 1
C1511 C1513 C1485 C1486
1000P_0603_50V7K
SPKR+

470P_0805_50V8J
SPKL+

+5CH_AUDIO
SPKR-

1000P_0603_50V7K
SPKL-

2 2 470P_0805_50V8J
2 2

1
4.7U_0603_6.3V6K
R1555 R1548
22_1206_5% 22_1206_5%
1 1
C1014 C1013

2
3

3D@ 3D@
D19 D20 2 2
<EMI> <EMI> 0.1U_0402_16V4Z L108 L105
@ @ FBMA-L11-160808-121LMA30T_0805 FBMA-L11-160808-121LMA30T_0805
OUTNR_SW 1 2 SPKR- OUTNL_SW SPKL-
1 2
1 3A/120ohm/100MHz 1 3A/120ohm/100MHz
1 1
C1510 C1512 C1515 C1514
+5CH_AUDIO R558 1 2 0_0603_5% 470P_0805_50V8J 1000P_0603_50V7K 1000P_0603_50V7K
+PVDD 2 2 470P_0805_50V8J
1

PESD5V0U2BT_SOT23-3 R561 1 @ 2 0_0603_5% +V_3.3V 1 2 2

1
4 R1560 R1550 4
PESD5V0U2BT_SOT23-3 22_1206_5% 22_1206_5%
2

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic1.A
Date: Thursday, June 16, 2011 Sheet 40 of 63
A B C D E
5 4 3 2 1

MIC_L_VREFO
1026 Add Diode for MIC_L_VREFO
12/10 Change symbol of D24/D25 from SC1H751H010 to SCS00002G00
http://adf.ly/3o8pJ
D24
2 1

RB751V40_SC76-2
D25
2 1

RB751V40_SC76-2
EXT MIC IN

1
D R593 R596 D

4.7K_0402_5% 4.7K_0402_5%
JMIC1 CONN@ 8/13 Change symbol of D30 to SCA00000T00(EMI Suggest)
5

2
MIC_PLUG# 4 MIC_CEN_R_1
39 MIC_PLUG#
1 2 MIC_CEN_R_1 3 MIC_LFE_L_1
39 MIC_CEN_R
L30 FBM-11-160808-601-T_0603 6
1 2 MIC_LFE_L_1 2
39 MIC_LFE_L

2
L34 FBM-11-160808-601-T_0603 1
D30
7 PESD5V0U2BT_SOT23-3
Need <EMI>
8
600 Ohm
2/18 Add 500 mA SINGATRON 2SJ-B351-S39

R438 R595 1 1

1
1 1
C710 C711
330P_0402_50V7K 330P_0402_50V7K C708 C647
2 2 .1U_0402_16V7K .1U_0402_16V7K
2 ESD request 2 ESD request
0_0603_5% 0_0603_5%
3D@ 3D@

2/24 Add D29 D28 Add for EMC suggest


L32 L33 MIC_PLUG# 2 2
1 1
C HP_PLUG# C
3 3

PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3
<EMI> <EMI>
75_0603_1% 75_0603_1%
3D@ 3D@ 8/13 Change symbol of D29 to SCA00000T00(EMI Suggest) 8/13 Change symbol of D28 to SCA00000T00(EMI Suggest)

2 1
33 HP_SCA_RIGHT R824 0_0402_5% HP OUT JHP1 CONN@ 8/13 Change symbol of D21 to SCA00000T00(EMI Suggest)
2 1 5
33 HP_SCA_LEFT R825 0_0402_5%
HP_PLUG# 4
33,39,43 HP_PLUG#
2D@

PR

PL
39 HP_RIGHT 1 2D@ 2INTSPK_CR+ 1 2 PR 3
R595 75_0603_1% L33 FBM-11-160808-601-T_0603 6
39 HP_LEFT 1 2D@ 2 INTSPK_CL+ 1 2 PL 2
R438 75_0603_1% L32 2D@ FBM-11-160808-601-T_0603 1
2

2
Need 7
@ R594 @ R597 1 1 D21
600 Ohm 8 <EMI>
20K_0402_5% 20K_0402_5% 500 mA C646 C709
330P_0402_50V7K SINGATRON 2SJ-B351-S39
1

330P_0402_50V7K 2 2
1 ESD request
C707

1
.1U_0402_16V7K PESD5V0U2BT_SOT23-3
2

10/22 Change U56 from SA00001ZW00 to SA00004IS00


B B

+PVDD

0.1U_0402_16V4Z
1 1 1
3D@
10U_0805_10V6K C1005 C806 C1002
@ 3D@ 10U_0805_10V6K
2 2 2
16

U56
PVDD

VDD

C1037
1 2 3D@ 1 7 INTSPK_CL+
CP+ LOUT
2.2U_0603_16V6K
3 9 INTSPK_CR+ +PVDD
CP- ROUT
C1003 1U_0603_10V6K
1 2 10 11 R971 1 2 100K_0402_5%
32 HP_2932_LEFT LIN /RSD
3D@ APA2176A @
C1004 1U_0603_10V6K
32 HP_2932_RIGHT 1 2 12 4
3D@ RIN NC

13 15 HP_AMP_DOWN#
NC /LSD HP_AMP_DOWN# 43
PGND

CVSS

GND
VSS

3D@
2

14

A A

1
C1038
2.2U_0603_16V6K Security Classification Compal Secret Data Compal Electronics, Inc.
2 3D@
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Jack
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 41 of 63
5 4 3 2 1
5 4 3 2 1

+3VS +1.5VS

http://adf.ly/3o8pJ
Mini Card Slot 1---TV tuner Currecnt: 3.3 : 2750mA, 1.5: 500mA
Max 2.7A
L11
+3VS_MINI Max 0.5A
L12
+1.5VS_MINI

MINI(TV) H=9mm
1
0_1206_5%
2 0.01U_0402_16V7K

C768
1
C763
1
4.7U_0603_6.3V6K

C404
1
2
0_0603_5%
1

C765
1
4.7U_0603_6.3V6K

C770
1
C769
1
1
C490
R4250_0402_5% JMINI3 0.1U_0402_16V7K
PCH_PCIE_W AKE# 1 @ +3VS_W LAN 2 2 2 2 2 2
13,36,38 PCH_PCIE_W AKE# 2 1 1 2 2
2
T55 PAD 3 3 4 4
5 6 +1.5VS 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z
T56 PAD 5 6
W LAN_CLKREQ# 7 8 +VCC_SIM
13 W LAN_CLKREQ# 7 8
D 9 10 B_DAT D
CLK_PCIE_W LAN# 9 10 B_CLK +5VS
17 CLK_PCIE_W LAN#
17 CLK_PCIE_W LAN
CLK_PCIE_W LAN
11
13
11
13
12
14
12
14 B_RST @ Smart Card Conn.(B-CAS)
15 15 16 16 1 R539 2 +VCC_SIM
B_DETECT_R 17 18 0_0603_5% 1
17 18
19
21
19
21
20
22
20
22 PLT_RST# PLT_RST# 13,22,36,37 C798 )ROORZ3&$SLQGHILQH
PCIE_DTX_C_PRX_N5 23 24 <EMI>
14 PCIE_DTX_C_PRX_N5 23 24 2 330P_0402_50V7K
PCIE_DTX_C_PRX_P5 25 26
14 PCIE_DTX_C_PRX_P5 25 26
27 27 28 28
29 30 PCH_SMBCLK PCH_SMBCLK 13
C152 2 .1U_0402_16V7K PCIE_PTX_C_DRX_N5 29 30 PCH_SMBDATA
14 PCIE_PTX_DRX_N5 1 31 31 32 32 PCH_SMBDATA 13
C153 2 1 .1U_0402_16V7K PCIE_PTX_C_DRX_P5 33 34
14 PCIE_PTX_DRX_P5 33 34
35 36 JBCAS1
35 36 USB20_N_TV 14 DET1 R586
37 37 38 38 USB20_P_TV 14 10 10 20 20 1 2 0_0402_5%
39 40 9 19 DET2 R585 1 2 0_0402_5% B_DETECT_R
+3VS_W LAN 39 40 9 19
41 41 42 42 8 8 18 18
43 43 44 44 7 7 17 17
45 46 6 16 B_DAT
45 46 6 16 B_CLK
47 47 48 48 5 5 15 15
36,43 E51TXD_P80DATA E51TXD_P80DATA 49 50 4 14
E51RXD_P80CLK 49 50 4 14 B_RST
43 E51RXD_P80CLK 51 51 52 52 3 3 13 13
2 2 12 12
53 54 1 11 +VCC_SIM
GND1 GND2 1 11
1
CONN@ C759
BELLW _80003-1021 PCH_SMBCLK C974 @ 1 2 1000P_0402_50V7K ACES_85203-10021 0.1U_0402_16V4Z
CONN@ PCH_SMBDATA C975 @ 1 2 1000P_0402_50V7K
2
C 8/20 Add C
10/26 Vertical pin define

WLAN
+3VS_W LAN R423 1 2 0_1206_5% +3VS
R424 1 @ 2 0_1206_5% +3VALW

H=4mm
JMINI2
1 1 2 2 +3VS_MINI
3 3 4 4
5 5 6 6 +1.5VS_MINI
7 8 +3VS_W LAN
13 TV_CLKREQ# 7 8 1 1
9 10 C767 C406
9 10 0.1U_0402_16V4Z
17 CLK_PCIE_TV# 11 11 12 12
13 14 39P_0402_50V8J 39P_0402_50V8J 1 1
B 17 CLK_PCIE_TV 13 14 2 2 B
15 15 16 16
17 18 C631 C632 C633
17 18 W L_OFF#
19 19 20 20 W L_OFF# 43
PLT_RST# 2 2
21 21 22 22
PCIE_DTX_C_PRX_N4 23 24 4.7U_0805_10V4Z 0.1U_0402_16V4Z
14 PCIE_DTX_C_PRX_N4 PCIE_DTX_C_PRX_P4 23 24
14 PCIE_DTX_C_PRX_P4 25 25 26 26
27 27 28 28
29 29 30 30 PCH_SMBCLK 13 10/5 Add C13/C15/C16 by Vivian
C628 2 1 .1U_0402_16V7K PCIE_PTX_C_DRX_N4 31 32 PCH_SMBDATA 13
14 PCIE_PTX_DRX_N4 31 32
C629 2 1 .1U_0402_16V7K PCIE_PTX_C_DRX_P4 33 34
14 PCIE_PTX_DRX_P4 33 34
35 35 36 36
37 38 PCH_SMBCLK C972 @ 1 2 1000P_0402_50V7K
R428 37 38 PCH_SMBDATA C973 @ 1
39 39 40 40 2 1000P_0402_50V7K
+3VS_MINI 1 2 +3V_MINI_R 41 42 R426 1 2 0_0402_5%
0_0603_5% 41 42 MINI1_LED#
43 43 44 44 MINI1_LED# 46 8/20 Add
45 45 46 46
47 47 48 48
36,43 E51TXD_P80DATA E51TXD_P80DATA 49 50
E51RXD_P80CLK 49 50
43 E51RXD_P80CLK 51 51 52 52
+3VS +1.5VS
53 GND1 GND2 54
0.1U_0402_16V4Z
1 1 1

1
C766 BELLW _80003-1021
CONN@ C764 R427 C634 C635 C636
39P_0402_50V8J 39P_0402_50V8J 10K_0402_5%
2 2 2
4.7U_0805_10V4Z 0.1U_0402_16V4Z
(9~16mA)

2
A A
MINI1_LED#
12/7 Add C156/C157/C167 by Vivian

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
WLAN&MINI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 16, 2011 Sheet 42 of 63
5 4 3 2 1
A B C D E

Place closely pin 12


http://adf.ly/3o8pJ
+3VSB +3VSB

2
CLK_PCI_LPC R441
R552 0_0603_5% 1 R447 2
57 VR_HOT# H_PROCHOT# 5

2
0_0603_5% 0_0402_5%
@ 1

1
C656

1
R444 1000P_0402_50V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z R443 D
10_0402_5% 1 1 1 1 1 1 +EC_AVCC 1 2 ECAGND 1 @ 2 H_PROCHOT#_EC 2 Q42 C860
0_0402_5% G 47P_0402_50V8J
1

C650 C651 C652 C653 C654 C655 0.1U_0402_16V4Z S 2N7002H_SOT23 2

3
1

111
125
1 2 2 2 2 2 2 1

22
33
96

67
9
C657 1000P_0402_50V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z U46
18P_0402_50V8J

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
2

EC_GA20 1 21 EC_OSD_PWM
12 EC_GA20 EC_KBRST# GATEA20/GPIO00 PWM0/GPIO0F EC_OSD_PWM 46 +3VSB
12 EC_KBRST# 2 23 BEEP# 39
PCH_PLT_RST# SERIRQ KBRST#/GPIO01 BEEP#/PWM1/GPIO10
12 SERIRQ
3
SERIRQ# PWM Output FANPWM0/GPIO12
26 FAN_CPU_PWM 46
LPC_FRAME# 4 27 TV_ON_OFF
13 LPC_FRAME# LPC_FRAME#/LFRAME# ACOFF/FANPWM1/GPIO13

2
1 LPC_AD3 5 1
@ 13 LPC_AD3 LPC_AD2 LPC_AD3/LAD3 R442
C658 13 LPC_AD2 LPC_AD1
7
8
LPC_AD2/LAD2
63 C675
Ra 100K_0402_5%
13 LPC_AD1 LPC_AD0 LPC_AD1/LAD1 BATT_TEMP/AD0/GPI38 GFXVR_IMON TV_ON_OFF 32
0.1U_0402_16V4Z 10 64 0.1U_0402_16V4Z AV@
2 13 LPC_AD0 LPC_AD0/LAD0 BATT_OVP/AD1/GPI39 GFXVR_IMON 57 2
LPC & MISC 65

1
CLK_PCI_LPC ADP_I/AD2/GPI3A AD_BID
17 CLK_PCI_LPC 12 CLK_PCI_EC/PCICLK AD3/GPI3B 66
PCH_PLT_RST# 13 AD Input 75 AD_BID
5,13,38 PCH_PLT_RST# ECRST# PCIRST#/GPIO05 AD4/GPI42 IMVP_IMON
Place closely pin 13 +3VSB 1 R446 2 37 EC_RST#/ECRST# AD5/GPI43 76 IMVP_IMON 57
47K_0402_5% EC_SCI# 20
12 EC_SCI# EC_SCI#/GPIO0E

2
1 38 CLKRUN#/GPIO1D
R925 1 @ 2 CLKRUN#_R 68 R762 1 2 0_0402_5% R445
13 CLKRUN# DAC_BRIG/DA0/GPO3C LSADC0 32,33
C659 0_0402_5% 70 R761 1 2 0_0402_5% Rb 0_0603_5%
EN_DFAN1/DA1/GPO3D LSADC1 32,33
0.1U_0402_16V4Z DA Output 71 R449 1 2 0_0402_5% NON_AV@
2 IREF/DA2/GPO3E LSADC2 32,33
UART_TX_R 55 72 R450 1 2 0_0402_5%

1
EC_MUTE# KSI0/GPIO30 DA3/GPO3F LSADC3 32,33
40 EC_MUTE# 56 KSI1/GPIO31
AMP_POWER_DOWN# 57
40 AMP_POWER_DOWN# CVBS_SYNC_DET KSI2/GPIO32 PS2_CLK
10/25 Add R968 32,33,36 CVBS_SYNC_DET 58 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 83
PS2_CLK 36
+3VSB KSI4 59 84 PS2_DATA
32,33 HDMI_SYNC_DET KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B PS2_DATA 36
KSI5 60 85 T86 @
33,39,41 HP_PLUG# KSI6 KSI5/GPIO35 CAP_INT#/PSCLK2/GPIO4C
61 PS2 Interface 86 T87 @
+3VSB 36,46 BT_RESET KSI6/GPIO36 PSDAT2/GPIO4D
4.7K_0402_5% 1 2 R968 KSI7 J5 1 @ 2 KSI7 62 87
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E HP_AMP_DOWN# EC_3V5V_EN 52 LSADC0
10K_0603_5% 39 88 R492 1 2 100K_0402_5%
2 KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F HP_AMP_DOWN# 41 LSADC1 2
R451 2 1 47K_0402_5% 40 R493 1 2 100K_0402_5%
R452 2 KSO2 KSO1/GPIO21 LSADC2
8/15 Add 1 47K_0402_5% 41 KSO2/GPIO22
R494 1 2 100K_0402_5%
KSO3 42 97 VGATE_R R453 2 1 0_0402_5% VGATE LSADC3 R495 1 2 100K_0402_5%
39 CODEC_CN EC_OSD_RST# KSO3/GPIO23 SDICS#/GPXIOA00 VGATE 13,57
46 EC_OSD_RST# 43 KSO4/GPIO24 WOL_EN/SDICLK/GPXIOA01 98
R474 1 2 0_0402_5% UART_TX_R SOURCE_LED
15,32,33 UART_TX
R485 1 UART_RX_R 46 SOURCE_LED EC_CAM_OFF
44 KSO5/GPIO25 Int. K/B ME_EN/SDIMOSI/GPXIOA02 99 ME_FLASH 13
15,32,33 UART_RX 2 0_0402_5% 34 EC_CAM_OFF 45 KSO6/GPIO26 Matrix LID_SW#/GPXIOD00 109 SCALER_ON# 33 10/5 Add R492~495(EC request)
AV_AUDIO_SEL# 46 SPI Device I/F
40 AV_AUDIO_SEL# KSO7/GPIO27
S3_1.5VEN 47
51,55 S3_1.5VEN KSO8/GPIO28
EC_ENVDD 48 119 EC_SI_SPI_SO
34 EC_ENVDD KSO9/GPIO29 SPIDI/MISO EC_SI_SPI_SO 44
3D_PWREN 49 120 EC_SO_SPI_SI R454 33_0402_5%
32 3D_PWREN KSO10/GPIO2A SPIDO/MOSI EC_SO_SPI_SI 44
50 SPI Flash ROM 126 SPI_CLK 1 2
18 PCH_ENABLE KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK_R 44
PCH_ENABLE 51 128 SPI_CS#
KSO12/GPIO2C SPICS# SPI_CS# 44 +3VSB
J8 1 @ 2 10K_0603_5% 52 1
KSO13/GPIO2D R455
8/19 Add R884(Vendor suggest) 32,33 PANEL_STATE_OFF 53 1 2 10K_0402_5% @
UART_RX_R KSO14/GPIO2E CIR_IN C660
54
KSO15/GPIO2F GPIO40
73 CIR_IN 46 9/29 Change net name from +V_5V to +5VSB
1K_0402_1% 2 1 R884 PANEL_STATE_OFF H_PROCHOT#_EC 81 74 100P_0402_50V8J +5VSB
EC_REVPWROK KSO16/GPIO48 H_PECI/GPIO41 GLAN_PCIE_WAKE# H_PECI 5,12 2
12 EC_REVPWROK 82
KSO17/GPIO49 GPIO FSTCHG/GPIO50
89 GLAN_PCIE_WAKE# 38
90 BT_ON# 46
BATT_CHG_LED#/GPIO52 BT_AUTOPAIR
91 BT_AUTOPAIR 46
VOL_SCL CAPS_LED#/GPIO53 WL_BLUE_LED# PS2_CLK 4.7K_0402_5% 1 @
40 VOL_SCL 77
EC_SMB_CK1/SCL0/GPIO44 BATT_LOW_LED#/GPIO54
92 WL_BLUE_LED# 46 2 R927
VOL_SDA 78 93 PWR_ON_LED#
40 VOL_SDA EC_SMB_CK2_M EC_SMB_DA1/SDA0/GPIO45 PWR_LED#/GPIO55 SYSON PWR_ON_LED# 46 PS2_DATA
79 95 4.7K_0402_5% 1 @ 2 R928
13 EC_SMB_CK2_M EC_SMB_DA2_M EC_SMB_CK2/SCL1/GPIO46 SYSON/GPIO56 VR_ON SYSON 36,47,55
13 EC_SMB_DA2_M 80 121 VR_ON 57
1000P_0402_50V7K 2 EC_SMB_CK2 EC_SMB_DA2/SDA1/GPIO47 VR_ON/XCLK32K/GPIO57 PSU_PG#
1 @ C982
AC_IN/GPIO59
127 PSU_PG# 51
1000P_0402_50V7K 2 1 @ C983 EC_SMB_DA2 SM Bus
PCH_PLT_RST# 1 R456 2
8/20 Add PM_SLP_S3# 6 100 EC_RSMRST# 100K_0402_5%
13 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# 13
PM_SLP_S5# 14 101 VCCSA_PG
13 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 VCCSA_PG 53
EC_SMI# 15 102
EC DEBUG port 13,36 EC_SMI# EC_ESB_INT 16
EC_SMI#/GPIO08 EC_ON/GPXIOA05
103
EC_ON 48
46 EC_ESB_INT GPIO0A EC_SWI#/GPXIOA06 EC_PWROK EC_SWI# 13
17 104 R458
46 EC_OSD_CK GPIO0B ICH_PWROK/GPXIOA07 BKOFF# EC_PWROK 13
46 EC_OSD_DA 18 GPIO 105 BKOFF# 34 1 2D@ 2 +3VSB
3 SUS_PWR_ACK GPIO0C BKOFF#/GPXIOA08 100K_0402_5% 3
13 SUS_PWR_ACK 19
SUS_PWR_DN_ACK/GPIO0D GPO RF_OFF#/GPXIOA09 106 WL_OFF# 42
INVT_PWM EC_ID
Reserve R460 for EC debug. 34 INVT_PWM FAN_CPU_SPEED
25
28
INVT_PWM/PWM2/GPIO11 GPXIOA10
107
108 R459
46 FAN_CPU_SPEED FAN_SPEED1/FANFB0/GPIO14 GPXIOA11 POWER_KEY 33
29
FANFB1/GPIO15 1 3D@ 2
R460 E51TXD_P80DATA 30 100K_0402_5%
36,42 E51TXD_P80DATA EC_TX/GPIO16
1 2 E51TXD_P80DATA E51RXD_P80CLK 31 110
42 E51RXD_P80CLK ON/OFF EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 ENBKL PM_SLP_S4# 13
48 ON/OFF 32 112 2 R461 1 S_BKOFF 32,33,34
100K_0603_5% CEN_PWR_LED ON_OFF/GPIO18 ENBKL/GPXIOD02 0_0402_5%
46 CEN_PWR_LED 34 114 EAPD_CODEC 39
SUSWARN# SUSP_LED#/GPIO19 EAPD/GPXIOD03 HDMI_CABLE_DET
13 SUSWARN# 36
NUM_LED#/GPIO1A GPI EC_THERM#/GPXIOD04
115 HDMI_CABLE_DET 36
116 SUSP#
SUSP#/GPXIOD05 SUSP# 47,53,54,56,59
C662 117 PBTN_OUT#
PBTN_OUT#/GPXIOD06 PBTN_OUT# 13
15P_0402_50V8J 118 35V_PG
CRY2 EC_PME#/GPXIOD07 35V_PG 52
1 2 122
XCLK1
100P_0402_50V8J 1 2 C876 ON/OFF 123 124 2 1
XCLK0 V18R C663 4.7U_0603_6.3V6K
+3VSB
1

AGND

32.768KHZ_12.5PF_Q13MC14610002
GND
GND
GND
GND
GND

2 NC @
OSC 1 R463 EC_OSD_RST# 2.2K_0402_5% R947
1 2
3 4 20M_0402_5% KB930QF-A1_LQFP128_14X14 BT_RESET 4.7K_0402_5% 1 2 R941
11
24
35
94
113

69

NC OSC AV_AUDIO_SEL# 4.7K_0402_5% 1 3D@ 2 R936


2

Y6 +V_3.3V HDMI_CABLE_DET 4.7K_0402_5% 1 2 R887


ECAGND

EC_OSD_CK 4.7K_0402_5% 1 2 R854


1 2 CRY1 EC_OSD_DA 4.7K_0402_5% 1 2 R853
+3VSB

4.7K_0402_5%
2

1
+3VSB

4.7K_0402_5%
C664 PANEL_STATE_OFF 4.7K_0402_5% 1 @ 2 R497
15P_0402_50V8J R467 AMP_POWER_DOWN# 4.7K_0402_5% 1 @ 2 R496
1

R550

R551
@ 0_0402_5% EC_ESB_INT 2.2K_0402_5% 1 2 R771
R465 GLAN_PCIE_WAKE# 100K_0402_5% 1 2 R462
@
2

10K_0402_5% ON/OFF 4.7K_0402_5% 1 2 R464


1

2
5
1

U39 @ POWER_KEY 4.7K_0402_5% 1 @ 2 R713


13 PCH_SUSCLK EC_SMB_CK2_M EC_SMB_CK2 PWR_ON_LED#
SN74AHCT1G125GW_SOT353-5 JP1 6 1 8.2K_0402_5% 1 @ 2 R466
OE#
P
2

EC_RSMRST# KSO2 EC_SMB_CK2 21 VOL_SCL


2 4 1 4.7K_0402_5% 1 2 R468
A Y 1
5

4 KSO3 Q61A VOL_SDA 4.7K_0402_5% R469 4


2 2 1 2
G

KSI5 3 DMN66D0LDW-7_SOT363-6 WL_BLUE_LED# 8.2K_0402_5% 1 @ 2 R470


KSI4 3 EC_SMB_DA2_M EC_SMB_DA2 EC_MUTE# 4.7K_0402_5% R472
1 4 3 4 1 2
3

KSI6 4 EC_SMB_DA2 21 TV_ON_OFF


@ 5 4.7K_0402_5% 1 2 R481
C665 KSI7 5 Q61B
6 6
0.1U_0402_10V6K E51TXD_P80DATA 7 DMN66D0LDW-7_SOT363-6
2 7
8 8
1 2 9

R471 0_0402_5%
10
G1
G2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
@ MOLEX 514410893 8P H1.1 FPC S H-CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB930/KB conn
@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic1.A
Date: Thursday, June 16, 2011 Sheet 43 of 63
A B C D E
A B C D E

http://adf.ly/3o8pJ
12mA
USB20_P0_1 6
D42 <EMI>
3 +USB_VCCA
Close to JP9.PIN1
1
0.1U_0402_16V4Z 2 1 C875 +3VSB C677
1 +USB_VCCA 5 2 0.1U_0402_16V4Z
<EMI>
C835 2
82P_0402_50V8J
2 <EMI> USB20_N0_1
4 1
U48 20mils
43 SPI_CS# SPI_CS# 1 8 CM1293A-04SO_SOT23-6
R720 1 CE# VDD
2 4.7K_0402_5% SPI_W P# 3 WP# SCK 6 EC_SPICLK_R 1 R722 2 0_0402_5% SPI_CLK_R SPI_CLK_R 43
1 +3VSB R721 1 2 4.7K_0402_5% SPI_HOLD# 7 5 EC_SO_SPI_SI_R 1 R723 2 0_0402_5% EC_SO_SPI_SI 10/25 Change symbol and footprint of D42 from SC300000100 to 1
HOLD# SI EC_SO_SPI_SI 43
4 2 EC_SI_SPI_SO_R 1 R724 2 0_0402_5% EC_SI_SPI_SO
VSS SO EC_SI_SPI_SO 43 SC300000O00(ESD request)
+USB_VCCA
MX25L1005AMC-12G_SO8
SA00002C100 Layout Note: Please Place R722/R723 Close to U46 JUSB1
150mils
128kB R431 1 @ 2 0_0402_5% USB30_RN1_L 5 SSRX-
L28 W CM-2012-900T_4P USB30_RP1_L 6 1
1 1 SSRX+ VBUS
14 USB20_N0 2 2 USB20_N0_1 7 GND1 D- 2 USB20_N0_1
USB30_TN1_L 8 3 USB20_P0_1
USB20_P0_1 USB30_TP1_L SSTX- D+
9 SSTX+ GND 4
4 4 3 3
14 USB20_P0
R433 1 @ 12 GND4 GND2 10
2 0_0402_5% 13 11
GND5 GND3

LOTES_AUSB0004-P001A
CONN@

0_0402_5% R8529 2 USB3@


11/2 Change PN of C640 from SF000002Y00 to 1
C9073
SF000001G00 0.1UF_0402_16V7 LB1 @
+USB_VCCA 1 2 USB30_TP1_C 1 2 USB30_TP1_L
16 USB30_TP1 1 2

1 1 1 2 USB30_TN1_C 4 3 USB30_TN1_L

330U_6.3V_M_R14
C641 16 USB30_TN1 4 3 DB1
+

C640
2 0.1UF_0402_16V7 USB30_RN1_L 1 10 USB30_RN1_L 2
+V_3.3V C9074 1 2
2 0_0402_5% R8530 USB3@ USB30_RP1_L USB30_RP1_L
2 9
2 470P_0402_50V7K 0_0402_5% R8531 2 USB3@
1 USB30_TN1_L 4 7 USB30_TN1_L
+V_5V
1

+USB_VCCA
U36 LB2 @ USB30_TP1_L 5 6 USB30_TP1_L
1 8 R432 1 2 USB30_RP1_L
GND OUT 16 USB30_RP1 1 2
2 IN OUT 7 3
3 6 100K_0402_5%
2

IN OUT USB30_RN1_L 8
1 4 EN# OC# 5 1 2 USB_OC#0 14 16 USB30_RN1 4 4 3 3
C643 R434 1
APL3510BXI-TRG MSOP8 10K_0402_5% C642 USB3@ RCLAMP0524PATCT
4.7U_0603_6.3V6K 1 2
2 0_0402_5% R8532 USB3@
0.1U_0402_16V4Z Part Number = SC300000T10
2
36,47 SYSON#

10/22 Add(EMI Request) 10/22 Add(EMI Request)


10/3 Add C789/C790(Place close to JP10) +USB_VCCA
+V_3.3V +V_5V
+USB_VCCA R435 1 @ 2 0_0402_5% JUSB2
1 1 USB30_RN2_L
1 L29 5 SSRX-
C826 C827 USB30_RP2_L 6 1
1 1 1 2 2 SSRX+ VBUS
+ 82P_0402_50V8J 82P_0402_50V8J 14 USB20_N1 USB20_N1_1 7 2 USB20_N1_1
2 2 USB30_TN2_L GND1 D- USB20_P1_1
C789 C790 <EMI> <EMI> USB20_P1_1 8 SSTX- D+ 3
220U_6.3V_M 470P_0402_50V7K USB30_TP2_L 9 4
4 4 3 3 SSTX+ GND
3 @ 2 2 @ 14 USB20_P1 3
W CM-2012-900T_4P 12 10
GND4 GND2
1 2 13 GND5 GND3 11
R436 @ 0_0402_5%

LOTES_AUSB0004-P001A
CONN@
0_0402_5% R8533 2 USB3@
1
8/13 Add D43/C678(EMI Suggest) C9075
0.1UF_0402_16V7 LB3 @
1 2 USB30_TP2_C 1 2 USB30_TP2_L
D43 <EMI> 16 USB30_TP2 1 2
+USB_VCCA USB20_P1_1 6 3
1 2 USB30_TN2_C 4 3 USB30_TN2_L DB2
1 16 USB30_TN2 4 3
C678 USB30_RN2_L 1 10 USB30_RN2_L
0.1UF_0402_16V7
0.1U_0402_16V4Z +USB_VCCA 5 2 1 2
C9076 USB30_RP2_L USB30_RP2_L
<EMI> 0_0402_5% R8534 USB3@ 2 9
2
0_0402_5% R8535 2 USB3@ USB30_TN2_L 4 7 USB30_TN2_L
1
4 1 USB20_N1_1
USB30_TP2_L 5 6 USB30_TP2_L
LB4 @
CM1293A-04SO_SOT23-6 USB30_RP2_L
16 USB30_RP2 1 1 2 2 3
10/25 Change symbol and footprint of D43 from SC300000100 to 8
SC300000O00(ESD request) 16 USB30_RN2 4 4 3 3 USB30_RN2_L
USB3@ RCLAMP0524PATCT
4 4
1 2
0_0402_5% R8536 USB3@ Part Number = SC300000T10

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB / BIOS ROM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic 1.A
Date: Thursday, June 16, 2011 Sheet 44 of 63
A B C D E
5 4 3 2 1

http://adf.ly/3o8pJ

D D

10/27 Add C558~C561(EMI request)

+5VSB +1.5VS

1 1
C558 C559
<EMI> <EMI>
1000P_0402_50V7K 2 1000P_0402_50V7K 2

+3VSB +V_3.3V

1 1
C560 C561
<EMI> <EMI>
1000P_0402_50V7K 2 1000P_0402_50V7K 2

C C

0818 Vendor suggest(Close to U42.Pin43/Pin44)


12/6 Change C947/C948 from 4.7uF to 1uF

NBQ100505T-800Y-N_2P
L59 3D@ C947 3D@ 3D@
1 2 1 2 1 2 AIN_TAS_L AIN_TAS_L 32
33,36 AIN_IO_L
0_0402_5% R877
NBQ100505T-800Y-N_2P 1U_0603_10V6K
L58 3D@ C948 3D@ 3D@
3D@ 1 2 1 2 1 2 AIN_TAS_R
33,36 AIN_IO_R AIN_TAS_R 32

470P_0402_50V8J

470P_0402_50V8J
1 1 0_0402_5% R878

1
C949 1U_0603_10V6K
C950
D48 3D@ R875 R876
2 2 10K_0402_5% 10K_0402_5%
SM05_SOT23
3D@ @ @

2
1

B B

De-Emphasis Control
DEMT1 (pin 17) DEMT0 (pin 16) AUDIO INTERFACE
LOW LOW OFF *
LOW HIGH 48 kHz
HIGH LOW 44.1 kHz
HIGH HIGH 32 kHz

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
5CH AUDIO_PCM1606
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic1.A
Date: Thursday, June 16, 2011 Sheet 45 of 63
5 4 3 2 1
A B C D E

http://adf.ly/3o8pJ 12/6 Change symbol of JFUN1 from


SP02000AN00 to SP01000HE00
+3VS +3VALW

Power switch board SENSOR BOTTOM

2
+3VSB
11/4 Change PN of Q16 from SB00000AR00 to R544
@
Follow NCQD0 SB00000EO10
@
10K_0402_5%

5
Q16B

1
12/6 Change symbol of JPWR1 from JFUN1 2N7002KDWH_SOT363-6
1 11 WL_BLUE_LED# 4 3
SP02000U100 to SP01000B100 1 11 43 WL_BLUE_LED# MINI1_LED# 42
1 @ 2 +3VS 2 12
JPWR1 R784 0_0402_5% R855 0_0402_5% 2 12
43 EC_OSD_PWM 1 2 3
3 13
13 R774
2 1 1 2 +3VALW 1 R540 2 0_0402_5% 4 14 1 2 0_0402_5%
2 1 43 EC_OSD_CK 4 14

6
1 1
4 3 PWRLED R785 0_0402_5%
43 EC_OSD_DA 1 R588 2 0_0402_5% 5 15
4 3 5 15
6 5 ON/OFFBTN#_R 1 2 ON/OFFBTN# 48 43 EC_ESB_INT 1 R589 2 0_0402_5% 6 16 1/11 Add R774
6 5 R473 0_0402_5% R770 0_0402_5% 6 16
8 7 43 EC_OSD_RST# 1 2 7 17
8 7 7 17 @ Q16A BT_LED
10 9 8 18 2
10 9 8 18 2N7002KDWH_SOT363-6
12 11 1 1 1 9 19
12 11 C761 9 19
10 20

1
ACES_85203-06021 C760 C762 10 20

1
CONN@ 33P_0402_50V8J 33P_0402_50V8J CONN@
2 2 2 ACES_85203-10021 @R543
@ R543

R475 0_0402_5% 33P_0402_50V8J 100K_0402_5%


PWRLED 1 2

2
PWR_ON_LED# 43

LED board conn. DECO LED board conn.


+3VS +3VSB

JLEDIR +3VSB JLED1


9 G1 A1 1 1 1
A2 2 43 CEN_PWR_LED 2 2
3 PCH_SATALED# 3
NC WL_BLUE_LED# PCH_SATALED# 12 3
K1 4 4 4
5 SOURCE_LED 5
K2 CIR_IN SOURCE_LED 43 G1
K3 6 CIR_IN 43 6 G2
7 BT_LED
NC ACES_88747-040N
10 G2 NC 8
CONN@
1000P_0402_50V7K C666

1000P_0402_50V7K C667

1000P_0402_50V7K C668
ACES_85202-08051 2 2 2
2 CONN@ 2

+3VALW +3VAUX_BT 12/6 Change symbol of JLED1 from


1 1 1 Q8661
10/3 Change symbol of J3DIR1 from SP020008V00
12/6 Change symbol of JLEDIR from
C669
AP2301GN-HF_SOT23-3 SP02000PO00 to SP010028400(3pin to 4 pin)
to SP02000GC00( 䚜䩳⺷
to R/A)
SP020008R00 to SP01000N500 2 1 3 1
+5VS
1U_0603_10V6K
DTV recorder

2
@ 1 1 @
C671 C670 R8599

2
10K_0402_5% J3DIR1
0.1U_0402_16V4Z 4.7U_0603_6.3V6K 1
2 2 1
2 R8600 1 2

1
43 BT_ON# 14 USB20_N_DTV 2
10K_0402_5% 3 5
14 USB20_P_DTV 3 GND

BT
4 6
4 GND
ACES_87213-0400G
10/26 Change symbol and footprint of JBT1 from SP02000FR00 CONN@
8/13 Change symbol of D27 to SCA00000E00(EMI Suggest) to SP02000F000
Connector 2
C672
PWRLED JBT1
1 1 1000P_0402_50V7K
1 +3VAUX_BT
ON/OFFBTN#_R 2
2 USB20_P10_R
3
3 R478 2 1 0_0402_5% USB20_P10
USB20_P10 14
3

4 USB20_N10_R R479 2 1 0_0402_5% USB20_N10


D27 4 BT_LED USB20_N10 14
5
PJSOT24C_SOT23-3 5
8 6 BT_AUTOPAIR 43
<EMI> G8 6
9 7 BT_RESET 36,43
@ G9 7
ACES_87213-0700G
1

3 CONN@ BT_LED 3
2 R490 1 10K_0402_5%

12/9 Add R490

+12VS

+3VS
Fan Control circuit

2
R765

2
0_0603_5%
R480
10K_0402_5%

1
JFAN1
+VCC_FAN1 1

1
1
43 FAN_CPU_SPEED 2
2
1 43 FAN_CPU_PWM 3
3
4
C673 4
5
1000P_0402_50V7K G5
6
2 G6
CONN@
ACES_85205-04001
4 4

11/29 Change symbol and footprint of JFAN1 from SP02000U900 to


SP020008X00

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WL/BT ON/OFF, PWR S/W, OSD
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom QLA01 M/B LA-7811P Schematic 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 16, 2011 Sheet 46 of 63
A B C D E
A B C D E

http://adf.ly/3o8pJ
+V_3.3V TO +3VS +V_5V TO +5VS +12V1 TO +12VS
+V_3.3V +3VS +V_5V +5VS +12V1 +12VS

U35 11/4 Change PN of U34 from SB000009580 to U34 U51


8
D S
1 SB000009510 8
D S
1 11/2 Change PN of U51 from 1
S D
8
1 1
7 2 7 2 SB00000N100 to SB00000DJ00 2 7
D S D S S D

2
6 3 1 6 3 1 3 6 1
D S C486 R611 D S R612 S D R744
5 4 5 4 4 5
D G 470_0603_5% D G C488 G D C884
AO4468L_SO8 AO4468L_SO8 1U_0603_10V6K 470_0603_5% AO4435_SO8 1U_0603_25V6 470_0603_5%
2
1U_0603_10V6K 2 2

1
11/4 Change PN of U35 from SB000009580 to
SB000009510

3
R613 R743
1 2 Q40B 2 1 5VS_GATE Q41B 2 1 Q57B
+12V1 +12V1 +12V1
R603 5 SUSP 5 SUSP 5 SUSP
47K_0402_5% 1 20K_0402_5% 1 20K_0402_5% 1
6

6
2N7002DW-T/R7_SOT363-6 C487 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

4
C485 C883
Q40A 0.1U_0603_25V7K Q41A 0.1U_0603_25V7K Q57A 0.1U_0603_25V7K
SUSP 2 2 SUSP 2 2 SUSP# 2 2

2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6


1

1
+1.5V
2 +1.5V TO +1.5VS 2

9/29 Change net name from +5VALW to +5VSB


+5VSB 9/29 Change net name from +5VALW to +5VSB
+1.5VS +5VSB

2
U33

2
8 D S 1
7 2 R605 R604
D S 100K_0402_5% 100K_0402_5%
6 3 1
D S
2

5 4 C467

1
D G R609

1
AO4468L_SO8 470_0805_5% 36,44 SYSON# SYSON# SUSP
2 SUSP 5,48,55

6
1U_0603_10V6K
1

3
11/4 Change PN of U33 from SB000009580 to
Q44A 1
SB000009510
3

36,43,55 SYSON SYSON 2 Q44B


2N7002DW-T/R7_SOT363-6 5 C466
43,53,54,56,59 SUSP#
+12V1 1 2 Q37B 100P_0402_50V8J

1
1
2N7002DW-T/R7_SOT363-6 2

470P_0402_50V8J
R610 5 SUSP

4
1
47K_0402_5% 1 R629
6

1
C468 2N7002DW-T/R7_SOT363-6 R640
4

10K_0402_5% C465
Q37A 0.1U_0603_25V7K 10K_0402_5%

2
SUSP 2 2

2
2N7002DW-T/R7_SOT363-6
1

+0.75VS
+VCCSA

2
@
Discharge circuit

2
3 R606 3

470_0805_5% @
+1.5V R608
+VRAM_1.5VS +1.05VS_DGPU 470_0805_5%

1
@ PJ21

1
2

@ 2 2 1
+3VALW 1 +V_3.3V
2

R607
NON-PDH @ 470_0805_5% @ JUMP_43X118

1
R908 R907 D @ @ PJ22

1
470_0805_5% 470_0805_5% SUSP Q45 D
2 2 2
1 1 +3VSB
1

G SUSP 2 Q46
1 1

H8 @ S SSM3K7002FU_SC70-3 G JUMP_43X118

3
H_8P0N FM1 FM2 FM3 FM4 D @ @ PJ23
S

3
1

SUSP Q24 D D SSM3K7002FU_SC70-3


1 1 1 1 2 2 2
G SUSP Q23 SYSON# Q22 +5VALW 1 1 +V_5V
2 2
@ @ @ @ @ S G G JUMP_43X118
1

SSM3K7002FU_SC70-3 S S @ PJ24
3

SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 10/28 Add R645/Q48 +VGA_CORE 2 2


1 1 +5VSB
JUMP_43X118

2
@
Screw R645
470_0805_5%
H1 H2 H3 H4 H5 H6 8/24 Add C1031~C1036
H_3P5 H_4P0 H_4P0 H_4P0 H_3P5 H_4P0

1
+V_5V

@ @ @ @ @ @ 0.1U_0603_25V7K
1

1 1 1 1 @
D
C1031 C1032 C1033 SUSP 2 Q48
H7 H10 H11 H12 H13 H14 0.1U_0603_25V7K <EMI> <EMI> G
4 H_3P3 H_4P5 H_4P5 H_4P5 H_4P5 H_4P5 <EMI> 2 2 2 S SSM3K7002FU_SC70-3 4
3

0.1U_0603_25V7K
8/24 Place C1031/C1032/C1033 close to H4/H5/H7(EMI request)
@ @ @ @ @ @
1

+V_5V

0.1U_0603_25V7K
H15 H16 H17 H20 H18 H19
H_4P5 H_4P5 H_4P5 H_3P8 H_3P8 H_3P8 <EMI>
1
<EMI>
1
<EMI>
1 Security Classification Compal Secret Data Compal Electronics, Inc.
C1036 C1034 C1035 Issued Date 2010/07/20 2011/07/20 Title
0.1U_0603_25V7K
Deciphered Date
@ @ @ @ @ @ 2 2 2 DC Interface/Screw
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.1U_0603_25V7K AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.A
8/24 Place C1034/C1035/C1036 close to H1/H2/H6(EMI request)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 16, 2011 Sheet 47 of 63
A B C D E
A B C D E

Power Button
http://adf.ly/3o8pJ

+3VSB

1 1

2
R731 R856
ON/OFF switch 100K_0402_5%
100K_0402_5% @
46 ON/OFFBTN#

1
SW1 D39
EVQPLHA15_4P 2
3 1 ON/OFFBTN# 1 ON/OFF 43
3 PS_ON#
4 2 PS_ON# 51
DAN202UT106_SC70-3
@
5
6

1
D
EC_ON 2
43 EC_ON G Q53

2
S SSM3K7002FU_SC70-3

3
R732

10K_0402_5%

+1.05VS to +1.05VS_DGPU Transfer


PJ25
2 2 1 1

@ JUMP_43X118
2 +1.05VS_PCH +1.05VS_DGPU 2
U50 100mil(1.5A)
8 D S 1
7 D S 2

2
6 D S 3
5 4 1 1 R739
D G C881 C882 470_0603_5%
SI4856ADY_SO8 VGA@ VGA@ @
@ 10U_0805_6.3V6M

1
2 2
0.1U_0402_16V4Z
9/15 Change net name from +12V1 to +12V2
R737
510K_0402_1%

3
1 @ 2 1.8VSDGPU_GATE
+12V2

6
1 Q55B
C879 DMN66D0LDW-7 2N_SOT363-6 5 1 @ 2 SUSP
Q55A 0.1U_0603_25V7K @ R740 0_0402_5%
SUSP 1 @ 2 2 @

4
5,47,55 SUSP 2
R738 0_0402_5% @
DMN66D0LDW-7 2N_SOT363-6

1
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK/PBN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 16, 2011 Sheet 48 of 63
A B C D E
A B C D

http://adf.ly/3o8pJ
PH1 under CPU botten side :
CPU thermal protection at 92 degree C
Recovery at 57 degree C
PL1
HCB4532KF-800T90_1812
1 2 +12V1
1 1

VL
@ PJP1 PL2

1
LOTES_ABA-POW -005-K70 HCB4532KF-800T90_1812

1
2 1 ATX12V1 1 2 PR1
2 1 @ PC1 20.5K_0402_1%
4 3 .1U_0402_16V7K @

2
4 3

2
PC5 @ PR2

470P_0402_50V7K

470P_0402_50V7K

2
6 5 GND 10K_0402_1%
6 5

1
1000P_0402_50V7K

2
8 7 PC2 PC3 PC4
8 7 +5VSB 1000P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J PR3

1
PC31

PC36
9.53K_0402_1%
PU1 @
1 8

1
VCC TMSNS1

1
2 GND RHYST1 7

3 6 PH1 @
OT1 TMSNS2 100K_0402_1%_NCP15W F104F03RC
52 VS_ON
+3VSB 4 5

2
OT2 RHYST2
G718TM1U_SOT23-8
PR30
@
1 2 PSU_PG 52

1
PR31
0_0402_5% 100K_0402_1%
PR4 PSU_PG# 43

1 2
PS_ON#_1
1 2 PS_ON# 48 D
+3VSB +5VSB
2

0_0402_5% 2 +12V1 2
2

@ PR5 G
10K_0402_1% S PQ36

3
PJ16

2
SSM3K7002FU_SC70-3 S0 S3 S5 PR32
1 100K_0402_1% 1 2
1 2

2
+12V2 @ PR33
1

100K_0402_1%
@ JUMP_43X79

5
6
7
8
LOTES_ABA-POW -005-K70

1
@ 0
PJP2

1
8 8 7 7

1
D
6 6 5 5 4

1
470P_0402_50V7K

2
4 3 43,55 S3_1.5VEN G @ PC214 AO4407A_SO8

SSM3K7002FU_SC70-3
4 3
1

1
S 0.1U_0402_25V6K PQ49

2
2 1 PC13 PC47 PC171 PC15

3
2
1
2 1

PQ37
1000P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7K
2

2
PC37

@
S3 EN is LOW +1.5VIN

1
PD3
B340A_SMA2

2
3
+5VSB 3

PU2 PL3
PJ2
4

1UH_MMD-06CZ-1R0M-V1_11A_20%
2 1 10 2 LX_3VSB 1 2
+5VSB
PG

2 1 PVIN LX +3VSBP
JUMP_43X79

68P_0402_50V8J
9 PVIN LX 3
1

1
4.7_0603_5%
1

1
PC7
PC6 8
@ SVIN
PR6

22U_0805_6.3VAM PR7
6 60.4K_0402_1%
2

2
FB @

22U_0805_6.3VAM

22U_0805_6.3VAM
5
FOR EC suspend
2

EN

1
NC

NC
TP

PC8

PC9
FB_3VSB VFB=0.6V
Vo=VFB*(1+PR7/PR9)=3.318 V
11

2
1 2 EN_3VSB
1

JBATT1
1

PR8
680P_0603_50V7K

Ipeak=0.062A, Imax=0.045A
1

PC10

10K_0402_1% SY8033BDBC_DFN10_3X3 PR9


1

PR10 13.3K_0402_1%
2

10K_0402_1% PC11 Current limit >=4A


2

1U_0402_6.3V6K
2

1 2
+RTCBATT
2

+ -

PJ1 SUYIN_060003FA002G202NL

4 +3VSBP 1 1 2 2 +3VSB CONN@


4

JUMP_43X79
@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 16, 2011 Sheet 51 of 63
A B C D
5 4 3 2 1

http://adf.ly/3o8pJ
2VREF_8205

1U_0603_10V6K
D D

1
PC12

2
PR11 PR12
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2

PR13 PR14
20K_0402_1% 20K_0402_1%
1 2 FB3 FB5 1 2

8205_12V
8205_12V
+12V1
HCB4532KF-800T90_1812
1 2 +3VLP
PL4

ENTRIP1
PR15 PR16

ENTRIP2
4.7U_0805_25V6K

110K_0402_1% 147K_0402_1%
4.7U_0805_25V6K

4.7U_0805_25V6K

4.7U_0805_25V6K
1

1
PC169

1 2 1 2 +V_3.3VP

4.7U_0805_10V6K

1
PC16

PC170
PC14

1
10K_0402_1%

2
6

5
6
7
8
PC17
PU3

PR202
8
7
6
5

1
C PQ2 C

TONSEL
ENTRIP2

FB2

FB1

ENTRIP1
REF
PQ1 FDS8884_SO8
FDS8884_SO8 25

2
P PAD
35V_PG 43 4
4 7 VO2 VO1 24
PC19
PR17 8 23 0.1U_0603_16V7K
BST3A BST_3V VREG3 PGOOD
1 2 1 2 1 2 BST5A 1 2

3
2
1
2.2_0603_5% BST_5V 2.2_0603_5% PR18
9
FB=2V 22
1
2
3

PL5 PC18 BOOT2 BOOT1 PL6


4.7U_LF919AS-4R7M-P3_5.2A_20% 0.1U_0603_16V7K UG_3V 10 21 UG_5V 3.3UH_1164AY-3R3N-P3_7.5A_30%
UGATE2 UGATE1
1 2 1 2
+V_3.3VP LX_3V 11 20 LX_5V
PHASE2 PHASE1
1

8
7
6
5

5
6
7
8

1
+V_5VP
4.7_1206_5%

1000P_0603_50V7K 4.7_1206_5%
PR19

PR20
+5VSB LG_3V 12 19 LG_5V
PQ3 LGATE2 LGATE1

330U_6.3V_M
SKIPSEL
FDS6690AS_NL_SO8
330U_6.3V_M

Rds(ON) :Max=15m-ohm

VREG5
1 1
1

PC21
1SS355_SOD323-2
100K_0402_5%

GND
PD2
2

2
VIN
+ +
PC20

PR21

NC
EN
4 4
Min=12m-ohm 1 2
1

PC23
RT8205EGQW _W QFN24_4X4
1000P_0603_50V7K

13

14

15

16

17

18
2 2
PC22

@ PR22 PQ4
ESR=14m
2

100K_0402_5% FDS6690AS_NL_SO8
Imax=3.93 A
2

1
2
3

3
2
1

2
1 2
51 PSU_PG
Ipeak=5.62 A VL

1
200K_0402_5%

0.1U_0402_25V6K
Iocp=6.74 A

4.7U_0805_10V6K
B 51 VS_ON B
PR24

PC24

PC25
1 2
ESR=14m
2

2
@ PR23
2

0_0402_5%

8205_12V Rds(ON) :Max=15m-ohm

1
43 EC_3V5V_EN

.1U_0603_25V7K
fsw=375kHz 1 2 Min=12m-ohm

2
PC26
@ PR29 2VREF_8205
Iocp=delta I/2+Vtrip/Rds(on)=6.89A~9.72A 0_0402_5% Imax=5.15A
Ipeak=7.37A
Iocp=8.84A
Vo=2(1+Rt/Rb)=3.37 V
fsw=300kHz
@ PJ3
2 2 1
+V_3.3VP 1 +V_3.3V
JUMP_43X118 Iocp=delta I/2+Vtrip/Rds(on)=9.21A~12.99A
Vo=2(1+Rt/Rb)=5.09 V
@ PJ4
2 2 1
+V_5VP 1 +V_5V
A A
JUMP_43X118

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
+V_5VP/ +V_3VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 16, 2011 Sheet 52 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ
+V_3.3V
Ipeak=1.86A, Imax=1.3A

Vo=0.8(1+Rt/Rb)=1.827 V
Pd=3W

1
PJ5 +V_5V

1
D D
@ JUMP_43X79

2
2

1
PC27
1U_0402_6.3V6K

2
PC28
4.7U_0805_6.3V6K

1
PU4
6 @
VCNTL PJ6
5 3

2
PR25 9
VIN
VIN
VOUT
VOUT 4 +1.8VSP +1.8VSP 1 1 2 2 +1.8VS

1
0_0402_5%

22U_0805_6.3V6M
1
1 2 8 PR26 PC29
EN JUMP_43X79

1
43,47,54,56,59 SUSP#

PC30
7 2

GND
POK FB 1.54K_0402_1%

2
2

1
@ 0.01U_0402_25V7K

2
PR27 PC32

1
@ 47K_0402_5% .1U_0402_16V7K APL5930KAI-TRG_SO8

1
1

PR28
1.2K_0402_1%
FB=0.8V

2
C C

@ PJ8
2 2 1 1 +1.05VCCIO
JUMP_43X118

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K
1

1
PC175

PC176
PC33
Imax=6.2A

2
5
6
7
8
4.7U_0805_6.3V6K
PQ42
FB=0.8V +V_5V 1 2
FDS8884_SO8
Ipeak=8.8A
PR205
PU16
1 2 1 EN VCC 6
4
ESR=14 mohm
43,47,54,56,59 SUSP#

49.9K_0402_1% 2 GNDDRV 5
1

Vo=0.8(1+Rt/Rb)=0.928 V

3
2
1
PC34 3 4 1 2
1U_0402_6.3V6K FB POK +3VS
Pd=2.5W
2

PR250 10K_0402_1%
APL5610CI-TRG_SOT23-6 +VCCSAP
VCCSA_PG 43

1
PC35
47P_0402_50V8J PR208
1 2 0_0402_5%

B
1 @ PJ7 B

2
PR209 2 2 1
+ PC173 +VCCSAP 1 +VCCSA
1 2 1 2
330U_6.3V_M JUMP_43X118
PR203 4.7K_0402_1% 10_0402_5% VCCSA_SENSE 5
+3VS 2
1
@

PR207
+3VS
1

49.9K_0402_1%
@

PR210 PR204
10K_0402_1% 29.4K_0402_1%
2
1
@

PR212 PR206
2

2
6

10K_0402_1% 10K_0402_1% D
1 2 2
G
2

PR211
3

10K_0402_1% D S
1
1

5 VCCSA_VID 1 2 5 PQ43A
@

G PC174 DMN66D0LDW -7_SOT363-6


.1U_0402_16V7K
2
1

S
4
1
@

PR213
PR213
1K_0402_1%
.1U_0402_16V7K
@ PC189
2

@
2

PQ43B VCCSA_VID +VCCSAP


DMN66D0LDW -7_SOT363-6

0 0.925V(0.928V) Default
A A
1 0.85V(0.851V)

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
+VCCSA/+1.8VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 16, 2011 Sheet 53 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ
HCB4532KF-800T90_1812

+1.05V_12V2 2 1 +12V2
PL9

4.7U_0805_25V6K

4.7U_0805_25V6K

4.7U_0805_25V6K
1

1
PC45
D D

PC44

PC46
2

2
5
6
7
8
PQ9
FDS8884_SO8

FB=0.7v 4

PU19 PR251 PC215


1 10 BST_1.05V 1 2 BST_1.05V-1 1 2

3
2
1
PGOOD VBST
PR39
3,56,59 SUSP# 1 2 TRIP_VCCIO 2 TRIP DRVH 9 DH_1.05V 2.2_0603_5% 0.22U_0603_25V7K PL10
PR47 107K_0402_1% 1UH_MMD-10DZ-1R0M-X1A_18A_20%
1 2 EN_1.05V 3 8 LX_1.05V +V_5V 1 2
EN SW +1.05VCCIOP
0_0402_5%
4 VFB V5IN 7
1

1000P_0402_50V7K
390U 2.5V M ESR10
1
@ PC49 5 6 DL_1.05V

1U_0603_6.3V6M
TST DRVL 1

5
6
7
8
.1U_0402_16V7K PC190 PR48
2

1
4.7U_0603_6.3V6K +

PC51
4.7_1206_5%

PC207

PC208
11

2
TP

2
PR252

2
TPS51212DSCR_SON10_3X3

0_0402_5%

2
2

PR49
470K_0402_5%

1
4 PC52
2

1000P_0603_50V7K

1
C C
PQ10

3
2
1
FB_1.05V

IRF8736TRPBF 1N SO8

PR44
PR52
5.1K_0402_1% 10_0402_5%
2 1 2 1
VCCIO_SENSE 5

Vtrip range ==> 0.2V ~ 3V


2

<Vo=1.05V> VFB=0.7V
PR46
10.2K_0402_1%
V=0.7*(1+5.1K/10.1958K)=1.05V
VCCIO_SELECT +VCCIO Fsw=290KHz
1

(SandyBridge) 1.05V
Rds(ON) :Max=6.8m-ohm
(IvyBridge) 1.05V Min=5.5m-ohm
B Imax=11.17 A B
Ipeak=15.96 A
Iocp= 19.15A
1.05V, Iocp=delta I/2+Vtrip/Rds(on)=19.35A~28.4A

@ PJ10
2 2 1
+1.05VCCIOP 1 +1.05VCCIO
JUMP_43X118

@ PJ9
2 2 1
1 +1.05VS_PCH
JUMP_43X118
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
+1.05VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 16, 2011 Sheet 54 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ
HCB2012KF-121T50_0805
+1.5V_12V1 2 1 +1.5VIN
PL11

4.7U_0805_25V6K

4.7U_0805_25V6K

4.7U_0805_25V6K
D D

1
PC55

PC56
PC54
FB=0.7v

2
5
6
7
8
PQ12

FDS8884_SO8

2.2_0603_5%
PU18 PR248 PC195
1 10 BST_1.5V 1 2 BST_1.5V-11 2

3
2
1
PGOOD VBST
PR249
PR245 1 2 2 9 DH_1.5V 0.22U_0603_25V7K PL12
0_0402_5% TRIP DRVH 1.8UH_1164AY-1R8N=P3_9.5A_30%
68K_0402_1%
EN_1.5V 1 2 3 8 LX_1.5V 1 2
EN SW +5VSB +1.5VP
4 VFB V5IN 7
1

1
PC194 @ RF_1.5V DL_1.5V

1U_0603_6.3V6M
5 TST DRVL 6 1

5
6
7
8
1U_0402_6.3V6K PR61

560U_2.5V_M
2

1
+

PC199

PC61
11 PC188 PQ13 4.7_1206_5%
TP 1U_0402_6.3V6K

2
TPS51212DSCR_SON10_3X3

IRF8736TRPBF 1N SO8

2
2

1
4 PC63
1

1000P_0603_50V7K

2
PR53
C C
470K_0402_5%

3
2
1
2

PR172
PR171
10K_0402_1%
1 2 1 2

11.5K_0402_1% 36,43,47 SYSON

+3VSB
PR258
0_0402_5%
1 2 @ PJ11
2

100K_0402_5%

JUMP_43X118
1 1 2 2
PR256

PD4
2
1 EN_1.5V
1

@ 3 @ PJ12
JUMP_43X118
SSM3K7002FU_SC70-3
1

2
D @ RB715F_SOT323-3 +1.5VP 1 1 2 2 +1.5V
PQ38

2 PR259 @
43,51 S3_1.5VEN G 30K_0402_5%
S @
3

+1.5V
B Vtrip range ==> 0.2V ~ 3V B

Ipeak=10.24A Imax=7.168A
1

PJ14
Iocp >=1.2*Ipeak=12.3A
1

@ JUMP_43X79
<Vo=1.5V> VFB=0.7V
2

PU8 Vo=VFB*(1+Rtop/Rdown)=1.505V
2

1 VIN NC 8 +V_3.3V Fsw=290 KHz


Cout ESR=15m ohm Rdson(max)=6.8m ohm, Rdson(typ)=5.5 mohm
2 GND NC 7
1

PC64
1

4.7U_0805_6.3V6K 3 VREF VCNTL 6 PC65 Delta I=((19-1.5)*(1.5/19))/(1.8u*290 K)=?? A


PR65 1U_0603_6.3V6M
=>1/2DeltaI=??A
2

1K_0402_1% 4 5
VOUT NC Vtrip=Itrip*Rtrip, Iocp=Vtrip/(8*Rds(on))
9 Iocpmax=((95.3K*11uA)/(8*0.0055))+1.3233A=??A
2

TP
APL5336KAI-TRL_SOP8P8
Iocpmin=((95.3K*9uA)/(8*0.0068)+1.3233A=??A
Iocp=12.5A~18.2A
1

PR66 +0.75VSP
1

0_0402_5% D PR67
PC66

1K_0402_1%
.1U_0402_16V7K

5,47,48 SUSP 1 2 2
1

G
2
1

S PQ14 PC67
3

PC68 SSM3K7002FU_SC70-3 10U_0805_6.3V6M


2

@ .1U_0402_16V7K
Imax=0.28A
2

Ipeak=0.4A
A A
Pd=1.25w

@
PJ15
1 2
+0.75VSP 1 2 +0.75VS Security Classification Compal Secret Data Compal Electronics, Inc.
JUMP_43X79 Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
1.5VP/+1.2VALWP/+0.75VS
(?A,??mils ,Via NO.= ??) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
0.1
Date: Thursday, June 16, 2011 Sheet 55 of 63
5 4 3 2 1
A B C D

http://adf.ly/3o8pJ

1 1

PU17 DIS@
DIS@
DIS@ PL25 SY8033BDBC_DFN10_3X3 PL26

4
HCB1608KF-121T30_0603 1UH_MMD-06CZ-1R0M-V1_11A_20%
1 2 +VRAM_IN 10 2 LX_1.5VRAM 1 2
+V_5V

PG
PVIN LX +VRAM_1.5VSP

68P_0402_50V8J
9 PVIN LX 3

1
4.7_0603_5%
1

1
PC183
PC179 8 DIS@
SVIN

PR218

DIS@
22U_0805_6.3VAM PR221
DIS@ 6 60.4K_0402_1%

2
FB

DIS@

DIS@
@

22U_0805_6.3VAM

22U_0805_6.3VAM
5

2
EN

1
NC

NC
TP

PC184

PC204
FB_1.5VRAM

11

2
1 2 EN_1.5VRAM
43,47,53,54,59 SUSP#

1
68P_0402_50V8J

DIS@
PR215 DIS@ @ PJ30

680P_0603_50V7K
1

PC186
10K_0402_1% PR222

1U_0402_6.3V6K
+VRAM_1.5VSP 2 2 1 1 +VRAM_1.5VS

1
DIS@ PC182

PC185
DIS@ PR242 40.2K_0402_1%

2
10K_0402_1% JUMP_43X118

2
DIS@

2
@

2
2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VCCPP/1.8VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QLA01 M/B LA-7811P Schematic
Date: Thursday, June 16, 2011 Sheet 56 of 63
A B C D
A B C D E F G H

CPU CORE OCP: 90A-----65W


http://adf.ly/3o8pJ
CSSUM PR68 100K_0603_1%
2 1 CSP1
PR69 75K_0402_1%
2 1
CSCOMP PR70 165K_0402_1% 2 PR71 1 CSP2
2 1 100K_0603_1%
220K_0402_5%_ERTJ0EV224J
PC70 4.32K_0402_1% PC71 2 1 1 2 2 PR72 1 CSP3
PR73 100P_0402_50V8J PR74 2700P_0402_50V7K PH2 PC69 470P_0402_50V7K 100K_0603_1%
1 2 1 2 1 2 1 2 2 1
47_0402_1% PR75 24K_0402_1% 1 2

PR77 2
1K_0402_1%

4.7K_0402_1%
1 1
PC72 1200P_0402_50V7K

1500P_0402_50V7K

1
1 2 PC73
47P_0402_50V8J 820P_0402_25V7K

2 1
2 PR80 1 1 2 2 1 CSN1
2 1 10_0402_1% PR81
10_0402_1%
4700P_0402_25V7K PC74 CSN2

PC76

PR79
2 1

2
PR78 1K_0402_1% 1 PR83 2 1 2 PR82 10_0402_1%

1
412_0402_1% PC75 2 PR86 1 2 1 CSN3
1 2 1 2 8.2K_0402_1% PR87 10_0402_1%

1
2K_0402_1% 22K_0402_1% PR89
PR84 PR85 2 1 IMVP_IMON 43
PC77 0_0402_5% PC78

2
4700P_0402_25V7K 0.1U_0402_25V6K

ILIM
1 2
DIFFOUT
1 2 CPU CORE Imax: 75A
PR90 24K_0402_1%

COMP

2
PC79
1000P_0402_50V8J

CSREF 1
CSCOMP
DIFFOUT

FB

CSSUM
PR92
100_0402_1%
1 2

PR93 0_0402_5%

53

52

51

50

49

48

47

46

45

44

43

42

41

40
1 2 PU9 CSN2 CSN2 58

1
5 VSSSENSE 0.047U_0402_16V7K

GND

VSN

NC

NC
DIFFOUT

TRBST

IOUT

CSREF
FB

COMP

DROOP

CSCOMP
ILIM

CSSUM
PR94 0_0402_5% PC81 PC82
1 2 1000P_0402_50V8J 39 1 2 CSP2 CSP2 58
2

2
5 VCCSENSE CSN2 PR98 6.98K_0402_1%
1
43 VR_HOT# VSP CSN3 CSN3 58
38

1
@ PR96 51_0402_5% TSENSE CSP2 0.047U_0402_16V7K
+CPU_CORE 1 2 2
PR95 TSENSE PC83
1 2 37
100_0402_1% PR97 107_0402_1% CSN3 CSP3 CSP3 58
2 +1.05VCCIO 3 1 2 2

2
VRHOT# PR99 6.98K_0402_1%
1 2 36
CSP3 CSN1 58
+1.05VCCIO PR100 54.9_0402_1% 4 CSN1

1
SDIO
TSENSE 1 2 5 H_VIDSOUT 35 PC84
100K_0402_1%_NCP15WF104F03RC

CSN1 0.047U_0402_16V7K
5
SCLK
2

1 2 5 H_VIDSCLK 34 1 2 CSP1 CSP1 58


10.5K_0402_1%

+1.05VCCIO
0.1U_0402_25V6K

2
1

CSP1
PC85

@ PR102 75_0402_1% PR103 6.98K_0402_1%


PR101

6
ALERT#
2 5 H_VIDALERT# DRVON 58
PH3

1 33
PR104 10K_0402_1% NCP6131S52MNR2G_QFN52_6X6 DRON
+3VS 7
2

VR_RDY PWM1 PWM1 58


32
1

13,43 VGATE PWM1/ADDR


8
VR_RDYA PWM3 PWM3 58
1 2 31
43 VR_ON PR105 0_0402_5% PWM3/VBOOT
9
ENABLE PWM2 PWM2 58
30
PWM2
+V_5V 10
VCC IMAX
1 2 1 2 29
PR107 9.09K_0402_1% IMAX
11
PR106 2.2_0603_5% ROSC PWMA PWMA 58
1 2 28
TSENSEA PWMA/IMAXA
12 2 1 +V_5V
VRMP

CSCOMPA
DIFFOUTA
PC86 1U_0603_6.3V6M 27

DROOPA

CSSUMA
VBOOTA

TRBSTA

COMPA
1 2 TSENSEA 13 1K_0402_1% PR108 DIS@ PR167 PWM3 PWMA
100K_0402_1%_NCP15WF104F03RC

+CPU_12V2

IOUTA
TSENSEA

CSNA
VSNA

CSPA
VSPA

ILIMA
DIS@ 0_0402_5%

FBA
2

PR109 1K_0402_1% 1 2 1 2 2 1
10.5K_0402_1%

0.1U_0402_25V6K
1

UMA@ PC88

PR111
PR110
PH4

PC87 0.01U_0402_50V7K 10K_0402_1% UMA@ UMA@ PC89 VCORE


14

15

16

DIFFOUTA17

18

19

20

21

CSCOMOA22

23

CSSUMA 24

25

26

1
1000P_0402_50V8J UMA@

10K_0402_1%
VBOOT
2

PR114 V_GT PR113

PR112
UMA@
UMA@1 2
1

SET AT
UMA@

DIS@ PR168 27.4K_0402_1%


FBA

IMAX SET
COMPA
PR169 UMA@ 0_0402_5% 0V
UMA@ DIS@ UMA@ PR114 0_0402_5% 2 1 CSNA 58 AT 35A

2
1
100_0402_1% 2 1 UMA@ PC90
680P_0402_50V7K

1 2 0.047U_0402_16V7K
1

0_0402_5% UMA@ PR117 UMA@ 1 2 CSPA CSPA 58

2
PR116 UMA@ PR115
PR110 5 VGFX_VSSSENSE 1 2 8.06K_0402_1% 2 1 6.98K_0402_1%
UMA@ PR118 0_0402_5%
2
GFXVR_IMON 43
PC93

UMA@ 0_0402_5%
25.5K_0402_1%
2

DIS@ 47_0402_1% UMA@ PR119 23.2K_0402_1% PR119


PR125
2

3 3
UMA@ PR122 UMA@ 2 1 PWM1 IMAX
1

PR164 UMA@ PC91 1 2 2 1


0_0402_5% 0_0402_5% 1000P_0402_50V8J 2 1 DIS@
4700P_0402_25V7K

DIS@ UMA@ PC95


2

.1U_0402_16V7K
220P_0402_50V7K
1

1
0_0402_5% UMA@ UMA@ 0_0402_5% VCORE
PC94 22P_0402_50V8J

1 2 UMA@ PR124 PWM PR127


UMA@

1.82K_0402_1%

IMAX SET
1

5 VGFX_VCCSENSE PR120 PR126 59K_0402_1%


UMA@ PR131 UMA@ PC96

1 2 ADDRESS AT 75A
PC92

2K_0402_1% UMA@ PC97 10K_0402_1%


1

PR128 UMA@ PR129 820P_0402_25V7K UMA@ PR130


2

2
+VGFX_CORE 1 2 UMA@ 2 1 1 2 2 1CSNA
UMA@

PR121 10_0402_1% 10_0402_1%


PR166 0_0402_5%
2
1

100_0402_1% DIS@
2

UMA@ PC98 UMA@ UMA@ PR132


1
2

1000P_0402_50V7K
PR123

UMA@ PR128

2 1
1K_0402_1%
4.53K_0402_1%
2

0_0402_5% 3.3K_0402_1%
1

1
1

UMA@ PC100 UMA@


1

1000P_0402_50V7K
1

2
UMA@ PR135
75K_0402_1%
DIS@

CSCOMOA

FBA 2 1 PR137 UMA@


UMA@ PR136 43.2K_0603_1%
2 1 CSSUMA 2 1CSPA
220P_0402_50V7K
2

165K_0402_1%
PC99

2 1
UMA@ PR133 1K_0402_1%

UMA@ PC101
1

UMA@ 220K_0402_5%_ERTJ0EV224J 1 2
UMA@ PH5
330P_0402_50V7K
2

UMA@ PC102
1 2
1
PR134
47_0402_1%

1200P_0402_50V7K
DIS@ PR165
1

2 1
UMA@

4 0_0402_5% 4
DIFFOUTA

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE_1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 16, 2011 Sheet 57 of 63
A B C D E F G H
5 4 3 2 1

HCB4532KF-800T90_1812
PL17
http://adf.ly/3o8pJ +CPU_12V2
1 2

FDMS7696A_POWER56-8-5
+12V2 HCB4532KF-800T90_1812

PC105
PL18

10U_1206_25V6M
1U_0805_25V6K
1 2

FDMS7696A_POWER56-8-5
+CPU_12V2 PC103

1
470P_0402_50V7K

1000P_0402_50V7K
1 1 1

PC104
BST_CPU1A PQ15 PQ16 PC106

10U_1206_25V6M
1 1 2

1
+ + + @ 10U_1206_25V6M

2
PC131

PC197

PC198
PC196 PC132 PC133 PC134
470P_0402_50V7K 220U_16V_M 220U_16V_M 220U_16V_M PR138 0.22U_0603_25V7K
2

2
2 2 2 2.2_0603_1% PU10 4 4

DH_CPU1
D D
1 2 BST_CPU1 1 BST FLAG 9

FDMS7696A_POWER56-8-5
+CPU_12V2
+CPU_CORE
2 8 DH_CPU1 PL13
57 PW M1 PWM DRVH 0.36UH_FDU1040J-H-R36M=P3_33A_20%

3
2
1

3
2
1
57 DRVON 2 PR1401 4.02K_0402_1%
3 7 LX_CPU1 1 4
EN SW

PC117
@

10U_1206_25V6M
1U_0805_25V6K
2 1 4 6 2 3

FDMS7696A_POWER56-8-5
PC115 VCC GND

5
PQ24

470P_0402_50V7K
+V_5V

PC116
BST_CPU3A 1 2 PQ23 PC118 PR141 5 DL_CPU1 PQ19 PQ20
DRVL

1
FDMS0309S_POWER56-8-5
10U_1206_25V6M

PC201
2.2_0402_1%

2
NCP5911MNTBG_DFN8_2X2

4.7_1206_5%
0.22U_0603_25V7K

1
PR146

DH_CPU3

2
PR144
2.2_0603_1% PU12 4 4 PC111 4 4
1 2 BST_CPU3 1 9 1U_0603_25V6K

2
BST FLAG
<BOM Structure>

1
57 PW M3 2 8 DH_CPU3 PL15
PR147 4.02K_0402_1% PWM DRVH 0.36UH_FDU1040J-H-R36M=P3_33A_20%

3
2
1

3
2
1

3
2
1

3
2
1
57 DRVON DRVON 2 LX_CPU3

1000P_0603_50V7K
1 3 EN SW 7 1 4 +CPU_CORE

PC113
2 1 4 6 PQ28 2 3 FDMS0309S_POW ER56-8-5
VCC GND

470P_0402_50V7K

0.1U_0402_25V6K
+V_5V

2
1
PR148 5 DL_CPU3
DRVL

1
2.2_0402_1% 57 57 CSP1 CSN1

PC200

PC210
NCP5911MNTBG_DFN8_2X2

4.7_1206_5%

2
1

2
PR149
PC123 4 4

FDMS7696A_POWER56-8-5
1U_0603_25V6K +CPU_12V2
2

1
3
2
1

3
2
1
@

1000P_0603_50V7K
1
C C

PC124

FDMS7696A_POWER56-8-5
PC107

PC109
PQ27 PQ18

10U_1206_25V6M
1U_0805_25V6K
1

1
BST_CPU2A 1 2 PQ17

PC108
57 57 CSP3 CSN3 PC110
FDMS0309S_POW ER56-8-5 FDMS0309S_POW ER56-8-5 10U_1206_25V6M

2
PR139 0.22U_0603_25V7K

DH_CPU2
2.2_0603_1% PU11 4 4
1 2 BST_CPU2 1 BST FLAG 9
+CPU_CORE
2 8 DH_CPU2 PL14
57 PW M2 PWM DRVH 0.36UH_FDU1040J-H-R36M=P3_33A_20%

3
2
1

3
2
1
2 PR142 1 3 7 LX_CPU2 1 4
UMA@ 57 DRVON 4.02K_0402_1%EN SW
2 1 4 VCC GND 6 2 3

5
HCB4532KF-800T90_1812 +CPU_12V2
PL22 @ PJ31 +V_5V PR143 5 DL_CPU2 PQ21 PQ22
+GFX_12V2 2 2.2_0402_1% DRVL

470P_0402_50V7K
1 2 1

<BOM Structure>
FDMS0309S_POWER56-8-5

FDMS0309S_POWER56-8-5
2 1

2
UMA@ 10U_1206_25V6M NCP5911MNTBG_DFN8_2X2

4.7_1206_5%
1

1
PC128 UMA@

PC130 UMA@

JUMP_43X118
1U_0805_25V6K

PC127
5

PR145

PC202
UMA@ PC112 4 4
BST_GFXA 1 2 PC129 UMA@ PC209 1U_0603_25V6K

2
10U_1206_25V6M 0.1U_0402_25V6K
2

1
PR154 UMA@ 0.22U_0603_25V7K

3
2
1

3
2
1
2.2_0603_1% PU14 UMA@

1000P_0603_50V7K
4

PC114
1 2 BST_GFX 1 BST FLAG 9
UMA@ PQ31
57 PW MA 2 8 DH_GFX FDMS7696A_POW ER56-8-5 PL19 UMA@

2
UMA@ PR155 PWM DRVH 0.36UH_FDU1040J-H-R36M=P3_33A_20%
3
2
1

57 DRVON DRVON
2 1 3 7 LX_GFX 1 4
EN SW +VGFX_CORE
4.02K_0402_1% 57 57 CSP2 CSN2
B 2 1 4 6 2 3 B
VCC GND
5

+V_5V
PR156 5 DL_GFX
2.2_0402_1% DRVL FDMS0309S_POW ER56-8-5
2

UMA@ NCP5911MNTBG_DFN8_2X2
4.7_1206_5%
1

PQ34 UMA@
UMA@

PR157

PC135 4
1U_0603_25V6K
2

UMA@
1
3
2
1

1000P_0603_50V7K
1

UMA@ PC136

57 57 CSPA CSNA
2

VGFX:
Cout ESR= m ohm Rdson=3~3.6m
Ipeak=35 A, Imax=25 A
Delta I=7A

OCP= 40 A

A CPU_CORE: A

Cout=22U*18+ 390u 10m*4+560u 10m*3 +330u 9m*3 +560u 15m*2


Rdson=3~3.6m
Ipeak= A, Imax=85 A
F=338k hz
Delta I= Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title
OCP= 135 A CPU_CORE_2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 16, 2011 Sheet 58 of 63
5 4 3 2 1
5 4 3 2 1

http://adf.ly/3o8pJ HCB4532KF-800T90_1812

+VGA_12V2 2 1 +12V2
PL21 DIS@

+3VS

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
1

1
PC139
PQ11 DIS@

PC137

PC142

PC144
D D

2
FDMS7696A_POWER56-8-5
5
1
DIS@
PR235
100K_0402_5%
DIS@ DIS@
PC53 4 DIS@ DIS@ DIS@ DIS@
PR161

2
BST_VGA 1 2 1 2
2.2_0603_5%
VGA_PG PU15 0.22U_0603_25V7K
DIS@ 1 10

3
2
1
PGOOD VBST
PR57
1 2 TRIP_VGA 2 9 UG_VGA DIS@
TRIP DRVH PL20
DIS@ PR158 27.4K_0402_1%
1 2 EN_VGA 3 8 SW _VGA 1 4
43,47,53,54,56 SUSP# EN SW +VGA_CORE
100K_0402_1%
FB_VGA 4 7 +V_5V 2 3
VFB V5IN +V_5V
1

1000P_0402_50V7K
FDMS0309S_POWER56-8-5
DIS@ PC140 RF_VGA 5 6 LG_VGA

1U_0603_6.3V6M
TST DRVL 0.36UH_FDU1040D-R36M_26A_20% 1 1

1
.1U_0402_16V7K DIS@

560U_2.5V_M

560U_2.5V_M
2

1
+ +

DIS@ PC141

PC143

PC205

PC206
TP 11

PQ35
PC62 PR159 DIS@

2
TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M 4.7_1206_5%

0_0402_5%
2

2
DIS@ 2 2 @

PR160
2
DIS@ 4 4
1

1
DIS@ PC138 DIS@ DIS@

1
PR162
1000P_0603_50V7K
470K_0402_5% DIS@

3
2
1

3
2
1

2
C DIS@ C
ESR=10m ohm
2

PQ32
FDMS0309S_POW ER56-8-5
PR54 DIS@
PR56 DIS@
2.87K_0402_1% 10_0402_5%
2 1 2 1
VGA_SENSE 21

+3VS
1

DIS@
PR225
2

1
13.3K_0402_1%
DIS@ PR228
13.3K_0402_1%

10K_0402_1%
DIS@

2
PR55

DIS@
DMN66D0LDW-7_SOT363-6

PR226
1

2
3

D 47K_0402_1%
PQ47B

5 2 1 GPU_VID1 22
G

DIS@ S DIS@
2200P_0402_50V7K
4

DIS@ PR163
10_0402_5%
PC177

B B
2 1
2

21 GND_SENSE
1

DIS@
PR231 VFB=0.7V
86.6K_0402_1% +3VS
Fsw=290 KHz
2

DIS@
PR234
PQ47A DIS@ 47K_0402_1% Cout ESR=10m ohm/2 Rdson=1.5~1.8m ohm
DMN66D0LDW -7_SOT363-6
DIS@ PR233 Ipeak=17.8A, Imax=14.46 A Iocp=21.36A
2
6

D 10K_0402_1%
2 2 1 GPU_VID0 22 Iocp=Vtrip/(Rdson*8)+1/2delta I
G
=21.61A~29.6A
2200P_0402_50V7K

S
1

PC178
2

DIS@
GPU_VID1 GPU_VID0 VGA_CORE
0 0 0.85V (Default)
1 0 1V
A A
1 1 1.025V

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/07/20 Title
2010/07/20 Deciphered Date
VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 16, 2011 Sheet 59 of 63
5 4 3 2 1

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