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    Arithmetic Processor: 10-2 Addition and Subtraction

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    Sarbesh Chaudhary
    This is the lecturer notes for Personal Computer Organization or simply Computer Organization which is helpful for electronics and communication or computer engineering students

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    Arithmetic Processor: 10-2 Addition and Subtraction

    Uploaded by

    Sarbesh Chaudhary
    124 views9 pages
    This is the lecturer notes for Personal Computer Organization or simply Computer Organization which is helpful for electronics and communication or computer engineering students

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    This is the lecturer notes for Personal Computer Organization or simply Computer Organization which is helpful for electronics and communication or computer engineering students

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    124 views9 pages

    Arithmetic Processor: 10-2 Addition and Subtraction

    Uploaded by

    Sarbesh Chaudhary
    This is the lecturer notes for Personal Computer Organization or simply Computer Organization which is helpful for electronics and communication or computer engineering students

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    Arithmetic processor

    
    The four basic arithmetic operations in computers are: Addition, Subtraction, Multiplications, and
    Division.
     Arithmetic processor is part of processor unit and it executes arithmetic operations.
     Arithmetic instructions specify data type binary or decimal , fixed point or floating point
     Fixed point numbers represents integers while floating point numbers represent fractional
    numbers.
     Negative numbers may be in signed magnitude or signed complement representation.
     Fixed point binary signed magnitude
     Fixed point binary 2’s complement
     Floating point binary
     Floating point BCD
    10-2 Addition and Subtraction
    1. Signed magnitude

    It Is familiar as used in every day arithmetic calculations .We designate magnitudes of two numbers
    as A and B. when those sign numbers are added we have eight different conditions depending on the
    sign bits and operations performed. Next table shows those conditions and other columns shows
    operations performed.


    Addition (Subtraction) Algorithm will be as
     When A and B have identical (different) signs, add the two magnitudes and attaché sign of A to result
     When signs of A and B are different (same), subtract smaller number from larger number. Choose sign
    of result as sign of A if A>B, or complement of sign of A if A<B.
     If two magnitudes are equal, subtract B from A and make sign of result positive.

    Hardware Implementation
     The two numbers are stored in registers A and B and their signs in flip-flops As and Bs. Result is
    transferred to A register with its sign

    1|Page
     Next figure the hardware of signed magnitude addition-subtraction. Consists of registers A and B, sign
    bits As and Bs
     Complementer can pass value of B or invert of B according to value of M (implemented with EX-OR).
     AVF holds overflow bit when A and B are added.
     The addition of A and B will be through parallel adder.

     When M=0, B is transferred to adder with A and output in A = A + B. while M=1 complement of B plus
    carry=1 is transferred to adder with A and output A = A – B.

    The algorithm is shown in next figure


     The two signs As and Bs are compared by EX-OR them. If result is 0 then As = Bs and if result is
    1 the
     As ≠ Bs.
     For add operations if have same sign bits the magnitude must be added. For subtract
    operations different sign bits means magnitudes be added as well.
     E bit is carry bit after addition and moves to AVE overflow bit only at this state.
     If sign bits are different in add operations or the same in subtract operations the two
    magnitudes will be subtracted A – B. No overflow can occur here.
     After subtract if E=1 this means A>B and if E=0 then A<B. then here it is necessary to get 2’s
    complement of A (by invert A then add 1) and sign of A is inverted only in this case.
     Final result will be in A and its sign in As.

    2|Page
    Figure: flow chart for add and subtract algorithm

    2. Signed 2’s complement

     The left most bit in 2’s complement represented binary number is the sign bit. If 0 the number is
    positive and if 1 then number is negative. If sign bit is 1 the entire number is represented in 2’s
    complement.
     The addition of two numbers represented in 2’s complement is carried out by normal binary addition
    with carry discarded.
     The subtraction is carried out by taking 2’s complement (B) of subtrahend and adding it to minuend
    (A).
     Overflow can be detected by inspecting last 2 carries out of addition by EX-OR them. If different then
    overflow is detected.
     For addition simply implement add then see overflow. For subtract add 2’s complement of B to A and
    watch overflow since the A and –B could be of same sign.

    3|Page
    Figure: algorithm for adding and subtracting numbers in signed 2’s complement representation

    Multiplication Algorithms
     The multiplication of two numbers in signed magnitude representation is carried out by successive shift
    and adds.
     Look at successive bits of multiplier (least significant bit first), if bit=1 multiplicand is copied else if
    bit=0, zero is copied down shifted one bit to left from previous copies. Finally all numbers are added
    and their sum forms the product.

    Hardware Implementation

    4|Page
     It is necessary to supply adder for summation two binary numbers and successively accumulate the
    partial products in a register.
     Instead of shifting multiplicand to the left the partial product is shifted to the right.
     When corresponding bit of multiplier is 0 no need to add zeros to partial product, just do nothing.
     Hardware for multiplication consist of complementer and parallel adder, Registers A and B with their
    sign bits As and Bs, multiplier Q register, and its sign in Qs. SC is set to number of bits in multiplier and
    when reaches zero it means partial addition has finished and product is ready in A.
     Multiplicand in A register while multiplier in Q register initially. The sum of A and B is the partial
    product in EA. A and Q registers are shifted together giving rise to new bit from Q in Qn bit which tells
    us if that bit is 0 or 1.

    Algorithm
     Signs of Qs and Bs are compared then As and Qs are set as sign of the product. A and E bit are cleared
    with SC set to number of bits in Q
     Low order bit in Q is tested. If Qn=1 then B is added to A. if Qn=0 then nothing is done.
     Registers EAQ are shifted to the right.
     SC is decremented.
     Process stops when SC=0.
     Note that product is occupying A and Q registers and after each shift it replaces A and Q registers.

    Example:
    Multiplicand(B)=23(1011)
    Multiplier(Q)=19(10011)

    5|Page
    Figure : flow chart for multiply operation
    6|Page
    Booth multiplication algorithm
    Booth Multiplication Algorithm gives procedures for multiplying binary integers in signed‐2’s complement
    representation. It operates on the fact that strings of 0’s in the multiplier requires no addition but just
    shifting and a string of 1’s in the multiplier from bit weight 2k to weight 2m can be treated as 2k+1-2m.
    Booth algorithm requires examination of the multiplier bits and shifting of the partial product.
    Rules for booth algorithm:
     Qn-LSB of multiplier
     Extra flip flop Qn+1is appended to the multiplier bits to facilitate
    double bit inspection of the multiplier.
     Compare bits of Qn and Qn+1l
    1. The multiplicand is subtracted from partial product upon
    encountering the first least significant 1 in a string of 1’s in the
    multiplier.
    1. The multiplicand is added to the partial product upon
    encountering the first 0 in a string of 0’s in the multiplier.
    2. The partial product doesn’t change when the multiplier bit is
    identical to the previous multiplier bit.
    Ex:
    0 0 –shift only
    1 1 –shift only
    0 1 –Add multiplicand to AC and shift
    1 0 –Subtract multiplicand from AC and shift
     Initial value of Sequence counter specifies the number of cycles to complete the algorithm.
     QR –contents of multiplier, BR –contents of multiplicand
     Combined contents of AC and QR gives the product depending on the operands’ sign.h

     Figure: hardware implementation for booth algorithm

    BR register Sequence counter(SC)

    Complementer and parallel adder


    Qn+1
    Qn

    AC register QR register

    7|Page
    Example of booth algorithm: (-9)X(-13)=+117, number of bit(n)=5 ,QR=multiplier, BR=multiplicand

    Table: booth algorithm

    Qn Qn+1 BR=10111 AC QR Qn+1 SC


    BR~+1=01001
    - initial 00000 10011 0 101
    10 Subtract BR -01001
    01001
    ashr 00100 11001 1 100
    11 ashr 00010 01100 1 011
    01 Add BR +10111
    11001
    ashr 11100 10110 0 010
    00 ashr 11110 01011 0 001
    10 Subtract BR -01001
    00111
    ashr 00011 10101 1 000
    8|Page
    The product appears in AC and QR .

    The final value of Qn+1 is the original sign bit of the multiplier and should not be taken as part of the
    product.

    9|Page

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