UNIT V - VHDL

RTL Design – Combinational logic – Sequential circuit – Operators – Behavioral, Dataflow, and structural modeling-

Introduction to Packages – Subprograms – Test bench. (Simulation /Tutorial Examples: adders, counters, flip flops,

Multiplexers & De multiplexers).

VERY HIGH SPEED HARWARE DESCRIPTION LANGUAGE (VHDL)

VHDL coding for Arithmetic circuits

 VHDL – VERY HIGH SPEED HARDWARE DESCRIPTION LANGUAGE
• All keyword in VHDL are reserved (of , is). They cannot be used for any other purpose.
• All keywords in VHDL are CASE SENSITIVE.

• Statement : library. ieee ; use.std_logic_1164. all – indicates that the VHDL program can use all the definitions
of IEEE standard 1164 logic package developed by IEEE to satisfy the requirements of the most of the designers.

• Signal declaration used for providing wire (internal connection) in a circuit. It is similar to port except that no
modes (in and out) need to be specified.

• Pre defined data types such as bit and bit _vector, STD_LOGIC, STD_LOGIC_Signed and STD_LOGIC_Unsigned
can be used with the signal declaration.

• bit data type can have values of 0 and 1.

• bit_vector data type is used to define a binary number. bit_vector(3 downto 0); bit 3 and 0 defines the MSB and LSB
of a 4 bit number respectively.
• STD_LOGIC – provide several data types 0, 1, Z (High impedance state) and – (don’t care conditions).

• VHDL provides a wait statement – used in a test program to stop an operation for a specified period of time.
 Each VHDL description contains two blocks - an Interface and a body
The interface – ENTITY, Body - ARCHITECTURE
The ENTITY description specifies the input and output connections (ports) to the hardware.
The architectural component defines the behavior of the hardware entity being designed.

Coding syntax of VHDL file

The entity declaration has a ENTITY NAME and an END.
< include the library files >
The entity name “ “ appears in the END statement also. entity <entity name> is
After PORT is an open parenthesis ; the closing parenthesis is <Define the I/O Ports >
end <entity name>;
after OUT BIT and before the semicolon.
architecture Behavioral of <entity name> is
< include the library files > <Define or declare the intermediate signals>
begin
entity Half adder is --------- ENTITY STATEMENT
Port --------- PORT STATEMENT <VHDL Coding >;
process
( X,Y : in bit ;
< VHDL Signal Sensitive Coding >;
Z : out bit ) ;
end Half adder
end process;
end Behavioral;
 Designing a system using HDL such as VHDL
Two basic levels of abstractions or modeling are used
Structural modelling and Behavioral modeling
• Behavioral modeling – Used to describe what the system does and how it behaves; Uses both concurrent and
sequential statements

• Structural modeling – used to describe a schematic or a logic diagram

• Dataflow modeling – is behavioral modeling with concurrent statement.

Behavioral modeling architecture Behavioral of <entity name> is

<Define or declare the intermediate signals>
The behavioral model contains statements that are executed sequentially begin
in a predefined order. <VHDL Coding >;
process
The sequential statements are defined using a process statement inside
< VHDL Signal Sensitive Coding >;
an architecture body
end process;
end Behavioral;
• Following the ENTITY statement is the ARCHITECTURE body. < include the library files >
• It declares the relationship between the inputs and outputs. entity <entity name> is
• ARCHITECTURE has a BEGIN and an END <Define the I/O Ports >
end <entity name>;
• Variable assignment inside a process are denoted by : =
• Signal assignment is denoted by the operator <= architecture Behavioral of <entity name> is
• Each equation ends with a semicolon.
<Define or declare the intermediate signals>
begin
• The END statement ends with a semicolon.
<VHDL Coding >;
The general form of process statement process
architecture Behavioral of <entity name> is < VHDL Signal Sensitive Coding >;
begin end process;
Process (Sensitivity list) end Behavioral;
Process declaration
List of sequential statements such as signal assignment, variable assignment • The sensitivity list includes signals to

and if statements. which the process is sensitive - the process

end process; will be executed as soon as any changes in

end Behavioral; the values of these signals occur.

 VHDL Coding for Half adder - Behavioral Modelling

entity Halfaddermain is -- Stimulus process

Port ( x : in STD_LOGIC; stim_proc1 : process
x S y : in STD_LOGIC; begin
s : out STD_LOGIC; x <= not x;
C c : out STD_LOGIC); wait for 100 ns;
y
end Halfaddermain; end process;

ഥ𝒚 + 𝒙ഥ architecture Behavioral of Halfaddermain is stim_proc2 : process

𝑺=𝒙 𝒚
begin begin
𝑪 = 𝒙𝒚 s <= x xor y; y <= not y;
c <= x and y; wait for 50 ns;
end Behavioral; end process;
END;
VHDL Coding for Half adder – Behavioral Modelling
Verification using TEST BENCH

x y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
 VHDL Code for Full adder - Behavioral Modelling

x X1
y S X1 < = x xor y
x z
S < = X1 xor z Output signals
x A1
y y A1 < = x and y

A2 A2 < = x and z
z x Intermediate or Local signals
z C A3 < = y and z

y C < = (A1 or A2) or A3

z A3

𝑺= 𝒙⊕𝒚⊕𝒛
𝑪 = 𝒚𝒛 + 𝒙𝒛 + 𝒙𝒚
 VHDL Code for Full adder - Behavioral Modelling

entity FAmain is -- Stimulus process

Port ( x, y, z : in bit ; s , c : out bit ) ; stim_proc1 : process
end FAmain; begin
x <= not x;
architecture Behavioral of FAmain is wait for 150 ns;
Signal X1,A1,A2,A3 : bit end process;
begin stim_proc2 : process
X1 < = x xor y ; begin
X1 < = x xor y y <= not y;
S < = X1 xor z ; wait for 100 ns;
S < = X1 xor z
A1 < = x and y;
A1 < = x and y stim_proc3 : process
A2 < = x and z ; begin
A2 < = x and z A3 < = y and z ; z <= not z;
wait for 50 ns;
A3 < = y and z C < = (A1 or A2) or A3 ; end process;
C < = (A1 or A2) or A3 end Behavioral; END;
VHDL Code for Full adder – Behavioral Modelling
Verification using TEST BENCH

x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
 VHDL Code for Full Subtractors – Behavioral Modelling

entity FSBM is
-- Stimulus process
Port ( x, y, Bin : in bit ; D , Bout : out bit ) ;
stim_proc1: process
end FSBM; begin
x <= not x;
architecture Behavioral of FSBM is
wait for 300 ns;
Signal X1, N1L, N2L, A1,A2: bit end process;
𝒙 X1L
begin
stim_proc2: process
𝒚 D X1 < = x xor y ; begin
y <= not y;
𝑩𝒊𝒏 N2L
A2L
D < = X1 xor Bin ;
wait for 150 ns;
N1L
N1L <= not x; end process;
B N2L <= not X1L;
A1L stim_proc3: process
A1 < = N1L and x; begin
Bin <= not Bin;
A2 < = N2L and Bin ;
wait for 50 ns;
Bout < = A1L or A2 L; end process;
END;
end Behavioral;
VHDL Code for Full Subtractors – Behavioral Modeling
 VHDL Code for 4 bit adder– Behavioral Modeling
stim_proc: process
entity fourbitadder is begin
Port ( Cin : in STD_LOGIC;
X : in STD_LOGIC_VECTOR (3 downto 0); wait for 100 ns;
Y : in STD_LOGIC_VECTOR (3 downto 0); X <= "0110";
Cout : out STD_LOGIC; Y <= "1100";
S : out STD_LOGIC_VECTOR (3 downto 0));
end fourbitadder; wait for 100 ns;
X <= "1111";
architecture Behavioral of fourbitadder is Y <= "1100";

Signal C: STD_LOGIC_VECTOR (4 downto 0); wait for 100 ns;

X <= "0110";
begin Y <= "0111";

C(0)<= Cin; wait for 100 ns;

S <= X xor Y xor C (3 downto 0); X <= "0110";
C(4 downto 1) <= (Y and C(3 downto 0)) or (X and C (3 downto 0)) or ( X and Y); Y <= "1110";
Cout <= C(4);
wait for 100 ns;
end Behavioral; X <= "1111";
Y <= "1111";

𝑺 = 𝒙 ⊕ 𝒚 ⊕ 𝑪𝒊𝒏 𝑪 = 𝒚𝑪𝒊𝒏 + 𝒙𝑪𝒊𝒏 + 𝒙𝒚 wait;

end process;
VHDL Code for 4 bit adder/Ripple adder – Structural Modeling
Verification using TEST BENCH
 STRUCTURAL MODELING
• Full Adder
• Full Subtractor
• 4 bit Binary/Parallel /Ripple Adder
Structural modeling – used to describe a schematic or a logic diagram
 VHDL Code for Full adder - Structural Modeling
entity XorGate is
port(X,Y: in bit; Z: out bit);
end XorGate;
x X1 architecture Behavioral of XorGate is
begin
y S Z <= X xor Y;
x z end Behavioral;
• XOR gate
x A1 entity AndGate is
• AND gate
y y port(X,Y: in bit; Z: out bit);
• Three input OR gate end AndGate;
z x A2 architecture Behavioral of AndGate is
C begin
z Z <= X and Y;
end Behavioral;
y
z A3 entity OrGate is
port(X,Y,W: in bit; Z: out bit);
end OrGate;
architecture Behavioral of OrGate is
begin
Z <= (X or Y)or W;
end Behavioral;
 entity FA is
Port ( x, y, z : in bit; S, C : out bit);
end FA;
STRUCTURAL MODELING architecture Structural of FA is
component AndGate
port(X,Y: in bit; Z: out bit);
end component;
x X1
component OrGate
y S port(X,Y,W: in bit; Z: out bit);
x z end component;
x A1 component XorGate
y y port(X,Y: in bit; Z: out bit);
end component;
z x A2
C signal X1, X2 ,A1, A2, A3: bit;
z
Begin
y
z A3 X1:XorGate port map(x, y, X1);
X2:XorGate port map(X1, z, S);
A1:AndGate port map(x, y, A1);
A2:AndGate port map(x, z, A2);
A3:AndGate port map(y, z, A3);
Describe a schematic or a logic diagram O1:OrGate port map(A1, A2, A3, C);

end Structural;
entity FA is
Port ( x, y, z : in bit; S, C : out bit);
end FA;
architecture Structural of FA is
entity XorGate is Structural Modelling
port(X,Y: in bit; Z: out bit);
component AndGate end XorGate;
port(X,Y: in bit; Z: out bit); architecture Behavioral of XorGate is stim_proc: process
end component; begin begin
Z <= X xor Y; In1 <= not In1;
component OrGate end Behavioral; wait for 100 ns;
port(X,Y,W: in bit; Z: out bit); end process;
end component; entity AndGate is
port(X,Y: in bit; Z: out bit); stim_proc1: process
component XorGate end AndGate; begin
port(X,Y: in bit; Z: out bit); architecture Behavioral of AndGate is In2 <= not In2;
end component; begin wait for 50 ns;
Z <= X and Y; end process;
signal X1, X2 ,A1, A2, A3: bit; end Behavioral;
stim_proc2: process
Begin entity OrGate is begin
port(X,Y,W: in bit; Z: out bit); Cin <= not Cin;
X1:XorGate port map(x, y, X1); end OrGate; wait for 150 ns;
X2:XorGate port map(X1, z, S); architecture Behavioral of OrGate is end process;
A1:AndGate port map(x, y, A1); begin
A2:AndGate port map(x, z, A2); Z <= (X or Y)or W;
A3:AndGate port map(y, z, A3); end Behavioral;
O1:OrGate port map(A1, A2, A3, C);

end Structural;
 entity andgate is
port( X, Y : in bit ; Z : out bit);
VHDL Code for Full Subtractor – end andgate;
architecture Behavioral of andgate is
begin

Structural Modeling Z <= X and Y;

end Behavioral;

entity notgate is
port( X: in bit; Z: out bit);
end notgate;
architecture Behavioral of notgate is
𝒙 X1L
begin
• XOR gate Z <= not X;
𝒚 D end Behavioral;
• AND gate
𝑩𝒊𝒏 N2L
A2L entity xorgate is
N1L • OR gate port( X,Y: in bit; Z: out bit);
end xorgate;
• NOT gate architecture Behavioral of xorgate is
B
begin
A1L
Z <= X xor Y;
end Behavioral;

entity orgate is
port(X,Y: in bit; Z: out bit);
end orgate;
architecture Behavioral of orgate is
begin
Z <= X or Y;
end Behavioral;
 entity Fullsub is
Port ( Bin : in bit;
x : in bit;
VHDL Code for Full Subtractor – y : in bit;
D : out bit;
Bout : out bit);
Structural Modeling end Fullsub;
architecture Structural of Fullsub is
component andgate
port(X, Y: in bit; Z: out bit);
end component;
component xorgate
𝒙 X1L port(X, Y: in bit; Z: out bit);
end component;
component notgate
𝒚 D port(X: in bit; Z: out bit);
end component;
𝑩𝒊𝒏 N2L
A2L component orgate
N1L
port(X, Y: in bit; Z: out bit);
end component;
B signal X1L,N1L,N2L,A1L,A2L,A3L: bit;
A1L Begin

X1: xorgate port map(x,y,X1L);

X2: xorgate port map (X1L,Bin,D);
N1: notgate port map(x,N1L);
A1: andgate port map(y, N1L, A1L);
N2: notgate port map(X1L, N2L);
A2: andgate port map(Bin, N2L,A2L);
O1: orgate port map(A2L, A1L, Bout);

end Structural;
entity Fullsub is
entity andgate is
Port ( Bin : in bit;
x : in bit;
port( X, Y : in bit ; Z : out bit); Structural Modelling
end andgate;
y : in bit;
architecture Behavioral of andgate is
D : out bit;
begin
Bout : out bit);
Z <= X and Y;
end Fullsub;
end Behavioral; -- Stimulus process
architecture Structural of Fullsub is
component andgate stim_proc1: process
entity notgate is
port(X, Y: in bit; Z: out bit);
port( X: in bit; Z: out bit);
begin
end component; A <= not A;
end notgate;
component xorgate
port(X, Y: in bit; Z: out bit);
architecture Behavioral of notgate is wait for 300 ns;
begin end process;
end component;
Z <= not X;
component notgate
end Behavioral;
port(X: in bit; Z: out bit);
stim_proc2: process
end component;
component orgate
entity xorgate is begin
port( X,Y: in bit; Z: out bit);
port(X, Y: in bit; Z: out bit);
end xorgate;
B <= not B;
end component; wait for 150 ns;
architecture Behavioral of xorgate is
signal X1L,N1L,N2L,A1L,A2L,A3L: bit;
Begin
begin end process;
Z <= X xor Y;
end Behavioral;
X1: xorgate port map(x,y,X1L); stim_proc3: process
X2: xorgate port map (X1L,Bin,D);
entity orgate is begin
N1: notgate port map(x,N1L);
A1: andgate port map(y, N1L, A1L);
port(X,Y: in bit; Z: out bit); Bin <= not Bin;
end orgate;
N2: notgate port map(X1L, N2L);
architecture Behavioral of orgate is
wait for 50 ns;
A2: andgate port map(Bin, N2L,A2L); end process;
begin
O1: orgate port map(A2L, A1L, Bout);
Z <= X or Y; END;
end Behavioral;
end Structural;
VHDL Code for Full Subtractors – Structural Modeling
VHDL Code for 4 bit adder– Structural Modeling

entity Fulladder is
port ( x, y, z : in bit; s,c: out bit);
end Fulladder;

architecture Behavioral of Fulladder is

Signal X1,A1,A2,A3: bit;

begin

X1 <= x xor y ;
s <= X1 xor z ;
𝑺 = 𝒙 ⊕ 𝒚 ⊕ 𝑪𝒊𝒏 A1 <= x and y;
A2 <= x and z ;
A3 <= y and z ;
𝑪 = 𝒚𝑪𝒊𝒏 + 𝒙𝑪𝒊𝒏 + 𝒙𝒚 c <= (A1 or A2) or A3 ;

end Behavioral;
 entity RippleadderS is
VHDL Code for Ripple/parallel – Port ( Cin : in bit;
A : in bit_VECTOR (3 downto 0);
Structural Modeling B : in bit_VECTOR (3 downto 0);
Cout : out bit;
S : out bit_VECTOR (3 downto 0));

end RippleadderS;

architecture Structural of RippleadderS is

component Fulladder
port ( x, y, z : in bit; s,c: out bit);
end component;

Signal C1,C2,C3: bit;

begin

FA1:Fulladder port map(A(0),B(0),Cin,S(0),C1);

FA2:Fulladder port map (A(1),B(1),C1,S(1),C2);
FA3:Fulladder port map (A(2),B(2),C2,S(2),C3);
FA4:Fulladder port map (A(3),B(3),C3,S(3),Cout);
end Structural;
 VHDL Code for 4 bit / parallel/Ripple adder Structural Modelling
entity RippleadderS is entity Fulladder is stim_proc: process
port ( x, y, z : in bit; s,c: out bit); begin
Port ( Cin : in bit; end Fulladder;
A : in bit_VECTOR (3 downto 0); wait for 100 ns;
B : in bit_VECTOR (3 downto 0); architecture Behavioral of Fulladder is A <= "0110";
Cout : out bit; B <= "1100";
S : out bit_VECTOR (3 downto 0)); Signal X1,A1,A2,A3: bit;
wait for 100 ns;
end RippleadderS; begin A <= "1111";
B <= "1100";
architecture Structural of RippleadderS is X1 <= x xor y ;
s <= X1 xor z ; wait for 100 ns;
component Fulladder A1 <= x and y; A <= "0110";
port ( x, y, z : in bit; s,c: out bit); A2 <= x and z ; B <= "0111";
end component; A3 <= y and z ;
c <= (A1 or A2) or A3 ; wait for 100 ns;
Signal C1,C2,C3: bit; A <= "0110";
end Behavioral; B <= "1110";
begin
wait for 100 ns;
FA1:Fulladder port map(A(0),B(0),Cin,S(0),C1); A <= "1111";
FA2:Fulladder port map (A(1),B(1),C1,S(1),C2); B <= "1111";
FA3:Fulladder port map (A(2),B(2),C2,S(2),C3);
FA4:Fulladder port map (A(3),B(3),C3,S(3),Cout); wait;
end Structural; end process;
VHDL Code for 4 bit adder/Ripple adder – Structural Modeling
Verification using TEST BENCH
VHDL code for Multiplexer and De Multiplexer
Design of a 4:1 Multiplexer using Dataflow, Behavioural and structural modeling

Design of a 1:2 & 1:4 De Multiplexer using Dataflow, Behavioural and structural modeling
A
B f f f f
2n : n : 1 f
C S1 S0 S1 S0 S1 S0 S1 S0
MUX
D
E
S0 S1

S1 S 0
E S1 S0 A B C D F F A1
A
0 0 0 X X X X 0 0
A2
1 0 0 0 X X X 0 A B
1 0 0 1 X X X 1 A f
1 0 1 X 0 X X 0 B C
1 0 1 X 1 X X 1 B A3

1 1 0 X X 0 X 0 C
D
1 1 0 X X 1 X 1 C A4
1 1 1 X X X 0 0 D
𝒇 = 𝑬(𝑺𝟏 𝑺𝟎 𝑨 + 𝑺𝟏 𝑺𝟎 𝑩 + 𝑺𝟏 𝑺𝟎 𝑪 + 𝑺𝟏 𝑺𝟎 𝑫)
1 1 1 X X X 1 1 D
 stim: process
A
entity MUX4_1 is Begin
B
Port ( i : in STD_LOGIC_VECTOR (3 downto 0); 2n : n : 1 i <= "1010";
C f
s : in STD_LOGIC_VECTOR (1 downto 0); MUX
D s <= "00";
y : out STD_LOGIC);
E wait for 20 ns;
end MUX4_1;
s <= "01";
architecture dataflow of MUX4_1 is
wait for 20 ns;
begin S1 S0
with s select s <= "10";
y <= i(0) when "00", wait for 20 ns;
i(1) when "01", s <= "11";
i(2) when "10", wait for 20 ns;
i(3) when others;
wait;
end dataflow;
end process;
end tb;
Dataflow modeling of 4:1 mux
stim_proc: process
Begin
entity MuxB is
A <= '1';
Port ( A,B,C,D,sel0,sel1 : in bit; y : out bit);
sel0 <= '0';
end MuxB;
sel1 <= '0';
wait for 20 ns;
architecture Dataflow of MuxB is
B <= '0';
sel0 <= '0';
signal selbar0, selbar1, A1, A2, A3, A4: bit;
sel1 <= '1';
wait for 20 ns;
begin
C <= '1';
sel0 <= '1';
selbar0 <= not sel0;
sel1 <= '0';
selbar1 <= not sel1;
wait for 20 ns;
A1 <= (A and selbar0) and selbar1;
D <= '1';
A2 <= (B and sel0) and selbar1;
sel0 <= '1';
A3 <= (C and selbar0) and sel1;
sel1 <= '1';
A4 <= (D and sel0) and sel1;
wait for 20 ns;
Y <= (A1 or A2) or (A3 or A4);
wait;
end process;
end Dataflow;
entity MUX4_1 is
Port ( i : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0); stim: process
y : out STD_LOGIC);
Begin
end MUX4_1;
i <= "1010";
s <= "00";
architecture Behavioral of MUX4_1 is
begin wait for 100 ns;

Process ( s, i) s <= "01";

begin wait for 100 ns;
if (s <= "00") then y<= I(0); s <= "10";
elsif (s <= "01") then y <= i(1); wait for 100 ns;
elsif (s <= "10") then y <= i(2);
s <= "11";
else y <= i(3);
wait for 100 ns;
end if;
wait;
end Process;
end Behavioral; end process;
end tb;
Behavioral Modeling of 4:1 mux

library ieee;
use ieee.std_logic_1164.all; stim: process
entity MuxBcase is Begin
Port ( i : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0); i <= "1010";
y : out STD_LOGIC);
end MuxBcase; s <= "00";
wait for 100 ns;
architecture Behavioral of MuxBcase is
s <= "01";
begin
mux : process (i,sel) is wait for 100 ns;
begin
s <= "10";
case sel is
when "00" => y <= i(3); wait for 100 ns;
when "01" => y <= i(2);
when "10" => y <= i(1); s <= "11";
when others => y <= i(0);
end case;
wait for 100 ns;
end process mux; wait;
end Behavioral; end process;
end tb;
 signal selbar0,selbar1,A1,A2,A3,A4: std_logic;
begin
INV0: inv port map (Sel0, selbar0);
INV1: inv port map (Sel1, selbar1);
Structural modeling of 4:1 mux A1: and3 port map (A, selbar0, selbar1, A1);
A2: and3 port map (B, Sel0, selbar1, A2);
library ieee; A3: and3 port map (C, selbar0, Sel1, A2);
use ieee.std_logic_1164.all; A4: and3 port map (D, Sel0, Sel1, A4);
O1: or4 port map (A1, A2, A3, A4, Y);
entity MUX4_1 is end structural;
port ( Sel0,Sel1 : in std_logic;
A, B, C, D : in std_logic;
Y : out std_logic );
end MUX4_1;

architecture structural of MUX4_1 is

component inv
port (pin : in std_logic; pout :out std_logic);
end component;
component and3
port (a0,a1,a2: in std_logic; aout:out std_logic);
end component;
component or4
port (r0,r1,r2,r3:in std_logic; rout:out std_logic);
end component;
entity and3 is stim_proc: process
port( X, Y,W: in bit ; Z : out bit); Begin
end and3; A <= '1';
sel0 <= '0';
architecture Behavioral of and3 is
sel1 <= '0';
begin wait for 20 ns;
Z <= (X and Y) and W ; B <= '0';
end Behavioral; sel0 <= '0';
sel1 <= '1';
entity inv is wait for 20 ns;
port( X: in bit; Z: out bit); C <= '1';
end inv; sel0 <= '1';
sel1 <= '0';
architecture Behavioral of inv is
wait for 20 ns;
begin D <= '1';
Z <= not X; sel0 <= '1';
end Behavioral; sel1 <= '1';
wait for 20 ns;
entity or4 is wait;
port(X,Y,W,U: in bit; Z: out bit); end process;
end or4;
architecture Behavioral of or4 is
begin
Z <= (X or Y) or (W or U);
end Behavioral;
library IEEE; stim: process
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; Begin
use IEEE.STD_LOGIC_UNSIGNED.ALL; I <= '0';
S <= '0';
entity DEMUX_SOURCE is wait for 100 ns; Routing device
Port ( I,S : in STD_LOGIC; y1, y2 : out STD_LOGIC); S <= '1';
end DEMUX_SOURCE; wait for 100 ns; I/E O1
I <= '1'; S <= '0';
DeMUX
O2
architecture dataflow of DEMUX_SOURCE is wait for 100 ns;
S <= '1'; S
begin wait for 100 ns;
O1 <= I and (not S); wait;
O2 <= I and S; end process;

end dataflow; end tb;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; stim: process
Routing device Y0
use IEEE.STD_LOGIC_ARITH.ALL; Begin
use IEEE.STD_LOGIC_UNSIGNED.ALL; I/E Y1
I <= '1'; DeMUX Y2
entity DEMUX_USINGTRUTHTABLE_SOURCE is S <= "00";
Y3
Port ( I : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0); wait for 20 ns; S1 S0
Y : out STD_LOGIC_VECTOR (3 downto 0)); S <= "01";
end DEMUX_USINGTRUTHTABLE_SOURCE;
wait for 20 ns;
architecture dataflow of DEMUX_USINGTRUTHTABLE_SOURCE is E S1 S0 z3 z2 z1 z0
S <= "10";
begin wait for 20 ns; 0 x x 0 0 0 0
with S select S <= "11"; 1 0 0 0 0 0 1
Y <= ("000" & I) when "00", wait for 20 ns; 1 0 1 0 0 1 0
("00" & I & "0") when "01", wait; 1 1 0 0 1 0 0
("0" & I & "00") when "10",
(I & "000") when others; end process; 1 1 1 1 0 0 0
end tb;
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; stim: process
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; Begin
I <= '1';
entity DEMUX_SOURCE is
Port ( I : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0); S <= "00";
Y : out STD_LOGIC_VECTOR (3 downto 0)); wait for 20 ns;
end DEMUX_SOURCE;
S <= "01";
architecture Behavioral of DEMUX_SOURCE is wait for 20 ns;
begin
process (I, S) S <= "10";
begin wait for 20 ns;
if (S <= "00") then Y(0) <= I ;
elsif (S <= "01") then Y(1) <= I ; S <= "11";
elsif (S <= "10") then Y(2) <= I ; wait for 20 ns;
else Y(3) <= I ;
end if; wait;
end process;
end process;
end Behavioral; end tb;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity demux1_4 is
port (
out0, out1, out2, out3 : out std_logic;
Stimulus:Process
sel : in std_logic_vector(1 downto 0);
i : in std_logic); BEGIN
end demux1_4;
i <= '1';
architecture Behavioral of demux1_4 is sel <="00";
wait for 2 ns;
begin
process(i,sel) sel <="01";
begin
wait for 2 ns;
case sel is
when "00" => out0 <= i; out1 <= '0'; out2 <= '0'; out3 <='0'; sel <="10";
when "01" => out1 <= i; out0 <= '0'; out2 <= '0'; out3 <='0';
wait for 2 ns;
when "10" => out2 <= i; out0 <= '0'; out1 <= '0'; out3 <='0';
when others => out3 <= i; out0 <= '0'; out1 <= '0'; out2 <='0'; sel <="11";
end case;
wait for 2 ns;
end process;
END PROCESS tb;
end Behavioral;
Dataflow modelling uses only Concurrent signal assignment statements

1. Concurrent signal assignment statements

a. Conditional signal assignment statements
b. Selected signal assignment statements
2. Delay in the signal assignment
a. Delta delay( Δ )
b. Delay using ‘after’ statement
3. when-else statements in VHDL
4. with-select statements in VHDL
5. Generate statements
 Concurrent signal assignment statements
• Concurrent statements are those statements that are executed in parallel.
• These are the primary choice for modeling the behaviour of an entity in the dataflow style.

entity ckt is
port (A: in BIT:=1; B: in BIT; Y,Z: out BIT);
end ckt;
architecture ckt of ckt is
Three concurrent signal assignment statements.
begin
B <= A and A; VHDL compiler executes those three statements

Y<= A and B; concurrently/parallel.

Z<= B after 10 ns;

end ckt;

An important detail to remember in dataflow modeling is that due to the concurrent nature of execution, the order of
the statements does not matter.
 Conditional signal assignment statements
• This conditional statement will assign the value to its target signal only when a condition is true.
• You can give multiple values with multiple conditions. They are similar to if-else statements.

Targeted_signal <= Value when condition else VHDL compiler assigns a value (or values) to ‘Targeted_signal’
Value_2 when condition_2 else when its corresponding condition is true. Conditions can be a
.....
Boolean expression, and value (or values) can be any waveform
Value_last;
element.

Output <= input(0) after 20 ns when S(0) = ‘0’ and S(1) = ‘0’ else
input(1) after 20 ns when S(0) = ‘0’ and S(1) = ‘1’ else When more than one conditions are true, then compiler
input(2) after 20 ns when S(0) = ‘1’ and S(1) = ‘0’ else
gives precedence to the first occurring true condition.
input(3) after 20 ns;

Whenever there is an event on signals input(0), input(1), input(2), input(3), S(0) or S(1). The VHDL compiler will
execute the above statements. So, these signals act as a sensitivity list (list of signals) for this conditional statement.
 Selected signal assignment statements
This signal assignment statement will select and assign a value to its target signal based on the value of the select
expression. They are similar to case statements in the C-programming language.
You can also give multiple values with multiple choices.

Target_signal <= Value1 when choice1,

Value2 when choice2,
Value3 when choice3,
....
Value(Nth)when choice(Nth);

This is very similar to conditional signal assignment statements.

The compiler will execute these statements whenever there is any change in any signal value or select expression.
VHDL compiler will assign the value whose corresponding choice matches the expression.
 when-else statements in VHDL
Delay in the signal assignment
2-bit magnitude comparator
Every component has its propagation delay, and it adds up as we
Library ieee;
use more and more gates. Delay should be considered because
use ieee.std_logic_1164.all;
otherwise, every signal will flow through gates almost use ieee.std_logic_arith.all;
instantaneously, which is a violation practically. There will always use ieee.std_logic_unsigned.all;
be delays (however small) between a signal starting off at one end entity Comparator is
and reaching the other via a bunch of logic gates. port ( inA,inB : in std_logic_vector(2 downto 0);
greater, equal, smaller : out std_logic );
to create definite delays, we use after clause. end Comparator;
architecture behavioral of Comparator is
Sum <= A xor B after 10 ns;
Begin
greater <= '1' when (inA > inB) else '0';
equal <= '1' when (inA = inB) else '0';
smaller <= '1' when (inA < inB) else '0';
end behavioral;
 with BCDin select
with-select statements in VHDL seven_segment <= "1000000" when "0000",
"1111001" when "0001",
BCD to seven segment code converter
"0100100" when "0010",
Library ieee; "0110000" when "0011",
use ieee.std_logic_1164.all; "0011001" when "0100",
entity SS_CC is port( enb : in std_logic; "0010010" when "0101",
BCDin : in std_logic_vector(3 downto 0); "0000010" when "0110",
Op_Active_high : out std_logic_vector(6 downto 0) ); "1111000" when "0111",
end SS_CC; "0000000" when "1000",
architecture dataflow of SS_CC is "0010000" when "1001",
signal seven_segment : std_logic_vector(6 downto 0); "0001000" when "1010",
begin "0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
use with-select statement having BCDin as expression and
"0000110" when "1110",
assign the pre-calculated values of output for every possible
"0001110" when others;
input.
Then to check the state of enabling pin use and operation for every bit individually. This to ensure that output appears only when the
enable pin is high. finish the program using end keyword.

Op_Active_high(0) <= not seven_segment(0) and enb;

Op_Active_high(1) <= not seven_segment(1) and enb;
Op_Active_high(2) <= not seven_segment(2) and enb;
Op_Active_high(3) <= not seven_segment(3) and enb;
Op_Active_high(4) <= not seven_segment(4) and enb;
Op_Active_high(5) <= not seven_segment(5) and enb;
Op_Active_high(6) <= not seven_segment(6) and enb;
end dataflow;
 4-bit parallel adder using generate statement.
Generate statements
library ieee;
In concurrent assignments, we use ieee.std_logic_1164.all;
use generate statements to create loops. But these entity Parallel_adder is
loops are not the same as we use in other port (A, B: in BIT_VECTOR(3 downto 0);
programming languages. Y: in BIT;
SUM: out BIT_VECTOR(3 downto 0); CARRY: out BIT);
In VHDL loops create a replica of the circuit N
end Parallel_adder;
times, which is not desirable in most of the cases.
architecture Looping of Parallel_adder is
Because then it also needs a much larger physical
signal CAR: BIT_VECTOR(4 downto 0);
space during fabrication.
begin
For creating an N-bit adder using just one full
CAR(0) <= Y;
adder. ( also do this simply by using structural
GenerateK: for K in 3 downto 0 generate
modeling).
SUM(K) <= A(K) xor B(K) xor CAR(K);
But still, if you need a 32-bit or 64-bit parallel
CAR(K+1) <= (A(K) and B(K)) or (B(K) and CAR(K)) or (CAR(K) and A(K));
adder, then you have to write 32 or 64 lines for it.
end generate GenerateK;
Instead, you can use generate statement for the
CARRY <= CAR(4);
purpose.
end Looping;
 1. The process block
a. Process label
b. Sensitivity list
c. Process data-object
d. Sequential statements
2. Sequential assignment statements
a. Variable assignment statement
b. Signal assignment statement
Describe the behaviour of an entity using sequential and 3. Sequential statements
process statements. a. case statement
b. if statement
c. wait statement
d. loop statement
e. Exit statement
f. Next statement
g. Assertion statements
 Syntax of process statement
The process block
process-label : process ( sensitivity-list )
A process block contains statements that the VHDL compiler executes process-data_object-declarations
sequentially. Statements inside the process block may describe the begin
working of the entity or a portion of the entity. The sequential execution sequential-statements; these are ->

of statements means that the compiler will execute them in the same variable-assignment statement

order as we write. signal-assignment –statement

case statement
Process-label
loop statement
It is optional and its absence would not create any errors.
if-else statement
assertion statement
Process ( sensitivity-list )
Wait –statement
It contains the name/ label of all the signals that the process end process process-label;
is sensitive to. This is also optional, but a process without a sensitivity list
runs forever, so to avoid include a wait statement at the end of the
process. That helps in suspending the process.

A process with a sensitivity list will be executed when the value of any signal from the list will change.
 Process data-object
These are data-objects like signals, variables, constants, generics, etc. Data objects defined inside a process only
belong to that particular process; no other process can access those data-objects. You can think of them as the local
variables in C

Sequential statements
The VHDL compiler allows sequential statements in the process block only. There are various sequential
statements, some of them are listed below:

1. variable-assignment-statement
2. signal-assignment-statement
3. case statement
4. loop statement
5. if-else statement
6. assertion-statement
7. wait-statement
After the execution of all the statements inside the process block, the compiler suspends the process.
 Variable assignment statement
Variables are declared inside a process before the begin keyword. The variable declared inside the process only
belongs to it.
Signal assignment statement

Signals can be defined inside a process or outside a process. When they appear inside a process, they behave as
sequential signal assignment statements. And when they appear outside a process, then they behave as concurrent
signal assignment statements.
case statement
The case statement is a type of conditional statement. We provide an expression as a case, and when the compiler
executes this block, it evaluates the expression first. Then it goes through all the choices, and when a choice matches
the expression’s value, it executes the corresponding statements.

if statement ‘ if ’ statements are also conditional statements.

The difference is that the case statement matches the condition with choices. But ‘if’ condition just checks the
condition, whether it is true or not. That is why it only takes conditions as a Boolean expression. And the statement
evaluates to a Boolean value, either ‘1’ or ‘0’, or you can say ‘HIGH’ or ‘LOW.’
wait statement
A process with a sensitivity list will be suspended after the execution of the last sequential statement. But is the
process does not have any sensitivity list; then we use the wait statement to suspend the process.
loop statement loop statements to iterate through a set of sequential statements

Exit statement use the exit statement to finish a loop

Next statement next statement to skip the current iteration of the loop

The execution of the next statement causes skipping of the remaining statement of the specified loop in the current
iteration. If we don’t provide any label, then the only innermost loop is considered. So as a comparison,
the exit statement terminates the loop while the next statement terminates the current iteration only.

Assertion statements

assertion statements to model constraints for an entity.

These are very helpful in verifying the test results automatically
you can check if setup and hold times for a signal arriving at any point are okay or not. You can also check if the
output from an entity or value of a signal lies within a range. If the check fails, an error message can be reported.
 Design of full adder using Behavioral modeling
entity FABM is
Port ( X : in STD_LOGIC; Truth table of Half adder
Y : in STD_LOGIC;
HA2: process (S1,Cin) x y
Cin : in STD_LOGIC;
begin
C S
Cout : out STD_LOGIC;
if S1 = '1' then 0 0 0 0 C >= S2
Sum : out STD_LOGIC);
Sum <= not Cin; S >= S1
end FABM; 0 1 0 1
S3 <= Cin;
architecture Behavioral of FABM is
else 1 0 0 1
Sum <= Cin;
signal S1,S2,S3 : STD_LOGIC; 1 1 1 0
S3 <= '0';
end if;
Begin
end process HA2;
HA1: process (X,Y)
OR1: Process (S3,S2)
begin
begin
if X = '1' then
if (S3 = '1') or (S2 = '1') then
S1 <= not Y;
Cout <= '1';
S2 <= Y;
else Sum
else X
Cout <= '0'; HA HA
S1 <= Y; Y
end if;
S2 <= '0'; Cout
end process OR1;
end if;
end Behavioral; C
end process HA1; in
Use structural modeling for large designs. It allows us to write reusable code. Define a smaller entity in a separate file
and can use it in a larger entity as a component. Use signals to interconnect components and eventually create large
systems using small sub-systems.

1. Component declaration
2. Package Declaration
3. Component instantiation
4. Association techniques
a. Positional association
b. Named association
c. Rules for association while instantiating a
component
5. Internal signal declaration
6. Mixed Modeling Style
 Component declaration
In structural modeling, the first thing to do is to instantiate components using component declaration.
In component declaration, define the name, Inputs/outputs, and type of Inputs/outputs of the component.
component AND1
port(A,B : in BIT; Y : out BIT);
end component; Declare components in the declaration part of the architecture body

component halfadder
port(A,B : in BIT; sum, carry : out BIT);
end component;

Package Declaration
The use of packages actually makes reusable code as designers can share the packages with other designers. Or one
can use a package in multiple designs without writing it again and again.

The use of packages and libraries does not reduce the size of actual code. While the compilation occurs, the compiler
fetches the respective code block automatically. The actual advantage is in the aesthetics of the code, especially in
large design units.
 Component instantiation
Component instantiation is nothing but just the syntax for using the component in the circuit.
component label: component-name port map ( association-list) ;

1. We can use any legal identifier as a label for the component, and it has to be unique in the architecture.
2. The component label is also known as the name of the instance.
3. The name of the component will remain the same as in its declaration.
4. The association list contains the signals and ports of the entity.
5. We use signals for the interconnection of components inside the circuit, and ports serve as a terminal point or input
/outputs.

1. Signals in the entity are called actuals.

2. An actual can only be an object of the signal class; VHDL does not allow variable and constants here.
3. Ports of a component in the association list are called locals.
4. If the port is not connected anywhere, then you must use the open keyword to indicate it.
 Association techniques
There are two ways to do the association of locals with actuals or signals with ports

1. Positional association.
2. Named association.

Positional association
In positional association, we map the signal or port to the port at the respective positions in the component
declaration.
component halfadder
port(A,B : in BIT; sum, carry : out BIT);
end component;
H1: halfadder port map(S1, S2, P(1), P(2));

H1 is the label for the current instantiation of component halfadder. And it will map S1 to A, S2 to B, P(1) to sum and,
P(2) to carry. As association occurs based on the position of the actual in the list
 Named association
In named association, every local is attached to an actual explicitly using the syntax
local => actual;

Here position and sequence do not matter as we defined each of them explicitly.

component halfadder
port(A,B : in BIT; sum, carry : out BIT);
end component;
H1: halfadder port map ( S1 => A, S2 => B, P(1) => sum, P(2) => carry);

Rules for association while instantiating a component - applies to both named and positional associations

1. The type of local and the actual must be the same for a valid association.
2. If the local is in readable mode, so must the actual.
3. Signals that are defined locally, we can read/ write to them so those can be associated with local of any mode.
4. If an actual is of mode in, it can’t be associated with a local of mode out/ inout.
5. If an actual is of mode out, it can’t be associated with a local of mode in/ inout.
6. But if an actual is of mode inout, it can be associated with a local of mode in, out or input.
 Internal / Intermediate signal declaration
in structural modeling, we use signals interconnect components. We initialize these signals inside the architecture
body, so we call them the internal signals.
architecture STRUCTURAL of DECADE_COUNTER is

component JK_FF port (J, K, CLK: in BIT; Q, QBAR: buffer BIT);

end component;

component AND_GATE
port (A, B: in BIT; C: out BIT);
end component;

signal S1, S2: BIT;

signal S_HIGH: BIT := '1';
begin

A1: AND_GATE port map (Z(2), Z(1), S1);

JK1: JK_FF port map (S_HIGH, S_HIGH, INPUT, Z(0), open);
JK2: JK_FF port map (S2, S_HIGH, Z(0), Z(1), open);
JK3: JK_FF port map (S_HIGH, S_HIGH, Z(1), Z(2), open);
JK4: JK_FF port map (S1, S_HIGH, Z(0), Z(3), S2);
end STRUCTURAL;
entity Fullsub is
entity andgate is
Port ( Bin : in bit;
x : in bit;
port( X, Y : in bit ; Z : out bit); Structural Modelling
end andgate;
y : in bit;
architecture Behavioral of andgate is
D : out bit;
begin
Bout : out bit); -- Stimulus process
Z <= X and Y;
end Fullsub;
architecture Structural of Fullsub is
end Behavioral; stim_proc1: process
component andgate begin
entity notgate is
port(X, Y: in bit; Z: out bit); A <= not A;
port( X: in bit; Z: out bit);
end component;
component xorgate
end notgate; wait for 300 ns;
architecture Behavioral of notgate is end process;
port(X, Y: in bit; Z: out bit);
begin
end component;
Z <= not X;
component notgate stim_proc2: process
end Behavioral;
port(X: in bit; Z: out bit);
end component; begin
entity xorgate is
component orgate B <= not B;
port( X,Y: in bit; Z: out bit);
port(X, Y: in bit; Z: out bit); wait for 150 ns;
end xorgate;
end component;
signal X1L,N1L,N2L,A1L,A2L,A3L: bit;
architecture Behavioral of xorgate is end process;
begin
Begin
Z <= X xor Y;
end Behavioral;
stim_proc3: process
X1: xorgate port map(x,y,X1L); begin
X2: xorgate port map (X1L,Bin,D);
N1: notgate port map(x,N1L);
entity orgate is Bin <= not Bin;
port(X,Y: in bit; Z: out bit);
A1: andgate port map(y, N1L, A1L); wait for 50 ns;
end orgate;
N2: notgate port map(X1L, N2L); end process;
architecture Behavioral of orgate is
A2: andgate port map(Bin, N2L,A2L);
O1: orgate port map(A2L, A1L, Bout);
begin END;
Z <= X or Y;
end Behavioral;
end Structural;
 VHDL Module Structural Modelling Using Package
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.all;
package HA is VHDL Package Test Bench
use work.HA.all; component HAP is
port (X,Y: in STD_LOGIC; C,S: out STD_LOGIC); -- Stimulus process
entity FAsuingHASM is end component; stim_proc1: process
Port ( X : in STD_LOGIC; end HA; begin
entity HAP is A <= not A;
Y : in STD_LOGIC;
Port ( X : in STD_LOGIC; wait for 300 ns;
cin : in STD_LOGIC; Y : in STD_LOGIC; end process;
C : out STD_LOGIC;
cout : out STD_LOGIC; S : out STD_LOGIC);
end HAP; stim_proc2: process
sum : out STD_LOGIC);
architecture Behavioral of HAP is begin
end FAsuingHASM; begin
B <= not B;
S <= X xor Y;
architecture Structural of FAsuingHASM is C <= X and Y; VHDL Module wait for 150 ns;
end Behavioral; end process;
signal S1,S2,S3: STD_LOGIC;
begin stim_proc3: process
U1: HAP port map (X,Y,S2,S1); S1 Sum begin
X Bin <= not Bin;
U2: HAP port map (S1,cin,S3,sum); HA HA
Y S3 wait for 50 ns;
cout <= S3 or S2; S2 Cout end process;
end Structural; END;
Cin
1. Arithmetic operators
2. Shift operators
3. Relational operators
4. Logical operators
Operator Name Shift Relational and Logical

Arithmetic sll shift left logical = test for equality

+ addition srl shift right logical /= test for inequality

– subtraction sla shift left arithmetic < test for less than

* multiplication sra shift right arithmetic <= test for less than or equal

/ division rol rotate left > test for greater than

** exponentiation ror rotate right >= test for greater than or equal

abs absolute value shift_left() New and more and logical and

not complement optimum. Read or logical or

shift_right()
mod modulo more below. nand the logical complement of and

rem remainder nor the logical complement of or

+ unary plus xor logical exclusive of or

– unary minus xnor the logical complement of exclusive of or

& concatenation