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FSDL0365RN, FSDM0365RN
Green Mode Fairchild Power Switch (FPSTM)

Features
OUTPUT POWER TABLE
• Internal Avalanche Rugged Sense FET
• Consumes only 0.65W at 240VAC & 0.3W load with 230VAC ±15%(3) 85-265VAC
Advanced Burst-Mode Operation PRODUCT Adapt- Open Adapt- Open
• Frequency Modulation for low EMI er(1) Frame(2) er(1) Frame(2)
• Precision Fixed Operating Frequency FSDL321 11W 17W 8W 12W
• Internal Start-up Circuit
FSDH321 11W 17W 8W 12W
• Pulse by Pulse Current Limiting
• Abnormal Over Current Protection FSDL0165RN 13W 23W 11W 17W
• Over Voltage Protection FSDM0265RN 16W 27W 13W 20W
• Over Load Protection FSDH0265RN 16W 27W 13W 20W
• Internal Thermal Shutdown Function
FSDL0365RN 19W 30W 16W 24W
• Auto-Restart Mode
• Under Voltage Lockout FSDM0365RN 19W 30W 16W 24W
• Low Operating Current (3mA) FSDL0165RL 13W 23W 11W 17W
• Adjustable Peak Current Limit FSDM0265RL 16W 27W 13W 20W
• Built-in Soft Start
FSDH0265RL 16W 27W 13W 20W
FSDL0365RL 19W 30W 16W 24W
Applications FSDM0365RL 19W 30W 16W 24W
• SMPS for VCR, SVR, STB, DVD & DVCD
• SMPS for Printer, Facsimile & Scanner
• Adaptor for Camcorder Table 1. Notes: 1. Typical continuous power in a non-ven-
tilated enclosed adapter measured at 50°C ambient. 2.
Maximum practical continuous power in an open frame
Description design at 50°C ambient. 3. 230 VAC or 100/115 VAC with
doubler.
The FSDx0365RN(x stands for L, M) are integrated Pulse
Width Modulators (PWM) and Sense FETs specifically
designed for high performance offline Switch Mode Power Typical Circuit
Supplies (SMPS) with minimal external components. Both
devices are integrated high voltage power switching regula-
tors which combine an avalanche rugged Sense FET with a
AC
current mode PWM control block. The integrated PWM con- IN DC
troller features include: a fixed oscillator with frequency OUT
modulation for reduced EMI, Under Voltage Lock Out
(UVLO) protection, Leading Edge Blanking (LEB), opti-
Vstr Drain
mized gate turn-on/turn-off driver, Thermal Shut Down
Ipk
(TSD) protection, Abnormal Over Current Protection PWM
(AOCP) and temperature compensated precision current
sources for loop compensation and fault protection circuitry. Vfb Vcc Source

When compared to a discrete MOSFET and controller or

RCC switching converter solution, the FSDx0365RN reduce
total component count, design size, weight and at the same
time increase efficiency, productivity, and system reliability.
Both devices are a basic platform well suited for cost effec- Figure 1. Typical Flyback Application
tive designs of flyback converters.

Rev.1.0.4
©2004 Fairchild Semiconductor Corporation
FSDL0365RN, FSDM0365RN

Internal Block Diagram

Vcc Vstr Drain

2 5 6,7,8

+ Istart
V BURL /V BURH
- Soft start
8V/12V
Vcc good Internal
V BURH Vcc Vref
Freq.
Bias
Modulation
I B_PEAK
Vcc Vcc
OSC
I delay I FB
V FB Normal S Q
3 PWM
Gate
2.5R Burst R Q
driver
Ipk R
4
LEB

V SD

Vcc 1 GND
S Q
Vovp
Vcc good R Q
AOCP
TSD
Vocp

Figure 2. Functional Block Diagram of FSDx0365RN

2
 FSDL0365RN, FSDM0365RN

Pin Definitions

Pin Number Pin Name Pin Function Description

1 GND Sense FET source terminal on primary side and internal control ground.
Positive supply voltage input. Although connected to an auxiliary transform-
er winding, current is supplied from pin 5 (Vstr) via an internal switch during
2 Vcc startup (see Internal Block Diagram section). It is not until Vcc reaches the
UVLO upper threshold (12V) that the internal start-up switch opens and de-
vice power is supplied via the auxiliary transformer winding.
The feedback voltage pin is the non-inverting input to the PWM comparator.
It has a 0.9mA current source connected internally while a capacitor and op-
tocoupler are typically connected externally. A feedback voltage of 6V trig-
3 Vfb gers over load protection (OLP). There is a time delay while charging
between 3V and 6V using an internal 5uA current source, which prevents
false triggering under transient conditions but still allows the protection
mechanism to operate under true overload conditions.
Pin to adjust the current limit of the Sense FET. The feedback 0.9mA current
source is diverted to the parallel combination of an internal 2.8kΩ resistor
4 Ipk
and any external resistor to GND on this pin to determine the current limit.
If this pin is tied to Vcc or left floating, the typical current limit will be 2.15A.
This pin connects directly to the rectified AC line voltage source. At start up
the internal switch supplies internal bias and charges an external storage
5 Vstr
capacitor placed between the Vcc pin and ground. Once the Vcc reaches
12V, the internal switch is disabled.
The Drain pin is designed to connect directly to the primary lead of the trans-
former and is capable of switching a maximum of 650V. Minimizing the
6, 7, 8 Drain
length of the trace connecting this pin to the transformer will decrease leak-
age inductance.

Pin Configuration

8DIP
8LSOP

GND 1 8 Drain
Vcc 2 7 Drain
Vfb 3 6 Drain
Ipk 4 5 Vstr

Figure 3. Pin Configuration (Top View)

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FSDL0365RN, FSDM0365RN

Absolute Maximum Ratings

(Ta=25°C, unless otherwise specified)

Characteristic Symbol Value Unit

(1)
Drain Current Pulsed IDM 12.0 ADC
Single Pulsed Avalanche Energy(2) EAS 127 mJ
Maximum Supply Voltage VCC,MAX 20 V
Analog Input Voltage Range VFB -0.3 to VSD V
Total Power Dissipation PD 1.56 W
Operating Junction Temperature. TJ +150 °C
Operating Ambient Temperature. TA -25 to +85 °C
Storage Temperature Range. TSTG -55 to +150 °C

Note:
1. Repetitive rating: Pulse width limited by maximum junction temperature
2. L = 51mH, starting Tj = 25°C
3. L = 13µH, starting Tj = 25°C
4. Vsd is shutdown feedback voltage ( see Protection Section in Electrical Characteristics )

Thermal Impedance

Parameter Symbol Value Unit

8DIP
Junction-to-Ambient Thermal θJA(1) 85.74 °C/W(3)
Junction-to-Case Thermal θJC(2) 30.38 °C/W

Note:
1. Free standing with no heatsink.
2. Measured on the GND pin close to plastic interface.
3. Soldered to 0.36 sq. inch(232mm2), 2 oz.(610g/m2) copper clad.

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 FSDL0365RN, FSDM0365RN

Electrical Characteristics
(Ta = 25°C unless otherwise specified)

Parameter Symbol Condition Min. Typ. Max. Unit

Sense FET SECTION

Startup Voltage (Vstr) Breakdown BVSTR VCC=0V, ID=1mA 650 - - V

Drain-Source Breakdown Voltage BVDSS VGS=0V, ID=50µA 650 - - V

VDS=660V, VGS=0V - - 50 µA
Off-State Current
IDSS VDS=0.8Max.Rating,
(Max.Rating =660V) - - 200 µA
VGS=0V, TC=125°C

On-State Resistance(1) RDS(ON) VGS=10V, ID=0.5A - 3.6 4.5 Ω

Input Capacitance CISS - 315 - pF

Output Capacitance COSS VGS=0V, VDS=25V, - 47 -

F=1MHz pF
Reverse Transfer Capacitance CRSS - 9 - pF

Turn On Delay Time TD(ON) - 11.2 - ns

VDS=325V, ID=1.0A
Rise Time TR (Sense FET switching - 34 - ns
time is essentially
Turn Off Delay Time TD(OFF) independent of - 28.2 - ns
operating temperature)
Fall Time TF - 32 - ns

CONTROL SECTION

Output Frequency FOSC 61 67 73 KHz

FSDM0365R
Output Frequency Modulation FMOD ±1.5 ±2.0 ±2.5 KHz

Output Frequency FOSC 45 50 55 KHz

FSDL0365R
Output Frequency Modulation FMOD ±1.0 ±1.5 ±2.0 KHz

Frequency Change With Temperature(2) - -25°C ≤ Ta ≤ 85°C - ±5 ±10 %

Maximum Duty Cycle DMAX 71 77 83 %

Minimum Duty Cycle DMIN 0 0 0 %

Start threshold voltage VSTART VFB=GND 11 12 13 V

Stop threshold voltage VSTOP VFB=GND 7 8 9 V

Feedback Source Current IFB VFB=GND 0.7 0.9 1.1 mA

Internal Soft Start Time TS/S VFB=4V 10 15 20 ms

BURST MODE SECTION

VBURH - 0.4 0.5 0.6 V

Burst Mode Voltages
VBURL - 0.25 0.35 0.45 V

PROTECTION SECTION

Drain to Source Peak Current Limit IOVER Max. inductor current 1.89 2.15 2.41 A

5
FSDL0365RN, FSDM0365RN

Current Limit Delay(3) TCLD - 500 - ns

Thermal Shutdown TSD - 125 140 - °C

Shutdown Feedback Voltage VSD 5.5 6.0 6.5 V

Over Voltage Protection VOVP 18 19 - V

Shutdown Feedback Delay Current IDELAY VFB=4V 3.5 5.0 6.5 µA

Leading Edge Blanking Time TLEB 200 - - ns

TOTAL DEVICE SECTION

Operating Current IOP VCC=14V 1 3 5 mA

Start Up Current ISTART VCC=0V 0.7 0.85 1.0 mA

Vstr Supply Voltage VSTR VCC=0V 35 - - V

Note:
1. Pulse test: Pulse width ≤ 300uS, duty ≤ 2%
2. These parameters, although guaranteed, are tested in EDS (wafer test) process
3. These parameters, although guaranteed, are not 100% tested in production

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 FSDL0365RN, FSDM0365RN

Comparison Between KA5x0365RN and FSDx0365RN

Function KA5x0365RN FSDx0365RN FSDx0365RN Advantages
Soft-Start not applicable 15mS • Gradually increasing current limit
during soft-start further reduces peak
current and voltage component
stresses
• Eliminates external components used
for soft-start in most applications
• Reduces or eliminates output
overshoot
External Current Limit not applicable Programmable of • Smaller transformer
default current limit • Allows power limiting (constant over-
load power)
• Allows use of larger device for lower
losses and higher efficiency.
Frequency Modulation not applicable ±2.0KHz @67KHz • Reduced conducted EMI
±1.5KHz @50KHz
Burst Mode Operation not applicable Yes-built into • Improve light load efficiency
controller • Reduces no-load consumption
• Transformer audible noise reduction
Drain Creepage at 1,02mm 7.62mm • Greater immunity to arcing as a result
Package of build-up of dust, debris and other
contaminants

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FSDL0365RN, FSDM0365RN

Typical Performance Characteristics (Sense FET part)

1
10
VGS
Top : 15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
ID, Drain Current [A]

Bottom : 5.5 V
0
10

-1
10 ※ Note :
1. 250µs Pulse Test
2. TC = 25℃

0 1
10 10

VDS, Drain-Source Voltage [V]

Output Characteristics

8.0

7.5
IDR , Reverse Drain Current [A]

1
10
Drain-Source On-Resistance

7.0

6.5
VGS = 10V
6.0
RDS(ON) [Ω ],

5.5
VGS = 20V
5.0 0
10
150℃
4.5
25℃
4.0 ※ Note :
1. VGS = 0V
3.5 2. 250µ s Pulse Test

3.0 ※ Note : TJ = 25℃

-1
2.5 10
0 1 2 3 4 5 6 7 0.2 0.4 0.6 0.8 1.0 1.2 1.4
ID, Drain Current [A] VSD , Source-Drain Voltage [V]

On-Resistance vs. Drain Current Source-Drain Diode Forward Voltage

700 12
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
600 Crss = Cgd 10 VDS = 130V
VGS, Gate-Source Voltage [V]

Ciss V DS = 325V
500
8
Capacitances [pF]

VDS = 520V
400 Coss
6
300

Crss ※ Note ; 4
200 1. VGS = 0 V
2. f = 1 MHz

100 2 ※ Note : ID = 3.0 A

-1 0 1
0
10 10 10 0 2 4 6 8 10 12

VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC]

Capacitance vs. Drain-Source Voltage Gate Charge vs. Gate-Source Voltage

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 FSDL0365RN, FSDM0365RN

Typical Performance Characteristics (Continued)

1.15
Drain-Source Breakdown Voltage

2.5

Drain-Source On-Resistance
1.10
BVDSS, (Normalized)

RDS(ON), (Normalized)
2.0
1.05

1.5
1.00

1.0
0.95
※ Note :
1. VGS = 0 V ※ Note :
2. ID = 250 µ A 1. VGS = 10 V
0.90 0.5 2. ID = 1.5 A

-50 0 50 100 150 -50 0 50 100 150

o o
TJ, Junction Temperature [ C] TJ, Junction Temperature [ C]

Breakdown Voltage vs. Temperature On-Resistance vs. Temperature

2.0
1
10 Operation in This Area
is Limited by R DS(on)

10 µs

100 µs 1.5
0
10
ID, Drain Current [A]
ID, Drain Current [A]

1 ms
10 ms
100 ms
1s 1.0
DC 10 s
-1
10

10
-2 0.5

-3
10 0.0
0 1 2
10 10 10 25 50 75 100 125 150

VDS, Drain-Source Voltage [V] TC, Case Temperature [℃]

Max. Safe Operating Area Max. Drain Current vs. Case Temperature

0.2
D=0.5

0.2
Zθ JC(t), Thermal Response

10
0.1
0.05

0.02
1 0.01
※ Notes :
1. Zθ JC(t) = 80 ℃/W Max.
2. Duty Factor, D=t1/t2
single pulse 3. TJM - TC = PDM * Zθ JC(t)
0.1

1E-5 1E-4 1E-3 0.01 0.1 1 10 100 1000

t1, Square Wave Pulse Duration [sec]

Thermal Response

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FSDL0365RN, FSDM0365RN

Typical Performance Characteristics (Control Part)

(These characteristic graphs are normalized at Ta = 25°C)

1.20 1.20
1.00 1.00
Normalized

Normalized
0.80 0.80
0.60 0.60
0.40 0.40
0.20 0.20
0.00 0.00
-50 0 50 100 150 -50 0 50 100 150
T emp[ ℃] T emp[ ℃]

Operating Frequency (Fosc) Frequency Modulation (FMOD)

1.20 1.20
1.00 1.00
Normalized

Normalized

0.80 0.80
0.60 0.60
0.40 0.40
0.20 0.20
0.00 0.00
-50 0 50 100 150 -50 0 50 100 150
T emp[ ℃] T emp[ ℃]

Maximum duty cycle (Dmax) Operating supply current (Iop)

1.20 1.20
1.00 1.00
Normalized
Nomalized

0.80 0.80
0.60 0.60
0.40 0.40
0.20 0.20
0.00 0.00
-50 0 50 100 150 -50 0 50 100 150
T emp[ ℃] T emp[ ℃]

Start Threshold Voltage (Vstart) Stop Threshold Voltage (Vstop)

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 FSDL0365RN, FSDM0365RN

Typical Performance Characteristics (Continued)

1.20 1.20
1.00 1.00

Normalized
Normalized

0.80 0.80
0.60 0.60
0.40 0.40
0.20 0.20
0.00 0.00
-50 0 50 100 150 -50 0 50 100 150

T emp[ ℃] T emp[ ℃]

Feedback Source Current (Ifb) Peak current limit (Iover)

1.20 1.20
1.00 1.00
Normalized

Normalized

0.80 0.80
0.60 0.60
0.40 0.40
0.20 0.20
0.00 0.00
-50 0 50 100 150 -50 0 50 100 150
T emp[ ℃] T emp[ ℃]

Start up Current (Istart) J-FET Start up current (Istr)

1.20 1.20
1.00 1.00
Normalized
Normalized

0.80 0.80
0.60 0.60
0.40 0.40

0.20 0.20

0.00 0.00
-50 0 50 100 150 -50 0 50 100 150

T emp[ ℃] Temp[℃]

Burst peak current (Iburst) Over Voltage Protection (Vovp)

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FSDL0365RN, FSDM0365RN

Functional Description
1. Startup : In previous generations of Fairchild Power Vcc Vref
Switches (FPS) the Vstr pin had an external resistor to the 2uA 0.9mA
DC input voltage line. In this generation the startup resistor Vo Vfb FB
is replaced by an internal high voltage current source and a 3
D1 D2
OSC

switch that shuts off when 15mS goes by after the supply Cfb 28R
Vfb*
voltage, Vcc, gets above 12V. The source turns back on if Gate
R driver
Vcc drops below 8V.
431

OLP
VSD
Vin,dc
Istr
Figure 5. Pulse width modulation (PWM) circuit

Vstr
Vcc UVLO <8V
on
J-FET
4. Protection Circuit : The FPS has several protective func-
tions such as over load protection (OLP), over voltage pro-
15m S After UVLO
start(>12V) tection (OVP), abnormal over current protection (AOCP),
off
under voltage lock out (UVLO) and thermal shutdown
(TSD). Because these protection circuits are fully integrated
inside the IC without external components, the reliability is
improved without increasing cost. Once the fault condition
occurs, switching is terminated and the Sense FET remains
Figure 4. High voltage current source off. This causes Vcc to fall. When Vcc reaches the UVLO
stop voltage, 8V, the protection is reset and the internal high
voltage current source charges the Vcc capacitor via the Vstr
pin. When Vcc reaches the UVLO start voltage,12V, the FPS
2. Feedback Control : The FSDx0365RN employs current resumes its normal operation. In this manner, the auto-restart
mode control, shown in figure 5. An opto-coupler (such as can alternately enable and disable the switching of the power
the H11A817A) and shunt regulator (such as the KA431) are Sense FET until the fault condition is eliminated.
typically used to implement the feedback network. Compar-
ing the feedback voltage with the voltage across the Rsense
resistor plus an offset voltage makes it possible to control the
switching duty cycle. When the reference pin voltage of the 4.1 Over Load Protection (OLP) : Overload is defined as the
KA431 exceeds the internal reference voltage of 2.5V, the load current exceeding a pre-set level due to an unexpected
H11A817A LED current increases, thus pulling down the event. In this situation, the protection circuit should be acti-
feedback voltage and reducing the duty cycle. This event vated in order to protect the SMPS. However, even when the
typically happens when the input voltage is increased or the SMPS is in the normal operation, the over load protection
output load is decreased. circuit can be activated during the load transition. In order to
avoid this undesired operation, the over load protection cir-
cuit is designed to be activated after a specified time to deter-
mine whether it is a transient situation or an overload
3. Leading edge blanking (LEB) : At the instant the internal situation. In conjunction with the Ipk current limit pin (if
Sense FET is turned on, there usually exists a high current used) the current mode feedback path would limit the current
spike through the Sense FET, caused by the primary side in the Sense FET when the maximum PWM duty cycle is
capacitance and secondary side rectifier diode reverse recov- attained. If the output consumes more than this maximum
ery. Excessive voltage across the Rsense resistor would lead power, the output voltage (Vo) decreases below the set volt-
to incorrect feedback operation in the current mode PWM age. This reduces the current through the opto-coupler LED,
control. To counter this effect, the FPS employs a leading which also reduces the opto-coupler transistor current, thus
edge blanking (LEB) circuit. This circuit inhibits the PWM increasing the feedback voltage (Vfb). If Vfb exceeds 3V, the feed-
comparator for a short time (TLEB) after the Sense FET is back input diode is blocked and the 5uA Idelay current source starts
turned on. to charge Cfb slowly up to Vcc. In this condition, Vfb continues
increasing until it reaches 6V, when the switching operation is ter-
minated as shown in figure 6. The delay time for shutdown is the
time required to charge Cfb from 3V to 6V with 5uA.

12
 FSDL0365RN, FSDM0365RN

monitors the current through the sensing resistor. The volt-

age across the resistor is then compared with a preset AOCP
level. If the sensing resistor voltage is greater than the AOCP
Vcc
level, pulse by pulse AOCP is triggered regardless of uncon-
trollable LEB time. Here, pulse by pulse AOCP stops Sense
8V FET within 350nS after it is activated.
OLP
6V
FPS switching

Following Vcc
3V 4.4 Over Voltage Protection (OVP) : In case of malfunc-
tion in the secondary side feedback circuit, or feedback loop
Delay current (5uA) charges the Cfb
open caused by a defect of solder, the current through the
t1 t2
opto-coupler transistor becomes almost zero. Then, Vfb
t3 t4 t
climbs up in a similar manner to the over load situation, forc-
1 V ( t 1)
ing the preset maximum current to be supplied to the SMPS
t1 = − In (1 − ); V ( t1) = 3V , R = 2 . 8 K Ω , C fb = C
RC fb R
fb _ fig . 2
until the over load protection is activated. Because excess
(V (t1 + t 2) − V (t1)) energy is provided to the output, the output voltage may
t 2 = C fb ; I delay = 5uA,V (t1 + t 2) − V (t1) = 3V
I delay exceed the rated voltage before the over load protection is
activated, resulting in the breakdown of the devices in the
secondary side. In order to prevent this situation, an over
Figure 6. Over load protection voltage protection (OVP) circuit is employed. In general,
Vcc is proportional to the output voltage and the FPS uses
Vcc instead of directly monitoring the output voltage. If
VCC exceeds 19V, OVP circuit is activated resulting in ter-
4.2 Thermal Shutdown (TSD) : The Sense FET and the con-
mination of the switching operation. In order to avoid undes-
trol IC are integrated, making it easier for the control IC to
ired activation of OVP during normal operation, Vcc should
detect the temperature of the Sense FET. When the tempera-
be properly designed to be below 19V.
ture exceeds approximately 140°C, thermal shutdown is acti-
vated.

5. Soft Start : The FPS has an internal soft start circuit that
increases the feedback voltage together with the Sense FET
4.3 Abnormal Over Current Protection (AOCP) :
current slowly after it starts up. The typical soft start time is
15msec, as shown in figure 8, where progressive increments
of Sense FET current are allowed during the start-up phase.
PWM
COMPARATOR The pulse width to the power switching device is progres-
Vfb CLK sively increased to establish the correct working conditions
LEB Drain
Out Driver
for transformers, inductors, and capacitors. The voltage on
Vsense the output capacitors is progressively increased with the
AOCP intention of smoothly establishing the required output volt-
COMPARATOR S Q
age. It also helps to prevent transformer saturation and
R reduce the stress on the secondary diode.

VAOCP Rsense

Drain current
[A]
Figure 7. AOCP Function & Block 2.15A

1mS
15steps

Even though the FPS has OLP (Over Load Protection) and
Current limit
current mode PWM feedback, these are not enough to pro-
0.98A
tect the FPS when a secondary side diode short or a trans-
former pin short occurs. In addition to start-up, soft-start is
t
also activated at each restart attempt during auto-restart and
when restarting after latch mode is activated. The FPS has an
internal AOCP (Abnormal Over Current Protection) circuit
as shown in figure 7. When the gate turn-on signal is applied
to the power Sense FET, the AOCP block is enabled and

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FSDL0365RN, FSDM0365RN

5V D R A IN

Burst Operation Burst Operation

Feedback
Normal Operation

S W IT C H GND
OFF 0.5V

Rsense
I_ o v e r 0.3V
Current
waveform

Switching OFF Switching OFF

Figure 8. Soft Start Function

Figure 10. Circuit for Burst Operation

6. Burst operation :In order to minimize power dissipation in

standby mode, the FPS enters burst mode operation.

7. Frequency Modulation : EMI reduction can be accom-

plished by modulating the switching frequency of a switched
+
power supply. Frequency modulation can reduce EMI by
0.3/0.5V - spreading the energy over a wider frequency range than the
0.5V
Vcc
band width measured by the EMI test equipment. The
amount of EMI reduction is directly related to the depth of
IB_PEAK
the reference frequency. As can be seen in Figure 11, the fre-
Vcc Vcc
quency changes from 65KHz to 69KHz in 4mS for the
Idelay
FB
IFB
Normal
FSDM0265RN. Frequency modulation allows the use of a
PWM
3 cost effective inductor instead of an AC input mode choke to
2.5R Burst
satisfy the requirements of world wide EMI limits.
R
MOSFET
Current

Internal
O scillator
Figure 9. Circuit for Burst operation

69kH z

As the load decreases, the feedback voltage decreases. As shown in

D rain to
figure 10, the device automatically enters burst mode when the S ourc e
voltage
feedback voltage drops below VBURH(500mV). Switching still con-
tinues but the current limit is set to a fixed limit internally to mini-
mize flux density in the transformer. The fixed current limit is
larger than that defined by Vfb = VBURH and therefore, Vfb is D rain to
V ds
S ource
driven down further. Switching continues until the feedback W aveform
current
voltage drops below VBURL(300mV). At this point switching 65kH z
4k H z

stops and the output voltages start to drop at a rate dependent 67kH z
on the standby current load. This causes the feedback volt- 69kH z

age to rise. Once it passes VBURH(500mV) switching resumes.

T urn-on T urn-off
The feedback voltage then falls and the process repeats. Burst point
mode operation alternately enables and disables switching of
the power Sense FET thereby reducing switching loss in Figure 11. Frequency Modulation Waveform
Standby mode.

14
 FSDL0365RN, FSDM0365RN

5uA 900uA
Feed
CISPR2QB Back
Amplitude (dBµV)

3
CISPR2AB
2 KΩ PWM
comparator

Current 4
Limit 0.8 KΩ

AK Ω Rsense SenseFET
Sense

Figure 14. Peak current adjustment

Frequency (MHz)

Figure 12. KA5-series FPS Full Range EMI scan(67KHz, For example, FSDx0265RN has a typical Sense FET current
no Frequency Modulation) with DVD Player SET
limit (IOVER) of 2.15A. The Sense FET current can be limited to
1A by inserting a 2.8kΩ between the current limit pin and
ground which is derived from the following equations:

2.15: 1 = 2.8KΩ : XKΩ ,

CISPR2QB
X = 1.3KΩ,
Amplitude (dBµV)

CISPR2AB

Since X represents the resistance of the parallel network, Y

can be calculated using the following equation:

Y = X / (1 - (X/2.8KΩ))

Frequency (MHz)

Figure 13. FSDX-series FPS Full Range EMI Scan (67KHz,

with Frequency Modulation) with DVD Player SET

8. Adjusting Current limit function: As shown in fig 14, a

combined 2.8KΩ internal resistance is connected into the
non-inverting lead on the PWM comparator. A external
resistance of Y on the current limit pin forms a parallel resis-
tance with the 2.8KΩ when the internal diodes are biased by
the main current source of 900uA.

15
FSDL0365RN, FSDM0365RN

Typical application circuit

1. Set Top Box Example Circuit (20W Output Power)
12
2A/250V C7 +23.0V
1
400V C8 D12 R15 C17
0.005~0.45A
FUSE 6.8n/ EGP20D 20R
/47u 100uF 100uF
R3 R1 1kV /50V /50V
56K/1/ 47K L3
85VAC 100pF 4W D5 11
+17.0V
~275VAC /400V LF1 UF4007
KBP06M D13
40mH 3 C15 C16 0.01~0.5A
C1 100pF EGP20D 470uF 220uF
/400V
/35V /35V
C2
L2
D14
5 10
D D D start +5.0V
GreenFPS EGP20D C14 0.2~0.85A
C13
FSDM0365RN 1000uF 470uF
/10V R20
S VccVfb I_pk /16V
R4 SB360
1 R5
PERFORMANCE SUMMARY 6kR
30R
4 6
D15 L1

Output Power: 20W C12

+3.3V
0.4~1.4A
D6
Regulation C6 UF4004 8
C11
1000uF 470uF
3.3V: ±5% 50V
47uF
5 /16V /10V R19

5.0V: ±5% C9
PC817
R21 R22
R14
R13
33n
17.0V: ±7% 330R 1KR 800R 2.7K
50V
23.0: ±7% Q1 FOD2741A
0.1uF/
monolithic
Efficiency: ≥75% PC817
C209
No load Consumption:
R15 6.9K
0.12W at 230Vac TL431AZ
R12
1.5K

Figure15. 20W multiple power supply using FSDM0365RN

Multiple Output, 20W, 85-265VAC Input Power supply: ing is provided by L3, L2 and L1. Resistor R15 prevents
Figure 15 shows a multiple output supply typical for high peak charging of the lightly loaded 23V output. The outputs
end set-top boxes containing high capacity hard disks for are regulated by the reference (TL431) voltage in secondary.
recording or LIPS(LCD Inverter Power Supply) for 15" Both the 3.3 V and 5 V outputs are sensed via R13 and R14.
LCD monitor. The supply delivers an output power of 20W Resistor R22 provides bias for TL431and R21 sets the over-
cont./24 W peak (thermally limited) from an input voltage of all DC gain. Resistor R21, C209, R14 and R13 provide loop
85 to 265 VAC. Efficiency at 20W, 85VAC is ≥75%. compensation.

The 3.3 V and 5 V outputs are regulated to ±5% without the

need for secondary linear regulators. DC stacking (the sec-
ondary winding reference for the other output voltages is
connected to the anode of D15. For more accuracy, connec-
tion to the cathode of D15 will be better.) is used to minimize
the voltage error for the higher voltage outputs. Due to the
high ambient operating temperature requirement typical of a
set-top box (60 °C) the FSDL0165RN is used to reduce con-
duction losses without a heatsink. Resistor R5 sets the device
current limit to limit overload power.

Leakage inductance clamping is provided by R1 and C8,

keeping the DRAIN voltage below 650 V under all condi-
tions. Resistor R1 and capacitor C8 are selected such that R1
dissipates power to prevent rising of DRAIN Voltage caused
by leakage inductance. The frequency modulation feature of
FSDL0165RN allows the circuit shown to meet CISPR2AB
with simple EMI filtering (C1, LF1 and C2) and the output
grounded. The secondaries are rectified and smoothed by
D12, D13, D14,and D15. Diode D15 for the 3.4V output is a
Schottky diode to maximize efficiency. Diode D14 for the 5
V output is a PN type to center the 5 V output at 5 V. The 3.3
V and 5 V output voltage require two capacitors in parallel to
meet the ripple current requirement. Switching noise filter-

16
 FSDL0365RN, FSDM0365RN

2. Transformer Specification

1. TR AN SFO RM ER SPECIFICATIO N

- SCHEM ATIC DIAG R AM (TR ANSFO RM ER)

3mm
6mm
1 12

11
2
NB
10 N P/2
3
N 23V
4 8 N 17V
N 5V
7 N 3.3V
top N P/2 bottom
5
6

2. W INDING SPEC IFIC ATIO N

NO. PIN(S → F) W IRE TURNS W INDING METHOD

N P/2 3 → 2 0.25 Φ × 1 22 SOLENOID W INDING

N 3.3V 6 → 8 0.3 Φ × 8 2 STACK W INDING

N 5V 10 → 6 0.3 Φ × 2 1 STACK W INDING

N 16V 11 → 6 0.3 Φ × 4 7 SOLENOID W INDING

N 23V 12 → 11 0.3 Φ × 2 3 SOLENOID W INDING

N P/2 2 → 1 0.25 Φ × 1 22 SOLENOID W INDING

NB 4 → 5 0.25 Φ × 1 10 CENTER W INDING

3. ELECTRIC CH AR ACTERISTIC

CLOSURE PIN SPEC. REM ARKS

INDUCTANCE 1-3 800uH ± 10% 1KHz, 1V

LEAKAGE L 1-3 15uH MAX. 2nd ALL SHORT

4. BOBBIN & CO R E.

CORE: EER 2828

BO BBIN: EER 2828

17
FSDL0365RN, FSDM0365RN

Layout Considerations

SURFACE MOUNTED
COPPER AREA FOR HEAT
SINKING

DC_link Capacitor

#1 : GND
#2 : VCC
#3 : Vfb
#4 : Ipk
#5 : Vstr
#6 : Drain
#7 : Drain - +
#8 : Drain
DC
Y1- OUT
CAPACITOR

Figure 15. Layout Considerations for FSDx0365RN using 8DIP

18
 FSDL0365RN, FSDM0365RN

Package Dimensions

8DIP

19
FSDL0365RN, FSDM0365RN

Package Dimensions (Continued)

8LSOP

20
 FSDL0365RN, FSDM0365RN

Ordering Information
Product Number Package Marking Code BVDSS FOSC RDS(on)
FSDM0365RN 8DIP DM0365R 650V 67KHz 3.6Ω
FSDL0365RN 8DIP DL0365R 650V 50KHz 3.6Ω
FSDM0365RL 8LSOP DM0365R 650V 67KHz 3.6Ω
FSDL0365RL 8LSOP DL0365R 650V 50KHz 3.6Ω

21
FSDL0365RN, FSDM0365RN

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, and (c) whose failure to reasonably expected to cause the failure of the life support
perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

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6/17/04 0.0m 001

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