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 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
October 2013

FSL117MRIN
Green-Mode Fairchild Power Switch (FPS™)

Features Description
 Advanced Soft Burst Mode for The FSL117MRIN is an integrated Pulse Width
Low Standby Power and Low Audible Noise Modulation (PWM) controller and 700 V SenseFET
specifically designed for offline Switched-Mode Power
 Random Frequency Fluctuation (RFF) for Low EMI Supplies (SMPS) with minimal external components.
 Under 50 mW Standby Power Consumption at The PWM controller includes an integrated fixed-
265 VAC, No-load Condition with Burst Mode frequency oscillator, Line Over-Voltage Protection
(LOVP), Under-Voltage Lockout (UVLO), Leading-
 Pulse-by-Pulse Current Limit Edge Blanking (LEB), optimized gate driver, internal
 Overload Protection (OLP), Over-Voltage Protection soft-start, temperature-compensated precise current
(OVP), Abnormal Over-Current Protection (AOCP), sources for loop compensation, and self-protection
Internal Thermal Shutdown (TSD) with Hysteresis, circuitry. Compared with a discrete MOSFET and
Output-Short Protection (OSP), Line Over-Voltage PWM controller solution, the FSL117MRIN can reduce
Protection (LOVP), and Under-Voltage Lockout total cost, component count, size, and weight; while
(UVLO) with Hysteresis simultaneously increasing efficiency, productivity, and
system reliability. This device provides a basic platform
 Low Operating Current (0.4 mA) in Burst Mode for cost-effective design of a flyback converter.
 Internal Startup Circuit
 Internal Avalanche-Rugged 700 V SenseFET
 Built-in Soft-Start: 15 ms
 Auto-Restart Mode

Applications
 Power Supply for Home Appliances, LCD Monitors,
STBs, and DVD Players

Ordering Information
Output Power Table(2)
Operating Current
(1) RDS(ON) 230VAC ±15% 85~265VAC
Part Number Package Junction Limit
(Max.)
Temperature (Typ.) Open Open
Adapter(3) Adapter(3)
Frame(4) Frame(4)
FSL117MRIN 8-DIP -40°C ~ +125°C 0.8 A 11 Ω 10 W 15 W 6W 10 W

Notes:
1. Pb-free package per JEDEC J-STD-020B.
2. The junction temperature can limit the maximum output power.
3. Typical continuous power in a non-ventilated enclosed adapter measured at 50C ambient temperature.
4. Maximum practical continuous power in an open-frame design at 50C ambient temperature.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev 1.0.3
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
Application Circuit
VO

AC
IN

VSTR
VIN
Drain

PWM
GND

FB VCC

Figure 1. Typical Application Circuit

Internal Block Diagram

VSTR VCC Drain
5 2 6,7,8

ICH
Vburst
0.35V / 0.50V
Soft Burst VREF
VCC Good 7.5V / 12V
Random

VCC VREF
OSC
2.0µA 90µA Soft-Start
IDELAY IFB S Q
PWM
Gate
FB 3 Driver
R Q
3R
R LEB (300ns)

tON<tOSP(1.0μs)

LPF 1 GND
VAOCP
VOSP

TSD S Q
VSD
7.0V
VCC Good R Q
VCC

VOVP
VINH / VINL
24.5V

4
VIN
Figure 2. Internal Block Diagram

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev. 1.0.3 2
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
Pin Configuration

1. GND 8. Drain

2. VCC 7. Drain
FSL117MRIN
3. FB 6. Drain

4. VIN 5. VSTR

Figure 3. Pin Assignments (Top View)

Pin Definitions
Pin # Name Description
1 GND Ground. This pin is the control ground and the SenseFET source.
Power Supply. This pin is the positive supply input, which provides the internal operating
2 VCC
current for both startup and steady-state operation.
Feedback. This pin is internally connected to the inverting input of the PWM comparator.
The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor
3 FB
should be placed between this pin and GND. If the voltage of this pin reaches 7 V, the
overload protection triggers, which shuts down the FPS.
Line Over-Voltage Input. This pin is the input pin of line voltage. The voltage, which is
divided by resistors, is input of this pin. If this pin voltage higher than VINH voltage, the LOVP
4 VIN
triggers, which shuts down the FPS Do not leave this pin floating. If LOVP is not used, this pin
should be connected directly to the GND.
Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link.
At startup, the internal high-voltage current source supplies internal bias and charges the
5 VSTR
external capacitor connected to the VCC pin. Once VCC reaches 12 V, the internal current
source (ICH) is disabled.
6
7 Drain SenseFET Drain. High-voltage power SenseFET drain connection.
8

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev. 1.0.3 3
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VSTR VSTR Pin Voltage 700 V
VDS Drain Pin Voltage 700 V
VCC VCC Pin Voltage 26 V
VFB Feedback Pin Voltage -0.3 10.0 V
VIN VIN Pin Voltage -0.3 10.0 V
(5)
IDM Drain Current Pulsed 4 A
ID Drain Current Continuous (TC=25C) 1 A
(6)
EAS Single Pulsed Avalanche Energy 50 mJ
(7)
PD Total Power Dissipation (TC=25C) 1.5 W
Maximum Junction Temperature +150 C
TJ (8)
Operating Junction Temperature -40 +125 C
TSTG Storage Temperature -55 +150 C
Electrostatic Human Body Model, JESD22-A114 5
ESD kV
Discharge Capability Charged Device Model, JESD22-C101 2
Notes:
5. Non-repetitive rating: pulse width is limited by maximum junction temperature.
6. L=51mH, starting TJ=25C.
7. Infinite cooling condition (refer to the SEMI G30-88).
8. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.

Thermal Impedance
TA=25°C unless otherwise specified. All items are tested with the standards JESD 51-2 and 51-10.

Symbol Parameter Value Unit

(9)
θJA Junction-to-Ambient Thermal Impedance 85 °C/W
(10)
θJC Junction-to-Case Thermal Impedance 20 °C/W
Notes:
9. Free standing without heat sink; without copper clad. (Measurement condition: Just before junction temperature
TJ enters into OTP.)
10. Measured on the DRAIN pin close to plastic interface.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev. 1.0.3 4
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
Electrical Characteristics
TJ = 25C unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Unit

SenseFET Section

BVDSS Drain-Source Breakdown Voltage VCC=0 V, ID=200 µA 700 V

IDSS Zero-Gate-Voltage Drain Current VDS=560 V, TA=125C 200 µA

RDS(ON) Drain-Source On-State Resistance VGS=10 V, ID=0.5 A 8.8 11.0 Ω
CISS Input Capacitance(11) VDS=25 V, VGS=0 V, f=1 MHz 250 pF
COSS Output Capacitance(11) VDS=25 V, VGS=0 V, f=1 MHz 25 pF
tr Rise Time VDS=350 V, ID=1.0 A 4 ns
tf Fall Time VDS=350 V, ID=1.0 A 10 ns
td(on) Turn-On Delay VDS=350 V, ID=1.0 A 12 ns
td(off) Turn-Off Delay VDS=350 V, ID=1.0 A 30 ns
Control Section
fS Switching Frequency(11) VCC=14 V, VFB=4 V 61 67 73 kHz
(11)
fS Switching Frequency Variation -25C < TJ < 125C ±5 ±10 %
DMAX Maximum Duty Ratio VCC=14 V, VFB=4 V 61 67 73 %
DMIN Minimum Duty Ratio VCC=14 V, VFB=0 V 0 %
IFB Feedback Source Current VFB=0 V 65 90 115 µA
VSTART VFB=0 V, VCC Sweep 11 12 13 V
UVLO Threshold Voltage
VSTOP After Turn-on, VFB=0 V 7.0 7.5 8.0 V
tS/S Internal Soft-Start Time VSTR=40 V, VCC Sweep 15 ms
VRECOMM Recommended VCC Range 13 23 V
Burst Mode Section
VBURH 0.45 0.50 0.55 V
VBURL Burst-Mode Voltage VCC=14 V, VFB Sweep 0.30 0.35 0.40 V
VHys 150 mV
Protection Section
ILIM Peak Drain Current Limit di/dt=170 mA/s 0.70 0.80 0.90 A
VSD Shutdown Feedback Voltage VCC=14 V, VFB Sweep 6.45 7.00 7.55 V
IDELAY Shutdown Delay Current VCC=14 V, VFB=4 V 1.2 2.0 2.8 µA
(11,12)
tLEB Leading-Edge Blanking Time 300 ns
VOVP Over-Voltage Protection VCC Sweep 23.0 24.5 26.0 V
Line Over-Voltage Protection
VINH VCC=14 V, VIN Sweep 1.885 1.950 2.015 V
Threshold Voltage
Line Over-Voltage Protection
VINHYS VCC=14 V, VIN Sweep 0.06 V
Hysteresis
tOSP Threshold Time OSP Triggered when 0.7 1.0 1.3 µs
Output-Short
VOSP Threshold VFB tON<tOSP & VFB>VOSP 1.8 2.0 2.2 V
Protection(11)
(Lasts Longer than tOSP_FB)
tOSP_FB VFB Blanking Time 2.0 2.5 3.0 µs
TSD Shutdown Temperature 125 135 145 C
Thermal Shutdown Temperature(11)
THys Hysteresis 60 C
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSL117MRIN • Rev. 1.0.3 5
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
Electrical Characteristics (Continued)
TJ = 25C unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Unit

Total Device Section
Operating Supply Current,
IOP VCC=14 V, VFB=0 V 0.3 0.4 0.5 mA
(Control Part in Burst Mode)
Operating Switching Current,
IOPS VCC=14 V, VFB=2 V 0.8 1.2 1.6 mA
(Control Part and SenseFET Part)
VCC=11 V (Before VCC
ISTART Start Current 85 120 155 A
Reaches VSTART)
ICH Startup Charging Current VCC=VFB=0 V, VSTR=40 V 0.7 1.0 1.3 mA
VSTR Minimum VSTR Supply Voltage VCC=VFB=0 V, VSTR Sweep 26 V
Notes:
11. Although these parameters are guaranteed, they are not 100% tested in production.
12. tLEB includes gate turn-on time.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev. 1.0.3 6
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
Typical Performance Characteristics
Characteristic graphs are normalized at TA=25°C.

1.20 1.20
1.15 1.15
1.10 1.10
1.05 1.05
Normalized

Normalized
1.00 1.00
0.95 0.95
0.90 0.90
0.85 0.85
0.80 0.80
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C] Temperature [ °C]

Figure 4. Operating Supply Current (IOP) vs. TA. Figure 5. Operating Switching Current (IOPS) vs. TA.

1.20 1.40

1.15 1.30
1.10 1.20
1.05 1.10
Normalized

Normalized

1.00 1.00
0.95 0.90
0.90 0.80
0.85 0.70
0.80 0.60
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C] Temperature [ °C]

Figure 6. Startup Charging Current (ICH) vs. TA. Figure 7. Peak Drain Current Limit (ILIM) vs. TA.

1.40 1.20

1.30 1.15

1.20 1.10

1.10 1.05
Normalized
Normalized

1.00 1.00

0.90 0.95

0.80 0.90

0.70 0.85

0.60 0.80
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C] Temperature [ °C]

Figure 8. Feedback Source Current (IFB) vs. TA. Figure 9. Shutdown Delay Current (IDELAY) vs. TA.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev. 1.0.3 7
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
Typical Performance Characteristics
Characteristic graphs are normalized at TA=25°C.

1.20 1.20

1.15 1.15

1.10 1.10

1.05 1.05
Normalized

Normalized
1.00 1.00

0.95 0.95

0.90 0.90

0.85 0.85

0.80 0.80
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C] Temperature [ °C]

Figure 10. UVLO Threshold Voltage (VSTART) vs. TA. Figure 11. UVLO Threshold Voltage (VSTOP) vs. TA.

1.20 1.20

1.15 1.15

1.10 1.10

1.05 1.05
Normalized
Normalized

1.00 1.00

0.95 0.95

0.90 0.90

0.85 0.85

0.80 0.80
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C] Temperature [ °C]

Figure 12. Shutdown Feedback Voltage (VSD) vs. TA. Figure 13. Over-Voltage Protection (VOVP) vs. TA.

1.20 1.20

1.15 1.15
1.10 1.10
1.05 1.05
Normalized

Normalized

1.00 1.00
0.95 0.95
0.90 0.90
0.85 0.85
0.80 0.80
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C] Temperature [ °C]

Figure 14. Switching Frequency (fS) vs. TA. Figure 15. Maximum Duty Ratio (DMAX) vs. TA

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev. 1.0.3 8
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
Typical Performance Characteristics
Characteristic graphs are normalized at TA=25°C.

1.20 1.20

1.15 1.15

1.10 1.10

1.05 1.05
Normalized

Normalized
1.00 1.00

0.95 0.95

0.90 0.90

0.85 0.85

0.80 0.80
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C] Temperature [ °C]

Figure 16. Line OVP (VINH) vs. TA Figure 17. Hysteresis of LOVP (VINHYS) vs. TA.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev. 1.0.3 9
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
Functional Description
1. Startup: At startup, an internal high-voltage current 3. Feedback Control: This device employs current-
source supplies the internal bias and charges the mode control, as shown in Figure 19. An opto-coupler
external capacitor (CVcc) connected to the VCC pin, as (such as the FOD817) and shunt regulator (such as the
illustrated in Figure 18. When VCC reaches 12 V, the KA431) are typically used to implement the feedback
FSL117MRIN begins switching and the internal high- network. Comparing the feedback voltage with the
voltage current source is disabled. Normal switching voltage across the RSENSE resistor makes it possible to
operation continues and the power is supplied from the control the switching duty cycle. When the reference pin
auxiliary transformer winding unless VCC goes below the voltage of the shunt regulator exceeds the internal
stop voltage of 7.5 V. reference voltage of 2.5 V, the opto-coupler LED current
increases, pulling down the feedback voltage and
VDC
reducing drain current. This typically occurs when the
input voltage is increased or the output load is decreased.
CVCC
3.1 Pulse-by-Pulse Current Limit: Because current-
mode control is employed, the peak current through
the SenseFET is limited by the inverting input of the
VCC VSTR PWM comparator (VFB*), as shown in Figure 19.
3 5
Assuming that the 90 μA current source flows only
through the internal resistor (3R + R = 27 kΩ), the
ICH
cathode voltage of diode D2 is about 2.5 V. Since D1
is blocked when the feedback voltage (VFB) exceeds
VREF 2.5 V, the maximum voltage of the cathode of D2 is
VCC Good
7.5V/12.0V clamped at this voltage. Therefore, the peak value of
Internal
the current through the SenseFET is limited.
Bias
3.2 Leading-Edge Blanking (LEB): At the instant the
Figure 18. Startup Block
internal SenseFET is turned on, a high-current spike
2. Soft-Start: The internal soft-start circuit increases the usually occurs through the SenseFET, caused by
PWM comparator inverting input voltage, together with primary-side capacitance and secondary-side rectifier
the SenseFET current, slowly after startup. The typical reverse recovery. Excessive voltage across the RSENSE
soft-start time is 15 ms. The pulse width to the power resistor leads to incorrect feedback operation in the
switching device is progressively increased to establish current-mode PWM control. To counter this effect, the
the correct working conditions for transformers, FSL117MRIN employs a leading-edge blanking (LEB)
inductors, and capacitors. The voltage on the output circuit. This circuit inhibits the PWM comparator for
capacitors is progressively increased to smoothly tLEB (300 ns) after the SenseFET is turned on.
establish the required output voltage. This helps prevent
transformer saturation and reduces stress on the
secondary diode during startup.
Drain
6,7,8
VCC VREF

IDELAY IFB OSC

FB
VOUT VFB 3R PWM
3
FOD817 D1 D2 Gate
* Driver
CFB VFB R
LEB (300ns)

OSP
KA431 VOSP RSENSE
AOCP GND
VAOCP 1
OLP
VSD

Figure 19. Pulse Width Modulation Circuit

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev. 1.0.3 10
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
4. Protection Circuits: The FSL117MRIN has several increasing until it reaches 7.0 V, when the switching
self-protective functions, such as Overload Protection operation is terminated, as shown in Figure 21. The
(OLP), Abnormal Over-Current Protection (AOCP), delay for shutdown is the time required to charge CFB
Output-Short Protection (OSP), Over-Voltage Protection from 2.5 V to 7.0 V with 2.0 µA. A 25 ~ 50 ms delay is
(OVP), and Thermal Shutdown (TSD). All the typical for most applications. This protection is
protections are implemented as auto-restart. Once a implemented as Auto-Restart Mode.
fault condition is detected, switching is terminated and
the SenseFET remains off. This causes VCC to fall. VFB
Overload Protection
When VCC falls to the Under-Voltage Lockout (UVLO)
B B

stop voltage of 7.5 V, the protection is reset and the

startup circuit charges the VCC capacitor. When VCC 7.0V
reaches the start voltage of 12.0 V, the FSL117MRIN
resumes normal operation. If the fault condition is not
removed, the SenseFET remains off and VCC drops to
stop voltage again. In this manner, the auto-restart can 2.5V
alternately enable and disable the switching of the
power SenseFET until the fault condition is eliminated.
Because these protection circuits are fully integrated t12= CFB×(7.0-2.5)/Idelay
into the IC without external components, the reliability is
improved without increasing cost.
t1 t2 t
Power Fault Fault Figure 21. Overload Protection
VDS on occurs removed

4.2 Abnormal Over-Current Protection (AOCP):

When the secondary rectifier diodes or the
transformer pins are shorted, a steep current with
extremely high di/dt can flow through the SenseFET
during the minimum turn-on time. Overload protection
is not enough to protect the FSL117MRIN in that
VCC abnormal case; since severe current stress is
imposed on the SenseFET until OLP is triggered. The
internal AOCP circuit is shown in Figure 22. When the
12.0V
gate turn-on signal is applied to the power SenseFET,
7.5V the AOCP block is enabled and monitors the current
through the sensing-resistor. The voltage across the
resistor is compared with a preset AOCP level. If the
t
sensing resistor voltage is greater than the AOCP
Normal Fault Normal level, the set signal is applied to the S-R latch,
operation situation operation resulting in the shutdown of the SMPS.
Figure 20. Auto-Restart Protection Waveforms Drain
6,7,8
4.1 Overload Protection (OLP): Overload is defined OSC
as the load current exceeding its normal level due to
an unexpected abnormal event. In this situation, the 3R
PWM
protection circuit should trigger to protect the SMPS. Gate
However, even when the SMPS is in normal *
R
Driver
VFB
operation, the overload protection circuit can be
LEB (300ns)
triggered during load transition. To avoid this
undesired operation, the overload protection circuit is
designed to trigger only after a specified time to
determine whether it is a transient situation or a true RSENSE
Q S GND
overload situation. Because of the pulse-by-pulse VAOCP 1
current-limit capability, the maximum peak current Q R VCC Good
through the SenseFET is limited and, therefore, the
maximum input power is restricted with a given input
voltage. If the output consumes more than this
maximum power, the output voltage (VOUT) decreases Figure 22. Abnormal Over-Current Protection
below the set voltage. This reduces the current
through the opto-coupler LED, which also reduces the
opto-coupler transistor current, thus increasing the
feedback voltage (VFB). If VFB exceeds 2.5 V, D1 is
blocked and the 2.0 µA current source starts to
charge CFB slowly up. In this condition, VFB continues

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev. 1.0.3 11
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
4.3. Output-Short Protection (OSP): If the output is 4.6 Line Over-Voltage Protection (LOVP): If the line
shorted, steep current with extremely high di/dt can input voltage is increased to an undesirable level, high
flow through the SenseFET during the minimum turn- line input voltage creates high-voltage stress on the
on time. Such a steep current creates high-voltage entire system. To protect from this abnormal condition,
stress on the drain of the SenseFET when turned off. LOVP is included. It is comprised of detecting VIN using
To protect the device from this abnormal condition, divided resistors. When VIN is higher than 1.95 V, this
OSP is included. It is comprised of detecting VFB and condition is recognized as an abnormal error and PWM
SenseFET turn-on time. When the VFB is higher than switching shuts down until VIN decreases to around
2.0 V and the SenseFET turn-on time is lower than 1.89 V (60 mV hysteresis).
1.0 μs, the FSL117MRIN recognizes this condition as
an abnormal error and shuts down PWM switching
VIN
until VCC reaches VSTART again. An abnormal condition VINH = 1.95 V
VINL = 1.89 V
output short is shown in Figure 23.
VAC

MOSFET Rectifier ILIM

Drain Diode IDS
VFB*=0.5V
Current Current
→ VFB=2.0V
VFB*

ILm

LOVP LOVP triggered

0 t
1.0μs 1.0μs
tOFF tON
Output Short Occurs

VOUT
VSTART = 12.0 V
VCC
IOUT
0 t
VSTOP = 7.5 V
OSP Triggered
OSP

0 t
Figure 24. Line Over-Voltage Protection
Unlike previous FPS™ families, FSL117MRIN’s VIN pin
Figure 23. Output-Short Protection
can detect the AC line over-voltage protection function.
4.4 Over-Voltage Protection (OVP): If the When the line input voltage exceeds pre-determined
secondary-side feedback circuit malfunctions or a level at the VIN pin, the controller initiates a fault signal
solder defect causes an opening in the feedback path, and shuts down PWM output. To prevent erroneous
the current through the opto-coupler transistor activation of LOVP, the LOVP function is triggered when
becomes almost zero. Then VFB climbs up in a similar line over-voltage lasts more than a specific time. An
manner to the overload situation, forcing the preset important feature of the LOVP function is auto-recovery.
maximum current to be supplied to the SMPS until the The controller continuously monitors line input voltage,
overload protection is triggered. Because more even under fault condition, and turns PWM output on
energy than required is provided to the output, the when over-voltage condition disappears. Equation (1)
output voltage may exceed the rated voltage before calculates the level of input over voltage to RMS value:
the overload protection is triggered, resulting in the
breakdown of the devices in the secondary side. To   R1  R 2  
prevent this situation, an OVP circuit is employed. In VIN _ ovp  1.95    (1)
 R 1 
general, the VCC is proportional to the output voltage  
and the FSL117MRIN uses VCC instead of directly
monitoring the output voltage. If VCC exceeds 24.5 V, The resistance of the divided resistor can be adjusted
an OVP circuit is triggered, resulting in the termination as necessary. Small resistance can bring relatively large
of the switching operation. To avoid undesired standby power consumption at light-load condition. To
activation of OVP during normal operation, VCC should avoid this situation, a several MΩ resistor is
be designed to be below 24.5 V. recommended. For stable operation, a several MΩ
resistor should accompany a capacitor with hundreds of
4.5 Thermal Shutdown (TSD): The SenseFET and pF capacitance between the VIN and GND pins.
the control IC on a die in one package makes it easier
for the control IC to detect the temperature of the
SenseFET. If the temperature exceeds ~140C, the
thermal shutdown is triggered and stops operation.
The FSL117MRIN operates in auto-restart mode until
the temperature decreases to around 75C, when
normal operation resumes.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev. 1.0.3 12
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
5. Soft Burst Mode: To minimize power dissipation in VO

Standby Mode, the FSL117MRIN enters Burst Mode. As

the load decreases, the feedback voltage decreases.
The device automatically enters Burst Mode when the t
feedback voltage drops below VBURL (300 mV), as VFB
shown in Figure 25. At this point, switching stops and
0.45V
the output voltages start to drop at a rate dependent on 0.30V
standby current load. This causes the feedback voltage t
to rise. Once it passes VBURH (450 mV), switching IDS
Soft Burst
resumes. Feedback voltage then falls and the process
repeats. Burst Mode alternately enables and disables
switching of the SenseFET, reducing switching loss in
t
Standby Mode.
VDS

6. Random Frequency Fluctuation (RFF): Fluctuating

switching frequency of an SMPS can reduce EMI by t
spreading the energy over a wide frequency range. The
Switching Switching
amount of EMI reduction is directly related to the disabled disabled
t1 t2 t3 t4
switching frequency variation, which is limited internally.
The switching frequency is determined randomly by Figure 25. Burst-Mode Operation
external feedback voltage and an internal free-running
IDS
oscillator at every switching instant. This random
frequency fluctuation scatters the EMI noise around
typical switching frequency (67 kHz) effectively and can
reduce the cost of the input filter included to meet the fSW
EMI requirements (e.g. EN55022).
ΔfSW t(μs)

fSW
fSW+1/2ΔfSW

fSW-1/2ΔfSW
No Repetition

t(ms)

Figure 26. Random Frequency Fluctuation

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev. 1.0.3 13
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)
Physical Dimensions

9.83
9.00

6.67
6.096

8.255
7.61

5.08 MAX 3.683 7.62

3.20

0.33 MIN

(0.56) 3.60
3.00 0.356
2.54 0.20
0.56
0.355
1.65 9.957
1.27 7.87

7.62

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M-1994
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.

Figure 27. 8-Lead, Dual Inline Package, 8DIP.

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/N0/N08F.pdf .

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev. 1.0.3 14
 FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSL117MRIN • Rev. 1.0.3 15
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