ON Semiconductor

Is Now

To learn more about onsemi™, please visit our website at

www.onsemi.com

onsemi and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
 FSL117MRIN — Green-Mode Power Switch
FSL117MRIN
Green-Mode Power Switch

Features Description
 Advanced Soft Burst Mode for The FSL117MRIN is an integr ated Puls e Width
Low Standby Pow er and Low Audible Noise Modulation ( PWM) controller and 700 V Sens eFET
 Random Frequency Fluctuation (RFF) for Low EMI specifically des igned for offline Sw itched- Mode Pow er
Supplies ( SMPS) w ith minimal external c omponents.
 Under 50 mW Standby Pow er Consumption at The PWM controller includes an integrated fixed-
265 V AC, No-load Condition w ith Burst Mode frequency oscillator , Line Over-Voltage Protection
(LOV P) , Under-Voltage Lockout ( UVLO), Leading-
 Pulse-by-Pulse Current Limit Edge Blanking (LEB) , optimized gate driver, internal
 Overload Protection (OLP), Over-Voltage Protection soft-start, temperatur e-compensated prec ise curr ent
(OVP), Abnormal Over-Current Protection (AOCP), sources for loop compensation, and self-protection
Internal Thermal Shutdow n (TSD) w ith Hysteresis, circuitry. Compar ed w ith a discrete MOSFET and
Output-Short Protection (OSP), Line Over-Voltage PWM controller solution, the FSL117MRIN can reduce
Protection (LOVP), and Under-Voltage Lockout total cost, component count, size, and w eight; w hile
(UVLO) w ith Hysteresis simultaneously increasing efficiency, productiv ity, and
system reliability. This dev ice pr ovides a bas ic platfor m
 Low Operating Current (0.4 mA) in Burst Mode for cost-effective design of a flyback converter.
 Internal Startup Circuit
 Internal Avalanche-Rugged 700 V SenseFET
 Built-in Soft-Start: 15 ms
 Auto-Restart Mode

Applications
 Pow er Supplyfor Home Appliances, LCD Monitors,
STBs, and DVD Players

Ordering Information
Output Power Table (2)
Operating Current 230VAC ±15% 85~265VAC
Part Number Package(1) RDS(ON)
Junction Limit
(Max.)
Temperature (Typ.) Open Open
Adapter(3) Adapter(3)
Frame(4) Frame (4)
FSL117MRIN 8-DIP -40°C ~ +125°C 0.8 A 11 Ω 10 W 15 W 6W 10 W

Notes:
1. Pb-free package per JEDEC J-STD-020B.
2. The junction temperature can limit the maximum output pow er.
3. Typical continuous pow er in a non-ventilated enclosed adapter measured at 50°C ambient temperature.
4. Maximum practical continuous pow er in an open-frame design at 50°C ambient temperature.

© 2012 Semiconductor Components Industries, LLC. Publication Order Number:

December-2017, Rev. 2 FSL117MRIN/D
 FSL117MRIN — Green-Mode Power Switch
Application Circuit
VO

AC
IN

VSTR
VIN
Drain

PWM
GND

FB VCC

Figure 1. Typical Application Circuit

Internal Block Diagram

VSTR VCC Drain
5 2 6,7,8

ICH
Vburst
0.35V / 0.50V
Soft Burst VREF
VCC Good 7.5V / 12V
Random

VCC VREF
OSC
2.0µA 90µA Soft-Start
IDELAY IFB S Q
PWM
Gate
FB 3 Driver
R Q
3R
R LEB (300ns)

tON<tOSP(1.0μs)

LPF 1 GND
VAOCP
VOSP

TSD S Q
VSD
7.0V
VCC Good R Q
VCC

VOVP
VINH / VINL
24.5V

4
VIN
Figure 2. Internal Block Diagram

www.onsemi.com
2
 FSL117MRIN — Green-Mode Power Switch
Pin Configuration

1. GND 8. Drain

2. VCC 7. Drain
FSL117MRIN
3. FB 6. Drain

4. VIN 5. VSTR

Figure 3. Pin Assignm ents (Top View )

Pin Definitions
Pin # Name Description
1 GND Ground. This pin is the control ground and the SenseFET source.
Pow er Supply. This pin is the positive supply input, w hich provides the internal operating
2 V CC
current for both startup and steady-state operation.
Feedback. This pin is internally connected to the inverting input of the PWM comparator.
The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor
3 FB
should be placed betw een this pin and GND. If the voltage of this pin reaches 7 V, the
overload protection triggers, w hich shuts dow n the Pow er Sw itch.
Line Over-Voltage Input. This pin is the input pin of line voltage. The voltage, w hich is
divided by resistors, is input of this pin. If this pin voltage higher than V INH voltage, the LOVP
4 V IN
triggers, w hich shuts dow n the Pow er Sw itch Do not leave this pin floating. If LOVP is not
used, this pin should be connected directly to the GND.
Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link.
At startup, the internal high-voltage current source supplies internal bias and charges the
5 V STR
external capacitor connected to the V CC pin. Once V CC reaches 12 V, the internal current
source (ICH) is disabled.
6
7 Drain SenseFET Drain. High-voltage pow er SenseFET drain connection.
8

www.onsemi.com
3
 FSL117MRIN — Green-Mode Power Switch
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

V STR V STR Pin Voltage 700 V
V DS Drain Pin Voltage 700 V
V CC V CC Pin Voltage 26 V
V FB Feedback Pin Voltage -0.3 10.0 V
V IN V IN Pin Voltage -0.3 10.0 V
(5)
IDM Drain Current Pulsed 4 A
ID Drain Current Continuous (TC=25°C) 1 A
(6)
EAS Single Pulsed Avalanche Energy 50 mJ
(7)
PD Total Pow er Dissipation (TC=25°C) 1.5 W
Maximum Junction Temperature +150 °C
TJ (8)
Operating Junction Temperature -40 +125 °C
TSTG Storage Temperature -55 +150 °C

Electrostatic Human Body Model, JESD22-A114 5

ESD kV
Discharge Capability Charged Device Model, JESD22-C101 2
Notes:
5. Non-repetitive rating: pulse w idth is limited by maximum junction temperature.
6. L=51mH, starting TJ=25°C.
7. Infinite cooling condition (refer to the SEMI G30-88).
8. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.

Thermal Impedance
TA=25°C unless otherw ise specified. All items are tested w ith the standards JESD 51-2 and 51-10.

Symbol Parameter Value Unit

( )
θJA Junction-to-Ambient Thermal Impedance 9 85 °C/W
(10)
θJC Junction-to-Case Thermal Impedance 20 °C/W
Notes:
9. Free standing w ithout heat sink; w ithout copper clad. (Measurement condition: Just before junction temperature
TJ enters into OTP.)
10. Measured on the DRAIN pin close to plastic interface.

www.onsemi.com
4
 FSL117MRIN — Green-Mode Power Switch
Electrical Characteristics
TJ = 25°C unless otherw ise specified.

Symbol Parameter Conditions Min. Typ. Max. Unit

SenseFET Section

BV DSS Drain-Source Breakdow n Voltage V CC=0 V, ID=200 µA 700 V

IDSS Zero-Gate-Voltage Drain Current V DS=560 V, TA=125°C 200 µA

RDS(ON) Drain-Source On-State Resistance V GS=10 V, ID=0.5 A 8.8 11.0 Ω
(11)
CISS Input Capacitance V DS=25 V, V GS=0 V, f=1 MHz 250 pF
(11)
COSS Output Capacitance V DS=25 V, V GS=0 V, f=1 MHz 25 pF
tr Rise Time V DS=350 V, ID=1.0 A 4 ns
tf Fall Time V DS=350 V, ID=1.0 A 10 ns
td(on) Turn-On Delay V DS=350 V, ID=1.0 A 12 ns
td(off) Turn-Off Delay V DS=350 V, ID=1.0 A 30 ns
Control Section
(11)
fS Sw itching Frequency V CC=14 V, V FB=4 V 61 67 73 kHz
(11)
∆f S Sw itching Frequency Variation -25°C < TJ < 125°C ±5 ±10 %
DMAX Maximum Duty Ratio V CC=14 V, V FB=4 V 61 67 73 %
DMIN Minimum Duty Ratio V CC=14 V, V FB=0 V 0 %
IFB Feedback Source Current V FB=0 V 65 90 115 µA
V START V FB=0 V, V CC Sw eep 11 12 13 V
UVLO Threshold Voltage
V STOP After Turn-on, V FB=0 V 7.0 7.5 8.0 V
tS/S Internal Soft-Start Time V STR=40 V, V CC Sw eep 15 ms
V RECOMM Recommended V CC Range 13 23 V
Burst Mode Section
V BURH 0.45 0.50 0.55 V
V BURL Burst-Mode Voltage V CC=14 V, V FB Sw eep 0.30 0.35 0.40 V
V Hys 150 mV
Protection Section
ILIM Peak Drain Current Limit di/dt=170 mA/µs 0.70 0.80 0.90 A
V SD Shutdow n Feedback Voltage V CC=14 V, V FB Sw eep 6.45 7.00 7.55 V
IDELAY Shutdow n Delay Current V CC=14 V, V FB=4 V 1.2 2.0 2.8 µA
(11,12)
tLEB Leading-Edge Blanking Time 300 ns
V OVP Over-Voltage Protection V CC Sw eep 23.0 24.5 26.0 V
Line Over-Voltage Protection
V INH V CC=14 V, V IN Sw eep 1.885 1.950 2.015 V
Threshold Voltage

V INHYS Line Over-Voltage Protection V CC=14 V, V IN Sw eep 0.06 V

Hysteresis
tOSP Threshold Time 0.7 1.0 1.3 µs
OSP Triggered w hen
Output-Short
V OSP (11) Threshold V FB tON<tOSP & V FB>V OSP 1.8 2.0 2.2 V
Protection
tOSP_FB V FB Blanking Time (Lasts Longer than tOSP_FB) 2.0 2.5 3.0 µs
TSD (11) Shutdow n Temperature 125 135 145 °C
Thermal Shutdow n Temperature
THys Hysteresis 60 °C
Continued on the following page…

www.onsemi.com
5
 FSL117MRIN — Green-Mode Power Switch
Electrical Characteristics (Continued)
TJ = 25°C unless otherw ise specified.

Symbol Parameter Conditions Min. Typ. Max. Unit

Total Device Section

IOP Operating Supply Current, V CC=14 V, V FB=0 V 0.3 0.4 0.5 mA

(Control Part in Burst Mode)
Operating Sw itching Current,
IOPS V CC=14 V, V FB=2 V 0.8 1.2 1.6 mA
(Control Part and SenseFET Part)
V CC=11 V (Before V CC
ISTART Start Current 85 120 155 µA
Reaches V START)
ICH Startup Charging Current V CC=V FB=0 V, V STR=40 V 0.7 1.0 1.3 mA
V STR Minimum V STR Supply Voltage V CC=V FB=0 V, V STR Sw eep 26 V
Notes:
11. Although these parameters are guaranteed, they are not 100% tested in production.
12. tLEB includes gate turn-on time.

www.onsemi.com
6
 FSL117MRIN — Green-Mode Power Switch
Typical Performance Characteristics
Characteristic graphs are normalized at TA=25°C.

1.20 1.20
1.15 1.15
1.10 1.10
1.05 1.05
Normalized

Normalized
1.00 1.00
0.95 0.95
0.90 0.90
0.85 0.85
0.80 0.80
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C] Temperature [ °C]

Figure 4. Operating Supply Current (IOP) vs. TA. Figure 5. Operating Sw itching Current (IOPS) vs. TA.

1.20 1.40

1.15 1.30

1.10 1.20

1.05 1.10
Normalized

Normalized

1.00 1.00
0.95 0.90
0.90 0.80
0.85 0.70
0.80 0.60
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C] Temperature [ °C]

Figure 6. Startup Charging Current (ICH) vs. TA. Figure 7. Peak Drain Current Lim it (ILIM ) vs. TA.

1.40 1.20

1.30 1.15

1.20 1.10

1.10 1.05
Normalized
Normalized

1.00 1.00

0.90 0.95

0.80 0.90

0.70 0.85

0.60 0.80
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C] Temperature [ °C]

Figure 8. Feedback Source Current (IFB) vs. TA. Figure 9. Shutdow n Delay Current (IDELAY) vs. TA.

www.onsemi.com
7
 FSL117MRIN — Green-Mode Power Switch
Typical Performance Characteristics
Characteristic graphs are normalized at TA=25°C.

1.20 1.20

1.15 1.15

1.10 1.10

1.05 1.05
Normalized

Normalized
1.00 1.00

0.95 0.95

0.90 0.90

0.85 0.85

0.80 0.80
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C] Temperature [ °C]

Figure 10. UVLO Threshold Voltage (V START) vs. TA. Figure 11. UVLO Threshold Voltage (V STOP) vs. TA.

1.20 1.20

1.15 1.15

1.10 1.10

1.05 1.05
Normalized
Normalized

1.00 1.00

0.95 0.95

0.90 0.90

0.85 0.85

0.80 0.80
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C] Temperature [ °C]

Figure 12. Shutdow n Feedback Voltage (V SD) vs. TA. Figure 13. Over-Voltage Protection (V OVP) vs. TA.

1.20 1.20

1.15 1.15

1.10 1.10

1.05 1.05
Normalized

Normalized

1.00 1.00
0.95 0.95
0.90 0.90
0.85 0.85
0.80 0.80
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C] Temperature [ °C]

Figure 14. Sw itching Frequency (f S) vs. TA. Figure 15. Maxim um Duty Ratio (DMAX) vs. TA

www.onsemi.com
8
 FSL117MRIN — Green-Mode Power Switch
Typical Performance Characteristics
Characteristic graphs are normalized at TA=25°C.

1.20 1.20

1.15 1.15

1.10 1.10

1.05 1.05
Normalized

Normalized
1.00 1.00

0.95 0.95

0.90 0.90

0.85 0.85

0.80 0.80
-40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C -40'C -25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C] Temperature [ °C]

Figure 16. Line OVP (V INH) vs. TA Figure 17. Hysteresis of LOVP (V INHYS) vs. TA.

www.onsemi.com
9
 FSL117MRIN — Green-Mode Power Switch
Functional Description
1. Startup: At startup, an internal high-voltage current 3. Feedback Control: This device employs current-
source supplies the internal bias and charges the mode control, as show n in Figure 19. An opto-coupler
external capacitor ( CVcc) connected to the V CC pin, as (such as the FOD817) and shunt regulator (such as the
illustrated in Figure 18. When V CC reaches 12 V, the KA431) are typically used to implement the feedback
FSL117MRIN begins sw itching and the internal high- netw ork. Comparing the feedback voltage w ith the
voltage current source is disabled. Nor mal sw itching voltage across the RSENSE resistor makes it possible to
operation continues and the pow er is supplied from the control the sw itching duty cycle. When the reference pin
auxiliary transformer w inding unless V CC goes below the voltage of the shunt regulator exceeds the internal
stop voltage of 7.5 V. reference voltage of 2.5 V, the opto-coupler LED current
increases, pulling dow n the feedback voltage and
VDC
reducing drain current. This typically occurs when the
input voltage is increased or the output load is decreased.
CVCC
3.1 Pulse-by-Pulse Current Lim it: Because current-
mode control is employed, the peak current through
the SenseFET is limited by the inverting input of the
VCC VSTR PWM comparator (V FB*), as show n in Figure 19.
3 5
Assuming that the 90 μA current source flows only
through the internal resistor (3R + R = 27 kΩ), the
ICH
cathode voltage of diode D2 is about 2.5 V. Since D1
is blocked w hen the feedback voltage (V FB) exceeds
VREF 2.5 V, the maximum voltage of the cathode of D2 is
VCC Good clamped at this voltage. Therefore, the peak value of
7.5V/12.0V

Internal
the current through the SenseFET is limited.
Bias
Figure 18. Startup Block 3.2 Leading-Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, a high-current spike
2. Soft-Start: The internal soft-start circuit increases the usually occurs through the SenseFET, caused by
PWM comparator inverting input voltage, together w ith primary-side capacitance and secondary-side rectifier
the SenseFET current, slow ly after startup. The typical reverse recovery. Excessive voltage across the RSENSE
soft-start time is 15 ms. The pulse w idth to the pow er resistor leads to incorrect feedback operation in the
sw itching device is progressively increased to establish current-mode PWM control. To counter this effect, the
the correct w orking conditions for transformers, FSL117MRIN employs a leading-edge blanking (LEB)
inductors, and capacitors. The voltage on the output circuit. This circuit inhibits the PWM comparator for
capacitors is progressively increased to s moothly tLEB (300 ns) after the SenseFET is turned on.
establish the required output voltage. This helps prevent
transformer saturation and reduces stress on the
secondary diode during startup.

Drain
6,7,8
VCC VREF

IDELAY IFB OSC

FB
VOUT VFB 3R PWM
3
FOD817 D1 D2 Gate
Driver
CFB VFB* R
LEB (300ns)

OSP
KA431 VOSP RSENSE
AOCP GND
VAOCP 1
OLP
VSD

Figure 19. Pulse Width Modulation Circuit

www.onsemi.com
10
 FSL117MRIN — Green-Mode Power Switch
4. Protection Circuits: The FSL117MRIN has several blocked and the 2.0 µA current source starts to
self-protective functions, such as Over load Protection charge CFB slow ly up. In this condition, V FB continues
(OLP), Abnor mal Over-Current Protection (AOCP), increasing until it reaches 7.0 V, w hen the sw itching
Output-Short Protection (OSP), Over-Voltage Protection operation is ter minated, as show n in Figure 21. The
(OV P), and Ther mal Shutdow n (TSD). All the delay for shutdow n is the time required to charge CFB
protections are implemented as auto-restart. Once a from 2.5 V to 7.0 V w ith 2.0 µA. A 25 ~ 50 ms delay is
fault condition is detected, sw itching is ter minated and typical for most applications. This protection is
the SenseFET remains off. This causes VCC to fall. implemented as Auto-Restart Mode.
When V CC falls to the Under-Voltage Lockout ( UVLO)
B B

stop voltage of 7.5 V, the protection is reset and the VFB

Overload Protection
startup circuit charges the V CC capacitor. When V CC
reaches the start voltage of 12.0 V, the FSL117MRIN
resumes nor mal operation. If the fault condition is not 7.0V
removed, the SenseFET remains off and V CC drops to
stop voltage again. In this manner, the auto-restart can
alternately enable and disable the sw itching of the
pow er SenseFET until the fault condition is eliminated. 2.5V
Because these protection circuits are fully integrated
into the IC w ithout external components, the reliability is
improved w ithout increasing cost. t12= CFB×(7.0-2.5)/Idelay

Power Fault Fault

VDS on occurs removed t1 t2 t
Figure 21. Overload Protection

4.2 Abnorm al Over-Current Protection (AOCP):

When the secondary rectifier diodes or the
transformer pins are shorted, a steep current w ith
extremely high di/dt can flow through the SenseFET
VCC during the minimum turn-on time. Overload protection
is not enough to protect the FSL117MRIN in that
abnor mal case; since severe current stress is
12.0V imposed on the SenseFET until OLP is tr iggered. The
7.5V internal AOCP circuit is show n in Figure 22. When the
gate turn-on signal is applied to the pow er SenseFET,
the AOCP bloc k is enabled and monitors the current
t through the sensing-resistor. The voltage across the
resistor is compared w ith a preset AOCP level. If the
Normal Fault Normal
operation situation operation
sensing resistor voltage is greater than the AOCP
Figure 20. Auto-Restart Protection Waveform s level, the set signal is applied to the S-R latch,
resulting in the shutdow n of the SMPS.
4.1 Overload Protection (OLP): Overload is defined Drain

as the load current exceeding its nor mal level due to 6,7,8
an unexpected abnor mal event. In this situation, the OSC
protection circuit should tr igger to protect the SMPS.
How ever, even w hen the SMPS is in nor mal 3R
PWM
operation, the overload protection c ircuit can be Gate
triggered during load trans ition. To avoid this Driver
VFB* R
undesired operation, the overload protection circuit is
LEB (300ns)
designed to trigger only after a specified time to
deter mine w hether it is a transient situation or a true
overload situation. Because of the pulse-by-pulse
current-limit capability, the maximum peak current RSENSE
Q S GND
through the SenseFET is limited and, therefore, the VAOCP 1
maximum input pow er is restricted w ith a given input
Q R VCC Good
voltage. If the output consumes more than this
maximum pow er, the output voltage (V OUT) decreases
below the set voltage. This reduces the current
through the opto-coupler LED, w hich also reduces the Figure 22. Abnorm al Over-Current Protection
opto-coupler transistor current, thus increasing the
feedback voltage (V FB). If V FB exceeds 2.5 V, D1 is

www.onsemi.com
11
 FSL117MRIN — Green-Mode Power Switch
4.3. Output-Short Protection (OSP): If the output is 4.6 Line Over-Voltage Protection (LOVP): If the line
shorted, steep current w ith extremely high di/dt can input voltage is increased to an undesirable level, high
flow through the SenseFET during the minimum turn- line input voltage creates high-voltage stress on the
on time. Such a steep current creates high-voltage entire system. To protect from this abnor mal condition,
stress on the drain of the SenseFET w hen turned off. LOV P is included. It is compr ised of detecting V IN using
To protect the device from this abnor mal condition, divided resistors. When V IN is higher than 1.95 V, this
OSP is included. It is comprised of detecting V FB and condition is recognized as an abnor mal error and PWM
SenseFET turn-on time. When the V FB is higher than sw itching shuts dow n until V IN decreases to around
2.0 V and the SenseFET turn-on time is low er than 1.89 V (60 mV hysteresis).
1.0 μs, the FSL117MRIN recognizes this condition as
an abnor mal error and shuts dow n PWM sw itching
VIN
until V CC reaches V START again. An abnor mal condition VINH = 1.95 V
VINL = 1.89 V
output short is show n in Figure 23.
VAC

MOSFET Rectifier ILIM

Drain Diode IDS
VFB*=0.5V
Current Current
→ VFB=2.0V
VFB*

ILm

LOVP LOVP triggered

0 t
1.0μs 1.0μs
tOFF tON
Output Short Occurs

VOUT
VSTART = 12.0 V
VCC
IOUT
0 t
VSTOP = 7.5 V
OSP Triggered
OSP

0
Figure 24. Line Over-Voltage Protection
t

Unlike previous Pow er Sw itch families, FSL117MRIN’s

Figure 23. Output-Short Protection
V IN pin can detect the A C line over-voltage protection
4.4 Over-Voltage Protection (OVP): If the function. When the line input voltage exceeds pre-
secondary-side feedback circuit malfunctions or a deter mined level at the V IN pin, the controller initiates a
solder defect causes an opening in the feedback path, fault signal and shuts dow n PWM output. To prevent
the current through the opto-coupler transistor erroneous activation of LOV P, the LOV P function is
becomes almost zero. Then V FB climbs up in a similar triggered w hen line over-voltage lasts more than a
manner to the overload situation, forcing the preset specific time. An important feature of the LOVP function
maximum current to be supplied to the SMPS until the is auto-recovery. The controller continuous ly monitors
overload protection is triggered. Because more line input voltage, even under fault condition, and turns
energy than required is provided to the output, the PWM output on w hen over-voltage condition
output voltage may exceed the rated voltage before disappears. Equation (1) calculates the level of input
the overload protection is triggered, resulting in the over voltage to RMS value:
breakdow n of the devices in the secondary side. To
prevent this situation, an OV P circuit is employed. In  ( R1 + R 2 ) 
general, the V CC is proportional to the output voltage = 1.95 × 
VIN _ ovp  (1)
 R1 
and the FSL117MRIN uses V CC instead of directly  
monitoring the output voltage. If V CC exceeds 24.5 V,
an OV P circuit is triggered, resulting in the ter mination The resistance of the divided resistor can be adjusted
of the sw itching operation. To avoid undesired as necessary. Small resistance can bring relatively large
activation of OV P during nor mal operation, V CC should standby pow er consumption at light-load condition. To
be designed to be below 24.5 V. avoid this situation, a several MΩ resistor is
recommended. For stable operation, a several MΩ
4.5 Therm al Shutdow n (TSD): The SenseFET and resistor should accompany a capacitor w ith hundreds of
the control IC on a die in one pac kage makes it eas ier pF capacitance betw een the V IN and GND pins.
for the control IC to detect the temperature of the
SenseFET. If the temperature exceeds ~140°C, the
ther mal shutdow n is triggered and stops operation.
The FSL117MRIN operates in auto-restart mode until
the temperature decreases to around 75°C, w hen
normal operation resumes.

www.onsemi.com
12
 FSL117MRIN — Green-Mode Power Switch
5. Soft Burst Mode: To minimize pow er dissipation in VO
Standby Mode, the FSL117MRIN enters Burst Mode. As
the load decreases, the feedbac k voltage decreases.
The device automatically enters Burst Mode w hen the t
feedback voltage drops below V BURL (300 mV), as VFB
show n in Figure 25. At this point, sw itching stops and
0.45V
the output voltages start to drop at a rate dependent on
0.30V
standby current load. This causes the feedback voltage t
to rise. Once it passes V BURH (450 mV), sw itching IDS
resumes. Feedback voltage then falls and the process Soft Burst

repeats. Burst Mode alternately enables and disables

sw itching of the SenseFET, reducing sw itching loss in
Standby Mode. t

VDS

6. Random Frequency Fluctuation ( RFF): Fluctuating

sw itching frequency of an SMPS can reduce EMI by
t
spreading the energy over a w ide frequency range. The
amount of EMI reduction is directly related to the Switching
disabled
Switching
disabled
sw itching frequency variation, w hich is limited internally. t1 t2 t3 t4

The sw itching frequency is deter mined randomly by Figure 25. Burst-Mode Operation
external feedback voltage and an internal free-running
IDS
oscillator at every sw itching instant. This random
frequency fluctuation scatters the EMI noise around
typical sw itching frequency (67 kHz) effectively and can
reduce the cost of the input filter included to meet the fSW
EMI requirements (e.g. EN55022).
ΔfSW t(μs)

fSW
fSW+1/2ΔfSW

fSW-1/2ΔfSW
No Repetition

t(ms)
Figure 26. Random Frequency Fluctuation

www.onsemi.com
13
 FSL117MRIN — Green-Mode Power Switch
Physical Dimensions

9.83
9.00

6.67
6.096

8.255
7.61

5.08 MAX 3.683 7.62

3.20

0.33 MIN

(0.56) 3.60
3.00 0.356
2.54 0.20
0.56
0.355
9.957
1.65 7.87
1.27

7.62

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M-1994
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.

Figure 27. 8-Lead, Dual Inline Package, 8DIP.

Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in
any manner without notice. Please note the revision and/or date on the drawing and contact an ON Semiconductor representative to
verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide terms and
conditions, specifically the warranty therein, which covers ON Semiconductor products.

www.onsemi.com
14
 FSL117MRIN — Green-Mode Power Switch
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the
United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A
listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make
changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor
products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by
ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and
actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for
use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or
any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor N. Amer ican Technical Support: 800-282-9855 Toll Free ON Semiconductor Website: www.onsemi.com
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA USA/Canada.
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Eur ope, Middle East and Afr ica Technical Support: Or der Literature: http://www.onsemi.com/orderlit
Fax : 303-675-2176 or 800-344-3867 Toll Free USA/Canada Phone: 421 33 790 2910
Email: orderlit@onsemi.com Japan Customer Focus Center For additional information, please contact your local
Phone: 81-3-5817-1050 Sales Representative

www.onsemi.com
15
Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

onsemi:
FSL117MRIN