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CD4051B, CD4052B, CD4053B

SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017

CD405xB CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

with Logic-Level Conversion
1 Features 3 Description
1• Wide Range of Digital and Analog Signal Levels The CD405xB analog multiplexers and demultiplexers
are digitally-controlled analog switches having low
– Digital: 3 V to 20 V ON impedance and very low OFF leakage current.
– Analog: ≤ 20 VP-P These multiplexer circuits dissipate extremely low
• Low ON Resistance, 125 Ω (Typical) Over 15 VP-P quiescent power over the full VDD – VSS and VDD –
Signal Input Range for VDD – VEE = 18 V VEE supply-voltage ranges, independent of the logic
state of the control signals.
• High OFF Resistance, Channel Leakage of
±100 pA (Typical) at VDD – VEE = 18 V Device Information(1)
• Logic-Level Conversion for Digital Addressing PART NUMBER PACKAGE BODY SIZE (NOM)
Signals of 3 V to 20 V (VDD – VSS = 3 V to 20 V) CDIP (16) 19.50 mm × 6.92 mm
to Switch Analog Signals to 20 VP-P (VDD – VEE =
PDIP (16) 19.30 mm × 6.35 mm
20 V) Matched Switch Characteristics, rON = 5 Ω
CD405xB SOIC (16) 9.90 mm × 3.91 mm
(Typical) for VDD – VEE = 15 V Very Low Quiescent
SOP (16) 10.30 mm × 5.30 mm
Power Dissipation Under All Digital-Control Input
and Supply Conditions, 0.2 µW (Typical) at TSSOP (16) 5.00 mm × 4.40 mm
VDD – VSS = VDD – VEE = 10 V (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Binary Address Decoding on Chip
• 5 V, 10 V, and 15 V Parametric Ratings Functional Diagrams of CD405xB
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current of 1 µA at 18 V Over Full INH C B A
CBA
Ch 0

Package Temperature Range, 100 nA at 18 V and 000 Ch 1

001
25°C 010
Ch 2

• Break-Before-Make Switching Eliminates Channel COM

011 Ch 3
100 Ch 4
Overlap 101
Ch 5
110
2 Applications 111 Ch 6

Ch 7
CD4051B
• Analog and Digital Multiplexing and
Demultiplexing
• A/D and D/A Conversion INH B A Ch X0
INH

• Signal Gating BA
Ch Y0
A ax
00 Ch X1 ax OR ay
• Factory Automation 01
A ay
X COM Ch Y1
• Televisions Y COM 10 Ch X2 bx OR by
B bx

by
• Appliances 11 Ch Y2
B

cx
• Consumer Audio Ch X3
cx OR cy
C

C cy
Ch Y3
• Programmable Logic Circuits CD4052B CD4053B

• Sensors

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.4 Device Functional Modes........................................ 18
2 Applications ........................................................... 1 9 Application and Implementation ........................ 19
3 Description ............................................................. 1 9.1 Application Information............................................ 19
4 Revision History..................................................... 2 9.2 Typical Application ................................................. 19
5 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 20
6 Specifications......................................................... 5 11 Layout................................................................... 21
6.1 Absolute Maximum Ratings ...................................... 5 11.1 Layout Guidelines ................................................. 21
6.2 ESD Ratings.............................................................. 5 11.2 Layout Example .................................................... 21
6.3 Recommended Operating Conditions....................... 5 12 Device and Documentation Support ................. 22
6.4 Thermal Information .................................................. 5 12.1 Documentation Support ........................................ 22
6.5 Electrical Characteristics........................................... 6 12.2 Related Links ........................................................ 22
6.6 AC Performance Characteristics............................... 8 12.3 Receiving Notification of Documentation Updates 22
6.7 Typical Characteristics .............................................. 9 12.4 Community Resources.......................................... 22
7 Parameter Measurement Information ................ 10 12.5 Trademarks ........................................................... 22
12.6 Electrostatic Discharge Caution ............................ 22
8 Detailed Description ............................................ 15
12.7 Glossary ................................................................ 22
8.1 Overview ................................................................. 15
8.2 Functional Block Diagrams ..................................... 15 13 Mechanical, Packaging, and Orderable
8.3 Feature Description................................................. 17
Information ........................................................... 22

4 Revision History
Changes from Revision H (April 2015) to Revision I Page

• Added: ON Channel Leakage Current to the Electrical Characteristics table ....................................................................... 6

• Added Note 3 to the Electrical Characteristics table .............................................................................................................. 6
• Added Figure 13 ................................................................................................................................................................... 11

Changes from Revision G (October 2003) to Revision H Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Added Device Information table. ............................................................................................................................................ 1

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5 Pin Configuration and Functions

CD4051B E, M, NS, and PW Package

16-Pin PDIP, CDIP, SOIC, SOP, and TSSOP CD4052B E, M, NS, and PW Package
(Top View) 16-Pin PDIP, CDIP, SOP, and TSSOP
(Top View)

CHANNELS 4 1 16 VDD
Y CHANNELS 0 1 16 VDD
IN/OUT 6 2 15 2 IN/OUT
2 2 15 2 X CHANNELS
COM OUT/IN 3 14 1 IN/OUT
CHANNELS IN/OUT COMMON “Y” OUT/IN 3 14 1
CHANNELS 7 4 13 0
Y CHANNELS 3 4 13 COMMON “X” OUT/IN
IN/OUT 5 5 12 3 IN/OUT
1 5 12 0 X CHANNELS
INH 6 11 A IN/OUT
INH 6 11 3
VEE 7 10 B
VEE 7 10 A
VSS 8 9 C
VSS 8 9 B

CD4053B E, M, NS, and PW Package

16-Pin PDIP, CDIP, SOP, and TSSOP
(Top View)

by 1 16 VDD

bx 2 15 OUT/IN bx OR by

cy 3 14 OUT/IN ax OR ay

OUT/IN CX OR CY 4 13 ay
IN/OUT
IN/OUT CX 5 12 ax
INH 6 11 A

VEE 7 10 B

VSS 8 9 C

Pin Functions CD4051B

PIN
I/O DESCRIPTION
NO. NAME
1 CH 4 IN/OUT I/O Channel 4 in/out
2 CH 6 IN/OUT I/O Channel 6 in/out
3 COM OUT/IN I/O Common out/in
4 CH 7 IN/OUT I/O Channel 7 in/out
5 CH 5 IN/OUT I/O Channel 5 in/out
6 INH I Disables all channels. See Table 1.
7 VEE — Negative power input
8 VSS — Ground
9 C I Channel select C. See Table 1.
10 B I Channel select B. See Table 1.
11 A I Channel select A. See Table 1.
12 CH 3 IN/OUT I/O Channel 3 in/out
13 CH 0 IN/OUT I/O Channel 0 in/out
14 CH 1 IN/OUT I/O Channel 1 in/out
15 CH 2 IN/OUT I/O Channel 2 in/out
16 VDD — Positive power input

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Pin Functions CD4052B

PIN
I/O DESCRIPTION
NO. NAME
1 Y CH 0 IN/OUT I/O Channel Y0 in/out
2 Y CH 2 IN/OUT I/O Channel Y2 in/out
3 Y COM OUT/IN I/O Y common out/in
4 Y CH 3 IN/OUT I/O Channel Y3 in/out
5 Y CH 1 IN/OUT I/O Channel Y1 in/out
6 INH I Disables all channels. See Table 1.
7 VEE — Negative power input
8 VSS — Ground
9 B I Channel select B. See Table 1.
10 A I Channel select A. See Table 1.
11 X CH 3 IN/OUT I/O Channel X3 in/out
12 X CH 0 IN/OUT I/O Channel X0 in/out
13 X COM IN/OUT I/O X common out/in
14 X CH 1 IN/OUT I/O Channel in/out
15 X CH 2 IN/OUT I/O Channel in/out
16 VDD — Positive power input

Pin Functions CD4053B

PIN
I/O DESCRIPTION
NO. NAME
1 BY IN/OUT I/O B channel Y in/out
2 BX IN/OUT I/O B channel X in/out
3 CY IN/OUT I/O C channel Y in/out
CX OR CY
4 I/O C common out/in
OUT/IN
5 CX IN/OUT I/O C channel X in/out
6 INH I Disables all channels. See Table 1.
7 VEE — Negative power input
8 VSS — Ground
9 C I Channel select C. See Table 1.
10 B I Channel select B. See Table 1.
11 A I Channel select A. See Table 1.
12 AX IN/OUT I/O A channel X in/out
13 AY IN/OUT I/O A channel Y in/out
AX OR AY
14 I/O A common out/in
OUT/IN
BX OR BY
15 I/O B common out/in
OUT/IN
16 VDD — Positive power input

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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1).
MIN MAX UNIT
Supply Voltage V+ to V-, Voltages Referenced to VSS Terminal –0.5 20 V
DC Input Voltage –0.5 VDD + 0.5 V
DC Input Current Any One Input –10 10 mA
TJMAX1 Maximum junction temperature, ceramic package 175 °C
TJMAX2 Maximum junction temperature, plastic package 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
CD4051B in PDIP, CDIP, SOIC, SOP, TSSOP Packages
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) +3000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
+2000
C101 (2)
CD4053B in PDIP, CDIP, SOP and TSSOP Packages
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) +2500
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
+1500
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).
MIN MAX UNIT
Temperature Range –55 125 °C

6.4 Thermal Information

CD405xB
PW
THERMAL METRIC (1) E (PDIP) M (SOIC) NS (SOP) UNIT
(TSSOP)
16 PINS 16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 67 73 64 108 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

Over operating free-air temperature range, VSUPPLY = ±5 V, and RL = 100 Ω, (unless otherwise noted) (1).
TEST CONDITIONS MIN TYP MAX UNIT
PARAMETER
VIS (V) VEE (V) VSS (V) VDD (V) TEMP
SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)
–55°C 5
–40°C 5
5 25°C 0.04 5
85°C 150
125°C 150
–55°C 10
–40°C 10
10 25°C 0.04 10
85°C 300
125°C 300
Quiescent Device Current, IDD Max µA
–55°C 20
–40°C 20
15 25°C 0.04 20
85°C 600
125°C 600
–55°C 100
–40°C 100
20 25°C 0.08 100
85°C 3000
125°C 3000
–55°C 800
–40°C 850
0 0 5 25°C 470 1050
85°C 1200
125°C 1300
–55°C 310
–40°C 300
Drain to Source ON Resistance rON Max
0 0 10 25°C 180 400 Ω
0 ≤ VIS ≤ VDD
85°C 520
125°C 550
–55°C 200
–40°C 210
0 0 15 25°C 125 240
85°C 300
125°C 300
0 0 5 15
Change in ON Resistance
(Between Any Two Channels), 0 0 10 25°C 10 Ω
∆rON
0 0 15 5
–55°C ± 100
–40°C
OFF Channel Leakage Current: Any Channel OFF (Max)
0 0 18 25°C ± 0.01 ± 100 (2) nA
or ALL Channels OFF (Common OUT/IN) (Max)
85°C ± 1000 (2)
125°C

ON Channel Leakage Current: Any Channel ON (Max) or 5 or 0 -5 0 10.5 85°C ± 300 (3)
nA
ALL Channels ON (Common OUT/IN) (Max) 5 0 0 18 85°C ± 300 (3)
Input, CIS –5 –5 –5 25°C 5
CD4051 30
Capacitance Output, COS CD4052 18 pF
25°C
CD4053 9
Feed through, CIOS 0.2

(1) Peak-to-Peak voltage symmetrical about (VDD – VEE) / 2.

(2) Determined by minimum feasible leakage measurement for automatic testing.
(3) Does not apply to Hi-Rel CD4051BF and CD4051BFA3 devices.
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Electrical Characteristics (continued)

Over operating free-air temperature range, VSUPPLY = ±5 V, and RL = 100 Ω, (unless otherwise noted)(1).
TEST CONDITIONS MIN TYP MAX UNIT
PARAMETER
VIS (V) VEE (V) VSS (V) VDD (V) TEMP
VDD RL = 200 kΩ , 5 30 60
Propagation Delay Time (Signal Input to Output) CL = 50 pF, 10 25°C 15 30 ns
tr , tf = 20 ns 15 10 20
CONTROL (ADDRESS OR INHIBIT), VC
–55°C 1.5
–40°C 1.5
5 25°C 1.5
85°C 1.5
125°C 1.5
–55°C 3
–40°C 3
Input Low Voltage, VIL , Max 10 25°C 3 V
85°C 3
125°C 3
–55°C 4
–40°C 4
15 25°C 4
VIL = VDD 85°C 4
through 1 VEE = VSS,
kΩ ; RL = 1 kΩ to VSS, 125°C 4
VIH = VDD IIS < 2 µA on All OFF –55°C 3.5
through 1 Channels
kΩ –40°C 3.5
5 25°C 3.5
85°C 3.5
125°C 3.5
–55°C 7
–40°C 7
Input High Voltage, VIH , Min 10 25°C 7 V
85°C 7
125°C 7
–55°C 11
–40°C 11
15 25°C 11
85°C 11
125°C 11
–55°C ± 0.1
–40°C ± 0.1

Input Current, IIN (Max) VIN = 0, 18 18 25°C ± 10–5 ± 0.1 µA

85°C ±1
125°C ±1
0 0 5 450 720
tr , tf = 20
Address-to-Signal OUT (Channels ON 0 0 10 160 320
Propagation ns,
or OFF) (See Figure 10, Figure 11, ns
Delay Time CL = 50 pF, 0 0 15 120 240
and Figure 15)
RL = 10 kΩ
–5 0 5 225 450
0 0 5 400 720
tr , tf = 20
Propagation Inhibit-to-Signal OUT (Channel ns, 0 0 10 160 320
ns
Delay Time Turning ON) (See Figure 11) CL = 50 pF, 0 0 15 120 240
RL = 1 kΩ
–10 0 5 200 400
0 0 5 200 450
tr , tf = 20
Propagation Inhibit-to-Signal OUT (Channel ns, 0 0 10 90 210
ns
Delay Time Turning OFF) (See Figure 17) CL = 50 pF, 0 0 15 70 160
RL = 10 kΩ
–10 0 5 130 300
Input Capacitance, CIN (Any Address or Inhibit Input) 5 7.5 pF

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6.6 AC Performance Characteristics

TEST CONDITIONS
PARAMETER TYP UNIT
VIS (V) VDD (V) RL (kΩ)
CD4053 30
5 (1) 10 1 VOS at Common OUT/IN CD4052 25
Cutoff (–3dB) CD4051 20
Frequency Channel
VEE = VSS , MHz
ON (Sine Wave
Input)
VOS VOS at Any Channel 60
20 Log = – 3 dB
VIS
2 (1) 5 0.3%

Total Harmonic 3 (1) 10 10 0.2%

Distortion, THD 5 (1) 15 0.12%
VEE = VSS, fIS = 1 kHz Sine Wave
–40dB Feedthrough
Frequency 5 (1) 10 1 CD4053 8
(All Channels OFF)
VOS at Common OUT/IN
VEE = VSS , CD4052 10 MHz
CD4051 12
VOS
20 Log = – 40dB VOS at Any Channel 8
VIS
(1)
5 10 1 Between Any two Channels 3

VEE = VSS, Between Sections, Measured on Common 6

–40dB Signal
Crosstalk CD4052 Only Measured on Any Channel 10 MHz
Frequency VOS In Pin 2, Out Pin 14 2.5
20 Log = – 40dB Between Any Two
VIS Sections, CD4053 Only In Pin 15, Out Pin 14 6

Address-or-Inhibit-to- 10 10 (2) 65
Signal VEE = 0, VSS = 0, tr , tf = 20 ns, mVPEAK
Crosstalk 65
VCC = VDD – VSS (Square Wave)

(1) Peak-to-Peak voltage symmetrical about (VDD - VEE) / 2.

(2) Both ends of channel.

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6.7 Typical Characteristics

600 300
VDD - VEE = 5V
rON , CHANNEL ON RESISTANCE (Ω)

rON , CHANNEL ON RESISTANCE (Ω)

500 250

200 TA = 125oC
400

300 TA = 125oC 150

TA = 25oC
TA = 25oC
200 100
TA = -55oC
TA = -55oC
100 50

0 0
-4 -3 -2 -1 0 1 2 3 4 5 -10 -7.5 -5 -2.5 0 2.5 5 7.5 10
VIS , INPUT SIGNAL VOLTAGE (V)

Figure 1. Channel ON Resistance vs Input Signal Voltage Figure 2. Channel ON Resistance vs Input Signal Voltage
(All Types) (All Types)
600 250
TA = 25oC rON , CHANNEL ON RESISTANCE (Ω)
VDD - VEE = 15V
rON , CHANNEL ON RESISTANCE (Ω)

VDD - VEE = 5V
500
200
TA = 125oC
400
150

300
100 TA = 25oC
200
TA = -55oC
10V
50
100 15V

0 0
-10 -7.5 -5 -2.5 0 2.5 5 7.5 10 -10 -7.5 -5 -2.5 0 2.5 5 7.5 10
VIS , INPUT SIGNAL VOLTAGE (V) VIS , INPUT SIGNAL VOLTAGE (V)

Figure 3. Channel ON Resistance vs Input Signal Voltage Figure 4. Channel ON Resistance vs Input Signal Voltage
(All Types) (All Types)
6 105
TEST CIRCUIT
PD , POWER DISSIPATION PACKAGE (µ W)

VDD = 5V
RL = 100kΩ, RL = 10kΩ TA = 25oC
VOS , OUTPUT SIGNAL VOLTAGE (V)

VSS = 0V VDD
1kΩ ALTERNATING “O”
4 VEE = -5V AND “I” PATTERN B/D
500Ω f
TA = 25oC CL = 50pF CD4029
100Ω 104 A B C
VDD
2 VDD = 15V 100Ω 11 10 9
13
14
0 103 15
12 CD4051
1
-2 VDD = 10V 5
2 3
102 48 7 6 C
VDD = 5V L
-4
100Ω Ι
CL = 15pF
-6 10
-6 -4 -2 0 2 4 6 1 10 102 103 104 105
VIS , INPUT SIGNAL VOLTAGE (V) SWITCHING FREQUENCY (kHz)

Figure 5. ON Characteristics for 1 of 8 Channels Figure 6. Dynamic Power Dissipation vs Switching

(CD4051B) Frequency (CD4051B)

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Typical Characteristics (continued)

105 105 TA = 25oC VDD = 15V
TA = 25oC

PD , POWER DISSIPATION PACKAGE (µW)

PD , POWER DISSIPATION PACKAGE (µW)

ALTERNATING “O” ALTERNATING “O” VDD = 10V

AND “I” PATTERN TEST CIRCUIT AND “I” PATTERN
CL = 50pF VDD CL = 50pF
f 104
104 CD4029 TEST CIRCUIT
VDD = 15V VDD B/D VDD f
A B
100Ω 9 4
10 9 100Ω CL
1 3 CL 3 12
103 5 13 103 5
100Ω 13
2 12 CD4053 2
VDD = 10V 4 CD4052 14 10
15 1

100Ω
6 11 VDD = 5V 11 15
102 VDD = 5V 7 102 6 14
7
CL = 15pF 8 8
Ι CL = 15pF Ι
10 10
1 10 102 103 104 105 1 10 102 103 104 105
SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz)

Figure 7. Dynamic Power Dissipation vs Switching Figure 8. Dynamic Power Dissipation vs Switching
Frequency (CD4052B) Frequency (CD4053B)

7 Parameter Measurement Information

VDD = 15V VDD = 7.5V VDD = 5V VDD = 5V

7.5V 5V 5V
16 16 16 16

VSS = 0V VSS = 0V
VSS = 0V

VEE = 0V
7 7 7 7
8 VEE = -7.5V 8 VEE = -10V 8 VEE = -5V 8
VSS = 0V
(A) (B) (C) (D)

Figure 9. Typical Bias Voltages

NOTE
The ADDRESS (digital-control inputs) and INHIBIT logic levels are: 0 = VSS
and 1 = VDD. The analog signal (through the TG) may swing from VEE to VDD.

tr = 20ns tf = 20ns tr = 20ns tf = 20ns

90% 90% 90% 90%
50% 50% 50% 50%
10% 10% 10% 10%
TURN-ON TIME
90% 90%
50%
10% 10% 10%
TURN-OFF TIME TURN-ON
TURN-OFF TIME TIME
tPHZ

Figure 10. Waveforms, Channel Being Turned ON Figure 11. Waveforms, Channel Being Turned OFF
(RL = 1 kΩ) (RL = 1 kΩ)

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Parameter Measurement Information (continued)

VDD VDD VDD

1 16 1 16 1 16
2 15 2 15 2 15
3 14 IDD 3 14 IDD 3 14
4 13 4 13 4 13 IDD
5 12 5 12 5 12
6 11 6 11 6 11
7 10 7 10 7 10
8 9 8 9 8 9

CD4052 CD4053

Figure 12. OFF Channel Leakage Current - Any Channel OFF

VDD VDD VDD

1 16 1 16 1 16
2 15 2 15 2 15
IDD 3 14 IDD 3 14 3 14
4 13 4 13 IDD 4 13
5 12 5 12 5 12
6 11 6 11 6 11
7 10 7 10 7 10
8 9 8 9 8 9

CD4051 CD4052 CD4053

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Figure 13. On Channel Leakage Current - Any Channel On

Figure 14. OFF Channel Leakage Current - All Channels OFF

VDD VDD
OUTPUT
OUTPUT OUTPUT
1 16 1 16 VDD 1 16
VDD 2 15 RL CL 2 15 2 15 RL CL
CL RL
3 14 3 14 3 14
4 13 VEE VDD 4 13
4 13
5 12 VDD 5 12 VDD VEE
5 12
VEE 6 11 VEE 6 11 VEE 6 11
VSS CLOCK VEE VDD VSS CLOCK
7 10 7 10 7 10
IN VSS CLOCK IN
8 9 8 9 8 9
VSS VSS IN VSS
CD4051 VSS CD4052 VSS CD4053 VSS

Figure 15. Propagation Delay - Address Input to Signal Output

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Parameter Measurement Information (continued)

VDD VDD
OUTPUT OUTPUT
OUTPUT
1 16 1 16 1 16 VDD
RL 50pF 2 15 RL 50pF 2 15 RL 2 15
50pF
3 14 3 14 3 14
VEE 4 13 VEE 4 13 4 13
VEE
VDD VDD 5 12 VDD 5 12 VDD 5 12
6 11 VDD 6 11 VDD 6 11
VSS VSS
CLOCK VEE 7 10 CLOCK VEE 7 10 VSS CLOCK VEE 7 10
IN VSS 8 9 IN VSS 8 9 IN VSS 8 9

tPHL AND tPLH VSS V

tPHL AND tPLH SS
V
tPHL AND tPLH SS
CD4051 CD4052 CD4053

Figure 16. Propagation Delay - Inhibit Input to Signal Output

VDD

VDD VDD
µA VIH
1K 1 16
1 16 1 1K 1K 2 15 µA
2 15 2 15 µA
3 14 1K
3 14 3 14 4 13
1K 4 13 VIH 4 13 VIH
VIH 5 12
5 12 5 12 1K
VIL 6 11 VIH
6 11 6 11 7 10
VIL 7 10 VIL 7 10 VIL
8 9
8 9 8 9 VIH
CD4053B
CD4051B CD4052B
VIL VIL
MEASURE < 2µA ON ALL MEASURE < 2µA ON ALL MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 6) “OFF” CHANNELS (e.g., CHANNEL 2x) “OFF” CHANNELS (e.g., CHANNEL by)

Figure 17. Input Voltage Test Circuits (Noise Immunity)

VDD VDD KEITHLEY
VDD 160 DIGITAL
MULTIMETER
1 16
1 16 2 15
2 15 3 14 10kΩ TG
3 14 “ON” 1kΩ
4 13 Y
4 13 5 12 RANGE
5 12 6 11
6 11 VSS X-Y
7 10 PLOTTER
7 10 8 9
8 9
H.P. X
Ι CD4052 MOSELEY
Ι
CD4053 7030A

Figure 18. Quiescent Device Current Figure 19. Channel ON Resistance Measurement
Circuit

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 CD4051B, CD4052B, CD4053B
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Parameter Measurement Information (continued)

VDD VDD

1 16 1 16
2 15 2 15
3 14 3 14
4 13 4 13
5 12 VDD 5 12 VDD
6 11 6 11
7 10 Ι 7 10 Ι
8 9 8 9
VSS VSS
VSS CD4051 VSS CD4052
CD4053 NOTE: Measure inputs sequentially, NOTE: Measure inputs sequentially,
to both VDD and VSS connect all to both VDD and VSS connect all
unused inputs to either VDD or VSS . unused inputs to either VDD or VSS .

Figure 20. Input Current

5VP-P
CHANNEL CHANNEL
5VP-P RF ON OFF
OFF VM RF
CHANNEL VM
1K COMMON RL
VDD

6 RL
7 CHANNEL RF CHANNEL
8 OFF VM ON
RL RL

Figure 21. Feedthrough (All Types) Figure 22. Crosstalk Between Any Two Channels
(All Types)

5VP-P
CHANNEL IN X CHANNEL IN Y RF
ON OR OFF ON OR OFF VM
RL RL

Figure 23. Crosstalk Between Duals or Triplets (CD4052B, CD4053B)

DIFFERENTIAL CD4052
CD4052
SIGNALS

LINK

DIFF. DIFF.
AMPLIFIER/ RECEIVER
LINE DRIVER

DIFF. DEMULTIPLEXING
MULTIPLEXING
Special Considerations: In applications where separate power sources are used to drive VDD and the signal inputs,
the VDD current capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent
current flow or clamp action on the VDD supply when power is applied or removed from the CD4051B, CD4052B or
CD4053B.

Figure 24. Typical Time-Division Application of the CD4052B

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Parameter Measurement Information (continued)

A A
B B
CD4051B
C C
INH

Q0 COMMON
D A A
Q1 B
1/2
E B CD4051B
CD4556 Q2 C
E INH

A
B
CD4051B
C
INH

Figure 25. 24-to-1 MUX Addressing

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8 Detailed Description

8.1 Overview
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low
ON impedance and very low OFF leakage current. Control of analog signals up to 20 VP-P can be achieved by
digital signal amplitudes of 4.5 V to 20 V (if VDD – VSS = 3 V, a VDD – VEE of up to 13 V can be controlled; for
VDD – VEE level differences above 13 V, a VDD – VSS of at least 4.5 V is required). For example, if VDD = +4.5 V,
VSS = 0 V, and VEE = –13.5 V, analog signals from –13.5 V to +4.5 V can be controlled by digital inputs of 0 V to
5 V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD – VSS and VDD – VEE
supply-voltage ranges, independent of the logic state of the control signals. When a logic 1 is present at the
inhibit input terminal, all channels are off.
The CD4051B device is a single 8-channel multiplexer having three binary control inputs, A, B, and C, and an
inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to
the output.
The CD4052B device is a differential 4-channel multiplexer having two binary control inputs, A and B, and an
inhibit input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog
inputs to the outputs.
The CD4053B device is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C,
and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole,
double-throw configuration.
When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs and the
COMMON OUT/IN terminals are the inputs.

8.2 Functional Block Diagrams

CHANNEL IN/OUT

7 6 5 4 3 2 1 0
16 VDD 4 2 5 1 12 15 14 13

TG

TG
A 11
TG

COMMON
TG OUT/IN
B 10 BINARY
LOGIC TO 3
1 OF 8
LEVEL TG
DECODER
CONVERSION WITH
C 9 INHIBIT TG

TG
INH 6

TG

8 VSS 7 VEE

All inputs are protected by standard CMOS protection network.

Figure 26. Functional Block Diagram, CD4051B

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Functional Block Diagrams (continued)

X CHANNELS IN/OUT
3 2 1 0
11 15 14 12

TG

16 VDD
TG

TG COMMON X
OUT/IN
TG 13

A 10
BINARY
TG 3
LOGIC TO
B 9 1 OF 4 COMMON Y
LEVEL
DECODER OUT/IN
CONVERSION TG
WITH
INH 6 INHIBIT
TG

TG
1 5 2 4
0 1 2 3
8 VSS 7 VEE
Y CHANNELS IN/OUT

All inputs are protected by standard CMOS protection network.

Figure 27. Functional Block Diagram, CD4052B

BINARY TO
1 OF 2 IN/OUT
LOGIC DECODERS
LEVEL 16 VDD WITH
CONVERSION INHIBIT cy cx by bx ay ax

3 5 1 2 13 12
COMMON
OUT/IN
TG ax OR ay
14
A 11 TG
COMMON
OUT/IN
TG bx OR by
15
B 10
TG
COMMON
OUT/IN
TG cx OR cy
C 9
4

TG

INH 6

VDD

8 VSS 7 VEE

All inputs are protected by standard CMOS protection network.

Figure 28. Functional Block Diagram, CD4053B

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8.3 Feature Description

The CD405xB line of multiplexers and demultiplexers can accept a wide range of digital and analog signal levels.
Digital signals range from 3 V to 20 V, and analog signals are accepted at levels ≤ 20 V. They have low ON
resistance, typically 125 Ω over 15 VP-P signal input range for VDD – VEE = 18 V. This allows for very little signal
loss through the switch. Matched switch characteristics are typically rON = 5 Ω for VDD – VEE = 15 V.
The CD405xB devices also have high OFF resistance, which keeps from wasting power when the switch is in the
OFF position, with typical channel leakage of ±100 pA at VDD – VEE = 18 V. Very low quiescent power dissipation
under all digital-control input and supply conditions, typically 0.2 µW at VDD – VSS = VDD – VEE = 10 V keeps
power consumption total very low. All devices have been 100% tested for quiescent current at 20 V with
maximum input current of 1 µA at 18 V over the full package temperature range, and only 100 nA at 18 V and
25°C.
Logic-level conversion for digital addressing signals of 3 V to 20 V (VDD – VSS = 3 V to 20 V) to switch analog
signals to 20 VP-P (VDD – VEE = 20 V). Binary address decoding on chip makes channel selection easy. When
channels are changed, a break-before-make system eliminates channel overlap.

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8.4 Device Functional Modes

Table 1. Truth Table (1)
INPUT STATES
ON CHANNEL(S)
INHIBIT C B A
CD4051B
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 X X X None
CD4052B
0 0 0 0x, 0y
0 0 1 1x, 1y
0 1 0 2x, 2y
0 1 1 3x, 3y
1 X X None
CD4053B
0 X X 0 ax
0 X X 1 ay
0 X 0 X bx
0 X 1 X by
0 0 X X cx
0 1 X X cy
1 X X X None

(1) X = Don't Care

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The CD405xB multiplexers and demultiplexers can be used for a wide variety of applications.

9.2 Typical Application

One application of the CD4051B is to use it in conjunction with a microcontroller to poll a keypad. Figure 29
shows the basic schematic for such a polling system. The microcontroller uses the channel select pins to cycle
through the different channels while reading the input to see if a user is pressing any of the keys. This is a very
robust setup, allowing for multiple simultaneous key-presses with very little power consumption. It also uses very
few pins on the microcontroller. The down side of polling is that the microcontroller must continually scan the
keys for a press and can do little else during this process.

Microcontroller

Input Channel Select

3.3 V
INH C B A k0
Ch 0
CBA
000 Ch 1 k1
001
Ch 2 k2
010
Ch 3 k3
011
COM
100 Ch 4 k4
3.3 V
101 k5
VDD Ch 5
110
Ch 6 k6
VEE 111

Ch 7 k7
VSS CD4051B

Pull-down resistors (10NŸ)

Figure 29. The CD4051B Being Used to Help Read Button Presses on a Keypad.

9.2.1 Design Requirements

These devices use CMOS technology and have balanced output drive. Take care to avoid bus contention
because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into
light loads, so routing and load conditions should be considered to prevent ringing.

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Typical Application (continued)

9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For switch time specifications, see propagation delay times in Electrical Characteristics.
– Inputs should not be pushed more than 0.5 V above VDD or below VEE.
– For input voltage level specifications for control inputs, see VIH and VIL in Electrical Characteristics.
2. Recommended Output Conditions
– Outputs should not be pulled above VDD or below VEE.
3. Input/output current consideration: The CD405xB series of parts do not have internal current drive circuitry
and thus cannot sink or source current. Any current will be passed through the device.

9.2.3 Application Curve

6
VDD = 5V
RL = 100kΩ, RL = 10kΩ
VOS , OUTPUT SIGNAL VOLTAGE (V)

VSS = 0V
VEE = -5V 1kΩ
4 500Ω
TA = 25oC
100Ω
2

-2

-4

-6
-6 -4 -2 0 2 4 6
VIS , INPUT SIGNAL VOLTAGE (V)
Figure 30. ON Characteristics for 1 of 8 Channels
(CD4051B)

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Electrical Characteristics.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.

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 CD4051B, CD4052B, CD4053B
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11 Layout

11.1 Layout Guidelines

Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the
trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and so they will have to
turn corners. Figure 31 shows progressively better techniques of rounding corners. Only the last example
maintains constant trace width and minimizes reflections.

11.2 Layout Example

WORST BETTER BEST
2W

1W min.

W
Figure 31. Trace Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
• Implications of Slow or Floating CMOS Inputs, SCBA004

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
CD4051B Click here Click here Click here Click here Click here
CD4052B Click here Click here Click here Click here Click here
CD4053B Click here Click here Click here Click here Click here

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

7901502EA ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 7901502EA
CD4052BF3A
8101801EA ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 8101801EA
CD4053BF3A
CD4051BE ACTIVE PDIP N 16 25 Green (RoHS NIPDAU | SN N / A for Pkg Type -55 to 125 CD4051BE
& no Sb/Br)
CD4051BEE4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD4051BE
& no Sb/Br)
CD4051BF ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 CD4051BF

CD4051BF3A ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 CD4051BF3A

CD4051BM ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051BM
& no Sb/Br)
CD4051BM96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CD4051BM
& no Sb/Br)
CD4051BM96G3 ACTIVE SOIC D 16 2500 Green (RoHS SN Level-1-260C-UNLIM -55 to 125 CD4051BM
& no Sb/Br)
CD4051BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051BM
& no Sb/Br)
CD4051BMG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051BM
& no Sb/Br)
CD4051BMT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051BM
& no Sb/Br)
CD4051BNSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051B
& no Sb/Br)
CD4051BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051B
& no Sb/Br)
CD4051BPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM051B
& no Sb/Br)
CD4051BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM051B
& no Sb/Br)
CD4051BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CM051B
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 28-Jul-2020

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CD4051BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM051B
& no Sb/Br)
CD4052BE ACTIVE PDIP N 16 25 Green (RoHS NIPDAU | SN N / A for Pkg Type -55 to 125 CD4052BE
& no Sb/Br)
CD4052BEE4 ACTIVE PDIP N 16 25 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD4052BE
(RoHS)
CD4052BF ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 CD4052BF

CD4052BF3A ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 7901502EA
CD4052BF3A
CD4052BM ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM
& no Sb/Br)
CD4052BM96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CD4052BM
& no Sb/Br)
CD4052BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM
& no Sb/Br)
CD4052BM96G3 ACTIVE SOIC D 16 2500 Green (RoHS SN Level-1-260C-UNLIM -55 to 125 CD4052BM
& no Sb/Br)
CD4052BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM
& no Sb/Br)
CD4052BMG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM
& no Sb/Br)
CD4052BMT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM
& no Sb/Br)
CD4052BNSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052B
& no Sb/Br)
CD4052BPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM052B
& no Sb/Br)
CD4052BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CM052B
& no Sb/Br)
CD4052BPWRG3 ACTIVE TSSOP PW 16 2000 Green (RoHS SN Level-1-260C-UNLIM -55 to 125 CM052B
& no Sb/Br)
CD4052BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM052B
& no Sb/Br)
CD4053BE ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD4053BE
& no Sb/Br)

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 28-Jul-2020

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CD4053BEE4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD4053BE
& no Sb/Br)
CD4053BF ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 CD4053BF

CD4053BF3A ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 8101801EA
CD4053BF3A
CD4053BM ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M
& no Sb/Br)
CD4053BM96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CD4053M
& no Sb/Br)
CD4053BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M
& no Sb/Br)
CD4053BM96G3 ACTIVE SOIC D 16 2500 Green (RoHS SN Level-1-260C-UNLIM -55 to 125 CD4053M
& no Sb/Br)
CD4053BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M
& no Sb/Br)
CD4053BMG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M
& no Sb/Br)
CD4053BMT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M
& no Sb/Br)
CD4053BNSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053B
& no Sb/Br)
CD4053BPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM053B
& no Sb/Br)
CD4053BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CM053B
& no Sb/Br)
CD4053BPWRG3 ACTIVE TSSOP PW 16 2000 Green (RoHS SN Level-1-260C-UNLIM -55 to 125 CM053B
& no Sb/Br)
CD4053BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM053B
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

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(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD4051B, CD4051B-MIL, CD4052B, CD4052B-MIL, CD4053B, CD4053B-MIL :

• Catalog: CD4051B, CD4052B, CD4053B

• Automotive: CD4051B-Q1, CD4051B-Q1, CD4053B-Q1, CD4053B-Q1
• Military: CD4051B-MIL, CD4052B-MIL, CD4053B-MIL

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 4
 PACKAGE OPTION ADDENDUM

www.ti.com 28-Jul-2020

• Military - QML certified for Military and Defense Applications

Addendum-Page 5
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD4051BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4051BM96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD4051BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4051BM96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD4051BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4051BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4051BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4051BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4051BPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4052BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4052BM96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD4052BM96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD4052BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4052BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4052BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4052BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4052BPWRG3 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4052BPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jul-2020

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD4053BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4053BM96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD4053BM96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD4053BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4053BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4053BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4053BPWRG3 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4053BPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4051BM96 SOIC D 16 2500 333.2 345.9 28.6
CD4051BM96 SOIC D 16 2500 364.0 364.0 27.0
CD4051BM96 SOIC D 16 2500 367.0 367.0 38.0
CD4051BM96G3 SOIC D 16 2500 364.0 364.0 27.0
CD4051BM96G4 SOIC D 16 2500 333.2 345.9 28.6
CD4051BM96G4 SOIC D 16 2500 367.0 367.0 38.0
CD4051BPWR TSSOP PW 16 2000 367.0 367.0 35.0
CD4051BPWR TSSOP PW 16 2000 364.0 364.0 27.0
CD4051BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jul-2020

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4052BM96 SOIC D 16 2500 333.2 345.9 28.6
CD4052BM96 SOIC D 16 2500 364.0 364.0 27.0
CD4052BM96G3 SOIC D 16 2500 364.0 364.0 27.0
CD4052BM96G4 SOIC D 16 2500 333.2 345.9 28.6
CD4052BNSR SO NS 16 2000 367.0 367.0 38.0
CD4052BPWR TSSOP PW 16 2000 367.0 367.0 35.0
CD4052BPWR TSSOP PW 16 2000 364.0 364.0 27.0
CD4052BPWRG3 TSSOP PW 16 2000 364.0 364.0 27.0
CD4052BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
CD4053BM96 SOIC D 16 2500 333.2 345.9 28.6
CD4053BM96 SOIC D 16 2500 364.0 364.0 27.0
CD4053BM96G3 SOIC D 16 2500 364.0 364.0 27.0
CD4053BM96G4 SOIC D 16 2500 333.2 345.9 28.6
CD4053BPWR TSSOP PW 16 2000 367.0 367.0 35.0
CD4053BPWR TSSOP PW 16 2000 364.0 364.0 27.0
CD4053BPWRG3 TSSOP PW 16 2000 364.0 364.0 27.0
CD4053BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0

Pack Materials-Page 3
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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