S805 Datasheet Revision 0.

9.3.7. GPIO 4 ~ 7 Pin Select: 0x2622

Bit(s) R/W Default Description
31-24 R/W 0 GPIO_PIN_SEL7: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 7
23-16 R/W 0 GPIO_PIN_SEL6: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 6
15-8 R/W 0 GPIO_PIN_SEL5: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 5
7-0 R/W 0 GPIO_PIN_SEL4: This value select which of up to 256 pins on the chip can be mapped to GPIO interrupt 4

9.3.8. GPIO Filter Select (interrupts 0~7): 0x2623

Bit(s) R/W Default Description
31 R/W 0 unused
30-28 R/W 0 FILTER_SEL7: (see FILTER_SEL0)
27 R/W 0 Unused
26-24 R/W 0 FILTER_SEL6: (see FILTER_SEL0)
23 R/W 0 Unused
22-20 R/W 0 FILTER_SEL5: (see FILTER_SEL0)
19 R/W 0 Unused
18-16 R/W 0 FILTER_SEL4: (see FILTER_SEL0)
15 R/W 0 Unused
14-12 R/W 0 FILTER_SEL3: (see FILTER_SEL0)
11 R/W 0 Unused
10-8 R/W 0 FILTER_SEL2: (see FILTER_SEL0)
7 R/W 0 Unused
6-4 R/W 0 FILTER_SEL1: (see FILTER_SEL0)
3 R/W 0 unused
2-0 R/W 0 FILTER_SEL0: This value sets the filter selection for GPIO interrupt 0. A value of 0 = no filtering. A value of 7
corresponds to 7 x 3 x (111nS) of filtering.

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S805 Datasheet Revision 0.8

10. DIRECT MEMORY ACCESS CONTROLLER (DMAC)

10.1. Overview
The DMA controller is an engine connected to the DDR controller for the purposes of moving data to/from DDR memory. The
DMA controller supports 4 independent threads. Each thread is driven by DMA table descriptors placed in DDR memory. Each
DMA descriptor consists of 8 entries that describe the source/destination location as well as the stride and burst. Inline
processing is also supported to allow data from DDR to be processed using an AES, Triple-DES or CRC module before being
placed back into DDR memory.

10.2. Descriptor Table

Entry 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Thread Slice Count

Pre INLINE (0 = use default slice)
0 - - - - - - - - - - - -
Endian Type Number of 256
256-byte blocks to
allocate to this thread

1 SP: Source Pointer (AHB address)

2 DP: Destination Pointer (AHB address) (0xFFFFFFFF = send data to the parser)
3 - - - - - - - Byte transfer count
4 Source Skip Source Burst Count
5 Destination Skip Destination Burst Count
6-TDES
re
Curr
st Post
ent
ar Endian
key
t

6-AES
Re En
CTR CTR
Mode set cry Type Post Endian Pre Endian
Endian Limit
IV pt

6-Divx

Post
Endian

6-CRC r
n
e
o
s
w Post
CRC Count t
ri Endian
a
t
r
e
t
7 UNUSED Fill with 0.
Filler to ensure each descriptor is 32-bytes so that the descriptors land on a cache line boundary

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S805 Datasheet Revision 0.8

10.3. DMA Hardware Algorithm

If( ~2D ) {
While( byte_transfer_count-- ) {
*DP = *SP; // Move data
SP += (move size);
DP += (move size);
}
} else {
SBBC_tmp = SBBC; // initialize the Source Burst Byte Count
DBBC_tmp = SBBC; // initialize the Destination Burst Byte Count
While( byte_transfer_count-- ) {
*DP = *SP; // Move data

if( SBS == 0 ) { // If NOT skipping the source pointer

SP += (move size);
} else { // 2D Move
SBBC_tmp -= (move size); // decrement the source burst byte count
if( !SBBC_tmp == 0 ) { // if burst is NOT done
SP += (move size);
} else { // If the burst is done, then skip
SBBC_tmp = SBBC; // reset the burst byte count
SP += SBS; // skip the source pointer
}
}

if( DBS == 0 ) { // If NOT skipping the destination pointer

DP += (move size);
} else { // 2D Move
DBBC_tmp -=
= (move size); // decrement the destination burst byte count
if( DBBC_tmp == 0 ) { // if burst is NOT done
DP += (move size);
} else { // If the burst is done, then skip
DBBC_tmp = SBBC; // reset the burst byte count
DP += DBS; // skip the destination pointer
}
}
}
}

CONTROL: Descriptor Entry 0

31-30 Thread ID: Each DMA table entry is assigned an ID. The DMA engine rotates between threads based on the ID
29-27 Pre-Endian:
Endian: DATA Endian [63:0] = <b0,b1,b2,b3,b4,b5,b6,b7}; where b0 = byte 0, b1 = byte1,...

Endian Byte order

----------------------------------------
000 7 6 5 4 3 2 1 0 // no change
001 6 7 4 5 2 3 0 1 // swap bytes
010 5 4 7 6 1 0 3 2 // swap words
011 4 5 6 7 0 1 2 3 // reverse
100 3 2 1 0 7 6 5 4
101 2 3 0 1 6 7 4 5
110 1 0 3 2 5 4 7 6
111 0 1 2 3 4 5 6 7
NOTE: AES has its own endian control as well
26 Source Hold: Normally the source pointer is incremented as data is transferred. Set this bit to force the source pointer to keep the same
position. This is useful if you want to DMA from an internal module at a fixed address.
25 Destination Hold: Normally the destination pointer is incremented as data is transferred. Set this bit to force the
th destination pointer to
keep the same position. This is useful if you want to DMA to an internal module at a fixed address.
24-22 INLINE_type: These bits dictate the format of the last entry of the descriptor
00: Normal 1D or 2D move. The last descriptor entry is ignored
001: The last descriptor entry is for Triple-DES processing
010: The last descriptor entry is for Rijndael (DIVX) processing
011: The last descriptor entry is for CRC processing
100: The last descriptor entry is for AES processing
21 IRQ: Set this bit if you want the DMA engine to generate an interrupt after this table entry has been processed
20-9 unused
8 NO Break: The DMA engine will move from thread to thread based on the thread slice count (bits[7:0] below). If you want a DMA
process to complete without interrupt set this bit to 1. If this bit is set to 0, then the DMA will be operation will be interrupted after
THREAD_SLICE*256 bytes have been transferred
7-0 THREAD_SLICE: This value represents the number of 256 byte transfers to allocate to this thread before the DMA engine suspends this
DMA transfer and moves to the next thread.
SOURCE POINTER: Descriptor Entry 1
31-0 Source Pointer. This value corresponds to the AHB address of the source data.

58/123 AMLOGIC, Inc. Proprietary