Problem 1 - Static Discipline: ( 2 Pages)

Problem 1 – Static Discipline [~2 pages]
For this problem, use the S-model of the MOSFET with 𝑽𝑻 = 𝟐𝑽. Consider the following
circuit with 𝑉𝑆 = 5𝑉 and 𝑅𝐿 = 2𝑘Ω.
a. If 𝐼𝑁 < 2𝑉, what will be the state and output of 𝑀1? Hence what would be the state
of 𝑀2 and the voltage value of 𝑂𝑈𝑇?
b. If 𝐼𝑁 ≥ 2𝑉, what will be the state and output of 𝑀1? Hence what would be the state
of 𝑀2 and the voltage value of 𝑂𝑈𝑇?
c. From the results of a. and b., what logical function does this circuit perform (NOT?
Buffer? NAND? NOR?)
d. From the results of a. and b., draw the voltage transfer characteristics of the entire
circuit, i.e., draw the 𝑂𝑈𝑇 𝑣𝑠 𝐼𝑁 graph.
e. Does the circuit satisfy the static discipline for the voltage thresholds 𝑉𝑂𝐿 = 1𝑉,
𝑉𝐼𝐿 = 1.5𝑉, 𝑉𝑂𝐻 = 4𝑉 and 𝑉𝐼𝐻 = 3𝑉? Why or why not?
[Hint: use graphical method as shown in lecture videos]
f. Does the circuit satisfy the static discipline if the 𝑉𝐼𝐿 specification was changed to
𝑉𝐼𝐿 = 2.5𝑉? Why or why not?
[Hint: use graphical method as shown in lecture videos]
g. What is the maximum value of 𝑉𝐼𝐿 for which the circuit will (marginally) satisfy the
static discipline? What is the 𝑁𝑀0 in this case?
h. What is the minimum value of 𝑉𝐼𝐻 for which the circuit will (marginally) satisfy the
static discipline? What is the 𝑁𝑀1 in this case?
Problem 2 – CMOS Logic Gates [~1.5 pages]
Background
We have learned about NMOS and its S-model in the lectures. According to this model, the
NMOS will be “OFF” (open circuit) if 𝑉𝐺𝑆 < 𝑉𝑇𝑛 (for example 𝑉𝐺𝑆 = 0𝑉) and it will be “ON”
(short circuit) if 𝑉𝐺𝑆 ≥ 𝑉𝑇𝑛 (for example 𝑉𝐺𝑆 = 5𝑉). Here, the threshold voltage 𝑉𝑇𝑛 is positive
for NMOS.
The other type of MOSFET, i.e., the PMOS, has a similar S-model, but the conditions are
reversed. That is, the PMOS will be “OFF” (open circuit) if 𝑉𝐺𝑆 ≥ 𝑉𝑇𝑝 (for example 𝑉𝐺𝑆 = 0𝑉)
and it will be “ON” (short circuit) if 𝑉𝐺𝑆 < 𝑉𝑇𝑝 (for example 𝑉𝐺𝑆 = −5𝑉). The summary of the
S-model for both NMOS and PMOS is given below. Unlike NMOS, the threshold voltage 𝑉𝑇𝑝
for PMOS is negative.
Currently, the most popular technology used in computer chip design, including CPU and
RAM, is called CMOS. CMOS stands for Complementary MOS, and this technology takes
advantage of a pair of PMOS and NMOS to build ICs with very low power consumption. In
fact, CMOS circuits have almost zero static power consumption, they only require small
amount of power to switch states.
Main Question Part 1

Consider the following CMOS circuit. Assume 𝑉𝑆 = 5𝑉, 𝑉𝑇𝑛 = 1𝑉 for the NMOS, and
𝑉𝑇𝑝 = −1𝑉 for the PMOS. Notice how the Drain and the Source of the PMOS are connected.
Use the S-model for both NMOS and PMOS for the rest of the question.
a. If 𝑉𝐼𝑁 = 0𝑉, what is the value of 𝑉𝐺𝑆 for the NMOS? What is the value of 𝑉𝐺𝑆 for the
PMOS? Hence, what are the states (ON/OFF) of the NMOS and the PMOS? Therefore,
what is the value of the output voltage 𝑉𝑂𝑈𝑇 ?
[Hint: Will the node 𝑉𝑂𝑈𝑇 get shorted to ground or 𝑉𝑆 in this case?]
b. If 𝑉𝐼𝑁 = 5𝑉, what is the value of 𝑉𝐺𝑆 for the NMOS? What is the value of 𝑉𝐺𝑆 for the
PMOS? Hence, what are the states (ON/OFF) of the NMOS and the PMOS? Therefore,
what is the value of the output voltage 𝑉𝑂𝑈𝑇 ?
[Hint: Will the node 𝑉𝑂𝑈𝑇 get shorted to ground or 𝑉𝑆 in this case?]
c. Considering 0V as logical 0 and 5V as logical 1, What logical operation does this circuit
perform? Write down the Boolean truth table of 𝐼𝑁 𝑣𝑠 𝑂𝑈𝑇.
Main Question Part 2
𝑉𝐴 (𝑉) 𝐴(0/1) 𝑉𝐵 (𝑉) 𝐵(0/1) StateM1 StateM2 StateM3 StateM4 𝑉𝐶 (𝑉) 𝐶(0/1)
0𝑉 0 0𝑉 0
0𝑉 0 5𝑉 1
5𝑉 1 0𝑉 0
5𝑉 1 5𝑉 1
Fill out the above table twice, once for each of the following circuits. Here assume 𝑉𝑆 = 5𝑉.
Note that if the input voltage 5V, you can consider an NMOS to be ON and a PMOS to be OFF.
On the other hand, if the input voltage is 0V, consider the NMOS to be OFF an the PMOS to
be ON. What logic function does Circuit (a) perform? What about Circuit (b)?
Hint: The first row of the table for Circuit (a) is done for you. The node C will be shorted to 𝑉𝑆
in this case.
𝑉𝐴 (𝑉) 𝐴(0/1) 𝑉𝐵 (𝑉) 𝐵(0/1) StateM1 StateM2 StateM3 StateM4 𝑉𝐶 (𝑉) 𝐶(0/1)
0𝑉 0 0𝑉 0 OFF OFF ON ON 5𝑉 1
Problem 3 – Method of Assumed State for MOSFET [~2 pages]
Design the following circuit in such a way that the MOSFET operates at a drain current, 𝑖𝐷 ,
𝑚𝐴
of 0.5 𝑚𝐴 and 𝑣𝑜 = 0.5𝑉. That is, find the value of 𝑅𝐷 and 𝑅𝑆 . Here, 𝑉𝑇 = 0.7𝑉, 𝐾 = 2 2 ,
𝑉
and 𝑅1 = 10 𝑘Ω. Note that you MUST verify your assumption! Use real MOSFET equations.
Hint: Here are some questions that will guide you to the solution:
1. What is the value of the voltage 𝑣𝐴 ? [Hint: Week 1, Lecture 1, Part 3, Last 4 minutes]
2. What is the gate voltage 𝑉𝐺 ? [Hint: The gate is shorted to ….]
3. The value of 𝑖𝐷 is given, and you know the voltage of the two terminals of 𝑅𝐷 . What is
the equation relating 𝑖𝐷 , 𝑣𝑜 = 0.5𝑉, and 2.5𝑉?
4. Assume the MOSFET is in one of the states. Which one should you start with?
5. From the equation of 𝑖𝐷 for the state you assumed, find the value of 𝑉𝑆 .
[Hint: 𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 and 𝑉𝐷𝑆 = 𝑉𝐷 − 𝑉𝑆 . What’s the value of 𝑉𝐺 ? What about 𝑉𝐷 ?
6. Is your assumption correct? Why or why not? If not, go back to step 4 and repeat for
another assumption.
7. Now you know the voltage of the two nodes of 𝑅𝑆 and the current through it. Find 𝑅𝑆 .
Problem 4 – MOSFET Amplifier [~1 page]
Consider the following small signal MOSFET amplifier circuit.
The input voltage is given as 𝑉𝐼𝑁 = 𝑉𝐺𝑆 = 𝑋 + 𝑣𝑖 (𝑡) = 5𝑉 + 𝑣𝑖 (𝑡) and output voltage is given
as 𝑣𝑂 = 𝑌 + 𝐴𝑣𝑖 (𝑡) = 8 + 𝐴𝑣𝑖 (𝑡). Here, 𝑣𝑖 (𝑡) is a sinusoidal voltage with amplitude 𝑎, 𝑋 is
the input DC voltage, 𝑌 is the output DC voltage. The input and output waveforms are given
below. Notice the output small signal is inverted compared to input small signal. Hence, the
small signal gain, 𝐴, will be negative.
a. From the above graph, what is the amplitude of the input small signal 𝑣𝑖 (𝑡)?
b. From the above graph, what is the amplitude of the output small signal?
c. Hence, what is the small signal gain 𝐴? (Note: A should be negative)
d. From the above graph, what is the value of input DC voltage 𝑋 and the output DC
voltage 𝑌?
e. Design the circuit, i.e., find the value of 𝑉𝑆 and 𝑅𝐿 to achieve given input-output
voltage relation and the given small signal amplification.
[Hint: See Week 8, Lecture 2 - Part 6 and Pop Quiz 2. Work backward from 𝐴 and 𝑌 to
find 𝑅𝐿 and 𝑉𝑆 ]
Problem 5 – BJT Logic Gates [~0.5 page]
Find the logic functions 𝑓 as function of the Boolean inputs 𝐴, 𝐵, 𝐶, 𝐷, and 𝐸 for the
following three BJT circuits. Use the S-model for the BJT.
Problem 6 – Method of Assumed State for BJT [~2 pages]
For the following BJT, 𝑉𝐵𝐸 (𝑎𝑐𝑡𝑖𝑣𝑒) = 0.7 𝑉, 𝑉𝐵𝐸 (𝑠𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛) = 0.8 𝑉, and 𝑉𝐶𝐸 (𝑠𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛) = 0.2 𝑉.
Use method of assumed state to find the following (note that you MUST verify your
assumption):
(i) 𝐼𝐶
(ii) 𝐼𝐸
(iii) 𝐼𝐵
(iv) 𝛽
(v) 𝛼
[Hint: See the solved problems in the handout of Week 9 Lecture 2]

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Problem 1 – Static Discipline [~2 pages]

Main Question Part 1

[Hint: See the solved problems in the handout of Week 9 Lecture 2]

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