264 Software Defined Radio Using MATLAB & Simulink and the RTL-SDR

(a) Open the MATLAB script:

/synch/PLL/configure_PLL_linear_model.m

(b) Inspect the contents of the MATLAB file. This is a simple script which sets the values of the
loop gain coefficients k p , k o , and k 1 , and then calculates the required value of k 2 based on
the chosen damping ratio, d ( ζ ). The damping ratio is initially set to a value of 1, i.e. the system
is said to be ‘critically damped’.

(c) Run the MATLAB script. This will create the variables necessary to parameterise the
Simulink model, in advance of opening it.

(d) Open the Simulink model:

/synch/PLL/PLL_linear_model_2.slx

Notice that this system represents a PLL, with a Type 3 loop filter. However, the last loop filter
coefficient, k 3 , is initially set to zero, meaning that it effectively forms a Type 2 PLL.

(e) Check out the Step response. Run the Simulink model by 1 on the ‘Run’ button, with
the input selector set to the Step input, and view the results. You should see that the PLL is
able to adapt with zero steady state phase error. It will follow a particular shape as it adapts.

? (f) Investigate the damping ratio. Try changing to a damping ratio of 0.3, by making an
appropriate change to the MATLAB script. After you have altered the code, first rerun the
MATLAB script, and then secondly the Simulink model. What do you notice about the transient
behaviour? You could also try other values, including a much higher damping ratio (say ζ =
3). You might also wish to experiment with different input types (ramp and hyperbola).

? (g) Try a Type 3! Lastly, change the PLL to a Type 3 and see what happens. Set the value of the
k 3 gain coefficient to be 2e-5 (you can make this alteration directly in the Simulink model), and
switch the input to the Hyperbola, by changing the positions of the manual switches. Ensure
that the MATLAB script is run for the case where ζ = 1 (you will need to change this back to
its original value, then rerun).

(h) Resimulate! Can this Type 3 PLL adapt effectively in the case of the Hyperbola input?

7.8 PLL Design

Although some of the characteristics and parameters of PLLs have been introduced, we have not so far
discussed how to design a PLL to achieve a certain set of requirements. This section presents a practical,
step-by-step guide to setting the parameters of a Type 2 PLL, in order to achieve the desired
characteristics. More detailed review and derivation may be found in Appendix D (page 593), which
follows the analysis presented in [38].

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Chapter 7: Frequency Tuning and Simple Synchronisation 265

7.8.1 Step 1: Determine the sample period

When designing a digital PLL, the sampling rate f s is likely to be a pre-determined aspect of the system.
The sample period can therefore be calculated simply as

1
T = --- . (7.24)
fs

Note that the parameter T will be required in later calculations.

If the sampling rate is not already set, it should be specified as a value at least 5 times higher than the
expected frequency of the input reference sine wave. This assumes the use of a multiplier-based phase
detector, which will generate components at approximately double the input frequency. (It may be
possible to run successfully with a lower sample rate, but using the above rule will keep matters simple
and clear!)

7.8.2 Step 2: Establish the gain of the phase detector

In this book, we consider two alternative methods of implementing the phase detector: (i) an ‘ideal’ phase
detector component that accurately measures the phase difference between two input signals; or (ii) as a
multiplier. The two alternatives result in different values for the phase detector gain coefficient, K p ,
which is due to their different characteristic ‘s-curves’ (more on this in Appendix D, page 593).
For our current purposes, we simply note the following:
• For an ‘ideal’ phase detector: Kp = 1
• For a ‘multiplier’ phase detector: Kp = A ⁄ 2
where A is the amplitude of the input reference signal applied to the multiplier phase detector.
The above indicates that, in the multiplier-based design, the phase detector gain varies with the
amplitude of the input signal. This dependency is undesirable, because a change in the input signal
amplitude could fundamentally alter the behaviour of the PLL. As a result, it is common to precede the
PLL with a stage of AGC [39], which dynamically adjusts the gain applied to the input signal, such that
it is scaled to the normalised range from -1 to +1.
It should be noted that the gain, K p , is an inherent property of the phase detector, and does not refer to
a separate gain coefficient set within the phase detector section of the PLL circuit.

7.8.3 Step 3: Establish the gain of the NCO

The structure and behaviour of the NCO component were reviewed in Section 7.5.3. The NCO is capable
of generating sine and cosine waves of a dynamically variable frequency, with the adjustment made via a
feedback signal supplied from the output of the loop filter. A gain of K o is applied to this feedback signal,
as shown in Figure 7.13. The gain coefficient can be freely chosen, but a common choice is to set K o = 1 .

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266 Software Defined Radio Using MATLAB & Simulink and the RTL-SDR

7.8.4 Step 4: Choose the Damping Ratio

The damping ratio parameter ζ was introduced in Section 7.7.3. It was shown that the value of ζ affects
the transient behaviour of the PLL as it adapts, and also its tracking capabilities. An appropriate value of
ζ should be selected based on the nature of the synchronisation task; as stated earlier, values in the range
0.5 to 2 are common because they achieve a good balance of stability and tracking properties.
The damping ratio is not set explicitly within the PLL. Rather, the parameter is incorporated into the
calculation of the loop filter coefficient values (as will be shown in Step 6 of our design process). The
desired damping ratio is achieved by appropriately setting the various parameters of the PLL.

7.8.5 Step 5: Specify the Noise Bandwidth

It was earlier established that specifying the bandwidth of a PLL is an important aspect of its design. A
narrow bandwidth lets very little noise into the PLL, but can result in the PLL taking a long time to
achieve lock; while a broad bandwidth enables quick adaptation, but with poorer noise performance.
Here, we will specify the noise bandwidth, B n , of a PLL in Hz.
The maximum expected frequency offset (i.e. the difference between an incoming sine wave, and the
locally generated sine wave) must be taken into account when defining B n , in order to ensure that the
PLL can successfully lock. The range of frequencies deviations over which the PLL can lock is referred to
the pull-in range, and it is an interaction between B n and damping ratio, ζ . Useful approximations for
pull-in range, along with approximate times to attain lock, are given in [38]. Suitable operation over the
range of expected offsets can also be confirmed through simulation.
Like damping ratio, PLL noise bandwidth is an implicit parameter of the PLL, rather than being set
directly within the loop implementation. Instead, the chosen value of noise bandwidth, B n , is
incorporated into the equations from which the loop filter coefficient values are determined.

7.8.6 Step 6: Calculate the Loop Filter Gain Coefficients

Two gain coefficients are needed in the Type 2 PLL: K 1 and K 2 , for the proportional and integral
branches, respectively. This was previously shown in Figure 7.14. Values for the coefficients can be
calculated, provided that the following parameters are known:
• Sampling period, T
• NCO gain, K o
• Phase detector gain, K p
• Damping ratio, ζ
• Noise bandwidth, B n
To calculate the required values, Eqs. (D.50) and (D.51) from Appendix D (page 593) can be rearranged
for K 1 and K 2 , respectively, to give:

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Chapter 7: Frequency Tuning and Simple Synchronisation 267

 B T 
---------------
n 
4ζ  1 
ζ + ----- 4ζ 
-

K 1 = -------------------------------------------------------------------------------------------
2
- (7.25)
  B T   B T  
 ---------------
n  --------------- n  
K o K p  1 + 2ζ  1   + 1  
 ζ + ----- 4ζ
-  ζ + ------  
4ζ
     

2
 B T 
---------------
n 
4 1 
ζ + ----- -
4ζ 

K 2 = -------------------------------------------------------------------------------------------
2
- . (7.26)
  B T   B T  
 ---------------
n  --------------- n  
K o K p  1 + 2ζ  1  +  1  
 ζ + ----- -  ζ + ------  
4ζ   4ζ  
 

Noting the repeated term, it is convenient to make the substitution

Bn T
η = --------------- , (7.27)
1
ζ + ------
4ζ

which results in

4ζη
K 1 = -------------------------------------------------
2
- (7.28)
K o K p ( 1 + 2ζη + η )

and
2
4η
K 2 = -------------------------------------------------
2
- . (7.29)
K o K p ( 1 + 2ζη + η )

According to [38], a pair of simpler approximations can be used, where the bandwidth of the loop is
defined as small in relation to the sample rate (i.e. where B n T « 1 ). These simplified expressions are

4ζB n T
K 1 ≈ ------------------------------------ (7.30)
1
K o K p  ζ + ------ 
4ζ

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268 Software Defined Radio Using MATLAB & Simulink and the RTL-SDR

and
2
4 ( Bn T )
K 2 ≈ --------------------------------------2- (7.31)
1
K o K p  ζ + ------ 
 4ζ 

respectively.

7.8.7 Step 7: Confirm the Complete PLL Model

We can now confirm the construction of a Type 2 PLL from low level blocks, and associate with it the
various parameters reviewed over the preceding sections. A diagram is shown in Figure 7.21. Note that
the signal supplied as the input reference signal is sampled at a rate of f s Hz, which results in a sampling
period of T seconds.
It should also be remembered that the value of K p depends on the amplitude of the input signal, if using
a multiplier phase detector (with K p = A ⁄ 2 ). As mentioned previously, it is usual to precede a PLL with
an AGC stage where the input signal amplitude is variable, thus ensuring that the amplitude of the signal
input to the PLL is approximately equal to 1, and therefore that the value of K p is 0.5.
Finally, note that a ‘modulo 2π ’ operation could also be inserted prior to the cos ( ) function within the
NCO. This may be preferable for visualisation purposes, and it would also prevent the possibility of
numerical overflow occurring.

7.8.8 Step 8: Simulate the PLL and Verify Behaviour

At this stage, the parameters T , K p , K o , B n and ζ have been established, and from these, the required
values of K 1 and K 2 have been derived. The value of μ q , the quiescent step size for the NCO, has been
set based on the quiescent frequency, using Eq. (7.20).
The model can now be realised in MATLAB or Simulink, and simulated. The simulated outputs should
be assessed in terms of transient behaviour, time to achieve lock, performance in noise, tracking
capability, steady state behaviour, and any other desired characteristics. Adjustments can then be made,
if necessary, by re-parameterising the model and repeating the simulation process.

7.8.9 Design Example

We will now consider an example with the following parameters:

• Sampling rate: fs = 10kHz
• Sample period: T = 1 ⁄ f s = 100e – 6 s
• Quiescent frequency: fq = 800Hz
• Damping ratio: ζ = 0.707
• Phase detector gain: Kp = 0.5
• Oscillator gain: Ko = 1
• Noise bandwidth: Bn = 5Hz

268
 sampled at
fs = 1/T Hz Phase Detector
Loop Filter

AGC

K1 K2

Arxcos(2SfcmT+T) cos(2SfcmT+T) Kp

(implicit gain)

z-1
Chapter 7: Frequency Tuning and Simple Synchronisation

sin(2SfcmT+T)
NCO

v[m]
P[m] Pa[m]
sin(.) -1
z K0

cos(2SfcmT+T) cos(.) Pq

Figure 7.21: PLL model showing low level implementation

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270 Software Defined Radio Using MATLAB & Simulink and the RTL-SDR

It can be calculated that the required NCO quiescent step size is

2πf q 2π × 800
μ q = ----------- = --------------------- = 0.5027 . (7.32)
fs 10, 000

The value of loop filter coefficient K 1 can be obtained from Eq. (7.28), and K 2 from Eq. (7.29). We first
determine the value of η using Eq. (7.27), i.e.

Bn T –6
5 × 100e
η = --------------- = ------------------------------------------------ = 4.714e –4 . (7.33)
1 1
ζ + ------
4ζ 0.707 +  ----------------------
4 × 0.707


The value for η can then be substituted into Eq. (7.28), i.e.

4ζη
K 1 = --------------------------------------------------- (7.34)
K o K p  1 + 2ζη + η 
2
 

4 × 0.707 × 4.714e –4
= ---------------------------------------------------------------------------------------------------------------------- = 0.0027 .
2
1 × 0.5 × ( 1 + 2 × 0.707 × 4.714e – 4 + 4.714e –4 )

Likewise, K 2 can be obtained from Eq. (7.29) using the value for η calculated in Eq. (7.33).
2
4η
K 2 = --------------------------------------------------- (7.35)
K o K p  1 + 2ζη + η 
2
 
2
4 × 4.714e – 4
= ---------------------------------------------------------------------------------------------------------------------
-
2 = 1.777e – 6 .
1 × 0.5 × ( 1 + 2 × 0.707 × 4.714e + 4.714e ) – 4 – 4

All of the necessary parameters are now available, and can be used to implement a PLL model and
simulate it.

Exercise 7.9 Challenge: Design of a Type 2 PLL

This example follows on from the design example in Section 7.8.9. This is quite a challenging exercise
that will require you to generate your own scripts and models (or if you wish, you could try to reuse and
modify existing ones from earlier exercises!).

(a) Open the MATLAB. Create a new MATLAB script, and save it with the filename:

/my_models/my_PLL_parameters.m

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Chapter 7: Frequency Tuning and Simple Synchronisation 271

(b) Write code to define the PLL parameters given in Section 7.8.9. Follow this with code that
implements equations (7.32) to (7.35), and calculates the remaining parameters. If you need
to refresh your memory on how to create MATLAB variables, please look back at the Getting
Started with MATLAB and Simulink chapter.

(c) Execute and check the results. Run the script you have created, and ensure that it generates
the expected numerical results.

(d) Create a new Simulink model. Save this with the filename:

/my_models/my_PLL.slx

(e) Build a PLL. Build a Type 2 PLL, following the diagram given in Figure 7.22. You can leave
out the AGC section if you wish, by ensuring that the input reference signal has an amplitude
of 1.
Remember that, having run the script and created the variables in the MATLAB Workspace,
you can now use the parameters directly in the model. For instance, you could use the variable
names K1 and K2 to set the gain of the Constant Multiplier blocks from the Loop Filter.
All of the components you will require to build the PLL can be found inside the Simulink Library
Browser. Blocks you are likely to need include:
Product > Simulink > Math Operations
Gain > Simulink > Math Operations
Add > Simulink > Math Operations
Trigonometric Function > Simulink > Math Operations
Delay > Simulink > Discrete

(f) Make sure to place some input sources from > Simulink > Sources and a Time Scope from
> DSP System Toolbox > Sinks, to allow you to test your PLL design out!

(g) Run a simulation. Run the model by 1 on the ‘Run’ button, and check that the PLL is
working as expected.

? (h) Design PLL parameters #2. Use your script to design PLL parameters for the following
scenario, and hence update the configuration of your PLL.
• Sampling rate of 48kHz
• Expected tone frequency of 256Hz
• Maximum expected frequency deviation 0.5Hz
• Multiplier phase detector
• Critically damped PLL.

(i) Run a simulation! Execute a simulation and ensure that the model behaves correctly.

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272 Software Defined Radio Using MATLAB & Simulink and the RTL-SDR

7.9 PLL Performance in Noise

In this section, we briefly look at the behaviour of PLLs in noisy conditions, and the effect of noise
bandwidth on performance. These simulations incorporate an Additive White Gaussian Noise (AWGN)
source, which is added to the reference sine wave at the input to the PLL.

Exercise 7.10 Type 2 PLL: Performance in Noise

In this example, we will consider the performance of a Type 2 PLL in noise, and note the impact of
altering the noise bandwidth.

(a) Open MATLAB. Set the working directory to an appropriate folder so you can open this script:

/synch/PLL/configure_noise_model.m

(b) Run the script to generate the PLL parameters. You may also wish to read through this
script to see which parameters have been created.

(c) Open the Simulink model:

/synch/PLL/PLL_type2_noise.slx

(d) Simulate the model. First, run the simulation in zero noise conditions (check the position of
the Manual Switch) and confirm that the PLL converges to the frequency of the input. How long
does it take?

(e) Re-simulate with added noise. Now flick the manual switch so that the input is corrupted by
noise, and rerun the simulation. Hence, ensure that the PLL converges in the presence of
noise. (You should notice from the time domain output that the PLL is able to synthesise a sine
wave of the correct frequency and phase, even in noisy conditions.)

Reference Input
1.5 Synthesised

0.5
Amplitude

−0.5

−1

−1.5

4.98 4.982 4.984 4.986 4.988 4.99 4.992 4.994 4.996 4.998
Time (s) x 10
−3

272