AT28HC64B

Features
• Fast Read Access Time - 55 ns
• Automatic Page Write Operation
Internal Address and Data Latches for 64-Bytes
• Fast Write Cycle Times
Page Write Cycle Time: 10 ms Maximum
1 to 64-Byte Page Write Operation
• Low Power Dissipation
40 mA Active Current
100 µA CMOS Standby Current
• Hardware and Software Data Protection 64K (8K x 8)
• DATA Polling and Toggle Bit for End of Write Detection
• High Reliability CMOS Technology High Speed
Endurance: 100,000 Cycles

•
Data Retention: 10 Years
Single 5V ± 10% Supply
CMOS
• CMOS and TTL Compatible Inputs and Outputs
E2PROM with
• JEDEC Approved Byte-Wide Pinout
• Commercial and Industrial Temperature Ranges
Page Write and
Description Software Data
The AT28HC64B is a high-performance electrically erasable and programmable read
only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Protection
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 55 ns with power dissipation of just 220 mW. When the device is
deselected, the CMOS standby current is less than 100 µA.
The AT28HC64B is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
(continued)
Pin Configurations
Pin Name Function TSOP AT28HC64B
A0 - A12 Addresses Top View
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect

PDIP, SOIC PLCC

Top View Top View

Note: PLCC package pins 1 and

17 are DON’T CONNECT. 0274D

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Description (Continued)
writing of up to 64-bytes simultaneously. During a write cy- Atmel’s AT28HC64B has additional features to ensure
cle, the addresses and 1 to 64-bytes of data are internally high quality and manufacturability. The device utilizes in-
latched, freeing the address and data bus for other opera- ternal error correction for extended endurance and im-
tions. Following the initiation of a write cycle, the device proved data retention. An optional software data protec-
will automatically write the latched data using an internal tion mechanism is available to guard against inadvertent
control timer. The end of a write cycle can be detected by writes. The device also includes an extra 64-bytes of
DATA Polling of I/O7. Once the end of a write cycle has EEPROM for device identification or tracking.
been detected, a new access for a read or write can begin.

Block Diagram

Absolute Maximum Ratings*

*NOTICE: Stresses beyond those listed under “Absolute Maxi-
Temperature Under Bias................. -55°C to +125°C mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
Storage Temperature...................... -65°C to +150°C device at these or any other conditions beyond those indi-
All Input Voltages cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
(including NC Pins)
for extended periods may affect device reliability.
with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground .............-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V

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 AT28HC64B

Device Operation
READ: The AT28HC64B is accessed like a Static RAM. read. Toggle bit reading may begin at any time during the
When CE and OE are low and WE is high, the data stored write cycle.
at the memory location determined by the address pins is DATA PROTECTION: If precautions are not taken, inad-
asserted on the outputs. The outputs are put in the high- vertent writes may occur during transitions of the host sys-
impedance state when either CE or OE is high. This dual tem power supply. Atmel has incorporated both hardware
line control gives designers flexibility in preventing bus and software features that will protect the memory against
contention in their systems. inadvertent writes.
BYTE WRITE: A low pulse on the WE or CE input with CE HARDWARE DATA PROTECTION: Hardware features
or WE low (respectively) and OE high initiates a write cy- protect against inadvertent writes to the AT28HC64B in
cle. The address is latched on the falling edge of CE or the following ways: (a) VCC sense - if VCC is below 3.8V
WE, whichever occurs last. The data is latched by the first (typical), the write function is inhibited; (b) VCC power-on
rising edge of CE or WE. Once a byte write has been delay - once VCC has reached 3.8V, the device will auto-
started, it will automatically time itself to completion. Once matically time out 5 ms (typical) before allowing a write; (c)
a programming operation has been initiated and for the write inhibit - holding any one of OE low, CE high or WE
duration of tWC, a read operation will effectively be a poll- high inhibits write cycles; (d) noise filter - pulses of less
ing operation. than 15 ns (typical) on the WE or CE inputs will not initiate
PAGE WRITE: T h e p a g e w r i t e o p e r a t i o n o f t h e a write cycle.
AT28HC64B allows 1 to 64-bytes of data to be written into SOFTWARE DATA PROTECTION: A software-control-
the device during a single internal programming period. A led data protection feature has been implemented on the
page write operation is initiated in the same manner as a AT28HC64B. When enabled, the software data protection
byte write; after the first byte is written, it can then be fol- (SDP), will prevent inadvertent writes. The SDP feature
lowed by 1 to 63 additional bytes. Each successive byte may be enabled or disabled by the user; the AT28HC64B
must be loaded within 150 µs (tBLC) of the previous byte. is shipped from Atmel with SDP disabled.
If the tBLC limit is exceeded, the AT28HC64B will cease
accepting data and commence the internal programming SDP is enabled by the user issuing a series of three write
operation. All bytes during a page write operation must re- commands in which three specific bytes of data are written
side on the same page as defined by the state of the A6 to to three specific addresses (refer to the Software Data
A12 inputs. For each WE high to low transition during the Protection Algorithm diagram in this data sheet). After writ-
page write operation, A6 to A12 must be the same. ing the 3-byte command sequence and waiting tWC, the
entire AT28HC64B will be protected against inadvertent
The A0 to A5 inputs specify which bytes within the page writes. It should be noted that even after SDP is enabled,
are to be written. The bytes may be loaded in any order the user may still perform a byte or page write to the
and may be altered within the same load period. Only AT28HC64B. This is done by preceding the data to be
bytes which are specified for writing will be written; unnec- written by the same 3-byte command sequence used to
essary cycling of other bytes within the page does not oc- enable SDP.
cur.
Once set, SDP remains active unless the disable com-
DATA POLLING: The AT28HC64B features DATA Poll- mand sequence is issued. Power transitions do not dis-
ing to indicate the end of a write cycle. During a byte or able SDP, and SDP protects the AT28HC64B during
page write cycle, an attempted read of the last byte written power-up and power-down conditions. All command se-
will result in the complement of the written data to be pre- quences must conform to the page write timing specifica-
sented on I/O7. Once the write cycle has been completed, tions. The data in the enable and disable command se-
true data is valid on all outputs, and the next write cycle quences is not actually written into the device; their ad-
may begin. DATA Polling may begin at any time during the dresses may still be written with user data in either a byte
write cycle. or page write operation.
TOGGLE BIT: I n a d d i t i o n t o DATA P o l l i n g , t he After setting SDP, any attempt to write to the device with-
AT28HC64B provides another method for determining the out the 3-byte command sequence will start the internal
end of a write cycle. During the write operation, succes- write timers. No data will be written to the device, however.
sive attempts to read data from the device will result in For the duration of tWC, read operations will effectively be
I/O6 toggling between one and zero. Once the write has polling operations.
completed, I/O6 will stop toggling, and valid data will be (continued)

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Device Operation (Continued)
DEVICE IDENTIFICATION: A n e x t r a 6 4 - b y t e s o f dress locations 1FC0H to 1FFFH, the additional bytes
EEPROM memory are available to the user for device may be written to or read from in the same manner as the
identification. By raising A9 to 12V ± 0.5V and using ad- regular memory array.

DC and AC Operating Range

AT28HC64B-55 AT28HC64B-70 AT28HC64B-90 AT28HC64B-120
Operating Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C
Temperature (Case) Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

Operating Modes
Mode CE OE WE I/O
Read VIL VIL VIH DOUT
Write (2) VIL VIH VIL DIN
(1)
Standby/Write Inhibit VIH X X High Z
Write Inhibit X X VIH
Write Inhibit X VIL X
Output Disable X VIH X High Z
(3)
Chip Erase VIL VH VIL High Z
Notes: 1. X can be VIL or VIH. 3. VH = 12.0V ± 0.5V.
2. Refer to the AC Write Waveforms diagrams
in this data sheet.

DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC + 1V 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
(1)
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V Com., Ind. 100 µA
(1)
ISB2 VCC Standby Current TTL CE = 2.0V to VCC + 1V 2 mA
ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 40 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2.1 mA .40 V
VOH Output High Voltage IOH = -400 µA 2.4 V
Note: 1. ISB1 and ISB2 for the 55 ns part is 40 mA maximum.

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 AT28HC64B

AC Read Characteristics
AT28HC64B-55 AT28HC64B-70 AT28HC64B-90 AT28HC64B-120
Symbol Parameter Min Max Min Max Min Max Min Max Units
tACC Address to Output Delay 55 70 90 120 ns
tCE (1) CE to Output Delay 55 70 90 120 ns
tOE (2) OE to Output Delay 0 30 0 35 0 40 0 50 ns
tDF (3, 4) OE to Output Float 0 30 0 35 0 40 0 50 ns
tOH Output Hold 0 0 0 0 ns

AC Read Waveforms (1, 2, 3, 4)

Notes: 1. CE may be delayed up to tACC - tCE after the address 3. tDF is specified from OE or CE, whichever occurs first
transition without impact on tACC. (CL = 5 pF).
2. OE may be delayed up to tCE - tOE after the falling 4. This parameter is characterized and is not 100% tested.
edge of CE without impact on tCE or by tACC - tOE
after an address change without impact on tACC.

Input Test Waveforms and Output Test Load

Measurement Level

tR, tF < 5ns

Pin Capacitance (f = 1 MHz, T = 25°C) (1)

Typ Max Units Conditions
CIN 4 6 pF VIN = 0V
COUT 8 12 pF VOUT = 0V
Note: 1. This parameter is characterized and is not 100% tested.

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AC Write Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Set-up Time 0 ns
tAH Address Hold Time 50 ns
tCS Chip Select Set-up Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE) 100 ns
tDS Data Set-up Time 50 ns
tDH, tOEH Data, OE Hold Time 0 ns

AC Write Waveforms
WE Controlled

CE Controlled

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 AT28HC64B

Page Mode Characteristics

Symbol Parameter Min Max Units
tWC Write Cycle Time 10 ms
tAS Address Set-up Time 0 ns
tAH Address Hold Time 50 ns
tDS Data Set-up Time 50 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Width 100 ns
tBLC Byte Load Cycle Time 150 µs
tWPH Write Pulse Width High 50 ns

Page Mode Write Waveforms (1, 2)

Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.

Chip Erase Waveforms

tS = tH = 5 µsec (min.)
tW = 10 msec (min.)
VH = 12.0V ± 0.5V

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Software Data Software Data
Protection Enable Algorithm (1) Protection Disable Algorithm (1)
LOAD DATA AA LOAD DATA AA
TO TO
ADDRESS 1555 ADDRESS 1555

LOAD DATA 55 LOAD DATA 55

TO TO
ADDRESS 0AAA ADDRESS 0AAA

LOAD DATA A0 LOAD DATA 80

TO TO
ADDRESS 1555 WRITES ENABLED (2) ADDRESS 1555

LOAD DATA XX LOAD DATA AA

TO TO
ANY ADDRESS (4) ADDRESS 1555

LOAD LAST BYTE LOAD DATA 55

TO TO
LAST ADDRESS ADDRESS 0AAA
ENTER DATA
PROTECT STATE
LOAD DATA 20
TO
ADDRESS 1555 EXIT DATA
Notes for software program code: PROTECT STATE (3)
1. Data Format: I/O7 - I/O0 (Hex); LOAD DATA XX
Address Format: A12 - A0 (Hex). TO
2. Write Protect state will be activated at end of write even if no ANY ADDRESS (4)
other data is loaded.
3. Write Protect state will be deactivated at end of write period LOAD LAST BYTE
even if no other data is loaded. TO
LAST ADDRESS
4. 1 to 64-bytes of data are loaded.

Software Protected Write Cycle Waveforms (1, 2)

Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after
the software code has been entered.
2. OE must be high only when WE and CE are both low.

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 AT28HC64B

Data Polling Characteristics (1)

Symbol Parameter Min Typ Max Units
tDH Data Hold Time 0 ns
tOEH OE Hold Time 0 ns
tOE OE to Output Delay (2) ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics.

Data Polling Waveforms

Toggle Bit Characteristics (1)

Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay (2) ns
tOEHP OE High Pulse 150 ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics.

Toggle Bit Waveforms (1, 2, 3)

Notes: 1. Toggling either OE or CE or both OE and CE will 3. Any address location may be used, but the
operate toggle bit. address should not vary.
2. Beginning and ending state of I/O6 will vary.

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2-276 AT28HC64B
 AT28HC64B

Ordering Information (1)

tACC ICC (mA)
Ordering Code Package Operation Range
(ns) Active Standby
55 40 0.1 AT28HC64B-55JC 32J Commercial
AT28HC64B-55PC 28P6 (0°C to 70°C)
AT28HC64B-55SC 28S
70 40 0.1 AT28HC64B-70JC 32J Commercial
AT28HC64B-70PC 28P6 (0°C to 70°C)
AT28HC64B-70SC 28S
AT28HC64B-70TC 28T
40 0.1 AT28HC64B-70JI 32J Industrial
AT28HC64B-70PI 28P6 (-40°C to 85°C)
AT28HC64B-70SI 28S
AT28HC64B-70TI 28T
90 40 0.1 AT28HC64B-90JC 32J Commercial
AT28HC64B-90PC 28P6 (0°C to 70°C)
AT28HC64B-90SC 28S
AT28HC64B-90TC 28T
40 0.1 AT28HC64B-90JI 32J Industrial
AT28HC64B-90PI 28P6 (-40°C to 85°C)
AT28HC64B-90SI 28S
AT28HC64B-90TI 28T
120 40 0.1 AT28HC64B-12JC 32J Commercial
AT28HC64B-12PC 28P6 (0°C to 70°C)
AT28HC64B-12SC 28S
AT28HC64B-12TC 28T
40 0.1 AT28HC64B-12JI 32J Industrial
AT28HC64B-12PI 28P6 (-40°C to 85°C)
AT28HC64B-12SI 28S
AT28HC64B-12TI 28T

Note: 1. See Valid Part Number table below.

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Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers Speed Package and Temperature Combinations
AT28HC64B 55 PC, SC
AT28HC64B 70 JI, PC, PI, SC, SI, TC, TI
AT28HC64B 90 JI, PC, PI, SC, SI, TC, TI
AT28HC64B 12 JI, PC, PI, SC, SI, TC, TI

Package Type
32J 32 Lead, Plastic J-Leaded Chip Carrier (PLCC)
28P6 28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28S 28 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28T 28 Lead, Plastic Thin Small Outline Package (TSOP)

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