SPC560P54L5 STMicroelectronics

SPC56AP60x, SPC56AP54x
SPC560P60x, SPC560P54x
32-bit Power Architecture® based MCU with 1088KB Flash memory
and 80KB RAM for automotive chassis and safety applications
Datasheet - production data
 General purpose I/Os (80 GPIO + 26 GPI on

LQFP144; 49 GPIO + 16 GPI on LQFP100)
 2 general purpose eTimer units
– 6 timers, each with up/down count
LQFP100 capabilities
LQFP144
14 x 14 mm
20 x 20 mm
– 16-bit resolution, cascadable counters
– Quadrature decode with rotation direction
Features flag
– Double buffer input capture and output
 AEC-Q10x qualified compare
 64 MHz, single issue, 32-bit CPU core complex  Communications interfaces
(e200z0h) – 2 LINFlex modules (LIN 2.1, 
– Compliant with Power Architecture® 1 × Master/Slave, 1 × Master Only)
embedded category – 5 DSPI modules with automatic chip select
– Variable Length Encoding (VLE) generation
 Memory organization – 2 FlexCAN interfaces (2.0B Active) with 32
– Up to 1024 KB on-chip code Flash memory message buffers
with additional 64 KB for EEPROM – 1 Safety port based on FlexCAN; usable as
emulation (data flash), with ECC, with third CAN when not used as safety port
erase/program controller – 1 FlexRay™ module (V2.1) with dual or
– Up to 80 KB on-chip SRAM with ECC single channel, 64 message buffers and up
to 10 Mbit/s
 Fail safe protection
 2 CRC units with three contexts and 3
– ECC protection on system SRAM and hardwired polynomials(CRC8,CRC32 and
Flash CRC-16-CCITT)
– Safety port
 10-bit A/D converter
– SWT with servicing sequence pseudo-
– 27 input channels and pre-sampling feature
random generator
– Conversion time < 1 µs including sampling
– Power management time at full precision
– Non-maskable interrupt for both cores – Programmable cross triggering unit (CTU)
– Fault collection and control unit (FCCU) – 4 analog watchdog with interrupt capability
– Safe mode of system-on-chip (SoC)  On-chip CAN/UART Bootstrap loader with boot
– Register protection scheme assist module (BAM)
 Nexus® L2+ interface  Ambient temperature ranges: –40 to 125 °C or
 Single 3.3 V or 5 V supply for I/Os and ADC –40 to 105 °C
 2 on-platform peripherals set with 2 INTC
 16-channel eDMA controller with multiple
transfer request sources
June 2016 DocID18340 Rev 6 1/105

This is information on a product in full production. www.st.com
SPC56xP54x, SPC56xP60x
Table 1. Device summary

Part number
Package
768 KB Flash 1 MB Flash
SPC560P54L5 SPC560P60L5
LQFP144
SPC56AP54L5 SPC56AP60L5
SPC560P54L3 SPC560P60L3
LQFP100
SPC56AP54L3 SPC56AP60L3
2/105 DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.1 High performance e200z0h core processor . . . . . . . . . . . . . . . . . . . . . . 14
1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.3 Enhanced direct memory access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.4 On-chip flash memory with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.5 On-chip SRAM with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.6 Interrupt controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.7 System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.8 Frequency modulated phase-locked loop (FMPLL) . . . . . . . . . . . . . . . . 17
1.5.9 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.10 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.11 Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.12 System timer module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.13 Software watchdog timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.14 Fault collection and control unit (FCCU) . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.15 System integration unit (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.16 Boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.17 Error correction status module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.18 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.19 Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.20 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.21 Serial communication interface module (LINFlex) . . . . . . . . . . . . . . . . . 22
1.5.22 Deserial serial peripheral interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 22
1.5.23 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5.24 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.5.25 Cross triggering unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.5.26 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.27 Nexus development interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.28 IEEE 1149.1 (JTAG) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DocID18340 Rev 6 3/105

5
Contents SPC56xP54x, SPC56xP60x
1.5.29 On-chip voltage regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 27

2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.1 Power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.3 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.5.1 General notes for specifications at maximum junction temperature . . . 56
3.6 Electromagnetic interference (EMI) characteristics . . . . . . . . . . . . . . . . . 58
3.7 Electrostatic discharge (ESD) characteristics . . . . . . . . . . . . . . . . . . . . . 58
3.8 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 58
3.8.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 58
3.8.2 Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60
3.9 Power Up/Down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.10 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.10.1 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.11 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.11.1 DC electrical characteristics (5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.11.2 DC electrical characteristics (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.11.3 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.12 Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.13 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.14 16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . 74
3.15 Analog-to-Digital converter (ADC) electrical characteristics . . . . . . . . . . . 74
3.15.1 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.15.2 ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.16 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4/105 DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Contents
3.17 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.17.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.18 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.18.1 RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.18.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.18.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.18.4 External interrupt timing (IRQ pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.18.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2.1 LQFP144 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2.2 LQFP100 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
DocID18340 Rev 6 5/105

5
List of tables SPC56xP54x, SPC56xP60x
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. SPC56xP54x/SPC56xP60x device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. SPC56xP54x/SPC56xP60x device configuration difference . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. SPC56xP54x/SPC56xP60x series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6. System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7. Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 10. Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 11. Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 12. Thermal characteristics for 144-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 13. Thermal characteristics for 100-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 14. EMI testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 15. ESD ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 16. Approved NPN ballast components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 17. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 18. Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 19. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 20. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) . . . . . . . . . . . . . . . . . . . . . . 64
Table 21. Supply current (5.0 V, NVUSRO[PAD3V5V]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 22. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1) . . . . . . . . . . . . . . . . . . . . . . 67
Table 23. Supply current (3.3 V, NVUSRO[PAD3V5V]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 24. Peripherals supply current (5 V and 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 25. I/O supply segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 26. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 27. Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) . . . . . . . . . . . . . 72
Table 28. Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1) . . . . . . . . . . . . . 72
Table 29. Input clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 30. PLLMRFM electrical specifications (VDDPLL = 1.08 V to 1.32 V, VSS = VSSPLL = 0 V, TA = TL
to TH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 31. 16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 32. ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 33. Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 34. Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 35. Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 36. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 37. RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 38. JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 39. Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 40. External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 41. DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 42. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 43. LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 44. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6/105 DocID18340 Rev 6

SPC56xP54x, SPC56xP60x List of figures
List of figures
Figure 1. SPC56xP54x/SPC56xP60x block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 2. LQFP176 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5. Power supplies constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 6. Independent ADC supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 7. Power supplies constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 8. Independent ADC supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 9. Voltage regulator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 10. Power-up typical sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 11. Power-down typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 12. Brown-out typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 13. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 14. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 15. ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 16. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 17. Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 18. Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 19. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 20. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 21. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 22. JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 23. JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 24. JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 25. Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 26. Nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 27. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 28. External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 29. DSPI classic SPI timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 30. DSPI classic SPI timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 31. DSPI classic SPI timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 32. DSPI classic SPI timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 33. DSPI modified transfer format timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 34. DSPI modified transfer format timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 35. DSPI modified transfer format timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 36. DSPI modified transfer format timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 37. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 38. LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 39. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 40. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Introduction SPC56xP54x, SPC56xP60x
1 Introduction
1.1 Document overview

This document provides electrical specifications, pin assignments, and package diagrams
for the SPC56xP54x/SPC56xP60x series of microcontroller units (MCUs). It also describes
the device features and highlights important electrical and physical characteristics. For
functional characteristics, refer to the device reference manual.
1.2 Description
This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest
achievement in integrated automotive application controllers. It belongs to an expanding
range of automotive-focused products designed to address chassis applications specifically
the airbag application.
This family is one of a series of next-generation integrated automotive microcontrollers
based on the Power Architecture technology.
The advanced and cost-efficient host processor core of this automotive controller family
complies with the Power Architecture embedded category. It operates up to 64 MHz and
offers high performance processing optimized for low power consumption. It capitalizes on
the available development infrastructure of current Power Architecture devices and is
supported with software drivers, operating systems and configuration code to assist with
users implementations.
1.3 Device comparison

Table 2 provides a summary of different members of the SPC56xP54x/SPC56xP60x family
and their features—relative to Full-featured version—to enable a comparison among the
family members and an understanding of the range of functionality offered within this family.
Table 2. SPC56xP54x/SPC56xP60x device comparison

Feature SPC560P54 SPC560P60 SPC56AP54 SPC56AP60
Code Flash memory (with ECC) 768 KB 1 MB 768 KB 1 MB

Data Flash / EE (with ECC) 64 KB
SRAM (with ECC) 64 KB 80 KB 64 KB 80 KB
Processor core 32-bit e200z0h 32-bit Dual e200z0h
Instruction set VLE
CPU performance 0-64 MHz
FMPLL (frequency-modulated phase-
1
locked loop) modules
INTC (interrupt controller) channels 148
PIT (periodic interrupt timer) 1 (includes four 32-bit timers)
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SPC56xP54x, SPC56xP60x Introduction
Table 2. SPC56xP54x/SPC56xP60x device comparison (continued)

Feature SPC560P54 SPC560P60 SPC56AP54 SPC56AP60
Enhanced DMA (direct memory

16
access) channels
FlexRay Yes (64 message buffer)
FlexCAN (controller area network) 3(1),(2)
Safety port Yes (via third FlexCAN module)
FCCU (fault collection and control unit) Yes(3)
CTU (cross triggering unit) Yes
eTimer channels 2×6
FlexPWM (pulse-width modulation)
No
channels
Analog-to-digital converters (ADC) One (10-bit, 27-channel)(4)
LINFlex modules 2 (1 × Master/Slave, 1 × Master only)(5)
DSPI (deserial serial peripheral
5(6)
interface) modules
CRC (cyclic redundancy check) units 2(7)
JTAG interface Yes
Nexus port controller (NPC) Yes (Level 2+)(8)
Digital power supply(9) 3.3 V or 5 V single supply with external transistor
Analog power supply 3.3 V or 5 V
Supply
Internal RC oscillator 16 MHz
External crystal oscillator 4–40 MHz
LQFP100
LQFP100
Packages LQFP144
LQFP144
LQFP176(10)
Standard ambient
Temperature –40 to 125 °C
temperature
1. Each FlexCAN module has 32 message buffers.
2. One FlexCAN module can act as a Safety Port with a bit rate as high as 7.5 Mbit/s.
3. Enhanced FCCU version.
4. Same amount of ADC channels as on SPC560P44/50 not considering the internally connected ones. 26 channels on
LQFP144 and 16 channels on LQFP100.
5. LinFlex_1 is Master Only.
6. Increased number of CS for DSPI_1.
7. Upgraded specification with addition of 8-bits polynomial (CRC-8 VDA CAN) support and 3rd context.
8. Improved debugging capability with data trace capability and increased Nexus throughput available on emulation package.
9. 3.3 V range and 5 V range correspond to different orderable parts.
10. Software development package only. Not available for production.
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SPC56xP54x/SPC56xP60x is present on the market in two different options enabling

different features: Full-featured, and Airbag configuration. Table 3 shows the main
differences between the two versions.
Table 3. SPC56xP54x/SPC56xP60x device configuration difference

Enhanced
Feature Full-featured Airbag
Full-featured
FlexCAN (controller area network) 3 2 2

CTU (cross triggering unit) Yes No
FlexRay Yes (64 message buffer) No
DSPI (deserial serial peripheral interface) modules 5 4
CRC (cyclic redundancy check) unit 2 1
1.4 Block diagram

Figure 1 shows a top-level block diagram of the SPC56xP54x/SPC56xP60x MCU. Table 4
summarizes the functions of the blocks.
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Figure 1. SPC56xP54x/SPC56xP60x block diagram
e200z0 Core e200z0 Core
PMU 32-bit Variable 32-bit Variable

general length Exception general length Exception
purpose encoded handler purpose encoded handler
registers instructions registers instructions INTC_1
INTC_0
Special Integer Special Integer
Instruction Instruction
purpose execution purpose execution
SWT_0 unit unit SWT_1
registers unit registers unit
STM_0 Branch Branch STM_1

Load/Store Load/Store
prediction JTAG prediction JTAG
unit unit
unit unit
ECSM_0 ECSM_1
Nexus
Nexus 2+ port Nexus 2+
SEMA4_0 controller SEMA4_1
DMAMUX_0
INSTR DATA INSTR DATA
DMA_0
M2 M3 M0 M1 M5 M6
Cross Bar Switch (XBAR, AMBA 2.0 v6 AHB) XBAR_0
Memory protection unit MPU_0 Memory protection unit MPU_1

S7 S2 S0 S1 S3 S6
NASPS_0 NASPS_1
P0 P1
PBRIDGE_0 PFLASHC_0
PBRIDGE_1
SRAMC_0
SRAMC_1
MC_PCU
48KB 1024KB 4x16KB 32KB

MC_ME
CRC_0
CRC_1
SSCM
SIUL
BAM
PIT
SRAM code flash data flash SRAM

with ECC with ECC with ECC with ECC
Peripheral Bus (IPS) Peripheral Bus (IPS)

SafetyPort_0
FlexCAN_0
FlexCAN_1
LINFlex_0
LINFlex_1
MC_CGM
MC_RGM
eTimer_0
eTimer_1
IRCOSC
FCCU_0
WakeUp
FlexRay
DSPI_0
DSPI_1
DSPI_2
DSPI_3
DSPI_4
CMU_0
CMU_1
ADC_0
FMPLL
CTU_0
XOSC
26
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Table 4. SPC56xP54x/SPC56xP60x series block summary

Block Function
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter

Block of read-only memory containing VLE code which is executed according to
Boot assist module (BAM)
the boot mode of the device
Clock generation module Provides logic and control required for the generation of system and peripheral
(MC_CGM) clocks
Controller area network
Supports the standard CAN communications protocol
(FlexCAN)
Enables synchronization of ADC conversions with a timer event from the
Cross triggering unit (CTU)
eMIOS or from the PIT
Supports simultaneous connections between two master ports and three slave
Crossbar switch (XBAR) ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus
width.
Is dedicated to the computation of CRC off-loading the CPU. Each context has
Cyclic redundancy checker
a separate CRC computation engine in order to allow the concurrent
(CRC) unit
computation of the CRC of multiple data streams.
Deserial serial peripheral Provides a synchronous serial interface for communication with external
interface (DSPI) devices
Enhanced direct memory access Performs complex data transfers with minimal intervention from a host
(eDMA) processor via “n” programmable channels
Enhanced timer (eTimer) Provides enhanced programmable up/down modulo counting
Provides a myriad of miscellaneous control functions for the device including
Error correction status module program-visible information about configuration and revision levels, a reset
(ECSM) status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
Provides an output clock used as input reference for FMPLL_0 or as reference
External oscillator (XOSC)
clock for specific modules depending on system needs
Fault collection and control unit
Provides functional safety to the device
(FCCU)
Flash memory Provides non-volatile storage for program code, constants and variables
FlexRay (FlexRay communication
Provides high-speed distributed control for advanced automotive applications
controller)
Frequency-modulated phase- Generates high-speed system clocks and supports programmable frequency
locked loop (FMPLL) modulation
Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests
Provides the means to test chip functionality and connectivity while remaining
JTAG controller
transparent to system logic when not in test mode
Manages a high number of LIN (Local Interconnect Network protocol)
LINFlex controller
messages efficiently with a minimum of CPU load
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control
Mode entry module (MC_ME)
unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
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Table 4. SPC56xP54x/SPC56xP60x series block summary (continued)

Block Function
Peripheral bridge (PBRIDGE) Is the interface between the system bus and on-chip peripherals
Periodic interrupt timer (PIT) Produces periodic interrupts and triggers
Reduces the overall power consumption by disconnecting parts of the device
Power control unit (MC_PCU) from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Reset generation module Centralizes reset sources and manages the device reset sequence of the
(MC_RGM) device
Provides the hardware support needed in multi-core systems for implementing
Semaphore unit (SEMA4) semaphores and provide a simple mechanism to achieve lock/unlock
operations via a single write access
Static random-access memory
Provides storage for program code, constants, and variables
(SRAM)
Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integration unit lite (SIUL) of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
Provides system configuration and status data (such as memory size and
System status and configuration
status, device mode and security status), device identification data, debug
module (SSCM)
status port enable and selection, and bus and peripheral abort enable/disable
Provides a set of output compare events to support AUTOSAR(1) and operating
System timer module (STM)
system tasks
System watchdog timer (SWT) Provides protection from runaway code
Supports up to 18 external sources that can generate interrupts or wakeup
Wakeup unit (WKPU) events, of which 1 can cause non-maskable interrupt requests or wakeup
events.
1. AUTOSAR: AUTomotive Open System ARchitecture (see autosar.org web site).
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1.5 Feature details
1.5.1 High performance e200z0h core processor

The e200z0h Power Architecture core provides the following features:
 High performance e200z0 core processor for managing peripherals and interrupts
 Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU
 Harvard architecture
 Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions
– Results in smaller code size footprint
– Minimizes impact on performance
 Branch processing acceleration using lookahead instruction buffer
 Load/store unit
– 1-cycle load latency
– Misaligned access support
– No load-to-use pipeline bubbles
 Thirty-two 32-bit general purpose registers (GPRs)
 Separate instruction bus and load/store bus Harvard architecture
 Hardware vectored interrupt support
 Reservation instructions for implementing read-modify-write constructs
 Long cycle time instructions, except for guarded loads, do not increase interrupt
latency
 Extensive system development support through Nexus debug port
 Non maskable Interrupt support
1.5.2 Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between six
master ports and six slave ports. The crossbar supports a 32-bit address bus width and a
32-bit data bus width.
The crossbar allows for two concurrent transactions to occur from any master port to any
slave port; but one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic selects the higher priority master and grant it ownership of the slave port. All
other masters requesting that slave port are stalled until the higher priority master
completes its transactions. Requesting masters are treated with equal priority and will be
granted access to a slave port in round-robin fashion, based upon the ID of the last master
to be granted access.
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The crossbar provides the following features:

 6 master ports:
– 2 e200z0 core complex Instruction ports
– 2 e200z0 core complex Load/Store Data ports
– eDMA
– FlexRay
 6 slave ports:
– 2 Flash memory (code flash and data flash)
– 2 SRAM (48 KB + 32 KB)
– 2 PBRIDGE
 32-bit internal address, 32-bit internal data paths
 Fixed Priority Arbitration based on Port Master
 Temporary dynamic priority elevation of masters
1.5.3 Enhanced direct memory access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels. This implementation is utilized to minimize the
overall block size.
The eDMA module provides the following features:
 16 channels support independent 8, 16 or 32-bit single value or block transfers
 Supports variable sized queues and circular queues
 Source and destination address registers are independently configured to post-
increment or remain constant
 Each transfer is initiated by a peripheral, CPU, or eDMA channel request
 Each eDMA channel can optionally send an interrupt request to the CPU on completion
of a single value or block transfer
 DMA transfers possible between system memories, DSPIs, ADC, eTimer and CTU
 Programmable DMA Channel Multiplexer for assignment of any DMA source to any
available DMA channel with up to 30 potential request sources
 eDMA abort operation through software
1.5.4 On-chip flash memory with ECC

The SPC56xP54x/SPC56xP60x provides up to 1024 KB of programmable, non-volatile,
flash memory. The non-volatile memory (NVM) can be used for instruction and/or data
storage. The flash memory module interfaces the system bus to a dedicated flash memory
array controller. It supports a 32-bit data bus width at the system bus port, and a 128-bit
read data interface to flash memory. The module contains a four-entry, 4x128-bit prefetch
buffers. Prefetch buffer hits allow no-wait responses. Normal flash memory array accesses
are registered and are forwarded to the system bus on the following cycle, incurring 2 wait
states.
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The flash memory module provides the following features:

 Up to 1024 KB flash memory
– 14 blocks (2×16 KB + 2×32 KB + 2×16 KB + 2×64 KB + 6×128 KB) code flash
– 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash
– Full Read While Write (RWW) capability between code and data flash
 Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch
buffers can be configured to prefetch code or data or both)
 Typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page
buffer miss at 64 MHz
 Hardware managed flash memory writes handled by 32-bit RISC Krypton engine
 Hardware and software configurable read and write access protections on a per-master
basis.
 Configurable access timing allowing use in a wide range of system frequencies.
 Multiple-mapping support and mapping-based block access timing (0–31 additional
cycles) allowing use for emulation of other memory types.
 Software programmable block program/erase restriction control.
 Erase of selected block(s)
 Read page size of 128 bits (4 words)
 64-bit ECC with single-bit correction, double-bit detection for data integrity
 Embedded hardware program and erase algorithm
 Erase suspend, program suspend and erase-suspended program
 Censorship protection scheme to prevent flash memory content visibility
 Hardware support for EEPROM emulation
1.5.5 On-chip SRAM with ECC

The SPC56xP54x/SPC56xP60x SRAM module provides a general-purpose memory of up
to 80 KB.
The SRAM module provides the following features:
 Supports read/write accesses mapped to the SRAM memory from any master
 Up to 80 KB general purpose RAM
– 2 blocks (48 KB + 32 KB)
 Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of
memory
 Typical SRAM access time: 0 wait state for reads and 32-bit writes; 1 wait state for 8-
and 16-bit writes if back to back with a read to same memory block
1.5.6 Interrupt controller (INTC)

The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt
requests, suitable for statically scheduled hard real-time systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from
the peripheral to when the processor is executing the interrupt service routine (ISR) has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR needs to be executed. It also provides an ample number
of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
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allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the resource can not preempt each other.
The INTC provides the following features:
 Unique 9-bit vector for each separate interrupt source
 8 software triggerable interrupt sources
 16 priority levels with fixed hardware arbitration within priority levels for each interrupt
source
 Ability to modify the ISR or task priority.
– Modifying the priority can be used to implement the Priority Ceiling Protocol for
accessing shared resources.
 2 external high priority interrupts directly accessing the main core and IOP critical
interrupt mechanism
The INTC module is replicated for each processor.
1.5.7 System clocks and clock generation

The following list summarizes the system clock and clock generation on the
SPC56xP54x/SPC56xP60x:
 Lock detect circuitry continuously monitors lock status
 Loss of clock (LOC) detection for PLL outputs
 Programmable output clock divider (1, 2, 4, 8)
 Programmable output clock divider (1, 2, 3 to 256)
 eTimer module running at the same frequency as the e200z0h core
 On-chip oscillator with automatic level control
 Internal 16 MHz RC oscillator for rapid start-up and safe mode
– Supports frequency trimming by user application
1.5.8 Frequency modulated phase-locked loop (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz
input clock. Further, the FMPLL supports programmable frequency modulation of the
system clock. The FMPLL multiplication factor, output clock divider ratio are all software
configurable.
The FMPLL has the following major features:
 Input clock frequency from 4 MHz to 40 MHz
 Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
 Reduced frequency divider (RFD) for reduced frequency operation without forcing the
PLL to relock
 Modulation enabled/disabled through software
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 Triangle wave modulation

 Programmable modulation depth (±0.25% to ±4% deviation from center frequency)
– Programmable modulation frequency dependent on reference frequency
 Self-clocked mode (SCM) operation
1.5.9 Main oscillator

The main oscillator provides these features:
 Input frequency range 4 MHz to 40 MHz
 Crystal input mode or Oscillator input mode
 PLL reference
1.5.10 Internal RC oscillator

This device has an RC ladder phase-shift oscillator. The architecture uses constant current
charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap
reference voltage.
The RC Oscillator provides these features:
 Nominal frequency 16 MHz
 ±6% variation over voltage and temperature after process trim
 Clock output of the RC oscillator serves as system clock source in case loss of lock or
loss of clock is detected by the PLL
 RC oscillator is used as the default system clock during startup
1.5.11 Periodic interrupt timer (PIT)

The PIT module implements these features:
 Up to four general purpose interrupt timers
 32-bit counter resolution
 Clocked by system clock frequency
 Each channel can be used as trigger for a DMA request
1.5.12 System timer module (STM)

The STM module implements these features:
 32-bit up counter with 8-bit prescaler
 Four 32-bit compare channels
 Independent interrupt source for each channel
 Counter can be stopped in debug mode
The STM module is replicated for each processor.
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1.5.13 Software watchdog timer (SWT)

The SWT has the following features:
 Fault tolerant output
 Safe internal RC oscillator as reference clock
 Windowed watchdog
 Program flow control monitor with 16-bit pseudorandom key generation
The SWT module is replicated for each processor.
1.5.14 Fault collection and control unit (FCCU)

The FCCU provides an independent fault reporting mechanism even if the CPU is exhibiting
unstable behaviors. The FCCU module has the following features:
 Redundant collection of hardware checker results
 Redundant collection of error information and latch of faults from critical modules on
the device
 Collection of self-test results
 Configurable and graded fault control
– Internal reactions (no internal reaction, IRQ)
– External reaction (failure is reported to the external/surrounding system via
configurable output pins)
1.5.15 System integration unit (SIUL)

The SPC56xP54x/SPC56xP60x SIUL controls MCU pad configuration, external interrupts,
general purpose I/O (GPIO) pin configuration, and internal peripheral multiplexing.
The pad configuration block controls the static electrical characteristics of I/O pins. The
GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.
The SIUL provides the following features:
 Centralized general purpose input output (GPIO) control of input/output pins and
analog input-only pads (package dependent)
 All GPIO pins can be independently configured to support pull-up, pull down, or no pull
 Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
 All peripheral pins (except ADC channels) can be alternatively configured as both
general purpose input or output pins
 ADC channels support alternative configuration as general purpose inputs
 Direct readback of the pin value is supported on all pins through the SIU
 Configurable digital input filter that can be applied to some general purpose input pins
for noise elimination
– Up to 4 internal functions can be multiplexed onto one pin
1.5.16 Boot and censorship

Different booting modes are available in the SPC56xP54x/SPC56xP60x:
 From internal flash memory
 Via a serial link
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The default booting scheme is the one which uses the internal flash memory (an internal
pull-down is used to select this mode). The alternate option allows the user to boot via
FlexCAN or LINFlex (using the boot assist module software).
A censorship scheme is provided to protect the contents of the flash memory and offer
increased security for the entire device.
A password mechanism is designed to grant the legitimate user access to the non-volatile
memory.
1.5.16.1 Boot assist module (BAM)

The BAM is a block of read-only one-time programmed memory and is identical for all
SPC56xP54x/SPC56xP60x devices that are based on the e200z0h core. The BAM program
is executed every time the device is powered on if the alternate boot mode has been
selected by the user.
The BAM provides the following features:
 Serial bootloading via FlexCAN or LINFlex.
 BAM can accept a password via the used serial communication channel to grant the
legitimate user access to the non-volatile memory.
1.5.17 Error correction status module (ECSM)

The ECSM on this device features the following:
 Platform configuration and revision
 ECC error reporting for flash memory and SRAM
 ECC error injection for SRAM
The ECSM module is replicated for each processor.
1.5.18 FlexCAN
The FlexCAN module is a communication controller implementing the CAN protocol
according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-
time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness
and required bandwidth. FlexCAN module contains 32 message buffers.
The FlexCAN module provides the following features:
 Full implementation of the CAN protocol specification, Version 2.0B
– Standard data and remote frames
– Extended data and remote frames
– 0 to 8 bytes data length
– Programmable bit rate as fast as 1 Mbit/s
 32 message buffers of 0 to 8 bytes data length
 Each message buffer configurable as Rx or Tx, all supporting standard and extended
messages
 Programmable loop-back mode supporting self-test operation
 3 programmable mask registers
20/105 DocID18340 Rev 6

 Programmable transmit-first scheme: lowest ID or lowest buffer number

 Time stamp based on 16-bit free-running timer
 Global network time, synchronized by a specific message
 Maskable interrupts
 Independent of the transmission medium (an external transceiver is assumed)
 High immunity to EMI
 Short latency time due to an arbitration scheme for high-priority messages
 Transmit features
– Supports configuration of multiple mailboxes to form message queues of scalable
depth
– Arbitration scheme according to message ID or message buffer number
– Internal arbitration to guarantee no inner or outer priority inversion
– Transmit abort procedure and notification
 Receive features
– Individual programmable filters for each mailbox
– 8 mailboxes configurable as a six-entry receive FIFO
– 8 programmable acceptance filters for receive FIFO
 Programmable clock source
– System clock
– Direct oscillator clock to avoid PLL jitter
1.5.19 Safety port (FlexCAN)

The SPC56xP54x/SPC56xP60x MCU has a second CAN controller synthesized to run at
high bit rates to be used as a safety port. The CAN module of the safety port provides the
following features:
 Identical to the FlexCAN module
 Bit rate as fast as 7.5 Mb at 60 MHz CPU clock using direct connection between CAN
modules (no physical transceiver required)
 32 Message buffers of 0 to 8 bytes data length
 Can be used as a third independent CAN module
1.5.20 FlexRay
The FlexRay module provides the following features:
 Full implementation of FlexRay Protocol Specification 2.1
 64 configurable message buffers can be handled
 Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
 Message buffers configurable as Tx, Rx or RxFIFO
 Message buffer size configurable
 Message filtering for all message buffers based on FrameID, cycle count and message
ID
 Programmable acceptance filters for RxFIFO message buffers
DocID18340 Rev 6 21/105

104
1.5.21 Serial communication interface module (LINFlex)

The LINFlex on the SPC56xP54x/SPC56xP60x features the following:
 Supports LIN Master mode (on both modules), LIN Slave mode (on one module) and
UART mode
 LIN state machine compliant to LIN1.3, 2.0, and 2.1 Specifications
 Handles LIN frame transmission and reception without CPU intervention
 LIN features
– Autonomous LIN frame handling
– Message buffer to store Identifier and up to 8 data bytes
– Supports message length as long as 64 bytes
– Detection and flagging of LIN errors: Sync field; Delimiter; ID parity; Bit; Framing;
Checksum and Time-out errors
– Classic or extended checksum calculation
– Configurable Break duration as long as 36-bit times
– Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional)
– Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection
– Interrupt-driven operation with 16 interrupt sources
 LIN slave mode features
– Autonomous LIN header handling
– Autonomous LIN response handling
 UART mode
– Full-duplex operation
– Standard non return-to-zero (NRZ) mark/space format
– Data buffers with 4-byte receive, 4-byte transmit
– Configurable word length (8-bit or 9-bit words)
– Error detection and flagging
– Parity, Noise and Framing errors
– Interrupt-driven operation with four interrupt sources
– Separate transmitter and receiver CPU interrupt sources
– 16-bit programmable baud-rate modulus counter and 16-bit fractional
– 2 receiver wake-up methods
1.5.22 Deserial serial peripheral interface (DSPI)

The deserial serial peripheral interface (DSPI) module provides a synchronous serial
interface for communication between the SPC56xP54x/SPC56xP60x MCU and external
devices.
22/105 DocID18340 Rev 6

The DSPI modules provide these features:

 Full duplex, synchronous transfers
 Master or slave operation
 Programmable master bit rates
 Programmable clock polarity and phase
 End-of-transmission interrupt flag
 Programmable transfer baud rate
 Programmable data frames from 4 to 16 bits
 Up to 28 chip select lines available
– 8 each on DSPI_0 and DSPI_1
– 4 each on DSPI_2, DSPI_3, and DSPI_4
 8 clock and transfer attributes registers
 Chip select strobe available as alternate function on one of the chip select pins for
deglitching
 FIFOs for buffering up to 5 transfers on the transmit and receive side
 Queueing operation possible through use of the eDMA
 General purpose I/O functionality on pins when not used for SPI
1.5.23 eTimer
Two eTimer modules are provided, each with six 16-bit general purpose up/down
timer/counter per module. The following features are implemented:
 Individual channel capability
– Input capture trigger
– Output compare
– Double buffer (to capture rising edge and falling edge)
– Separate prescaler for each counter
– Selectable clock source
– 0 % to 100% pulse measurement
– Rotation direction flag (Quad decoder mode)
 Maximum count rate
– Equals peripheral clock/2 — for external event counting
– Equals peripheral clock — for internal clock counting
 Cascadeable counters
 Programmable count modulo
 Quadrature decode capabilities
 Counters can share available input pins
 Count once or repeatedly
 Preloadable counters
 Pins available as GPIO when timer functionality not in use
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104
1.5.24 Analog-to-digital converter (ADC)

The ADC module provides the following features:
Analog part:
 1 on-chip analog-to-digital converter
 10-bit AD resolution
 1 sample and hold unit per ADC
 Conversion time, including sampling time, less than 1 s (at full precision)
 Typical sampling time is 150 ns min. (at full precision)
 Differential non-linearity error (DNL) ±1 LSB
 Integral non-linearity error (INL) ±1.5 LSB
 Total unadjusted error (TUE) <3 LSB
 Single-ended input signal range from 0 to 3.3 V / 5.0 V
 ADC and its reference can be supplied with a voltage independent from VDDIO
 ADC supply can be equal or higher than VDDIO
 ADC supply and the ADC reference are not independent from each other (they are
internally bonded to the same pad)
 Sample times of 2 (default), 8, 64, or 128 ADC clock cycles
Digital part:
 27 input channels (26 + 1 internally connected)
 4 analog watchdogs to compare ADC results against predefined levels (low, high,
range) before results are stored
 2 operating modes: Normal mode and CTU control mode
 Normal mode features
– Register-based interface with the CPU: control register, status register, 1 result
register per channel
– ADC state machine managing 3 request flows: regular command, hardware
injected command, and software injected command
– Selectable priority between software and hardware injected commands
– DMA compatible interface
 CTU control mode features
– Triggered mode only
– 4 independent result queues (2 × 16 entries, 2 × 4 entries)
– Result alignment circuitry (left justified; right justified)
– 32-bit read mode allows to have channel ID on one of the 16-bit part
– DMA compatible interfaces
1.5.25 Cross triggering unit (CTU)

The Cross Triggering Unit (CTU) allows automatic generation of ADC conversion requests
on user selected conditions with minimized CPU load for dynamic configuration.
24/105 DocID18340 Rev 6

It implements the following features:

 Double buffered trigger generation unit with up to eight independent triggers generated
from external triggers
 Trigger generation unit configurable in sequential mode or in triggered mode
 Each Trigger can be appropriately delayed to compensate the delay of external low
pass filter
 Double buffered global trigger unit allowing eTimer synchronization and/or ADC
command generation
 Double buffered ADC command list pointers to minimize ADC-trigger unit update
 Double buffered ADC conversion command list with up to 24 ADC commands
 Each trigger has the capability to generate consecutive commands
 ADC conversion command allows to control ADC channel from each ADC, single or
synchronous sampling, independent result queue selection
1.5.26 Cyclic redundancy check (CRC)

 3 contexts for the concurrent CRC computation
 Separate CRC engine for each context
 Zero-wait states during the CRC computation (pipeline scheme)
 3 hard-wired polynomials (CRC-8 VDA CAN, CRC-32 Ethernet and CRC-16-CCITT)
 Support for byte/half-word/word width of the input data stream
 Support for expected and actual CRC comparison
1.5.27 Nexus development interface (NDI)

The NDI block provides real-time development support capabilities for the
SPC56xP54x/SPC56xP60x Power Architecture based MCU in compliance with the IEEE-
ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring
external address and data pins for internal visibility. The NDI block is an integration of
several individual Nexus blocks that are selected to provide the development support
interface for this device. The NDI block interfaces to the host processor and internal buses
to provide development support as per the IEEE-ISTO 5001-2003 Class 2+ standard. The
development support provided includes access to the MCU’s internal memory map and
access to the processor’s internal registers during run time.
The Nexus Interface provides the following features:
 Configured via the IEEE 1149.1
 All Nexus port pins operate at VDDIO (no dedicated power supply)
 Nexus 2+ features supported
– Static debug
– Watchpoint messaging
– Ownership trace messaging
– Program trace messaging
– Real time read/write of any internally memory mapped resources through JTAG
pins
– Overrun control, which selects whether to stall before Nexus overruns or keep
executing and allow overwrite of information
DocID18340 Rev 6 25/105

104
– Watchpoint triggering, watchpoint triggers program tracing

– DDR
 Auxiliary Output Port
– 4 MDO (Message Data Out) pins
– MCKO (Message Clock Out) pin
– 2 MSEO (Message Start/End Out) pins
– EVTO (Event Out) pin
 Auxiliary Input Port
– EVTI (Event In) pin(a)
1.5.28 IEEE 1149.1 (JTAG) controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and
connectivity while remaining transparent to system logic when not in test mode. All data
input to and output from the JTAGC block is communicated in serial format. The JTAGC
block is compliant with the IEEE standard.
The JTAG controller provides the following features:
 IEEE Test Access Port (TAP) interface with four pins (TDI, TMS, TCK, TDO)
 Selectable modes of operation include JTAGC/debug or normal system operation.
 A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined
instructions:
– BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD
 A 5-bit instruction register that supports the additional following public instructions:
– ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_CORE0,
ACCESS_AUX_TAP_CORE1, ACCESS_AUX_TAP_NASPS_0,
ACCESS_AUX_TAP_NASPS_1
 Three test data registers: a bypass register, a boundary scan register, and a device
identification register.
 A TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry.
1.5.29 On-chip voltage regulator (VREG)

The on-chip voltage regulator module provides the following features:
 Uses external NPN transistor
 Regulates external 3.3 V to 5.0 V down to 1.2 V for the core logic
 Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V
a. At least one TCK clock is necessary for the EVTI signal to be recognized by the MCU.
26/105 DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Package pinouts and signal descriptions
2 Package pinouts and signal descriptions
2.1 Package pinouts

The LQFP pinouts are shown in the following figures.
Figure 2. LQFP176 pinout (top view)(b)
VDD_LV_COR2
VSS_LV_COR2
VDD_HV_IO4
VDD_HV_IO3
VSS_HV_IO4
VSS_HV_IO3
MDO10
MDO11
PC[15]
PC[10]
PE[15]
PE[14]
PE[13]
PF[14]
PF[15]
PF[13]
PA[15]
PA[14]
PA[13]
PA[12]
PA[10]
PA[11]
PG[1]
PC[6]
PD[2]
PC[8]
PD[4]
PD[3]
PD[0]
PC[9]
PB[6]
PB[3]
PB[2]
PB[1]
PB[0]
PF[3]
PF[2]
PF[1]
PF[0]
PA[9]
RDY
NC
NC
NC
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
NMI 1 132 PA[4]
PA[6] 2 131 VPP_TEST
PD[1] 3 130 PF[12]
PF[4] 4 129 PD[14]
VDD_HV_IO5 5 128 PG[3]
VSS_HV_IO5 6 127 PC[14]
MDO4 7 126 PG[2]
MDO5 8 125 PC[13]
MDO6 9 124 PG[4]
NC 10 123 PD[12]
NC 11 122 PG[6]
NC 12 121 VDD_HV_FL
PF[5] 13 120 VSS_HV_FL
VDD_HV_IO0 14 119 PD[13]
VSS_HV_IO0 15 118 VSS_LV_COR1
PF[6] 16 117 VDD_LV_COR1
MDO0 17 116 PA[3]
PA[7] 18 115 VDD_HV_IO2
PC[4] 19 114 VSS_HV_IO2
PA[8] 20 113 NC
PC[5]
PA[5]
21
22 LQFP176 112
111
MDO9
MDO8
PC[7] 23 110 MDO7
PC[3] 24 109 VSS_HV_IO6
VSS_LV_COR0 25 108 VDD_HV_IO6
VDD_LV_COR0 26 107 TDO
PF[7] 27 106 TCK
PF[8] 28 105 TMS
VDD_HV_IO1 29 104 TDI
VSS_HV_IO1 30 103 PG[5]
PF[9] 31 102 PA[2]
PF[10] 32 101 PG[7]
PF[11] 33 100 PC[12]
PD[9] 34 99 NC
VDD_HV_OSC 35 98 NC
VSS_HV_OSC 36 97 PG[8]
XTAL 37 96 PC[11]
EXTAL 38 95 PG[9]
RESET 39 94 PD[11]
PD[8] 40 93 PG[10]
PD[5] 41 92 PD[10]
PD[6] 42 91 PG[11]
VSS_LV_COR3 43 90 PA[1]
VDD_LV_COR3 44 89 PA[0]
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VDD_HV_REG
NC
NC
NC
NC
NC
NC
NC
NC
NC
PD[7]
PG[0]
PE[1]
PE[3]
PC[1]
PE[4]
PB[7]
PE[5]
PC[2]
PE[6]
PB[8]
PE[7]
PE[2]
VREG_BYPASS
PB[9]
PB[10]
PB[11]
PB[12]
VDD_HV_AD
VSS_HV_AD
PD[15]
PE[8]
PB[13]
PE[9]
PB[15]
PE[10]
PB[14]
PE[11]
PC[0]
PE[12]
PE[0]
BCTRL
VDD_LV_REGCOR
VSS_LV_REGCOR
b. Software development package only. Not available for production.
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104
Package pinouts and signal descriptions SPC56xP54x, SPC56xP60x
Figure 3. LQFP144 pinout (top view)(c)
VDD_LV_COR2
VSS_LV_COR2
VDD_HV_IO3
VSS_HV_IO3
PC[15]
PC[10]
PE[15]
PE[14]
PE[13]
PF[14]
PF[15]
PF[13]
PA[15]
PA[14]
PA[13]
PA[12]
PA[10]
PA[11]
PG[1]
PC[6]
PD[2]
PC[8]
PD[4]
PD[3]
PD[0]
PC[9]
PB[6]
PB[3]
PB[2]
PB[1]
PB[0]
PF[3]
PF[2]
PF[1]
PF[0]
PA[9]
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
109
119
118
117
116
115
114
113
112
110
111
NMI 1 108 PA[4]
PA[6] 2 107 VPP_TEST
PD[1] 3 106 PF[12]
PF[4] 4 105 PD[14]
PF[5] 5 104 PG[3]
VDD_HV_IO0 6 103 PC[14]
VSS_HV_IO0 7 102 PG[2]
PF[6] 8 101 PC[13]
MDO 9 100 PG[4]
PA[7] 10 99 PD[12]
PC[4] 11 98 PG[6]
PA[8] 12 97 VDD_HV_FL
PC[5] 13 96 VSS_HV_FL
PA[5] 14 95 PD[13]
PC[7] 15 94 VSS_LV_COR1
PC[3] 16 93 VDD_LV_COR1
VDD_LV_COR0 18 91 VDD_HV_IO2
PF[7] 19
20
LQFP144 90
89
VSS_HV_IO2
TDO
PF[8]
VDD_HV_IO1 21 88 TCK
VSS_HV_IO1 22 87 TMS
PF[9] 23 86 TDI
PF[10] 24 85 PG[5]
PF[11] 25 84 PA[2]
PD[9] 26 83 PG[7]
VDD_HV_OSC 27 82 PC[12]
VSS_HV_OSC 28 81 PG[8]
XTAL 29 80 PC[11]
EXTAL 30 79 PG[9]
RESET 31 78 PD[11]
PD[8] 32 77 PG[10]
PD[5] 33 76 PD[10]
PD[6] 34 75 PG[11]
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
BCTRL
PD[7]
PG[0]
PE[1]
PE[3]
PC[1]
PE[4]
PB[7]
PE[5]
PC[2]
PE[6]
PB[8]
PE[7]
PE[2]
NC
VREG_BYPASS
PB[9]
PB[10]
PB[11]
PB[12]
VDD_HV_AD
VSS_HV_AD
PD[15]
PE[8]
PB[13]
PE[9]
PB[15]
PE[10]
PB[14]
PE[11]
PC[0]
PE[12]
PE[0]
VDD_LV_REGCOR
VSS_LV_REGCOR
VDD_HV_REG
c. Availability of port pin alternate functions depends on product selection.
28/105 DocID18340 Rev 6

Figure 4. LQFP100 pinout (top view)(d)
VDD_LV_COR2
VSS_LV_COR2
VDD_HV_IO3
VSS_HV_IO3
PC[15]
PC[10]
PA[15]
PA[14]
PA[13]
PA[12]
PA[10]
PA[11]
PC[6]
PD[2]
PC[8]
PD[4]
PD[3]
PD[0]
PC[9]
PB[6]
PB[3]
PB[2]
PB[1]
PB[0]
PA[9]
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NMI 1 75 PA[4]
PA[6] 2 74 VPP TEST
PD[1] 3 73 PD[14]
PA[7] 4 72 PC[14]
PC[4] 5 71 PC[13]
PA[8] 6 70 PD[12]
PC[5] 7 69 VDD_HV_FL
PA[5] 8 68 VSS_HV_FL
PC[7] 9 67 PD[13]
PC[3] 10 66 VSS_LV_COR1
VSS_LV_COR0 11 65 VDD_LV_COR1
63 VDD_HV_IO2
VDD_HV_IO1
VSS_HV_IO1
13
14
LQFP100 62 VSS_HV_IO2
PD[9] 15 61 TDO
VDD_HV_OSC 16 60 TCK
VSS_HV_OSC 17 59 TMS
XTAL 18 58 TDI
EXTAL 19 57 PA[2]
RESET 20 56 PC[12]
PD[8] 21 55 PC[11]
PD[5] 22 54 PD[11]
PD[6] 23 53 PD[10]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
VREG_BYPASS
PD[7]
PC[1]
PC[2]
VDD_HV_AD
VSS_HV_AD
PC[0]
BCTRL
VDD_LV_REGCOR
VSS_LV_REGCOR
VDD_HV_REG
PE[1]
PB[7]
PB[8]
PE[2]
PB[9]
PB[10]
PB[11]
PB[12]
PD[15]
PB[13]
PB[15]
PB[14]
PE[0]
2.2 Pin descriptions

The following sections provide signal descriptions and related information about the
functionality and configuration of the SPC56xP54x/SPC56xP60x devices.
2.2.1 Power supply and reference voltage pins

Table 5 lists the power supply and reference voltage for the SPC56xP54x/SPC56xP60x
devices.
Table 5. Supply pins

Supply Pin
LQFP LQFP LQFP

Symbol Description
100 144 176(1)
VREG control and power supply pins

BCTRL Voltage regulator external NPN Ballast base control pin 47 69 81
d. Availability of port pin alternate functions depends on product selection.
DocID18340 Rev 6 29/105

104
Table 5. Supply pins (continued)

Supply Pin
LQFP LQFP LQFP

Symbol Description
100 144 176(1)
VDD_HV_REG (3.3 V or
Voltage regulator supply voltage 50 72 86
5.0 V)
1.2 V decoupling(2) pins for core logic supply and voltage
VDD_LV_REGCOR regulator feedback. Decoupling capacitor must be connected 48 70 82
between this pins and VSS_LV_REGCOR.
1.2 V decoupling(2) pins for core logic GND and voltage regulator
VSS_LV_REGCOR feedback. Decoupling capacitor must be connected between this 49 71 85
pins and VDD_LV_REGCOR.
ADC0 reference and supply voltage
VDD_HV_AD ADC supply and high reference voltage 39 56 64
VSS_HV_AD ADC ground and low reference voltage 40 57 65
Power supply pins (3.3 V or 5.0 V)
VDD_HV_IO0 Input/Output supply voltage — 6 14
VSS_HV_IO0 Input/Output ground — 7 15
VDD_HV_IO1 Input/Output supply voltage 13 21 29
VSS_HV_IO1 Input/Output ground 14 22 30
VDD_HV_IO4 Input/Output supply voltage — — 169
VSS_HV_IO4 Input/Output ground — — 170
VDD_HV_FL Code and data flash supply voltage 69 97 121
VSS_HV_FL Code and data flash supply ground 68 96 120
VDD_HV_OSC Crystal oscillator amplifier supply voltage 16 27 35
VSS_HV_OSC Crystal oscillator amplifier ground 17 28 36
Power supply pins (1.2 V)
1.2 V Decoupling pins for core logic supply. Decoupling capacitor
VDD_LV_COR0 must be connected between these pins and the nearest 12 18 26
VSS_LV_COR0 pin.
30/105 DocID18340 Rev 6

Table 5. Supply pins (continued)

Supply Pin
LQFP LQFP LQFP

Symbol Description
100 144 176(1)
1.2 V Decoupling pins for core logic GND. Decoupling capacitor

VSS_LV_COR0 must be connected between these pins and the nearest 11 17 25
VDD_LV_COR0 pin.
VSS_LV_COR1 pin.
VDD_LV_COR1 pin.
VSS_LV_COR2 pin.
VDD_LV_COR 2 pin.
VSS_LV_COR3 pin.
VDD_LV_COR 3 pin.
1. LQFP176 available only as development package.
2. See datasheet Voltage Regulator Electrical Characteristics section for more details.
2.2.2 System pins

Table 6 and Table 7 contain information on pin functions for the SPC56xP54x/SPC56xP60x
devices. The pins listed in Table 6 are single-function pins. The pins shown in Table 7 are
multi-function pins, programmable via their respective Pad Configuration Register (PCR)
values.
Table 6. System pins

Pad Speed(1) Pin
Symbol Description Direction
LQFP LQFP LQFP
SRC=0 SRC=1
100 144 176(2)
Dedicated pins
Output
MDO0 Nexus Message Data Output—line 0 Fast — 9 17
Only
Output
MDO4 Nexus Message Data Output—line 4 Fast — — 7
Only
DocID18340 Rev 6 31/105

104
Table 6. System pins (continued)

Pad Speed(1) Pin
Symbol Description Direction
LQFP LQFP LQFP
SRC=0 SRC=1
100 144 176(2)
Output
Only
Output
Only
Output
Only
Output
Only
Output
Only
Output
Only
Output
Only
Output
RDY Nexus ready output — — — — 172
Only
NMI Non-Maskable Interrupt Input Only — — 1 1 1
Analog output of the oscillator amplifier
XTAL circuit. Needs to be grounded if oscillator is — — — 18 29 37
used in bypass mode.
Analog input of the oscillator amplifier
circuit, when the oscillator is not in bypass
EXTAL mode.  — — — 19 30 38
Analog input for the clock generator when
the oscillator is in bypass mode.
TMS(3) JTAG state machine control Input Only — — 59 87 105
TCK(3) JTAG clock Input Only — — 60 88 106
(3)
TDI JTAG data input Input Only — — 58 86 104
Output
TDO(3) JTAG data output — — 61 89 107
Only
Reset pin
Bidirectional reset with Schmitt trigger
Bidirection
RESET(4) characteristics and Medium — 20 31 39
al
noise filter
Test pin
Pin for testing purpose only. To be tied to
VPP TEST — — — 74 107 131
ground in normal operating mode.
Pin for testing purpose only. To be tied to
VREG_BYPASS — — — 34 51 59
ground in normal operating mode.
1. SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.
32/105 DocID18340 Rev 6


3. In this pin there is an internal pull; refer to JTAGC chapter in the device reference manual for pull direction.
4. Its configuration can be set up by the PCR[108] register inside the SIU module. See SIUL chapter in the device reference
manual.
2.2.3 Pin muxing

Table 7 defines the pin list and muxing for the SPC56xP54x/SPC56xP60x devices relative
to Full-featured version.
Each row of Table 7 shows all the possible ways of configuring each pin, via “alternate
functions”. The default function assigned to each pin after reset is the ALT0 function.
Pins marked as external interrupt capable can also be used to resume from STOP and
HALT mode.
SPC56xP54x/SPC56xP60x devices provide four main I/O pad types depending on the
associated functions:
 Slow pads are the most common, providing a compromise between transition time and
low electromagnetic emission.
 Medium pads provide fast enough transition for serial communication channels with
controlled current to reduce electromagnetic emission.
 Fast pads provide maximum speed. They are used for improved NEXUS debugging
capability.
 Symmetric pads are designed to meet FlexRay requirements.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance.
Table 7. Pin muxing(1)

Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
function(2), Functions (4) direction
pin No. (3) (5) LQFP LQFP LQFP
SRC = 0 SRC = 1
100 144 176(7)
Port A
ALT0 GPIO[0] SIUL I/O
ALT1 ETC[0] eTimer_0 I/O
A[0] PCR[0] ALT2 SCK_2 DSPI_2 I/O Slow Medium 51 73 89
ALT3 F[0] FCCU O
— EIRQ[0] SIUL I
A[1] PCR[1] ALT2 SOUT_2 DSPI_2 O Slow Medium 52 74 90
ALT3 F[1] FCCU O
— EIRQ[1] SIUL I
DocID18340 Rev 6 33/105

104
Table 7. Pin muxing(1) (continued)

Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)

ALT2 CS3_4 DSPI_4 O
A[2]
(8) PCR[2] ALT3 — — — Slow Medium 57 84 102
— SIN_2 DSPI_2 I
— ABS[0] MC_RGM I
— EIRQ[2] SIUL I
A[3] ALT2 CS0_2 DSPI_2 I/O
(8) PCR[3] Slow Medium 64 92 116
ALT3 — — —
— ABS[1] MC_RGM I
— EIRQ[3] SIUL I
A[4] ALT2 CS1_2 DSPI_2 O
(8) PCR[4] Slow Medium 75 108 132
— FAB MC_RGM I
— EIRQ[4] SIUL I
ALT1 CS0_1 DSPI_1 I/O
A[5] PCR[5] ALT2 ETC[5] eTimer_1 I/O Slow Medium 8 14 22
ALT3 CS7_0 DSPI_0 O
— EIRQ[5] SIUL I
ALT1 SCK_1 DSPI_1 I/O
A[6] PCR[6] ALT2 CS2_4 DSPI_4 I/O Slow Medium 2 2 2
ALT3 — — —
— EIRQ[6] SIUL I
ALT1 SOUT_1 DSPI_1 O
A[7] PCR[7] ALT2 CS1_4 DSPI_4 I/O Slow Medium 4 10 18
ALT3 — — —
— EIRQ[7] SIUL I
ALT1 — — —
A[8] PCR[8] Slow Medium 6 12 20
ALT3 — — —
— SIN_1 DSPI_1 I
— EIRQ[8] SIUL I
34/105 DocID18340 Rev 6


Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)

ALT1 CS1_2 DSPI_2 O
A[9] PCR[9] ALT2 — — — Slow Medium 94 134 158
ALT3 — — —
— SIN_4 DSPI_4 I
ALT3 — — —
— EIRQ[9] SIUL I
ALT3 — — —
— EIRQ[10] SIUL I
ALT3 — — —
— EIRQ[11] SIUL I
ALT1 CS4_1 DSPI_1 O
ALT2 — — —
A[13] PCR[13] Slow Medium 95 136 160
ALT3 — — —
— SIN_2 DSPI_2 I
— EIRQ[12] SIUL I
ALT1 TXD Safety Port O
A[14] PCR[14] ALT2 ETC[4] eTimer_1 I/O Slow Medium 99 143 175
ALT3 CS5_1 DSPI_1 O
— EIRQ[13] SIUL I
ALT1 CS6_1 DSPI_1 O
A[15] PCR[15] Slow Medium 100 144 176
ALT3 — — —
— RXD Safety Port I
— EIRQ[14] SIUL I
DocID18340 Rev 6 35/105

104

Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)
Port B
ALT1 TXD FlexCAN_0 O
B[0] PCR[16] ALT2 ETC[2] eTimer_1 I/O Slow Medium 76 109 133
ALT3 DEBUG[0] SSCM —
— EIRQ[15] SIUL I
ALT1 CS7_1 DSPI_1 O
B[1] PCR[17] Slow Medium 77 110 134
— RXD FlexCAN_0 I
— EIRQ[16] SIUL I
ALT1 TXD LINFlex_0 O
B[2] PCR[18] ALT2 SOUT_4 DSPI_4 I/O Slow Medium 79 114 138
— EIRQ[17] SIUL I
ALT1 — — —
B[3] PCR[19] ALT2 SCK_4 DSPI_4 I/O Slow Medium 80 116 140
— RXD LINFlex_0 I
ALT1 clk_out MC_CGL O
ALT2 CS2_2 DSPI_2 O
B[6] PCR[22] Slow Medium 96 138 162
ALT3 clk_out_div2 MC_CGL O
56
— EIRQ[18] SIUL I
ALT0 GPIO[23] SIUL
ALT1 — —
ALT2 — —
B[7] PCR[23] Input Only — — 29 43 51
ALT3 — —
— AN[0] ADC_0
— RXD LINFlex_0
ALT0 GPIO[24] SIUL
ALT1 — —
ALT2 — —
B[8] PCR[24] Input Only — — 31 47 55
ALT3 — —
— AN[1] ADC_0
— ETC[5] eTimer_0
36/105 DocID18340 Rev 6


Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)
ALT0 GPIO[25] SIUL

ALT1 — —
B[9] PCR[25] ALT2 — — Input Only — — 35 52 60
ALT3 — —
— AN[11] ADC_0
ALT0 GPIO[26] SIUL
ALT1 — —
ALT3 — —
— AN[12] ADC_0
ALT0 GPIO[27] SIUL
ALT1 — —
ALT3 — —
— AN[13] ADC_0
ALT0 GPIO[28] SIUL
ALT1 — —
ALT3 — —
— AN[14] ADC_0
ALT0 GPIO[29] SIUL
ALT1 — —
ALT2 — —
B[13] PCR[29] Input Only — — 42 60 68
ALT3 — —
— AN[16] ADC_0
— RXD LINFlex_1
ALT0 GPIO[30] SIUL
ALT1 — —
ALT2 — —
— AN[17] ADC_0
— ETC[4] eTimer_0
— EIRQ[19] SIUL
ALT0 GPIO[31] SIUL
ALT1 — —
ALT2 — —
B[15] PCR[31] Input Only — — 43 62 70
ALT3 — —
— AN[18] ADC_0
— EIRQ[20] SIUL
DocID18340 Rev 6 37/105

104

Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)
Port C
ALT0 GPIO[32] SIUL
ALT1 — —
C[0] PCR[32] ALT2 — — Input Only — — 45 66 78
ALT3 — —
— AN[19] ADC_0
ALT0 GPIO[33] SIUL
ALT1 — —
ALT3 — —
— AN[2] ADC_0
ALT0 GPIO[34] SIUL
ALT1 — —
ALT3 — —
— AN[3] ADC_0
ALT1 CS1_0 DSPI_0 O
C[3] PCR[35] ALT2 ETC[4] eTimer_1 I/O Slow Medium 10 16 24
— EIRQ[21] SIUL I
C[4] PCR[36] ALT2 — — — Slow Medium 5 11 19
— EIRQ[22] SIUL I
C[5] PCR[37] ALT2 SCK_4 DSPI_4 I/O Slow Medium 7 13 21
— EIRQ[23] SIUL I
C[6] PCR[38] ALT2 — — — Slow Medium 98 142 174
— EIRQ[24] SIUL I
38/105 DocID18340 Rev 6


Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)

ALT1 — — —
ALT2 — — —
C[7] PCR[39] Slow Medium 9 15 23
— SIN_0 DSPI_0 I
— SIN_4 DSPI_4 I
ALT1 CS1_1 DSPI_1 O
ALT2 CS1_4 DSPI_4 O
ALT3 CS6_0 DSPI_0 O
ALT1 CS3_2 DSPI_2 O
ALT3 — — —
ALT1 CS2_2 DSPI_2 O
C[10] PCR[42] Slow Medium 78 111 135
ALT2 CS2_4 DSPI_4 O
ALT3 — — —
ALT2 CS2_2 DSPI_2 O
ALT2 CS3_2 DSPI_2 O
ALT3 CS1_3 DSPI_3 O
ALT2 — — —
C[13] PCR[45] Slow Medium 71 101 125
ALT3 — — —
— EXT_IN CTU_0 I
— RXD FlexCAN_1 I
C[14] PCR[46] Slow Medium 72 103 127
ALT2 EXT_TGR CTU_0 O
DocID18340 Rev 6 39/105

104

Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)

ALT1 CA_TR_EN FlexRay_0 O
C[15] PCR[47] ALT2 ETC[0] eTimer_1 I/O Slow Symmetric 85 124 148
ALT3 — — —
— EXT_IN CTU_0 I
Port D
ALT1 CA_TX FlexRay_0 O
D[0] PCR[48] Slow Symmetric 86 125 149
ALT3 — — —
ALT1 CS4_1 DSPI_1 O
D[1] PCR[49] ALT2 ETC[2] eTimer_1 I/O Slow Medium 3 3 3
ALT3 EXT_TRG CTU_0 O
— CA_RX FlexRay_0 I
ALT1 CS5_1 DSPI_1 O
D[2] PCR[50] ALT2 ETC[3] eTimer_1 I/O Slow Medium 97 140 168
ALT3 — — —
— CB_RX FlexRay_0 I
ALT1 CB_TX FlexRay_0 O
ALT3 — — —
ALT1 CB_TR_EN FlexRay_0 O
ALT3 — — —
ALT1 CS3_0 DSPI_0 O
D[5] PCR[53] Slow Medium 22 33 41
ALT2 — — —
ALT1 CS2_0 DSPI_0 O
40/105 DocID18340 Rev 6


Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)

ALT1 CS3_1 DSPI_1 O
D[7] PCR[55] ALT2 — — — Slow Medium 26 37 45
ALT3 CS4_0 DSPI_0 O
— SIN_3 DSPI_3 I
ALT1 CS2_1 DSPI_1 O
ALT2 RDY nexus_0 O
ALT3 CS5_0 DSPI_0 O
ALT1 — — —
ALT3 CS6_1 DSPI_1 O
ALT1 — — —
ALT3 — — —
ALT1 — — —
ALT2 CS1_3 DSPI_3 O
ALT1 — — —
D[12] PCR[60] ALT2 — — — Slow Medium 70 99 123
ALT3 CS7_1 DSPI_1 O
— RXD LINFlex_1 I
ALT1 — — —
ALT2 CS2_3 DSPI_3 O
ALT1 — — —
D[14] PCR[62] ALT2 CS3_3 DSPI_3 O Slow Medium 73 105 129
ALT3 — — —
— SIN_3 DSPI_3 I
ALT0 GPIO[63] SIUL
ALT1 — —
D[15] PCR[63] ALT2 — — Input Only — — 41 58 66
ALT3 — —
— AN[20] ADC_0
DocID18340 Rev 6 41/105

104

Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)
Port E
ALT0 GPIO[64] SIUL
ALT1 — —
E[0] PCR[64] ALT2 — — Input Only — — 46 68 80
ALT3 — —
— AN[21] ADC_0
ALT0 GPIO[65] SIUL
ALT1 — —
ALT3 — —
— AN[4] ADC_0
ALT0 GPIO[66] SIUL
ALT1 — —
ALT3 — —
— AN[5] ADC_0
ALT0 GPIO[67] SIUL
ALT1 — —
E[3] PCR[67] ALT2 — — Input Only — — — 40 48
ALT3 — —
— AN[6] ADC_0
ALT0 GPIO[68] SIUL
ALT1 — —
ALT3 — —
— AN[7] ADC_0
ALT0 GPIO[69] SIUL
ALT1 — —
ALT3 — —
— AN[8] ADC_0
ALT0 GPIO[70] SIUL
ALT1 — —
ALT3 — —
— AN[9] ADC_0
42/105 DocID18340 Rev 6


Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)
ALT0 GPIO[71] SIUL

ALT1 — —
ALT3 — —
— AN[10] ADC_0
ALT0 GPIO[72] SIUL
ALT1 — —
ALT3 — —
— AN[22] ADC_0
ALT0 GPIO[73] SIUL
ALT1 — —
ALT3 — —
— AN[23] ADC_0
ALT0 GPIO[74] SIUL
ALT1 — —
ALT3 — —
— AN[24] ADC_0
ALT0 GPIO[75] SIUL
ALT1 — —
ALT3 — —
— AN[25] ADC_0
ALT0 GPIO[76] SIUL
ALT1 — —
ALT3 — —
— AN[26] ADC_0
E[13] PCR[77] ALT2 — — — Slow Medium — 117 141
ALT3 — — —
— EIRQ[25] SIUL I
E[14] PCR[78] ALT2 — — — Slow Medium — 119 143
ALT3 — — —
— EIRQ[26] SIUL I
DocID18340 Rev 6 43/105

104

Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)

ALT1 — — —
ALT2 — — —
E[15] PCR[79] Slow Medium — 121 145
ALT3 — — —
— SIN_3 DSPI_3 I
— EIRQ[27] SIUL I
Port F
ALT1 DBG_0 FlexRay_0 O
F[0] PCR[80] ALT2 CS3_3 DSPI_3 O Slow Medium — 133 157
ALT3 — — —
— EIRQ[28] SIUL I
F[1] PCR[81] ALT2 CS2_3 DSPI_3 O Slow Medium — 135 159
ALT3 — — —
— EIRQ[29] SIUL I
F[2] PCR[82] Slow Medium — 137 161
ALT2 CS1_3 DSPI_3 O
ALT3 — — —
ALT3 — — —
ALT0 — — —
ALT1 — — —
F[4] PCR[84] Slow Fast — 4 4
ALT2 MDO[3] nexus_0 O
ALT3 — — —
ALT0 — — —
ALT1 — — —
ALT3 — — —

ALT1 — — —
ALT3 — — —
44/105 DocID18340 Rev 6


Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)

ALT1 — — —
ALT2 MCKO nexus_0 O
ALT3 — — —

ALT1 — — —
ALT2 MSEO1 nexus_0 O
ALT3 — — —

ALT1 — — —
ALT2 MSEO0 nexus_0 O
ALT3 — — —

ALT1 — — —
F[10] PCR[90] Slow Fast — 24 32
ALT2 EVTO nexus_0 O
ALT3 — — —
ALT1 EVTI nexus_0 I
ALT2 — — —
ALT3 — — —
ALT2 — — —
ALT3 — — —
ALT2 — — —
ALT3 — — —
ALT2 — — —
ALT3 — — —
ALT1 — — —
F[15] PCR[95] ALT2 — — — Slow Medium — 113 137
ALT3 — — —
— RXD LINFlex_1 I
DocID18340 Rev 6 45/105

104

Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)
Port G
ALT1 F[0] FCCU O
G[0] PCR[96] ALT2 — — — Slow Medium — 38 46
ALT3 — — —
— EIRQ[30] SIUL I
ALT1 F[1] FCCU O
ALT3 — — —
— EIRQ[31] SIUL I
ALT1 — — —
ALT3 — — —
— SIN_4 DSPI_4 I
ALT1 — — —
G[3] PCR[99] Slow Medium — 104 128
ALT3 — — —
ALT1 — — —
ALT3 — — —
ALT1 — — —
ALT3 — — —
ALT1 — — —
ALT2 CS1_4 DSPI_4 O
ALT3 — — —
ALT1 — — —
ALT2 CS2_4 DSPI_4 O
ALT3 — — —
46/105 DocID18340 Rev 6


Pad speed(6) Pin
Alternate I/O
Port PCR Peripheral
SRC = 0 SRC = 1
100 144 176(7)
ALT0
GPIO[104] SIUL I/O
ALT1
— — —
G[8] PCR[104] ALT2 Slow Medium — 81 97
CS3_4 DSPI_4 O
ALT3
— — —
—
ALT1 — — —
ALT3 — — —
— RXD FlexCAN_1 I
ALT1 — — —
ALT3 — — —
ALT1 — — —
ALT2 — — —
ALT3 — — —
1. This table concerns Enhanced Full-featured version. Please refer to “SPC56xP54x/SPC56xP60x device configuration
difference” table for difference between Enhanced Full-featured, Full-featured, and Airbag configuration.
2. ALT0 is the primary (default) function for each port after reset.
3. Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIU module.
PCR[PA] = 00  ALT0; PCR[PA] = 01  ALT1; PCR[PA] = 10  ALT2; PCR[PA] = 11 ALT3. This is intended to select
the output functions; to use one of the input-only functions, the PCR[IBE] bit must be written to ‘1’, regardless of the values
selected in the PCR[PA] bitfields. For this reason, the value corresponding to an input only function is reported as “—”.
4. Module included on the MCU.
5. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMI[PADSELx] bitfields inside the SIUL module.
6. Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.
8. Weak pull down during reset.
DocID18340 Rev 6 47/105

104
Electrical characteristics SPC56xP54x, SPC56xP60x
3 Electrical characteristics
3.1 Introduction
This section contains electrical characteristics of the device as well as temperature and
power considerations.
This product contains devices to protect the inputs against damage due to high static
voltages. However, it is advisable to take precautions to avoid application of any voltage
higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD
or VSS). This can be done by the internal pull-up or pull-down, which is provided by the
product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and
its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.
Caution: All of the following parameter values can vary depending on the application and must be
confirmed during silicon validation, silicon characterization or silicon reliability trial.
3.2 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 8 are used and
the parameters are tagged accordingly in the tables where appropriate.
Table 8. Parameter classifications

Classification tag Tag description
P Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
C
relevant sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from
T typical devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.
D Those parameters are derived mainly from simulations.
Note: The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
48/105 DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Electrical characteristics
3.3 Absolute maximum ratings

Table 9. Absolute maximum ratings(1)
Symbol Parameter Conditions Min Max(2) Unit
VSS_HV SR Digital ground — 0 0 V

3.3 V / 5.0 V input/output supply
VDD_HV_IOx(3) SR voltage with respect to ground — –0.3 6.0 V
(VSS_HV)
Input/output ground voltage with
VSS_HV_IOx SR — –0.1 0.1 V
respect to ground (VSS_HV)
3.3 V / 5.0 V code and data flash — –0.3 6.0

VDD_HV_FL SR memory supply voltage with respect Relative to VDD_HV_IOx + V
to ground (VSS_HV) –0.3
VDD_HV_IOx 0.3
Code and data flash memory ground
VSS_HV_FL SR — –0.1 0.1 V
with respect to ground (VSS_HV)
3.3 V / 5.0 V crystal oscillator — –0.3 6.0

VDD_HV_OSC SR amplifier supply voltage with respect Relative to VDD_HV_IOx + V
to ground (VSS_HV) –0.3
VDD_HV_IOx 0.3
3.3 V / 5.0 V crystal oscillator
VSS_HV_OSC SR amplifier reference voltage with — –0.1 0.1 V
respect to ground (VSS_HV)
3.3 V / 5.0 V voltage regulator supply — – 0.3 6.0

VDD_HV_REG SR voltage with respect to ground Relative to VDD_HV_IOx + V
(VSS_HV) – 0.3
VDD_HV_IOx 0.3
VDD_HV_REG VDD_HV_REG
3.3 V / 5.0 V ADC supply and high – 0.3
< 2.7 V + 0.3
VDD_HV_AD SR reference voltage with respect to V
ground (VSS_HV) VDD_HV_REG
– 0.3 6.0
> 2.7 V
ADC ground and low reference
VSS_HV_AD SR voltage with respect to ground — –0.1 0.1 V
(VSS_HV)
Slope characteristics on all VDD
500 x 103 V/s
TVDD SR during power up(4) with respect to — 3.0(5)
(0.5 [V/µs])
ground (VSS_HV)
Voltage on any pin with respect to — –0.3 6.0

VIN SR ground (VSS_HV_IOx) with respect to Relative to VDD_HV_IOx + V
ground (VSS_HV) –0.3
VDD_HV_IOx 0.3
VDD_HV_REG VSS_HV_AD VDD_HV_AD +
V
< 2.7 V 0.3 0.3
VINAN SR Analog input voltage
VDD_HV_REG
VSS_HV_AD VDD_HV_AD V
> 2.7 V
Injected input current on any pin
IINJPAD SR — –10 10 mA
during overload condition
DocID18340 Rev 6 49/105

104
Table 9. Absolute maximum ratings(1) (continued)

Absolute sum of all injected input

IINJSUM SR — –50 50 mA
currents during overload condition
Low voltage static current sink
IVDD_LV SR — — 155 mA
through VDD_LV
TSTG SR Storage temperature — –55 150 °C
TJ SR Junction temperature under bias — –40 150 °C
1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.
2. Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress
have not yet been determined.
3. The difference between each couple of voltage supplies must be less than 300 mV, |VDD_HV_IOy – VDD_HV_IOx | < 300 mV.
4. Guaranteed by device validation.
5. Minimum value of TVDD must be guaranteed until VDD_HV_REG reaches 2.6 V (maximum value of VPORH).
Figure 5 shows the constraints of the different power supplies.
Figure 5. Power supplies constraints
VDD_HV_xxx
6.0V
-0.3V VDD_HV_IOx
-0.3V 6.0V
The SPC56xP54x/SPC56xP60x supply architecture provides an ADC supply that is

managed independently of standard VDD_HV supply. Figure 6 shows the constraints of the
ADC power supply.
50/105 DocID18340 Rev 6

Figure 6. Independent ADC supply(e)
VDD_HV_AD
6.0V
-0.3V VDD_HV_REG
-0.3V 2.7V 6.0V
3.4 Recommended operating conditions

Table 10. Recommended operating conditions (5.0 V)

5.0 V input/output supply
VDD_HV_IOx(2) SR — 4.5 5.5 V
voltage
VSS_HV_IOx SR Input/output ground voltage — 0 0 V
— 4.5 5.5
5.0 V code and data flash
VDD_HV_FL SR Relative to V
memory supply voltage VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
VDD_HV_IOx
Code and data flash
VSS_HV_FL SR — 0 0 V
memory ground
— 4.5 5.5
5.0 V crystal oscillator
VDD_HV_OSC SR Relative to V
amplifier supply voltage VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
VDD_HV_IOx
VSS_HV_OSC SR — 0 0 V
amplifier reference voltage
e. Device design targets the removal of this conditions. To be confirmed by design during device validation.
DocID18340 Rev 6 51/105

104
Table 10. Recommended operating conditions (5.0 V) (continued)

— 4.5 5.5
5.0 V voltage regulator
VDD_HV_REG SR Relative to V
supply voltage VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
VDD_HV_IOx
— 4.5 5.5
5.0 V ADC supply and high
VDD_HV_AD SR Relative to V
reference voltage V – 0.1 —
VDD_HV_REG DD_HV_REG
ADC ground and low
VSS_HV_AD SR — 0 0 V
reference voltage
VDD_LV_REGCOR(3),(4) SR Internal supply voltage — — — V
(3)
VSS_LV_REGCOR SR Internal reference voltage — 0 0 V
VDD_LV_CORx (3),(4) SR Internal supply voltage — — — V
VSS_LV_CORx(3) SR Internal reference voltage — 0 0 V
Ambient temperature under
TA SR — –40 125 °C
bias
1. Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.
In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.
3. To be connected to emitter of external NPN. Low voltage supplies are not under user control—these are produced by an
on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to
high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast
emitter.
4. The low voltage supplies (VDD_LV_xxx) are not all independent. 
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low
voltage supply to the data flash memory module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
VDD_LV_REGCOR and VDD_LV_REGCORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Table 11. Recommended operating conditions (3.3 V)


3.3 V input/output supply
VDD_HV_IOx(2) SR — 3.0 3.6 V
voltage
VSS_HV_IOx SR Input/output ground voltage — 0 0 V
— 3.0 3.6
3.3 V code and data flash
VDD_HV_FL SR Relative to V
memory supply voltage VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
VDD_HV_IOx
Code and data flash
VSS_HV_FL SR — 0 0 V
memory ground
— 3.0 3.6
VDD_HV_OSC SR Relative to V
amplifier supply voltage VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
VDD_HV_IOx
VSS_HV_OSC SR — 0 0 V
amplifier reference voltage
52/105 DocID18340 Rev 6

Table 11. Recommended operating conditions (3.3 V) (continued)

— 3.0 3.6
3.3 V voltage regulator
VDD_HV_REG SR Relative to V
supply voltage VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
VDD_HV_IOx
— 3.0 5.5
3.3 V ADC supply and high
VDD_HV_AD SR Relative to V
reference voltage V – 0.1 5.5
VDD_HV_REG DD_HV_REG
ADC ground and low
VSS_HV_AD SR — 0 0 V
reference voltage
VDD_LV_REGCOR(3),(4) SR Internal supply voltage — — — V
(3)
VSS_LV_REGCOR SR Internal reference voltage — 0 0 V
VDD_LV_CORx(3),(4) SR Internal supply voltage — — — V
VSS_LV_CORx(3) SR Internal reference voltage — 0 0 V
Ambient temperature under
TA SR — –40 125 °C
bias
1. Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.
In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.
3. To be connected to emitter of external NPN. Low voltage supplies are not under user control—these are produced by an
on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to
high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast
emitter.
4. The low voltage supplies (VDD_LV_xxx) are not all independent. 
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low
voltage supply to the data flash memory module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
VDD_LV_REGCOR and VDD_LV_REGCORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Figure 7 shows the constraints of the different power supplies.
DocID18340 Rev 6 53/105

104
Figure 7. Power supplies constraints(f)
VDD_HV_xxx
5.5V
3.3V
3.2V
VDD_HV_IOx
3.2V 3.3V 5.5V
The SPC56xP54x/SPC56xP60x supply architecture provides an ADC supply that is

managed independently of standard VDD_HV supply. Figure 8 shows the constraints of the
ADC power supply.
f. IO AC and DC characteristics are guaranteed only in the range 3.0 V–3.6 V when PAD3V5V is low, and in the
range 4.5 V–5.5 V when PAD3V5V is high.
54/105 DocID18340 Rev 6

Figure 8. Independent ADC supply
VDD_HV_AD
5.5V
3.0V
VDD_HV_REG
3.0V 5.5V
3.5 Thermal characteristics

Table 12. Thermal characteristics for 144-pin LQFP
Symbol Parameter Conditions Typical value Unit
D Thermal resistance junction-to-ambient, Single layer board—1s 53.4 °C/W

RJA
D natural convection(1) Four layer board—2s2p 43.9 °C/W
RJB D Thermal resistance junction-to-board(2) Four layer board—2s2p 29.6 °C/W
(3)
RJCtop D Thermal resistance junction-to-case (top) Single layer board—1s 9.3 °C/W
JB D Junction-to-board, natural convection(4) Operating conditions 29.8 °C/W
JC D Junction-to-case, natural convection(5) Operating conditions 1.3 °C/W
1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets JEDEC specification
for this package.
2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package.
3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
4. Thermal characterization parameter indicating the temperature difference between the board and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.
5. Thermal characterization parameter indicating the temperature difference between the case and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JC.
DocID18340 Rev 6 55/105

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Table 13. Thermal characteristics for 100-pin LQFP

Symbol Parameter Conditions Typical value Unit
D Thermal resistance junction-to-ambient, Single layer board—1s 47.3 °C/W

RJA
D natural convection(1) Four layer board—2s2p 35.6 °C/W
(2)
RJB D Thermal resistance junction-to-board Four layer board—2s2p 19.1 °C/W
RJCtop D Thermal resistance junction-to-case (top)(3) Single layer board—1s 9.1 °C/W
(4)
JB D Junction-to-board, natural convection Operating conditions 19.1 °C/W
(5)
JC D Junction-to-case, natural convection Operating conditions 1.1 °C/W
1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets JEDEC specification
for this package.
2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package.
3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
4. Thermal characterization parameter indicating the temperature difference between the board and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.
5. Thermal characterization parameter indicating the temperature difference between the case and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JC.
3.5.1 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
Equation 1 TJ = TA + (RJA × PD)

where:
TA= ambient temperature for the package (oC)
RJA= junction to ambient thermal resistance (oC/W)
PD= power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by a
factor of two. Which value is closer to the application depends on the power dissipated by
other components on the board. The value obtained on a single layer board is appropriate
for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are
well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a
junction to case thermal resistance and a case to ambient thermal resistance:
Equation 2 RJA = RJC + RCA

where:
RJA = junction to ambient thermal resistance (°C/W)
RJC= junction to case thermal resistance (°C/W)
RCA= case to ambient thermal resistance (°C/W)
56/105 DocID18340 Rev 6

RJC is device related and cannot be influenced by the user. The user controls the thermal
environment to change the case to ambient thermal resistance, RCA. For instance, the user
can change the size of the heat sink, the air flow around the device, the interface material,
the mounting arrangement on printed circuit board, or change the thermal dissipation on the
printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are
not used, the Thermal Characterization Parameter (JT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using Equation 3:
Equation 3 TJ = TT + (JT × PD)

where:
TT= thermocouple temperature on top of the package (°C)
JT= thermal characterization parameter (°C/W)
PD= power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40
gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the package.
A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of
wire extending from the junction. The thermocouple wire is placed flat against the package
case to avoid measurement errors caused by cooling effects of the thermocouple wire.
3.5.1.1 References
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134 U.S.A.
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering
Documents at 800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at jedec.org web site.
1. C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module, Proceedings of SemiTherm, San Diego, 1998, pp.
47-54.
2. G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled
Applications, Electronic Packaging and Production, pp. 53-58, March 1998.
3. B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling, Proceedings of SemiTherm, San
Diego, 1999, pp. 212-220.
DocID18340 Rev 6 57/105

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3.6 Electromagnetic interference (EMI) characteristics

Table 14. EMI testing specifications
Level
Parameter Symbol Conditions fOSC/fBUS Frequency Unit
(Max)
VDD = 5 V; 8 MHz crystal 150 kHz–150 MHz 18

TA = 25 °C 64 MHz bus dBV
150–1000 MHz 12
No PLL frequency
150 kHz–30 MHz modulation IEC Level M —
Radiated
RBW 9 kHz, Step 150 kHz–150 MHz 18
VRE_TEM emissions, 8 MHz crystal
electric field Size 5 kHz dBV
64 MHz bus 150–1000 MHz 12
30 MHz–1 GHz ±2% PLL
RBW 120 kHz, frequency IEC Level M —
Step Size 80 kHz modulation
3.7 Electrostatic discharge (ESD) characteristics

Table 15. ESD ratings(1)(2)
Symbol Parameter Conditions Value Unit
VESD(HBM) SR Electrostatic discharge (Human Body Model) — 2000 V

750 (corners)
VESD(CDM) SR Electrostatic discharge (Charged Device Model) — V
500 (other)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
3.8 Power management electrical characteristics
3.8.1 Voltage regulator electrical characteristics

The internal voltage regulator requires an external NPN ballast to be connected as shown in
Figure 9. Table 16 contains all approved NPN ballast components. Capacitances should be
placed on the board as near as possible to the associated pins. Care should also be taken
to limit the serial inductance of the VDD_HV_REG, BCTRL and VDD_LV_CORx pins to less than
LReg, see Table 17.
Note: The voltage regulator output cannot be used to drive external circuits. Output pins are used
only for decoupling capacitances.
VDD_LV_COR must be generated using internal regulator and external NPN transistor. It is
not possible to provide VDD_LV_COR through external regulator.
For the SPC56xP54x/SPC56xP60x microcontroller, capacitors, with total values not below
CDEC1, should be placed between VDD_LV_CORx/VSS_LV_CORx close to external ballast
transistor emitter. 4 capacitors, with total values not below CDEC2, should be placed close to
microcontroller pins between each VDD_LV_CORx/VSS_LV_CORx supply pairs and the
58/105 DocID18340 Rev 6

VDD_LV_REGCOR/VSS_LV_REGCOR pair. Additionally, capacitors with total values not below

CDEC3, should be placed between the VDD_HV_REG/VSS_HV_REG pins close to ballast
collector. Capacitors values have to take into account capacitor accuracy, aging and
variation versus temperature.
All reported information are valid for voltage and temperature ranges described in
recommended operating condition, Table 10 and Table 11.
Figure 9. Voltage regulator configuration
VDD_HV_REG
SPC56xP54x/SPC5 CDEC3
BCTRL BJT(1)
VDD_LV_COR
CDEC2 CDEC1
1. Refer to Table 16.
Table 16. Approved NPN ballast components

Part Manufacturer Approved derivatives(1)
ON Semi BCP68
BCP68 NXP BCP68-25
Infineon BCP68-25
BCX68 Infineon BCX68-10;BCX68-16;BCX68-25
BC868 NXP BC868
Infineon BC817-16;BC817-25;BC817SU;
BC817
NXP BC817-16;BC817-25
ST BCP56-16
Infineon BCP56-10;BCP56-16
BCP56
ON Semi BCP56-10
NXP BCP56-10;BCP56-16
1. For automotive applications please check with the appropriate transistor vendor for automotive grade
certification.
DocID18340 Rev 6 59/105

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Table 17. Voltage regulator electrical characteristics

Value
Symbol C Parameter Conditions Unit
Min Typ Max
Output voltage under

VDD_LV_REGCOR CC P maximum load run supply Post-trimming 1.15 — 1.32 V
current configuration
BJT from Table 16. 3
capacitances (i.e. X7R or
19.5 30 — µF
External decoupling/stability X8R capacitors) with nominal
CDEC1 SR — value of 10 µF
ceramic capacitor
BJT BC817, one capacitance
14.3 22 µF
of 22 µF
BJT from Table 16. 3x10 µF.
Resulting ESR of all three Absolute maximum value
— — 50 m
capacitors of CDEC1 between 100 kHz and
10 MHz
RREG SR —
BJT BC817, 1x 22 µF.
Resulting ESR of the unique Absolute maximum value
10 — 40 m
capacitor CDEC1 between 100 kHz and
10 MHz
4 capacitances (i.e. X7R or
External decoupling/stability
CDEC2 SR — X8R capacitors) with nominal 1200 1760 — nF
ceramic capacitor
value of 440 nF
3 capacitances (i.e. X7R or
External decoupling/stability X8R capacitors) with nominal
CDEC3 SR — ceramic capacitor on value of 10 µF; CDEC3 has to 19.5 30 — µF
VDD_HV_REG be equal or greater than
CDEC1
Resulting ESL of VDD_HV_REG,
LReg SR — — — — 15 nH
BCTRL and VDD_LV_CORx pins
3.8.2 Voltage monitor electrical characteristics

The device implements a Power On Reset module to ensure correct power-up initialization,
as well as three low voltage detectors to monitor the VDD and the VDD_LV voltage while
device is supplied:
 POR monitors VDD during the power-up phase to ensure device is maintained in a safe
reset state
 LVDHV3 monitors VDD to ensure device reset below minimum functional supply
 LVDHV5 monitors VDD when application uses device in the 5.0V ± 10% range
 LVDLVCOR monitors low voltage digital power domain
60/105 DocID18340 Rev 6

Table 18. Low voltage monitor electrical characteristics

Value
Symbol Parameter Conditions(1) Unit
Min Max
VPORH T Power-on reset threshold — 1.5 2.7 V

VPORUP P Supply for functional POR module TA = 25°C 1.0 — V
VREGLVDMOK_H P Regulator low voltage detector high threshold — — 2.95 V
VREGLVDMOK_L P Regulator low voltage detector low threshold — 2.6 — V
VFLLVDMOK_H P Flash memory low voltage detector high threshold — — 2.95 V
VFLLVDMOK_L P Flash memory low voltage detector low threshold — 2.6 — V
VIOLVDMOK_H P I/O low voltage detector high threshold — — 2.95 V
VIOLVDMOK_L P I/O low voltage detector low threshold — 2.6 — V
VIOLVDM5OK_H P I/O 5V low voltage detector high threshold — — 4.4 V
VIOLVDM5OK_L P I/O 5V low voltage detector low threshold — 3.8 — V
VMLVDDOK_H P Digital supply low voltage detector high — — 1.15 V
VMLVDDOK_L P Digital supply low voltage detector low — 1.08 — V
1. VDD = 3.3V ± 10% / 5.0V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified.
3.9 Power Up/Down sequencing

To prevent an overstress event or a malfunction within and outside the device, the
SPC56xP54x/SPC56xP60x implements the following sequence to ensure each module is
started only when all conditions for switching it ON are available:
1. A POWER_ON module working on voltage regulator supply controls the correct start-
up of the regulator. This is a key module ensuring safe configuration for all voltage
regulator functionality when supply is below 1.5V. Associated POWER_ON (or POR)
signal is active low.
– Several low voltage detectors, working on voltage regulator supply monitor the
voltage of the critical modules (voltage regulator, I/Os, flash memory and low
voltage domain). LVDs are gated low when POWER_ON is active.
– A POWER_OK signal is generated when all critical supplies monitored by the LVD
are available. This signal is active high and released to all modules including I/Os,
flash memory and RC16 oscillator needed during power-up phase and reset
phase. When POWER_OK is low the associated modules are set into a safe state.
DocID18340 Rev 6 61/105

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Figure 10. Power-up typical sequence
VLVDHV3H
VDD_HV_REG VPORH 3.3V
VPOR_UP
0V
3.3V
POWER_ON
0V
LVDM (HV)
3.3V
0V
VDD_LV_REGCOR VMLVDOK_H
1.2V
0V
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator 1.2V
~1us
0V
Internal Reset Generation Module 1.2V

FSM
P0 P1 0V
Figure 11. Power-down typical sequence
VLVDHV3L 3.3V
VPORH
VDD_HV_REG
0V
3.3V
LVDM (HV)
0V
3.3V
POWER_ON
0V
1.2V
VDD_LV_REGCOR
0V
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
Internal Reset Generation Module
1.2V
FSM
IDLE P0 0V
62/105 DocID18340 Rev 6

Figure 12. Brown-out typical sequence
VLVDHV3H
VLVDHV3L 3.3V
VDD_HV_REG
0V
3.3V
LVDM (HV)
0V
3.3V
POWER_ON
0V
1.2V
VDD_LV_REGCOR
0V
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
~1us
1.2V
0V
Internal Reset Generation Module
1.2V
FSM
IDLE P0 P1 0V
3.10 NVUSRO register

Portions of the device configuration, such as high voltage supply, and watchdog
enable/disable after reset are controlled via bit values in the non-volatile user options
register (NVUSRO) register.
For a detailed description of the NVUSRO register, please refer to the device reference
manual.
3.10.1 NVUSRO[PAD3V5V] field description

Table 19 shows how NVUSRO[PAD3V5V] controls the device configuration.
Table 19. PAD3V5V field description(1)

Value(2) Description
0 High voltage supply is 5.0 V

1 High voltage supply is 3.3 V
1. See the device reference manual for more information on the NVUSRO register.
2. '1' is delivery value. It is part of shadow Flash, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V bit value.
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3.11 DC electrical characteristics
3.11.1 DC electrical characteristics (5 V)

Table 20 gives the DC electrical characteristics at 5 V (4.5 V < VDD_HV_IOx < 5.5 V,
NVUSRO[PAD3V5V]=0) as described in Figure 13.
Figure 13. I/O input DC electrical characteristics definition
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Table 20. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0)

Symbol Parameter Conditions Min Max Unit
VIL D Minimum low level input voltage — –0.1(1) — V

VIL P Maximum level input voltage — — 0.35 VDD_HV_IOx V
VIH P Minimum high level input voltage — 0.65 VDD_HV_IOx — V
VIH D Maximum high level input voltage — — VDD_HV_IOx + 0.1(1) V
VHYS T Schmitt trigger hysteresis — 0.1 VDD_HV_IOx — V
VOL_S P Slow, low level output voltage IOL = 3 mA — 0.1 VDD_HV_IOx V
VOH_S P Slow, high level output voltage IOH = –3 mA 0.8VDD_HV_IOx — V
VOL_M P Medium, low level output voltage IOL = 3 mA — 0.1 VDD_HV_IOx V
VOH_M P Medium, high level output voltage IOH = –3 mA 0.8 VDD_HV_IOx — V
VOL_F P Fast, low level output voltage IOL = 3 mA — 0.1 VDD_HV_IOx V
VOH_F P Fast, high level output voltage IOH = –3 mA 0.8 VDD_HV_IOx — V
Symmetric, low level output
VOL_SYM P IOL = 3 mA — 0.1 VDD_HV_IOx V
voltage
Symmetric, high level output
VOH_SYM P IOH = –3 mA 0.8 VDD_HV_IOx — V
voltage
64/105 DocID18340 Rev 6

Table 20. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) (continued)

VIN = VIL –130 —

IPU P Equivalent pull-up current µA
VIN = VIH — –10
VIN = VIL 10 —
IPD P Equivalent pull-down current µA
VIN = VIH — 130
Input leakage current
IIL P TA = –40 to 125 °C –1 1 µA
(all bidirectional ports)
Input leakage current
IIL P TA = –40 to 125 °C –0.5 0.5 µA
(all ADC input-only ports)
CIN D Input capacitance — — 10 pF
VIN = VIL –130 —
IPU D RESET, equivalent pull-up current µA
VIN = VIH — –10
RESET, equivalent pull-down VIN = VIL 10 —

IPD D µA
current VIN = VIH — 130
1. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.
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Table 21. Supply current (5.0 V, NVUSRO[PAD3V5V]=0)

Value
Symbol Parameter Conditions Unit
Typ Max
VDD_LV_CORE
externally forced at 1.3 V
RUN — Maximum Mode(1) 64 MHz 90 120
ADC Freq = 32 MHz
PLL Freq = 64 MHz
16 MHz 21 37
T RUN - Platform consumption,
40 MHz 35 55
single core(2)
VDD_LV_CORE 64 MHz 48 72
externally forced to 1.3V 16 MHz 24 41
IDD_LV_CORE RUN - Platform consumption,
40 MHz 42 64
dual core(3)
64 MHz 58 85
VDD_LV_CORE
Supply RUN — Maximum Mode(4) 64 MHz 85 113
externally forced at 1.3 V mA
current
VDD_LV_CORE
P HALT Mode(5) — 5.5 15
externally forced at 1.3 V
VDD_LV_CORE
STOP Mode(6) — 4.5 13
externally forced at 1.3 V
Flash memory supply current
VDD_HV_FL at 5.0 V — — 14
during read
IDD_FLASH T Flash memory supply current
during erase operation on 1 VDD_HV_FL at 5.0 V — — 42
flash memory module
ADC supply current — VDD_HV_AD at 5.0 V

IDD_ADC T — 3 4
Maximum Mode ADC Freq = 16 MHz
IDD_OSC T OSC supply current VDD_OSC at 5.0 V 8 MHz 2.6 3.2
1. Maximum mode configuration: Code fetched from Flash executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,
LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM
enabled. I/O supply current excluded.
2. RAM, Code and Data Flash powered, code fetched from Flash executed by single core, all peripherals gated; IRC16MHz
on, PLL64MHz OFF (except for code running at 64 MHz).
Code is performing continuous data transfer from Flash to RAM.
3. RAM, Code and Data Flash powered, code fetched from Flash executed by dual core, all peripherals gated; IRC16MHz on,
PLL64MHz OFF (except for code running at 64 MHz).
4. Maximum mode configuration: Code fetched from RAM executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,
5. HALT mode configuration, only for the “P” classification: Code Flash memory in low power mode, data Flash memory in
power down mode, OSC/PLL are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.
6. STOP mode configuration, only for the “P” classification: Code and data Flash memories in power down mode, OSC/PLL
are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.
66/105 DocID18340 Rev 6

3.11.2 DC electrical characteristics (3.3 V)

Table 22 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V,
NVUSRO[PAD3V5V]=1) as described in Figure 14.
Figure 14. I/O input DC electrical characteristics definition
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Table 22. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)(1)

VIL D Minimum low level input voltage — –0.1(2) — V

VIL P Maximum low level input voltage — — 0.35 VDD_HV_IOx V
VIH P Minimum high level input voltage — 0.65 VDD_HV_IOx — V
VIH D Maximum high level input voltage — — VDD_HV_IOx + 0.1(2) V
VHYS T Schmitt trigger hysteresis — 0.1 VDD_HV_IOx — V
VOL_S P Slow, low level output voltage IOL = 1.5 mA — 0.5 V
VOH_S P Slow, high level output voltage IOH = –1.5 mA VDD_HV_IOx – 0.8 — V
VOL_M P Medium, low level output voltage IOL = 2 mA — 0.5 V
VOH_M P Medium, high level output voltage IOH = –2 mA VDD_HV_IOx – 0.8 — V
VOL_F P Fast, high level output voltage IOL = 11 mA — 0.5 V
VOH_F P Fast, high level output voltage IOH = –11 mA VDD_HV_IOx – 0.8 — V
VOL_SYM P IOL = 1.5 mA — 0.5 V
voltage
VOH_SYM P IOH = –1.5 mA VDD_HV_IOx – 0.8 — V
voltage
VIN = VIL –130 —
IPU P Equivalent pull-up current µA
VIN = VIH — –10
DocID18340 Rev 6 67/105

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Table 22. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)(1) (continued)

VIN = VIL 10 —
IPD P Equivalent pull-down current µA
VIN = VIH — 130
Input leakage current 
IIL P TA = –40 to 125 °C — 1 µA
(all bidirectional ports)
Input leakage current 
IIL P TA = –40 to 125 °C — 0.5 µA
(all ADC input-only ports)
CIN D Input capacitance — — 10 pF
VIN = VIL –130 —
IPU D RESET, equivalent pull-up current µA
VIN = VIH — –10
RESET, equivalent pull-down VIN = VIL 10 —

IPD D µA
current VIN = VIH — 130
1. These specifications are design targets and subject to change per device characterization.
2. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.
68/105 DocID18340 Rev 6

Table 23. Supply current (3.3 V, NVUSRO[PAD3V5V]=1)

Value
Typ Max
VDD_LV_CORE
externally forced at
RUN — Maximum Mode(1) 1.3 V 64 MHz 90 120
ADC Freq = 32 MHz
PLL Freq = 64 MHz
16 MHz 21 37
T RUN - Platform consumption,
40 MHz 35 55
single core(2)
VDD_LV_CORE 64 MHz 48 72
externally forced to 1.3V 16 MHz 24 41
RUN - Platform consumption,
IDD_LV_CORE 40 MHz 42 64
dual core(3)
64 MHz 58 85
VDD_LV_CORE
RUN — Maximum Mode(4) externally forced at 64 MHz 85 113
Supply 1.3 V mA
current
VDD_LV_CORE
P HALT Mode(5) externally forced at — 5.5 15
1.3 V
VDD_LV_CORE
STOP Mode(6) externally forced at — 4.5 13
1.3 V
Flash memory supply current
VDD_HV_FL at 3.3 V — — 14
during read
IDD_FLASH D Flash memory supply current
during erase operation on 1 VDD_HV_FL at 3.3 V — — 42
flash memory module
ADC supply current — VDD_HV_AD at 3.3 V

IDD_ADC T — 3 4
Maximum Mode ADC Freq = 16 MHz
IDD_OSC T OSC supply current VDD_OSC at 3.3 V 8 MHz 2.4 3
1. Maximum mode configuration: Code fetched from Flash executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,
2. RAM, Code and Data Flash powered, code fetched from Flash executed by single core, all peripherals gated; IRC16MHz
on, PLL64MHz OFF (except for code running at 64 MHz).
3. RAM, Code and Data Flash powered, code fetched from Flash executed by dual core, all peripherals gated; IRC16MHz on,
PLL64MHz OFF (except for code running at 64 MHz).
4. Maximum mode configuration: Code fetched from RAM executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,
5. HALT mode configuration, only for the “P” classification: Code Flash memory in low power mode, data Flash memory in
power down mode, OSC/PLL are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.
6. STOP mode configuration, only for the “P” classification: Code and data Flash memories in power down mode, OSC/PLL
are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.
DocID18340 Rev 6 69/105

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70/105
Electrical characteristics
Table 24. Peripherals supply current (5 V and 3.3 V)(1)
Value
Typ Max
Total (static + dynamic)

consumption:
CAN (FlexCAN) – FlexCAN in loop-back mode
IDD_HV(CAN) T supply current on 500 Kbyte/s – XTAL@ 8 MHz used as CAN 21.6 * fperiph 28.1* fperiph
VDD_HV_REG engine clock source
– Message sending period is 580
µs
SCI (LINFlex) supply Total (static + dynamic) consumption:

IDD_HV(SCI) T current on – LIN mode 10.8 * fperiph 14.1 * fperiph µA
VDD_HV_REG – Baudrate: 115.2 Kbyte/s
DocID18340 Rev 6
Ballast dynamic consumption (continuous

SPI (DSPI) supply communication):
IDD_HV(SPI) T current on – Baudrate: 2 Mbit/s 4.8 * fperiph 6.3 * fperiph
VDD_HV_REG – Transmission every 8 µs
– Frame: 16 bits
ADC supply current Ballast dynamic consumption
IDD_HV(ADC) T VDD = 5.5 V 120 * fperiph 156 * fperiph
on VDD_HV_REG (continuous conversion)
ADC supply current Analog dynamic consumption
IDD_HV_ADC(ADC) T VDD = 5.5 V 0.005 * fperiph + 2.8 0.007 * fperiph + 3.4 mA
on VDD_HV_ADC (continuous conversion)
eTimer supply current PWM signals generation Dynamic consumption does not
IDD_HV(eTimer) T 1.8 2.4 mA
on VDD_HV_REG on all 1 channel @10kHz change varying the frequency
FlexRay supply
IDD_HV(FlexRay) T current on Static consumption 4.2 * fperiph 5.5 * fperiph µA
VDD_HV_REG
1. Operating conditions: fperiph = 8 MHz to 64 MHz
3.11.3 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD/VSS supply pair as described in Table 25.
Table 25. I/O supply segment

Supply segment
Package
1 2 3 4 5 6 7
pin23 – pin39 – pin58 – pin73 – pin92 – pin128 –

LQFP144 pin8 – pin20
pin38 pin55 pin68 pin89 pin125 pin5
pin15 – pin27 – pin41 – pin51 – pin64 –
LQFP100 pin89 – pin10 —
pin26 pin38 pin46 pin61 pin86
Table 26. I/O consumption

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max
VDD = 5.0 V ± 10%,

Dynamic I/O current — — 20
PAD3V5V = 0
ISWTSLW(2) CC D for SLOW CL = 25 pF mA
configuration VDD = 3.3 V ± 10%,
— — 16
PAD3V5V = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
(2)
ISWTMED CC D for MEDIUM CL = 25 pF mA
— — 17
PAD3V5V = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
ISWTFST(2) CC D for FAST CL = 25 pF mA
— — 50
PAD3V5V = 1
CL = 25 pF, 2 MHz — — 2.3
VDD = 5.0 V ± 10%,
CL = 25 pF, 4 MHz — — 3.2
PAD3V5V = 0
Root medium square C = 100 pF, 2 MHz — — 6.6
L
IRMSSLW CC D I/O current for SLOW mA
configuration CL = 25 pF, 2 MHz — — 1.6
VDD = 3.3 V ± 10%,
CL = 25 pF, 4 MHz — — 2.3
PAD3V5V = 1
CL = 100 pF, 2 MHz — — 4.7
CL = 25 pF, 13 MHz — — 6.6
VDD = 5.0 V ± 10%,
CL = 25 pF, 40 MHz — — 13.4
Root medium square PAD3V5V = 0
I/O current for CL = 100 pF, 13 MHz — — 18.3
IRMSMED CC D mA
MEDIUM CL = 25 pF, 13 MHz — — 5
CL = 25 pF, 40 MHz — — 8.5
PAD3V5V = 1
CL = 100 pF, 13 MHz — — 11
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Table 26. I/O consumption (continued)

Value
Min Typ Max
CL = 25 pF, 40 MHz — — 22
VDD = 5.0 V ± 10%,
CL = 25 pF, 64 MHz — — 33
PAD3V5V = 0
Root medium square C = 100 pF, 40 MHz — — 56
L
IRMSFST CC D I/O current for FAST mA
configuration CL = 25 pF, 40 MHz — — 14
VDD = 3.3 V ± 10%,
CL = 25 pF, 64 MHz — — 20
PAD3V5V = 1
CL = 100 pF, 40 MHz — — 35
Sum of all the static VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 70
IAVGSEG SR D I/O current within a mA
supply segment VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 65
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified.
2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
3.12 Main oscillator electrical characteristics

The SPC56xP54x/SPC56xP60x provides an oscillator/resonator driver.
Table 27. Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0)

Symbol Parameter Min Max Unit
fOSC SR Oscillator frequency 4 40 MHz

gm P Transconductance 6.5 25 mA/V
VOSC T Oscillation amplitude on EXTAL pin 1 — V
tOSCSU T Start-up time(1),(2) 8 — ms
1. The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive
capacitive loads can cause long start-up time.
2. Value captured when amplitude reaches 90% of EXTAL.
Table 28. Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)

Symbol Parameter Min Max Unit
fOSC SR Oscillator frequency 4 40 MHz

gm P Transconductance 4 20 mA/V
VOSC T Oscillation amplitude on EXTAL pin 1 — V
tOSCSU T Start-up time(1),(2) 8 — ms
1. The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive
capacitive loads can cause long start-up time.
2. Value captured when amplitude reaches 90% of EXTAL.
72/105 DocID18340 Rev 6

Table 29. Input clock characteristics

Symbol Parameter Min Typ Max Unit
fOSC SR Oscillator frequency 4 — 40 MHz

fCLK SR Frequency in bypass — — 64 MHz
trCLK SR Rise/fall time in bypass — — 1 ns
tDC SR Duty cycle 47.5 50 52.5 %
3.13 FMPLL electrical characteristics

Table 30. PLLMRFM electrical specifications (VDDPLL = 1.08 V to 1.32 V, VSS = VSSPLL = 0 V,
TA = TL to TH)
Value
min max
fref_crystal
D PLL reference frequency range(1) Crystal reference 4 40 MHz
fref_ext
Phase detector input frequency range
fpll_in D — 4 16 MHz
(after pre-divider)
fFMPLLOUT D Clock frequency range in normal mode — 4 120 MHz
Measured using
fFREE P Free running frequency clock division — 20 150 MHz
typically /16
fsys D On-chip PLL frequency — 16 64 MHz
tCYC D System clock period — — 1 / fsys ns
fLORL Lower limit 1.6 3.7

D Loss of reference frequency window(2) MHz
fLORH Upper limit 24 56
fSCM D Self-clocked mode frequency(3),(4) — 20 150 MHz
(9)
Short-term jitter fSYS maximum –4 4 % fCLKOUT
CLKOUT fPLLIN = 16 MHz
CJITTER T period Long-term jitter (avg. (resonator),
jitter(5),(6),(7),(8) over 2 ms interval) — 10 ns
fPLLCLK at 64 MHz,
4000 cycles
tlpll D PLL lock time (10), (11) — — 200 µs
tdc D Duty cycle of reference — 40 60 %
fLCK D Frequency LOCK range — –6 6 % fsys
fUL D Frequency un-LOCK range — –18 18 % fsys
fCS Center spread ±0.25 ±4.0(12)

D Modulation Depth %fsys
fDS Down Spread –0.5 –8.0
fMOD D Modulation frequency(13) — — 70 kHz
1. Considering operation with PLL not bypassed.
DocID18340 Rev 6 73/105

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2. “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.
3. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR
window.
4. fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced
mode.
5. This value is determined by the crystal manufacturer and board design.
6. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER
percentage for a given interval.
7. Proper PC board layout procedures must be followed to achieve specifications.
8. Values are obtained with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
9. Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.
10. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this
PLL, load capacitors should not exceed these limits.
11. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
12. This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).
13. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
3.14 16 MHz RC oscillator electrical characteristics

Table 31. 16 MHz RC oscillator electrical characteristics
Symbol Parameter Conditions Min Typ Max Unit
fRC P RC oscillator frequency TA = 25 °C — 16 — MHz

Fast internal RC oscillator variation
over temperature and
RCMVAR P — –6 — 6 %
supply with respect to fRC at TA = 25 °C
in high-frequency configuration
Post Trim Accuracy: The variation of
RCMTRIM T
the PTF(1) from the 16 MHz
TA = 25 °C –1 — 1 %
Fast internal RC oscillator trimming

RCMSTEP T
step
TA = 25 °C — 1.6 — %
1. PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and
temperature
3.15 Analog-to-Digital converter (ADC) electrical characteristics

The device provides a 10-bit Successive Approximation Register (SAR) Analog-to-Digital
Converter.
74/105 DocID18340 Rev 6

Figure 15. ADC characteristics and error definitions
Offset Error OSE Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
5 (1) Example of an actual transfer

(5) curve
4 (2) The ideal transfer curve
(4)
3 (3) Differential non-linearity error
(DNL)
2 (3)
(4) Integral non-linearity error
(INL)
1
1 LSB (ideal)
0
1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error OSE
3.15.1 Input impedance and ADC accuracy

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high-frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuate the noise present on the input pin; further, it
sources charge during the sampling phase, when the analog signal source is a high-
impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the source
impedance value of the transducer or circuit supplying the analog signal to be measured.
DocID18340 Rev 6 75/105

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The filter at the input pins must be designed taking into account the dynamic characteristics
of the input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: being CS and CP2 substantially two switched capacitances, with a
frequency equal to the ADC conversion rate, it can be seen as a resistive path to ground.
For instance, assuming a conversion rate of 1 MHz, with CS + CP2 equal to 3 pF, a
resistance of 330 k is obtained (REQ = 1 / (fc ×(CS + CP2)), where fc represents the
conversion rate at the considered channel). To minimize the error induced by the voltage
partitioning between this resistance (sampled voltage on CS + CP2) and the sum of RS + RF,
the external circuit must be designed to respect the Equation 4:
Equation 4
RS + RF 1
V A  ---------------------  --- LSB
R EQ 2
Equation 4 generates a constraint for external network design, in particular on resistive path.
Internal switch resistances (RSW and RAD) can be neglected with respect to external
resistances.
Figure 16. Input equivalent circuit (precise channels)
EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME
VDD
Channel
Sampling
Selection
Source Filter Current Limiter
RS RF RL RSW1 RAD
VA CF CP1 CP2 CS
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL Current Limiter Resistance
RSW1 Channel Selection Switch Impedance
RADSampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and
CP2)
76/105 DocID18340 Rev 6

Figure 17. Input equivalent circuit (extended channels)
EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME
VDD
Channel Extended
Sampling
Selection Switch
Source Filter Current Limiter
RS RF RL RSW1 RSW2 RAD
VA CF CP1 CP3 CP2 CS
RS: Source impedance

RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance (two contributions, RSW1 and RSW2)
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1, CP2 and CP3)
CS: Sampling capacitance
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the
equivalent circuit reported in Figure 16): A charge sharing phenomenon is installed when
the sampling phase is started (A/D switch close).
Figure 18. Transient behavior during sampling phase
VCS Voltage Transient on CS
VA
VA2 V <0.5 LSB
1 2
1 < (RSW + RAD) CS << TS
VA1 2 = RL (CS + CP1 + CP2)
TS t
DocID18340 Rev 6 77/105

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In particular two different transient periods can be distinguished:

 A first and quick charge transfer from the internal capacitance CP1 and CP2 to the
sampling capacitance CS occurs (CS is supposed initially completely discharged):
considering a worst case (since the time constant in reality would be faster) in which
CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and
CS are in series, and the time constant is
Equation 5
CP  CS
 1 =  R SW + R AD   ----------------------
CP + CS
Equation 5 can again be simplified considering only CS as an additional worst

condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time TS is always much
longer than the internal time constant:
Equation 6
 1   R SW + R AD   C S « T S
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the
voltage VA1 on the capacitance according to Equation 7:
Equation 7
V A1   C S + C P1 + C P2  = V A   C P1 + C P2 
 A second charge transfer involves also CF (that is typically bigger than the on-chip
capacitance) through the resistance RL: again considering the worst case in which CP2
and CS were in parallel to CP1 (since the time constant in reality would be faster), the
time constant is:
Equation 8
 2  R L   C S + C P1 + C P2 
In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time TS, a constraint on
RL sizing is obtained:
Equation 9
8.5   2 = 8.5  R L   C S + C P1 + C P2   TS
Of course, RL shall be sized also according to the current limitation constraints, in

combination with RS (source impedance) and RF (filter resistance). Being CF
definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the
charge transfer transient) will be much higher than VA1. Equation 10 must be respected
(charge balance assuming now CS already charged at VA1):
Equation 10
VA2   C S + C P1 + C P2 + C F  = V A  C F + V A1   C P1 + C P2 + C S 
The two transients above are not influenced by the voltage source that, due to the presence
of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on
78/105 DocID18340 Rev 6

CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with
respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
Figure 19. Spectral representation of input signal
Analog Source Bandwidth (VA)

TC 2 RFCF (Conversion Rate vs. Filter Pole)
Noise fF  f0 (Anti-aliasing Filtering Condition)

2 f0 fC (Nyquist)
f0 f
Anti-Aliasing Filter (fF = RC Filter pole) Sampled Signal Spectrum (fC = conversion Rate)
fF f f0 fC f
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of
the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be
at least 2f0; it means that the constant time of the filter is greater than or at least equal to
twice the conversion period (TC). Again the conversion period TC is longer than the
sampling time TS, which is just a portion of it, even when fixed channel continuous
conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it
is evident that the time constant of the filter RFCF is definitively much higher than the
sampling time TS, so the charge level on CS cannot be modified by the analog signal source
during the time in which the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce
the accuracy error due to the voltage drop on CS; from the two charge balance equations
above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS:
Equation 11
VA C P1 + C P2 + C F
---------
- = -------------------------------------------------------
-
V A2 C P1 + C P2 + C F + C S
From this formula, in the worst case (when VA is maximum, that is for instance 5 V),
assuming to accept a maximum error of half a count, a constraint is evident on CF value:
Equation 12
C F  2048  C S
DocID18340 Rev 6 79/105

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3.15.2 ADC conversion characteristics

Table 32. ADC conversion characteristics
Value
Min Typ Max
VSS_HV_AD VSS_HV_AD
VINAN SR Analog input voltage(2) — — V
0.3 + 0.3
ADC Clock frequency
(depends on ADC
fCK SR configuration) — 3(4) — 60 MHz
(The duty cycle depends on
AD_clk(3) frequency)
fs SR Sampling frequency — — — 1.53 MHz
fADC = 20 MHz,
125 — — ns
INPSAMP = 3
tADC_S D Sample time(5)
fADC = 9 MHz,
— — 28.2 µs
INPSAMP = 255
fADC = 20 MHz(7),
tADC_C P Conversion time(6) 0.650 — — µs
INPCMP = 1
ADC input sampling
CS(8) D — — — 2.5 pF
capacitance
CP1(8) D ADC input pin capacitance 1 — — — 3 pF
Internal resistance of analog VDD_HV_AD = 5 V ±10% — — 0.6 k

RSW1(8) D
source VDD_HV_AD = 3.3 V ±10% — — 3 k
Internal resistance of analog VDD_HV_AD = 5 V ±10% — — 2.15 k

RSW2(8) D
source VDD_HV_AD = 3.3 V ±10% — — 3.6 k
Internal resistance of analog
RAD(8) D — — — 2 k
source
Current injection on one ADC
input, different from the
IINJ T Input current injection –5 — 5 mA
converted one. Remains
within TUE spec.
INL P Integral Non Linearity No overload — ±1.5 — LSB
DNL P Differential Non Linearity No overload –1.0 — 1.0 LSB
OFS T Offset error — — ±1 — LSB
GNE T Gain error — — ±1 — LSB
Total unadjusted error
TUE P 16 precision channels –2.5 — 2.5 LSB
without current injection
80/105 DocID18340 Rev 6

Table 32. ADC conversion characteristics (continued)

Value
Min Typ Max
Total unadjusted error with

TUE T 16 precision channels –3 — 3 LSB
current injection
Total unadjusted error with
TUE T 10 standard channels –4 — 4 LSB
current injection
1. VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 °C to TA MAX, unless otherwise specified and analog input voltage from
VSS_HV_AD to VDD_HV_AD.
2. VINAN may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the conversion
will be clamped respectively to 0x000 or 0x3FF.
3. AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
4. When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost.
5. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the
sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample
clock tADC_S depend on programming.
6. This parameter includes the sample time tADC_S.
7. 20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.
8. See Figure 16.
3.16 Flash memory electrical characteristics

Table 33. Program and erase specifications
Value
Initial
Min Typ(1) Max(3)
max(2)
Twprogram P Word Program (32 bits) Time(4) Data Flash — 30 70 500 µs

Tdwprogram P Double Word (64 bits) Program Time(4) Code Flash — 18 50 500 µs
P Bank Program (64 KB)(4), (5) Data Flash — 0.49 1.2 4.1 s
TBKPRG
P Bank Program (1056 KB)(4), (5) Code Flash — 2.6 6.6 66 s
TMDPRG P Module Program (512 KB)(4) Code Flash — 1.3 1.65 33 s
Code Flash 200 500
T16kpperase P 16 KB Block Pre-program and Erase Time — 5000 ms
Data Flash 700 800
T32kpperase P 32 KB Block Pre-program and Erase Time Code Flash — 300 600 5000 ms
Code Flash 20
tESRT P Erase Suspend Request Rate(6) — — — ms
Data Flash 10
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
DocID18340 Rev 6 81/105

104
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
5. Typical bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will require
more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).
6. Time between erase suspend resume and next erase suspend.
Table 34. Flash memory module life

Value
Min Typ
Number of program/erase cycles per block

P/E C for 16 KB blocks over the operating — 100000 100000 cycles
temperature range (TJ)
Blocks with 0 – 1000
20 — years
P/E cycles
Minimum data retention at 85 °C average Blocks with 10000 P/E
Retention C 10 — years
ambient temperature(1) cycles
Blocks with 100000 P/E
5 — years
cycles
1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature
range.
Table 35. Flash read access timing

Symbol C Parameter Conditions(1) Max Unit
Maximum working frequency for Code Flash 2 wait states 66

Fmax C MHz
at given number of WS in worst conditions 0 wait states 22
Maximum working frequency for Data Flash at
Fmax C 8 wait states 66 MHz
given number of WS in worst conditions
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified.
82/105 DocID18340 Rev 6

3.17 AC specifications
3.17.1 Pad AC specifications
Table 36. Output pin transition times
Value
Min Typ Max
D CL = 25 pF — — 50
VDD = 5.0 V ± 10%,
T CL = 50 pF — — 100
PAD3V5V = 0
D Output transition time output pin(2) CL = 100 pF — — 125
Ttr CC  ns
D SLOW configuration CL = 25 pF — — 40
VDD = 3.3 V ± 10%,
T CL = 50 pF — — 50
PAD3V5V = 1
D CL = 100 pF — — 75
D CL = 25 pF — — 10
VDD = 5.0 V ± 10%,
T CL = 50 pF PAD3V5V = 0 — — 20
SIUL.PCRx.SRC = 1
D Output transition time output pin(2) CL = 100 pF — — 40
Ttr CC ns
D MEDIUM configuration CL = 25 pF — — 12
VDD = 3.3 V ± 10%,
T CL = 50 pF PAD3V5V = 1 — — 25
SIUL.PCRx.SRC = 1
D CL = 100 pF — — 40
CL = 25 pF — — 4
VDD = 5.0 V ± 10%,
CL = 50 pF PAD3V5V = 0 — — 6
SIUL.PCRx.SRC = 1
Output transition time output pin(2) CL = 100 pF — — 12
Ttr CC D ns
FAST configuration CL = 25 pF — — 4
VDD = 3.3 V ± 10%,
CL = 50 pF PAD3V5V = 1 — — 7
SIUL.PCRx.SRC = 1
CL = 100 pF — — 12
Symmetric, same drive strength VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 4

Tsim(3) CC T ns
between N and P transistor VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 5
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified.
2. CL includes device and package capacitances (CPKG < 5 pF).
3. Transition timing of both positive and negative slopes will differ maximum 50 %.
3.18 AC timing characteristics
3.18.1 RESET pin characteristics

The SPC56xP54x/SPC56xP60x implements a dedicated bidirectional RESET pin.
DocID18340 Rev 6 83/105

104
Figure 20. Start-up reset requirements(g)
VDD
VDDMIN
VRESET
VIH
VIL
device reset forced by VRESET device start-up phase
TPOR
Figure 21. Noise filtering on reset signal
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by filtered by filtered by unknown reset
hysteresis lowpass filter lowpass filter state device under hardware reset
WFRST WFRST
WNFRST
g. The output drive provided is open drain and hence must be terminated by an external resistor of value 1 k
84/105 DocID18340 Rev 6

Table 37. RESET electrical characteristics

Value
Min Typ Max
Input High Level CMOS

VIH SR P — 0.65VDD — VDD+0.4 V
(Schmitt Trigger)
Input low Level CMOS
VIL SR P — 0.4 — 0.35VDD V
(Schmitt Trigger)
Input hysteresis CMOS
VHYS CC C — 0.1VDD — — V
(Schmitt Trigger)
Push Pull, IOL = 2mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD
(recommended)
VOL CC P Output low level — — 0.1VDD V
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 0.5
(recommended)
CL = 25pF,
— — 10
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 50pF,
— — 20
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 100pF,
Output transition time — — 40
VDD = 5.0 V ± 10%, PAD3V5V = 0
Ttr CC D output pin(3) ns
MEDIUM configuration CL = 25pF,
— — 12
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL = 50pF,
— — 25
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL = 100pF,
— — 40
VDD = 3.3 V ± 10%, PAD3V5V = 1
WFRST SR P RESET input filtered pulse — — — 40 ns
RESET input not filtered
WNFRST SR P — 500 — — ns
pulse
maximum delay before
internal reset is released
TPOR CC D Monotonic VDD_HV supply ramp — — 1 ms
after all VDD_HV reach
nominal supply
VDD = 3.3 V ± 10%, PAD3V5V = 1 10 — 150
Weak pull-up current
|IWPU| CC P VDD = 5.0 V ± 10%, PAD3V5V = 0 10 — 150 µA
absolute value
VDD = 5.0 V ± 10%, PAD3V5V = 1(4) 10 — 250
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified.
2. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of device
reference manual).
3. CL includes device and package capacitance (CPKG < 5 pF).
4. The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
DocID18340 Rev 6 85/105

104
3.18.2 IEEE 1149.1 interface timing
Table 38. JTAG pin AC electrical characteristics

No. Symbol C Parameter Conditions Min Max Unit
1 tJCYC CC D TCK cycle time — 100 — ns

2 tJDC CC D TCK clock pulse width (measured at VDD_HV_IOx/2) — 40 60 ns
3 tTCKRISE CC D TCK rise and fall times (40% – 70%) — — 3 ns
4 tTMSS, tTDIS CC D TMS, TDI data setup time — 5 — ns
5 tTMSH, tTDIH CC D TMS, TDI data hold time — 25 — ns
6 tTDOV CC D TCK low to TDO data valid — — 40 ns
7 tTDOI CC D TCK low to TDO data invalid — 0 — ns
8 tTDOHZ CC D TCK low to TDO high impedance — 40 — ns
9 tBSDV CC D TCK falling edge to output valid — — 50 ns
10 tBSDVZ CC D TCK falling edge to output valid out of high impedance — — 50 ns
11 tBSDHZ CC D TCK falling edge to output high impedance — — 50 ns
12 tBSDST CC D Boundary scan input valid to TCK rising edge — 50 — ns
13 tBSDHT CC D TCK rising edge to boundary scan input invalid — 50 — ns
Figure 22. JTAG test clock input timing
TCK
2
3 2
1 3
86/105 DocID18340 Rev 6

Figure 23. JTAG test access port timing
TCK
TMS, TDI
7 8
TDO
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104
Figure 24. JTAG boundary scan timing
TCK
9 11
Output
Signals
10
Output
Signals
12
13
Input
Signals
3.18.3 Nexus timing
Table 39. Nexus debug port timing(1)

Value
No. Symbol C Parameter Unit
Min Typ Max
1 tMCYC CC D MCKO cycle time 32 — — ns

–
2 tMDOV CC D MCKO edge to MDO data valid — 0.25 × tMCYC ns
0.1 × tMCYC
–
3 tMSEOV CC D MCKO edge to MSEO data valid — 0.25 × tMCYC ns
0.1 × tMCYC
–
4 tEVTOV CC D MCKO edge to EVTO data valid — 0.25 × tMCYC ns
0.1 × tMCYC
5 tTCYC CC D TCK cycle time 64(2) — — ns
88/105 DocID18340 Rev 6

Table 39. Nexus debug port timing(1) (continued)

Value
No. Symbol C Parameter Unit
Min Typ Max
tNTDIS CC D TDI data setup time 6 — — ns

6
tNTMSS CC D TMS data setup time 6 — — ns
tNTDIH CC D TDI data hold time 10 — — ns
7
tNTMSH CC D TMS data hold time 10 — — ns
8 tTDOV CC D TCK low to TDO data valid — — 35 ns
9 tTDOI CC D TCK low to TDO data invalid 6 — — ns
1. All values need to be confirmed during device validation.
2. Lower frequency is required to be fully compliant to standard.
Figure 25. Nexus output timing
MCKO
4
MDO
MSEO Output Data Valid
EVTO
Figure 26. Nexus event trigger and test clock timings
TCK
EVTI
EVTO 5
DocID18340 Rev 6 89/105

104
Figure 27. Nexus TDI, TMS, TDO timing
TCK
TMS, TDI
9
8
TDO
3.18.4 External interrupt timing (IRQ pin)
Table 40. External interrupt timing(1)

1 tIPWL CC D IRQ pulse width low — 4 — tCYC

2 tIPWH CC D IRQ pulse width high — 4 — tCYC
3 tICYC CC D IRQ edge to edge time(2) — 4 + N (3) — tCYC
1. IRQ timing specified at fSYS = 64 MHz and VDD_HV_IOx = 3.0 V to 5.5 V, TA = TL to TH, and CL = 200pF with SRC = 0b00.
2. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
3. N= ISR time to clear the flag.
90/105 DocID18340 Rev 6

Figure 28. External interrupt timing
IRQ
2
3
3.18.5 DSPI timing
Table 41. DSPI timing(1)

Master (MTFE = 0) 60 —
1 tSCK CC D DSPI cycle time ns
Slave (MTFE = 0) 60 —
2 tCSC CC D PCS to SCK delay — 16 — ns
3 tASC CC D After SCK delay — 26 — ns
4 tSDC CC D SCK duty cycle — 0.4 × tSCK 0.6 × tSCK ns
5 tA CC D Slave access time SS active to SOUT valid — 30 ns
SS inactive to SOUT High-Z or
6 tDIS CC D Slave SOUT disable time — 16 ns
invalid
7 tPCSC CC D PCSx to PCSS time — 13 — ns
8 tPASC CC D PCSS to PCSx time — 13 — ns
Master (MTFE = 0) 35 —
Slave 4 —
9 tSUI CC D Data setup time for inputs ns
Master (MTFE = 1, CPHA = 0) 35 —
Master (MTFE = 0) –5 —
Slave 4 —
10 tHI CC D Data hold time for inputs ns
Master (MTFE = 1, CPHA = 1) –5 —
Master (MTFE = 0) — 12
Slave — 36
11 tSUO CC D Data valid (after SCK edge) ns
Master (MTFE = 1, CPHA = 0) — 12
Master (MTFE = 1, CPHA = 1) — 12
DocID18340 Rev 6 91/105

104
Table 41. DSPI timing(1) (continued)

Master (MTFE = 0) –2 —
Slave 6 —
12 tHO CC D Data hold time for outputs ns
Master (MTFE = 1, CPHA = 1) –2 —
1. All timing are provided with 50pF capacitance on output, 1ns transition time on input signal
Figure 29. DSPI classic SPI timing — master, CPHA = 0
2 3
PCSx
4 1
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
SIN First Data Data Last Data
12 11
SOUT First Data Data Last Data
92/105 DocID18340 Rev 6

Figure 30. DSPI classic SPI timing — master, CPHA = 1
CSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
12 11
Figure 31. DSPI classic SPI timing — slave, CPHA = 0
3
2
SS
1
SCK Input 4
(CPOL=0)
4
SCK Input
(CPOL=1)
5 11
12 6
9
10
DocID18340 Rev 6 93/105

104
Figure 32. DSPI classic SPI timing — slave, CPHA = 1
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5 6
12
9
10
Figure 33. DSPI modified transfer format timing — master, CPHA = 0
3
PCSx
4 1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9 10
12 11
94/105 DocID18340 Rev 6

Figure 34. DSPI modified transfer format timing — master, CPHA = 1
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
12 11
Figure 35. DSPI modified transfer format timing — slave, CPHA = 0
3
2
SS
SCK Input
(CPOL=0)
4 4
SCK Input
(CPOL=1)
11 12 6
5
9 10
DocID18340 Rev 6 95/105

104
Figure 36. DSPI modified transfer format timing — slave, CPHA = 1
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5 6
12
9
10
Figure 37. DSPI PCS strobe (PCSS) timing
7 8
PCSS
PCSx
96/105 DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Package characteristics
4 Package characteristics
4.1 ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.2 Package mechanical data
4.2.1 LQFP144 mechanical outline drawing
Figure 38. LQFP144 package mechanical drawing

Seating plane
C
A A2 A1 c
b
0.25 mm
gage plane
ccc C
k
D
D1 A1 L
D3 L1
108 73
72
109
E3 E1 E
144
37
Pin 1 1 36
identification ME_1A
e
DocID18340 Rev 6 97/105

104
Package characteristics SPC56xP54x, SPC56xP60x
Table 42. LQFP144 mechanical data

mm inches(1)
Symbol
Min Typ Max Min Typ Max
A — — 1.600 — — 0.0630
A1 0.050 — 0.150 0.0020 — 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 — 0.200 0.0035 — 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.8740
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 — 17.500 — — 0.6890 —
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 — 17.500 — — 0.6890 —
e — 0.500 — — 0.0197 —
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 — 1.000 — — 0.0394 —
k 0.0 ° 3.5 ° 7.0° 3.5 ° 0.0 ° 7.0 °
(2)
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Tolerance.
98/105 DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Package characteristics
4.2.2 LQFP100 mechanical outline drawing
Figure 39. LQFP100 package mechanical drawing
0.25 mm
0.10 inch
GAGE PLANE
D
L
D1
D3 L1
75 51 C
76 50
E3 E1 E
100 26
Pin 1 1 25
ccc C
identification
e
A1
A2
A
SEATING PLANE C
1L_ME
Table 43. LQFP100 mechanical data

mm inches(1)
Symbol
A — — 1.600 — — 0.0630
A1 0.050 — 0.150 0.0020 — 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
DocID18340 Rev 6 99/105

104
Package characteristics SPC56xP54x, SPC56xP60x
Table 43. LQFP100 mechanical data (continued)

mm inches(1)
Symbol
b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 — 0.200 0.0035 — 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 — 12.000 — — 0.4724 —
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 — 12.000 — — 0.4724 —
e — 0.500 — — 0.0197 —
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 — 1.000 — — 0.0394 —
k 0.0 ° 3.5 ° 7.0 ° 0.0 ° 3.5 ° 7.0 °
ccc(2) 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Tolerance.
100/105 DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Ordering information
5 Ordering information
Figure 40. Ordering information scheme(h)

Example code:
Product identifier Core Family Memory Package Temperature Custom vers. Conditioning
SPC56 A P 60 L3 C EFA Y
Y = Tray
R = Tape and Reel
X = Tape and Reel 90°

A = 5 V, 64 MHz
B = 3,3 V, 64 MHz

A = “Airbag” feature set
F = “Full feature” set

E = Data flash memory

B = –40 to 105 °C
C = –40 to 125 °C

L5 = LQFP144
L3 = LQFP100

60 = 1 MB
54 = 768 KB

P = SPC56xP54x/SPC56xP60x family

A = Dual core e200z0h
0 = Single core e200z0h

SPC56 = Power Architecture in 90nm
h. Not all configurations are available on the market. Please contact your ST sales representative to get the list of
orderable commercial part number.
DocID18340 Rev 6 101/105

104
Revision history SPC56xP54x, SPC56xP60x
6 Revision history
Table 44 summarizes revisions to this document.
Table 44. Document revision history

Date Revision Substantive changes
21-Dec-2010 1 Initial release

In the Feature list: 
Revised the first bullet.
Changed “Up to 82 GPIO” to “Up to 80 GPIO”
Changed “and 82 GPIO” to “and 49 GPIO”
Changed “FlexRay module“ to “1 FlexRay™ module”.
Added Section 1.5: Feature details
Table 4: SPC56xP54x/SPC56xP60x series block summary, added
FlexRay entry.
In the “LQFP176 pinout (top view)” figure:
– Pin 104 now is TDI, was PB[5]
– Pin 107 now is TDO, was PB[4]
– Pin 71 now is NC, was OKOUT
– Pin 72 now is NC, was OKOUT_B
– Pin 87 now is NC, was NBYPASS_HV
– Pin 88 now is NC, was IPP_LIVI_B_VDDIO
Table 7: Pin muxing:
PB[6] was clk_out_div5, is now clk_out_div256
Removed PB[4] and PB[5] rows
In the A[3] row, changed ABS[2] to ABS[1]
Section 3.11: DC electrical characteristics, added “Peripherals supply
18-Oct-2011 2 current (5 V and 3.3 V)” table
Table 14: EMI testing specifications, removed all references to SAE
Replaced both Table 12: Thermal characteristics for 144-pin LQFP and
Table 13: Thermal characteristics for 100-pin LQFP
Table 30: PLLMRFM electrical specifications (VDDPLL = 1.08 V to
1.32 V, VSS = VSSPLL = 0 V, TA = TL to TH), changed the max value
of fSYS from 120 to 64
Table 33: Program and erase specifications:
Removed all TBC
changed the initial max value of TBKPRG (Code Flash) from 3.3 to
6.6 s
changed the max value of TBKPRG (Data Flash) from 1.9 to 4.1 s
changed the max value of Twprogram (Data Flash) from 300 to 500 µs
Added tESRT row
Table 17: Voltage regulator electrical characteristics, updated
VDD_LV_REGCOR values
Updated Table 18: Low voltage monitor electrical characteristics
Updated Table 21: Supply current (5.0 V, NVUSRO[PAD3V5V]=0) and
Table 23: Supply current (3.3 V, NVUSRO[PAD3V5V]=1)
Removed “NVUSRO[OSCILLATOR_MARGIN] field description”
section.
Removed orderable parts tables.
102/105 DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Revision history
Table 44. Document revision history (continued)

Removed “Enhanced Full-featured” version.

In the cover page, added “(1 × Master/Slave, 1 × Master Only)“ at the
end of the bullet “2 LINFlex modules (LIN 2.1)”
Table 2: SPC56xP54x/SPC56xP60x device comparison, updated the
value of “LINFLEX module” to “2 (1 × Master/Slave, 1 × Master only)”
Section 1.5.4: On-chip flash memory with ECC
replaced two occurrences of “3 wait states” to “2 wait states”
replaced 60 MHz to 64 MHz
Section 1.5.21: Serial communication interface module (LINFlex),
updated first bullet to “Supports LIN Master mode (on both modules),
LIN Slave mode (on one module) and UART mode”
Section 1.5.24: Analog-to-digital converter (ADC), removed bullet
concerning the analog watchdogs from Normal mode features.
Table 5: Supply pins, removed VREG_BYPASS row.
Table 6: System pins:
added VREG_BYPASS row
added a footnote about RESET
Table 9: Absolute maximum ratings:
changed typical value of TVDD to 0.25 and added a footnote
added VINAN entry
Updated Section 3.8.1: Voltage regulator electrical characteristics
Updated Table 14: EMI testing specifications
Table 18: Low voltage monitor electrical characteristics, changed
15-May-2012 3 maximum value of VMLVDDOK_H to 1.15
Table 20: DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0),
added IPU and IPD rows for RESET pin.
Table 21: Supply current (5.0 V, NVUSRO[PAD3V5V]=0):
added maximum values of IDD_LV_CORE for: RUN, HALT, and STOP
mode
updated values and parameter classification of IDD_FLASH
Table 22: DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1),
added IPU and IPD rows for RESET pin.
Table 23: Supply current (3.3 V, NVUSRO[PAD3V5V]=1):
added maximum values of IDD_LV_CORE for: RUN, HALT, and STOP
mode
updated values and parameter classification of IDD_FLASH
Added Table 26: I/O consumption
Table 31: 16 MHz RC oscillator electrical characteristics, changed
minimum and maximum values of RCMVAR respectively to -6 and 6.
Renamed Figure 16: Input equivalent circuit (precise channels) (was
“Input equivalent circuit”)
Added Figure 17: Input equivalent circuit (extended channels)
Section 3.15.1: Input impedance and ADC accuracy, updated Equation
4 and Equation 10
Table 32: ADC conversion characteristics, added VINAN, CP3 and RSW2
rows
DocID18340 Rev 6 103/105

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Revision history SPC56xP54x, SPC56xP60x
Table 44. Document revision history (continued)

In the cover page, replaced “64 MHz, dual issue, 32-bit CPU core
complex” with “64 MHz, single issue, 32-bit CPU core complex”
Table 9: Absolute maximum ratings, updated TVDD entry
Table 22: DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1):
Updated conditions value of VOL_F to 11 mA
21-Nov-2012 4 Updated conditions value of VOH_F to – 11 mA
Table 24: Peripherals supply current (5 V and 3.3 V):
Replaced all occurrences of IDD_BV in this table with IDD_HV
Replaced all occurrences of VDD_BV in this table with
VDD_HV_REG.
Figure 40: Ordering information scheme, fixed typo in the footnote.
18-Sep-2013 5 Updated Disclaimer.
Added “AEC-Q10x qualified” in Features section.
In Table 2: SPC56xP54x/SPC56xP60x device comparison added
footnote “LinFlex_1 is Master Only.” related to row “LINFlex modules”
Updated Table 3: SPC56xP54x/SPC56xP60x device configuration
difference
Figure 2: LQFP176 pinout (top view):
– Changed PB[4] to TDO
– Changed PB[5] to TDI
– Changed pins 71,72 to NC
15-Jun-2016 6 – Changed pins 87,88 to NC
In Section 1.5.27: Nexus development interface (NDI), added note “At
least one TCK clock is necessary for the EVTI signal to be
recognized by the MCU.” for EVTI pin.
In Table 7: Pin muxing:
– Replaced “PCR register” with “PCR No.”
– Updated “CS3” with “CS3_4” function related to A[2] port pin
– In column “I/O direction”, added “O” for “DSPI_1” peripheral
– In “Functions” column related to D[12] port pin, changed DS7_1 to
CS7_1
104/105 DocID18340 Rev 6

IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
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SPC56AP60x, SPC56AP54x

 General purpose I/Os (80 GPIO + 26 GPI on

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Table 1. Device summary

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1.5.29 On-chip voltage regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 27

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5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

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Figure 1. SPC56xP54x/SPC56xP60x block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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1.1 Document overview

1.3 Device comparison

Table 2. SPC56xP54x/SPC56xP60x device comparison

Code Flash memory (with ECC) 768 KB 1 MB 768 KB 1 MB

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Table 2. SPC56xP54x/SPC56xP60x device comparison (continued)

Enhanced DMA (direct memory

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SPC56xP54x/SPC56xP60x is present on the market in two different options enabling

Table 3. SPC56xP54x/SPC56xP60x device configuration difference

FlexCAN (controller area network) 3 2 2

1.4 Block diagram

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Figure 1. SPC56xP54x/SPC56xP60x block diagram

e200z0 Core e200z0 Core

PMU 32-bit Variable 32-bit Variable

STM_0 Branch Branch STM_1

Memory protection unit MPU_0 Memory protection unit MPU_1

48KB 1024KB 4x16KB 32KB

SRAM code flash data flash SRAM

Peripheral Bus (IPS) Peripheral Bus (IPS)

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Table 4. SPC56xP54x/SPC56xP60x series block summary

Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter

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Table 4. SPC56xP54x/SPC56xP60x series block summary (continued)

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1.5 Feature details

1.5.1 High performance e200z0h core processor

1.5.2 Crossbar switch (XBAR)

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The crossbar provides the following features:

1.5.3 Enhanced direct memory access (eDMA)

1.5.4 On-chip flash memory with ECC

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The flash memory module provides the following features:

1.5.5 On-chip SRAM with ECC

1.5.6 Interrupt controller (INTC)

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1.5.7 System clocks and clock generation

1.5.8 Frequency modulated phase-locked loop (FMPLL)

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 Triangle wave modulation