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    Ect206-Qp June21

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    Rajeena Vasudevan
    This document is a two page exam paper for a Fourth Semester B.Tech Degree Examination in Computer Architecture and Microcontrollers. It contains 20 multiple choice questions across 5 modules related to computer architecture, processors, memory systems, microcontrollers, and interfacing. The questions assess knowledge of topics like RISC vs CISC processors, floating point representations, 8051 memory organization, timers, serial communication, ARM architecture, cache mapping, and memory hierarchies. Students are required to answer all questions in Part A and choose one full question from each module in Part B.

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    Ect206-Qp June21

    Uploaded by

    Rajeena Vasudevan
    61 views2 pages
    This document is a two page exam paper for a Fourth Semester B.Tech Degree Examination in Computer Architecture and Microcontrollers. It contains 20 multiple choice questions across 5 modules related to computer architecture, processors, memory systems, microcontrollers, and interfacing. The questions assess knowledge of topics like RISC vs CISC processors, floating point representations, 8051 memory organization, timers, serial communication, ARM architecture, cache mapping, and memory hierarchies. Students are required to answer all questions in Part A and choose one full question from each module in Part B.

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    ECT206-QP_JUNE21

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    This document is a two page exam paper for a Fourth Semester B.Tech Degree Examination in Computer Architecture and Microcontrollers. It contains 20 multiple choice questions across 5 modules related to computer architecture, processors, memory systems, microcontrollers, and interfacing. The questions assess knowledge of topics like RISC vs CISC processors, floating point representations, 8051 memory organization, timers, serial communication, ARM architecture, cache mapping, and memory hierarchies. Students are required to answer all questions in Part A and choose one full question from each module in Part B.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    61 views2 pages

    Ect206-Qp June21

    Uploaded by

    Rajeena Vasudevan
    This document is a two page exam paper for a Fourth Semester B.Tech Degree Examination in Computer Architecture and Microcontrollers. It contains 20 multiple choice questions across 5 modules related to computer architecture, processors, memory systems, microcontrollers, and interfacing. The questions assess knowledge of topics like RISC vs CISC processors, floating point representations, 8051 memory organization, timers, serial communication, ARM architecture, cache mapping, and memory hierarchies. Students are required to answer all questions in Part A and choose one full question from each module in Part B.

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    You are on page 1of 2

    D 02000ECT206052102 Pages: 2

    Reg No.:_______________ Name:__________________________


    APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
    Fourth Semester B.Tech Degree Examination July 2021 (2019 Scheme)

    Course Code: ECT206


    Course Name: COMPUTER ARCHITECTURE AND MICROCONTROLLERS
    Max. Marks: 100 Duration: 3 Hours
    PART A
    (Answer all questions; each question carries 3 marks) Marks
    1 Explain the significance of accumulator, program counter and stack pointer in 3
    processor operation.
    2 List the difference between RISC and CISC processors. 3
    3 Describe the function of Program status word (PSW) in 8051 microcontroller. 3
    4 List the interrupts of 8051 and its ROM locations. 3
    5 Write an 8051 C program to send values 00-FF to port P1. 3
    6 Write an 8051assembly language program to add two 8bit numbers stored in 3
    external RAM memory.
    7 Explain the procedure of doubling the baud rate of data transfer in 8051 serial 3
    communication.
    8 Assume XTAL=11.0592. Compute the value to be loaded into TH0 and TL0 3
    (mode 1) to incorporate a time delay of 5ms.
    9 Explain ‘Locality of reference’ in Cache memory system. 3
    10 Differentiate SRAM and DRAM memory cells. 3
    PART B
    (Answer one full question from each module, each question carries 14 marks)
    Module -1
    11 a) Illustrate the algorithm for division of two 4 bit signed binary numbers, -6/4. 8
    Write the algorithm or draw the flowchart also.
    b) Explain the basic operations of a general processor in executing an instruction. 6
    12 a) Write down the range of numbers that can be represented using IEEE 754 8
    single precision floating point representation. How do we represent zero,
    infinity and 49 in IEEE 754 format.
    b) Draw the internal architecture of a general processor and explain the various 6
    components.

    Page 1 of 2
    02000ECT206052102

    Module -2
    13 a) Explain the RAM memory organization of 8051microcontroller using a 9
    schematic diagram. Also list the 8051 Special function registers and its
    functions.
    b) What is stack? Explain the role of stack in program execution during a CALL 5
    instruction.
    14 a) Explain about the ports of 8051 and also illustrate the Port 0 circuit read and 8
    write operation.
    b) Explain the ‘Rotate’ instructions used in 8051 microcontroller. 6
    Module -3
    15 a) Write an 8051 assembly language program to sort the ten numbers stored in 8
    memory locations 30H to 39H in ascending order. Comment all lines of the
    program.
    b) Write an 8051 C code to convert the analog input provided to ADC chip to the 6
    digital value and store the result in memory location.
    16 a) Write an 8051 C program to send letters ‘M’, ‘D’ to LCD using delays. 7
    b) Using a schematic diagram explain the procedure of interfacing KEYBOARD 7
    to 8051 microcontroller.
    Module -4
    17 a) Explain the characteristics and operations of mode 1 programming of Timers in 6
    8051 microcontroller.
    b) Explain the steps to transfer data serially in 8051. 8
    Write an 8051 assembly language program to transfer ‘Y’ serially at baud rate
    9600 continuously through Port 0.
    18 a) Explain ARM 7 register architecture. 8
    b) Explain the operation of a) Assembler b) compiler c) Debugger 6
    Module -5
    19 a) Explain programmed I/O and interrupt driven I/O for data transfer in 8
    computers.
    b) Explain RAM and ROM memory chips. 6
    20 a) Explain associative mapping of cache memory for a 4K cache with block size 8
    128 and word size 16. Draw necessary figures. Specify the main memory
    address.
    b) Explain the memory hierarchy model using a layout diagram. 6
    *****

    Page 2 of 2

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