HEF4020B

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HEF4020B

14-stage binary counter


Rev. 11 — 7 December 2021 Product data sheet

1. General description
The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The
counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages
and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle
flip-flop. Inputs include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess of VDD.

2. Features and benefits


• Wide supply voltage range from 3.0 V to 15.0 V
• CMOS low power dissipation
• High noise immunity
• High speed operation
• Fully static operation
• 5 V, 10 V, and 15 V parametric ratings
• Standardized symmetrical output characteristics
• Complies with JEDEC standard JESD 13-B
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-B exceeds 200 V
• Specified from -40 °C to +85 °C

3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
HEF4020BT -40 °C to +85 °C SO16 plastic small outline package; 16 leads; SOT109-1
body width 3.9 mm
Nexperia HEF4020B
14-stage binary counter

4. Functional diagram

10
CP T
11 14-STAGE COUNTER
MR CD

9 7 5 4 6 13 12 14 15 1 2 3

Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13


001aad722

Fig. 1. Functional diagram

CTR14
Q0 9 + 0 9
10
Q3 7 7
11 CT
Q4 5 5
Q5 4 4
10 CP
Q6 6 6
Q7 13 13
CT
Q8 12 12
Q9 14 14
11 MR
Q10 15 15
Q11 1 1
Q12 2 2
Q13 3 13 3

001aad723 001aad724

Fig. 2. Logic symbol Fig. 3. IEC Logic symbol

Q Q Q Q Q Q Q
FF FF FF FF FF FF FF
CP T 0 T 1 T 2 T 3 T 4 T 5 T 6

Q Q Q Q Q Q Q
RD RD RD RD RD RD RD

MR

Q0 Q3 Q4 Q5 Q6

Q Q Q Q Q Q Q
FF FF FF FF FF FF FF
T 7 T 8 T 9 T 10 T 11 T 12 T 13

Q Q Q Q Q Q Q
RD RD RD RD RD RD RD

Q7 Q8 Q9 Q10 Q11 Q12 Q13

001aad725

Fig. 4. Logic diagram

HEF4020B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 11 — 7 December 2021 2 / 11


Nexperia HEF4020B
14-stage binary counter

5. Pinning information

5.1. Pinning
HEF4020B

Q11 1 16 VDD

Q12 2 15 Q10

Q13 3 14 Q9

Q5 4 13 Q7

Q4 5 12 Q8

Q6 6 11 MR

Q3 7 10 CP

VSS 8 9 Q0

001aaj101

Fig. 5. Pin configuration SOT109-1 (SO16)

5.2. Pin description


Table 2. Pin description
Symbol Pin Description
Q3, Q4, Q5, Q6, Q7, Q8, 7, 5, 4, 6, 13, 12, parallel output (Q3 to Q13)
Q9, Q10, Q11, Q12, Q13 14, 15, 1, 2, 3
VSS 8 ground supply voltage
Q0 9 parallel output
CP 10 clock input (HIGH-to-LOW edge triggered)
MR 11 master reset input (active HIGH)
VDD 16 supply voltage

6. Functional description
Table 3. Functional table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition; ↓ = negative-going transition.
Input Output
CP MR Q0, Q3 to Q13
↑ L no change
↓ L count
X H L

HEF4020B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 11 — 7 December 2021 3 / 11


Nexperia HEF4020B
14-stage binary counter

1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384


CP input

MR input

Q0

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Q13
001aad726

Fig. 6. Timing diagram

7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage -0.5 +18 V
IIK input clamping current VI < -0.5 V or VI > VDD + 0.5 V - ±10 mA
VI input voltage -0.5 VDD + 0.5 V
IOK output clamping current VO < -0.5 V or VO > VDD + 0.5 V - ±10 mA
II/O input/output current - ±10 mA
IDD supply current - 50 mA
Tstg storage temperature -65 +150 °C
Tamb ambient temperature -40 +85 °C
Ptot total power dissipation Tamb -40 °C to +85 °C - 500 mW
P power dissipation per output - 100 mW

8. Recommended operating conditions


Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3 - 15 V
VI input voltage 0 - VDD V
Tamb ambient temperature in free air -40 - +85 °C
Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V
VDD = 10 V - - 0.5 μs/V
VDD = 15 V - - 0.08 μs/V

HEF4020B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 11 — 7 December 2021 4 / 11


Nexperia HEF4020B
14-stage binary counter

9. Static characteristics
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Unit
Min Max Min Max Min Max
VIH HIGH-level input voltage |IO| < 1 μA 5V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage |IO| < 1 μA 5V - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
VOH HIGH-level output voltage |IO| < 1 μA 5V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level output voltage |IO| < 1 μA 5V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level output current VO = 2.5 V 5V - -1.7 - -1.4 - -1.1 mA
VO = 4.6 V 5V - -0.52 - -0.44 - -0.36 mA
VO = 9.5 V 10 V - -1.3 - -1.1 - -0.9 mA
VO = 13.5 V 15 V - -3.6 - -3.0 - -2.4 mA
IOL LOW-level output current VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA
II input leakage current 15 V - ±0.3 - ±0.3 - ±1.0 μA
IDD supply current IO = 0 A 5V - 20 - 20 - 150 μA
10 V - 40 - 40 - 300 μA
15 V - 80 - 80 - 600 μA
CI input capacitance - - - - 7.5 - - pF

HEF4020B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 11 — 7 December 2021 5 / 11


Nexperia HEF4020B
14-stage binary counter

10. Dynamic characteristics


Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; for test circuit see Fig. 8.
Symbol Parameter Conditions VDD Extrapolation formula [1] Min Typ Max Unit
tPHL HIGH to LOW CP to Q0; 5V 78 ns + (0.55 ns/pF)CL - 105 210 ns
propagation delay see Fig. 7 10 V 34 ns + (0.23 ns/pF)CL - 45 90 ns
15 V 22 ns + (0.16 ns/pF)CL - 30 65 ns
Qn to Qn + 1 5V 53 ns + (0.55 ns/pF)CL - 80 160 ns
10 V 19 ns + (0.23 ns/pF)CL - 30 60 ns
15 V 12 ns + (0.16 ns/pF)CL - 20 40 ns
MR to Qn; 5V 153 ns + (0.55 ns/pF)CL - 180 360 ns
see Fig. 7 10 V 79 ns + (0.23 ns/pF)CL - 90 180 ns
15 V 62 ns + (0.16 ns/pF)CL - 70 140 ns
tPLH LOW to HIGH CP to Q0; 5V 78 ns + (0.55 ns/pF)CL - 105 210 ns
propagation delay see Fig. 7 10 V 39 ns + (0.23 ns/pF)CL - 50 95 ns
15 V 27 ns + (0.16 ns/pF)CL - 35 70 ns
Qn to Qn + 1 5V 43 ns + (0.55 ns/pF)CL - 70 140 ns
10 V 14 ns + (0.23 ns/pF)CL - 25 50 ns
15 V 12 ns + (0.16 ns/pF)CL - 20 40 ns
tt transition time see Fig. 7 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns
10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns
15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns
tW pulse width CP = HIGH; 5V 50 25 - ns
minimum width; 10 V 25 15 - ns
see Fig. 7
15 V 20 10 - ns
MR = HIGH; 5V 130 65 - ns
minimum width; 10 V 95 50 - ns
see Fig. 7
15 V 90 45 - ns
trec recovery time MR input; 5V 115 60 - ns
see Fig. 7 10 V 65 35 - ns
15 V 55 25 - ns
fmax maximum frequency see Fig. 7 5V 5 10 - MHz
10 V 13 25 - MHz
15 V 18 35 - MHz

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

Table 8. Dynamic power dissipation PD


PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter VDD Typical formula for PD (μW) where:
2
PD dynamic power 5 V PD = 600 × fi + ∑(fo × CL) × VDD fi = input frequency in MHz,
dissipation 10 V PD = 2800 × fi + ∑(fo × CL) × VDD
2 fo = output frequency in MHz,
2
CL = output load capacitance in pF,
15 V PD = 8200 × fi + ∑(fo × CL) × VDD VDD = supply voltage in V,
∑(fo × CL) = sum of the outputs.

HEF4020B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 11 — 7 December 2021 6 / 11


Nexperia HEF4020B
14-stage binary counter

10.1. Waveforms and test circuit


VI
MR INPUT VM
VSS
tW
trec 1/fmax
VI
CP INPUT VM
VSS
tW
tPHL tPLH tPHL
VOH
Q0 or Qn
OUTPUT VM
VOL
tt tt
001aae591

Measurement points are given in Table 9.


Fig. 7. Propagation delays, minimum pulse widths, transition and recovery times and maximum clock frequency

Table 9. Measurement points


Supply voltage Input Output
VDD VM VM
5 V to 15 V 0.5VDD 0.5VDD

tW
VI
90 % 90 %
negative
pulse VM VM
10 % 10 %
0V
tf tr VDD

tr tf VI VO
VI G
90 % 90 % DUT
positive
pulse VM VM CL
RT
10 % 10 %
0V
tW
001aaj781 001aag182

a. Input waveforms b. Test circuit


Test data is given in Table 10.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig. 8. Test circuit for measuring switching times

Table 10. Test data


Supply voltage Input Load
VDD VI tr, tf CL
5 V to 15 V VSS or VDD ≤ 20 ns 50 pF

HEF4020B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 11 — 7 December 2021 7 / 11


Nexperia HEF4020B
14-stage binary counter

11. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

D E A
X

y HE v M A

16 9

Q
A2
(A 3) A
A1
pin 1 index
θ
Lp

1 8 L

e w M detail X
bp

0 2.5 5 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)


A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1
0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8
o
o
0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012

Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN


ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT109-1 076E07 MS-012
03-02-19

Fig. 9. Package outline SOT109-1 (SO16)

HEF4020B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 11 — 7 December 2021 8 / 11


Nexperia HEF4020B
14-stage binary counter

12. Abbreviations
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model

13. Revision history


Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4020B v.11 20211207 Product data sheet - HEF4020B v.10
Modifications: • Section 1 and Section 2 updated.
HEF4020B v.10 20181018 Product data sheet - HEF4020B v.9
Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
HEF4020B v.9 20160321 Product data sheet - HEF4020B v.8
Modifications: • Type number HEF4020BP (SOT38-4) removed.
HEF4020B v.8 20111118 Product data sheet - HEF4020B v.7
Modifications: • Legal pages updated.
• Changes in "General description" and "Features and benefits".
• Section "Applications" removed.
HEF4020B v.7 20111010 Product data sheet - HEF4020B v.6
HEF4020B v.6 20091127 Product data sheet - HEF4020B v.5
HEF4020B v.5 20090707 Product data sheet - HEF4020B v.4
HEF4020B v.4 20081204 Product data sheet - HEF4020B_CNV v.3
HEF4020B_CNV v.3 19950101 Product specification - HEF4020B_CNV v.2
HEF4020B_CNV v.2 19950101 Product specification - -

HEF4020B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 11 — 7 December 2021 9 / 11


Nexperia HEF4020B
14-stage binary counter
injury, death or severe property or environmental damage. Nexperia and its

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such equipment or applications and therefore such inclusion and/or use is at
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Quick reference data — The Quick reference data is an extract of the
Data sheet status product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
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[1][2] status [3] products are for illustrative purposes only. Nexperia makes no representation
Objective [short] Development This document contains data from or warranty that such applications will be suitable for the specified use
data sheet the objective specification for without further testing or modification.
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and products using Nexperia products, and Nexperia accepts no liability for
Preliminary [short] Qualification This document contains data from
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Draft — The document is a draft version only. The content is still under the Absolute Maximum Ratings System of IEC 60134) will cause permanent
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HEF4020B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 11 — 7 December 2021 10 / 11


Nexperia HEF4020B
14-stage binary counter

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description............................................................. 3
6. Functional description................................................. 3
7. Limiting values............................................................. 4
8. Recommended operating conditions..........................4
9. Static characteristics....................................................5
10. Dynamic characteristics............................................ 6
10.1. Waveforms and test circuit........................................ 7
11. Package outline.......................................................... 8
12. Abbreviations.............................................................. 9
13. Revision history..........................................................9
14. Legal information......................................................10

© Nexperia B.V. 2021. All rights reserved


For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 7 December 2021

HEF4020B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 11 — 7 December 2021 11 / 11

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