MC74HC4040A

12-Stage Binary Ripple

Counter
High−Performance Silicon−Gate CMOS
The MC74C4040A is identical in pinout to the standard CMOS http://onsemi.com
MC14040. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 12 master−slave flip−flops. The output of
each flip−flop feeds the next and the frequency at each output is half of SOIC−16 TSSOP−16
that of the preceding one. The state counter advances on the D SUFFIX DT SUFFIX
negative−going edge of the Clock input. Reset is asynchronous and CASE 751B CASE 948F
active−high.
PIN ASSIGNMENT
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject VCC Q11 Q10 Q8 Q9 Reset Clock Q1
to decoding spikes and may have to be gated with the Clock of the 16 15 14 13 12 11 10 9
HC4040A for some designs.

Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL 1 2 3 4 5 6 7 8
• Operating Voltage Range: 2.0 to 6.0 V Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND
• Low Input Current: 1 mA
16−Lead Package (Top View)
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements MARKING DIAGRAMS
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates 16 16
• NLV Prefix for Automotive and Other Applications Requiring HC40
HC4040AG 40A
Unique Site and Control Change Requirements; AEC−Q100 AWLYWW ALYWG
Qualified and PPAP Capable G
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant 1 1
SOIC−16 TSSOP−16

9 A = Assembly Location
Q1 L, WL = Wafer Lot
7
Q2 Y, YY = Year
6
Q3 W, WW = Work Week
5 G or G = Pb−Free Package
Q4
10 3 (Note: Microdot may be in either location)
Clock Q5
2
Q6
4 FUNCTION TABLE
Q7
13
Q8
12 Clock Reset Output State
Q9
14 L No Charge
Q10
15 L Advance to Next State
Q11
1 X H All Outputs Are Low
Q12
11 Pin 16 = VCC
Reset
Pin 8 = GND ORDERING INFORMATION
See detailed ordering and shipping information in the package
Figure 1. Logic Diagram dimensions section on page 6 of this data sheet.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

August, 2014 − Rev. 9 MC74HC4040A/D
 MC74HC4040A

MAXIMUM RATINGS
Symbol Parameter Value Unit This device contains protection
VCC DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V circuitry to guard against damage
due to high static voltages or electric
Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V fields. However, precautions must
Vout DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V be taken to avoid applications of any
voltage higher than maximum rated
Iin DC Input Current, per Pin ±20 mA
voltages to this high−impedance cir-
Iout DC Output Current, per Pin ±25 mA cuit. For proper operation, Vin and
ICC DC Supply Current, VCC and GND Pins ±50 mA Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
PD Power Dissipation in Still Air, SOIC Package† 500 mW Unused inputs must always be
TSSOP Package† 450 tied to an appropriate logic voltage
Tstg Storage Temperature Range –65 to +150 _C level (e.g., either GND or VCC).
Unused outputs must be left open.
TL Lead Temperature, 1 mm from Case for 10 Seconds _C
SOIC or TSSOP Package 260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature Range, All Package Types –55 +125 _C
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 2) VCC = 3.0 V 0 600
VCC = 4.5 V 0 500
VCC = 6.0 V 0 400
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V −55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High−Level Input Voltage Vout = 0.1V or VCC −0.1V 2.0 1.50 1.50 1.50 V
|Iout| ≤ 20mA 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low−Level Input Voltage Vout = 0.1V or VCC − 0.1V 2.0 0.50 0.50 0.50 V
|Iout| ≤ 20mA 3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH Minimum High−Level Output Voltage Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
|Iout| ≤ 20mA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.20
|Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 5.2mA 6.0 5.48 5.34 5.20
VOL Maximum Low−Level Output Voltage Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
|Iout| ≤ 20mA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 mA
Current (per Package) Iout = 0mA

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 MC74HC4040A

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V −55 to 25°C ≤85°C ≤125°C Unit
fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 10 9.0 8.0 MHz
(Figures 2 and 5) 3.0 15 14 12
4.5 30 28 25
6.0 50 45 40
tPLH, Maximum Propagation Delay, Clock to Q1* 2.0 96 106 115 ns
tPHL (Figures 2 and 5) 3.0 63 71 88
4.5 31 36 40
6.0 25 30 35
tPHL Maximum Propagation Delay, Reset to Any Q 2.0 65 72 90 ns
(Figures 3 and 5) 3.0 30 36 40
4.5 30 35 40
6.0 26 32 35
tPLH, Maximum Propagation Delay, Qn to Qn+1 2.0 69 80 90 ns
tPHL (Figures 4 and 5) 3.0 40 45 50
4.5 17 21 28
6.0 14 15 22
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 2 and 5) 3.0 27 32 36
4.5 15 19 22
6.0 13 15 19
Cin Maximum Input Capacitance 10 10 10 pF
* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n−1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n−1)] ns
VCC = 3.0 V: tP = [61.5 + 34.4 (n−1)] ns VCC = 6.0V: tP = [24.4 + 12 (n−1)] ns

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 31 pF

* Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC .

TIMING REQUIREMENTS (Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V −55 to 25°C ≤85°C ≤125°C Unit
trec Minimum Recovery Time, Reset Inactive to Clock 2.0 30 40 50 ns
(Figure 3) 3.0 20 25 30
4.5 5 8 12
6.0 4 6 9
tw Minimum Pulse Width, Clock 2.0 70 80 90 ns
(Figure 2) 3.0 40 45 50
4.5 15 19 24
6.0 13 16 20
tw Minimum Pulse Width, Reset 2.0 70 80 90 ns
(Figure 3) 3.0 40 45 50
4.5 15 19 24
6.0 13 16 20
tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns
(Figure 2) 3.0 800 800 800
4.5 500 500 500
6.0 400 400 400

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 MC74HC4040A

PIN DESCRIPTIONS

INPUTS OUTPUTS
Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)
Clock (Pin 10)
Negative−edge triggering clock input. A high−to−low Active−high outputs. Each Qn output divides the Clock
transition on this input advances the state of the counter. input frequency by 2N.

Reset (Pin 11)

Active−high reset. A high level applied to this input
asynchronously resets the counter to its zero state, thus
forcing all Q outputs low.

SWITCHING WAVEFORMS

tf tr VCC
VCC Clock 50%
90%
Clock 50% GND
10% trec
GND
tw tw
VCC
1/fMAX
tPLH tPHL Reset 50%
GND
90% tPHL
Q1 50%
10%
Any Q 50%
tTLH tTHL

Figure 2. Figure 3.

TEST
POINT

VCC
Qn OUTPUT
50%
DEVICE
GND UNDER
tPLH tPHL TEST CL*

Qn+1 50%

*Includes all probe and jig capacitance

Figure 4. Figure 5. Test Circuit

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 MC74HC4040A

Q1 Q2 Q3 Q10 Q11 Q12

9 7 6 14 15 1

10
Clock C Q C Q C Q C Q C Q C Q

C Q C Q C Q C Q C Q C

R R

11
Reset
Q4 = Pin 5 Q7 = Pin 4 VCC = Pin 16
Q5 = Pin 3 Q8 = Pin 13 GND = Pin 8
Q6 = Pin 2 Q9 = Pin 12

Figure 6. Expanded Logic Diagram

1 2 4 8 16 32 64 128 256 512 1024 2048 4096

Clock
Reset

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Figure 7. Timing Diagram

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 MC74HC4040A

APPLICATIONS INFORMATION

Time−Base Generator waveform and feeds the HC4040A. Selecting outputs Q5,
A 60Hz sinewave obtained through a 100 K resistor Q10, Q11, and Q12 causes a reset every 3600 clocks. The
connected to a 120 Vac power line through a step down HC20 decodes the counter outputs, produces a single
transformer is applied to the input of the MC54/74HC14A, (narrow) output pulse, and resets the binary counter. The
Schmitt-trigger inverter. The HC14A squares−up the input resulting output frequency is 1.0 pulse/minute.

VCC

1.0M HC4040A
13
Clock Q5
12 1.0 Pulse/Minute
1
≥20pF Q10 8 2 6 Output
120Vac 1/2 1/2
4
60Hz 10 HC20 HC20
5
Q11
9
Q12
NOTE: Ground MUST be isolated
by a transformer or
opto−isolator for safety
reasons.

Figure 8. Time−Base Generator

ORDERING INFORMATION
Device Package Shipping†
MC74HC4040ADG SOIC−16 48 Units / Rail
(Pb−Free)

MC74HC4040ADR2G SOIC−16 2500 Units / Reel

(Pb−Free)

NLV74HC4040ADR2G* SOIC−16 2500 Units / Reel

(Pb−Free)

MC74HC4040ADTR2G TSSOP−16 2500 Units / Reel

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.

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 MC74HC4040A

PACKAGE DIMENSIONS

TSSOP−16
CASE 948F
ISSUE B

16X K REF
NOTES:
0.10 (0.004) M T U S V S 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
0.15 (0.006) T U S K 2. CONTROLLING DIMENSION: MILLIMETER.

ÉÉÉ
ÇÇÇ
3. DIMENSION A DOES NOT INCLUDE MOLD
K1 FLASH. PROTRUSIONS OR GATE BURRS.

ÇÇÇ
ÉÉÉ
MOLD FLASH OR GATE BURRS SHALL NOT
16 9 EXCEED 0.15 (0.006) PER SIDE.
2X L/2 J1 4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
B SECTION N−N NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
L −U− DAMBAR PROTRUSION. ALLOWABLE
J
DAMBAR PROTRUSION SHALL BE 0.08
PIN 1
(0.003) TOTAL IN EXCESS OF THE K
IDENT. N DIMENSION AT MAXIMUM MATERIAL
1 8 0.25 (0.010) CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
M 7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
0.15 (0.006) T U S
A MILLIMETERS INCHES
N
−V− DIM MIN MAX MIN MAX
F A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
DETAIL E D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
C −W− H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
0.10 (0.004) K 0.19 0.30 0.007 0.012
H DETAIL E K1 0.19 0.25 0.007 0.010
−T− SEATING L 6.40 BSC 0.252 BSC
PLANE D G
M 0_ 8_ 0_ 8_

SOLDERING FOOTPRINT*

7.06

0.65
PITCH

16X 16X
0.36
1.26 DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 MC74HC4040A

PACKAGE DIMENSIONS

SOIC−16
CASE 751B−05
ISSUE K
−A− NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
16 9 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
−B− P 8 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
1 8
0.25 (0.010) M B S SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
G A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F F 0.40 1.25 0.016 0.049
K R X 45 _
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
C K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
−T− SEATING P 5.80 6.20 0.229 0.244
PLANE
M J R 0.25 0.50 0.010 0.019
D 16 PL

0.25 (0.010) M T B S A S

SOLDERING FOOTPRINT*
8X
6.40
16X 1.12
1 16

16X
0.58

1.27
PITCH

8 9

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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