Programmable Logic Devices

Tutorial 2
Michal Kubíček
Department of Radio Electronics, FEEC BUT Brno
Vytvořeno za podpory projektu OP VVV Moderní a otevřené studium techniky CZ.02.2.69/0.0/0.0/16_015/0002430.
Tutorial 2

❑ Short introduction to VHDL

❑ Synchronous sequence systems
❑ Counters

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 Tutorial 1 summary

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FPGA - structure

Electronically programmable interconnect and cell function

Basic cell: LUT (Look-Up Table) + FF (D-type Flip-Flop)

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FPGA - LUT
4-input LUT: Memory 16x1b
Address Data
a b d

c y
d c b a y minterm 0 0 0 0 b
0 0 0 0 0 /a·/b·/c·/d
c a
0 0 0 1 0 a·/b·/c·/d 0 0 0 1
0 0 1 0 0 /a·b·/c·/d
0 0 1 1 0 a·b·/c·/d d 1 1 0 0
0 1 0 0 0 /a·/b·c·/d
0 1 0 1 0 a·/b·c·/d 1 1 0 0
0 1 1 0 1 /a·b·c·/d
0 1 1 1 0 a·b·c·/d
1 0 0 0 1 /a·/b·/c·d y = /a·/b·c·d + /a·/b·/c·d + a·/b·/c·d + a·/b·c·d + /a·b·c·/d =
1 0 0 1 1 a·/b·/c·d = /b·d + /a·b·c·/d
1 0 1 0 0 /a·b·/c·d
1 0 1 1 0 a·b·/c·d

Minterms
1 1 0 0 1 /a·/b·c·d
1 1 0 1 1 a·/b·c·d Term
1 1 1 0 0 /a·b·c·d
1 1 1 1 0 a·b·c·d

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Implementation - Synthesis

Digital design synthesis ("Elaboration" in Vivado)

❑ Conversion of design description (textual, schematic...) to a circuit composed of generic
digital components (gates) including optimization (logic minimization...).
❑ Synthesis tools are integrated in modern FPGA CAD systems
❑ Output of the synthesis tool is an RTL schematic (Register Transfer Logic)

ENTITY prepinac IS PORT(

a,b,c: IN STD_LOGIC;

Synthesis
volba: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
y: OUT STD_LOGIC);
END prepinac;
ARCHITECTURE Behavioral OF prepinac IS BEGIN
y <= a WHEN volba = "00" ELSE
b WHEN volba = "01" OR volba = "10" ELSE
c;
END Behavioral;

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Implementation - MAP

Translate, Map ("Synthesis" in Vivado)

Constraints
FREQ "clk" = 80 MHz
LOC "clk" = 193
LOC "Tx_data" = 87
...

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Implementation - PLACE

Cell placement: PLACE

(PAR = P&R = Place and Route)

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Implementation - ROUTE

Cell connection: ROUTE

(PAR = P&R = Place and Route)

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 Short introduction to VHDL
The aim of the MPLD course is not to teach you complete VHDL language. During tutorials and PC labs
you will get familiar with the most important and most problematic aspects of the VHDL language with
regards to implementation and simulation of digital systems targeting FPGAs.

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VHDL

VHDL (VHSIC Hardware Description Language)

❑ VHSIC = Very High Speed Integrated Circuit
Sometimes also VHDL = Verification and Hardware Description Language

❑ Standard IEEE Std 1076-xxxx (1987, 1993, 2000, 2002, 2008, 2019)
❑ Originally only for simulation of large digital systems
❑ For synthesis (implementation of the code into chips) one can use only a
"synthesable subset", some functions are not supported.
• Some arithmetic operations (/, MOD, REM)
• Some basic commands (WAIT)
• Algorithmic code, particularly loops (FOR, WHILE)
❑ When not respecting some basic rules, a simulation may give different results
from implementation (for example incomplete sensitivity list)

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VHDL

VHDL (VHSIC Hardware Description Language)

❑ VHDL 2008 and 2019: great features but limited support

VHDL-2008 for Vivado synthesis : limited support. Please refer to UG901 Vivado Design
Suite User Guide: Synthesis under Appendix D for more details.

VHDL-2008 for Vivado simulation : limited support. Please refer to UG900 Vivado Design
Suite User Guide: Simulation under Appendix D for more details.

Xilinx currently does not support VHDL-2019. Xilinx might consider adding VHDL-2019
support based on customer demand in future. Xilinx simulation flow also supports simulation
tools from 3rd party EDA vendors that might be offering VHDL-2019 support. We encourage
our customers to evaluate 3rd party EDA vendor tools for simulation support for VHDL-2019.

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VHDL

VHDL (VHSIC Hardware Description Language)

Xilinx synthesis v2021.2: VHDL-2008 supported features

• Matching relational operators. • Expressions in port maps.

• Maximum and minimum operators. • Process (all) statement.
• Shift operators (rol, ror, sll, srl, sla, and sra). • Referencing generics in generic lists.
• Unary logical reduction operators. • Generics in Packages
• Mixing array and scalar logical operators. • Generic types in entities.
• If-else-if and case generate. • Functions in Generics
• Sequential assignments. • Relaxed return rules for function return values.
• Case? Statements. • Extensions to globally static and locally static
• Select? Statements. expressions.
• Using Slices in Aggregates • Static ranges and integer expressions in range
• Unconstrained element types. bounds.
• boolean_vector and integer_vector array types. • Block comments.
• Reading output ports.

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VHDL

VHDL (VHSIC Hardware Description Language)

Xilinx simulator v2021.2: VHDL-2008 supported features

• Matching relational operators. • Process (all) statement.

• Maximum and minimum operators. • Referencing generics in generic lists.
• Shift operators (rol, ror, sll, srl, sla, and sra). • Generic types in entities.
• Unary logical reduction operators. • Relaxed return rules for function return values.
• Mixing array and scalar logical operators. • Extensions to globally static and locally static
• If-else-if and case generate. expressions.
• Sequential assignments. • Static ranges and integer expressions in range
• Case? Statements. bounds.
• Select? Statements. • Block comments.
• Unconstrained element types. • Context declaration.
• boolean_vector and integer_vector array types.
• Reading output ports.
• Expressions in port maps.

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 VHDL – basic terms

Source code structure

Predefined entities (blocks)
library IEEE;
Data types
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; Operations with types
Operators overload
-----------------------------------------------
ALU
ENTITY ALU IS
PORT (A,B: IN STD_LOGIC_VECTOR (7 DOWNTO 0); A
SUM: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); SUM
END ALU; B

-----------------------------------------------
ALU
ARCHITECTURE Behavioral OF ALU IS
BEGIN A
SUM <= STD_LOGIC_VECTOR(UNSIGNED(A) + UNSIGNED(B)); + SUM
END Behavioral; B

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 VHDL – basic terms

Source code structure Entity name (ALU)

can be found on three
library IEEE; places in the source
use IEEE.STD_LOGIC_1164.ALL; code.
use IEEE.NUMERIC_STD.ALL;
The entity name should
----------------------------------------------- be same as the filename
of the source code
ENTITY ALU IS
PORT (A,B: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
(ALU.vhd in this case)
SUM: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END ALU; One file (source code)
should contain only a
----------------------------------------------- single entity with its
architecture.
ARCHITECTURE Behavioral OF ALU IS
BEGIN
SUM <= STD_LOGIC_VECTOR(UNSIGNED(A) + UNSIGNED(B));
END Behavioral;

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VHDL – basic terms

Entity
Entity declaration describes its interface to the outside world. The
PORT section defines inputs and outputs of the block.
Available modes of the PORT signals:
❑ IN it is not allowed to assign any value to this signal (port) within the
entity (read only)
❑ OUT it is not allowed to read value of this signal (port) within the
entity (write only, cannot be used in conditions of conditional
statements, cannot be used on the right side of assignments)
❑ INOUT used for tri-state signals on the top level entity only (usually in
conjunction with a platform specific buffer)
❑ BUFFER shall not be used => no need to know anything about it ;-)

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VHDL – basic terms

Architecture
Defines relations between entity inputs and outputs (contains the description of
entity functionality). It is always related to a particular Entity.
Functionality of one Entity can be described using several Architectures.
Several different types of description:
❑ Behavioral Algorithmic, high-level language constructs
❑ RTL Register Transfer Logic; using processes
❑ Structural Text equivalent of schema (netlist)

The best praxis is to combine all the description methods to get most
EFFECTIVE and most READABLE description of the required functionality.

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 VHDL – basic terms

Source code structure

Architecture name
library IEEE; (Behavioral in this
use IEEE.STD_LOGIC_1164.ALL; case) can be arbitrary,
use IEEE.NUMERIC_STD.ALL; but should correspond
to the used coding style.
-----------------------------------------------

ENTITY ALU IS However, the selected

PORT (A,B: IN STD_LOGIC_VECTOR (7 DOWNTO 0); name has no effect on
SUM: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); the implementation.
END ALU;
The most common
----------------------------------------------- names are Behavioral,
Structural, Dataflow and
ARCHITECTURE Behavioral OF ALU IS
BEGIN RTL.
SUM <= STD_LOGIC_VECTOR(UNSIGNED(A) + UNSIGNED(B));
END Behavioral;

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VHDL

Objects of the VHDL

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VHDL – objects

SIGNAL
❑ One of basic VHDL objects
❑ Similar to variables in other programming languages (as important)
❑ After synthesis the signal is represented by a physical wire (can be physically
located)
❑ Signals are declared within the entity as PORTs or inside the architecture as
internal SIGNALs, which are not visible from outside of the entity.
❑ To assign a value to a signal use the signal assignment <= (also called
concurrent, delayed)

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 VHDL – objects

Two types of signals: PORT, SIGNAL

ENTITY ALU IS
PORT (A,B : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
OpSel : IN STD_LOGIC;
SUM : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
sig_1 : INOUT STD_LOGIC; -- tri-state I/O
sig_2 : BUFFER STD_LOGIC); -- BUFFER; DO NOT USE!!!
END ALU;
-----------------------------------------------
ARCHITECTURE Behavioral OF ALU IS
SIGNAL SUM_i : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL CARRY : STD_LOGIC;
BEGIN
ALU
... A SUM
SUM_i
B sig_1
OpSel CARRY sig_2

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VHDL – objects

VARIABLE
❑ Another basic object of VHDL
❑ Auxiliary variable for algorithmic description (iteration variable of loops...)
❑ No direct equivalent of the variable in the synthesized/implemented design
❑ Variables may be declared in declarative part of the architecture (shared
variables; rarely used) or in a declarative part of a process (non-shared
variables)
❑ To assign a value to a variable use variable assignment := (also called
immediate), which can only be used either in declaration of the variable or
within a process body.

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VHDL – objects

CONSTANT
❑ Another VHDL object
❑ Used to store fixed values, can be assigned to both SIGNALS and
VARIABLES
❑ Constants may be declared in declarative part of an architecture or a process
(similar to shared and non-shared variable)
❑ It is only allowed to assign a value to the constant during its declaration
using the := assignment.

note: declaration = declare a type of signal/variable/constant

definition = assign a value to variable/constant

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VHDL

Data types

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VHDL – data types (of objects)
STANDARD
BOOLEAN -- True or False
INTEGER -- 32 or 64 bits
NATURAL -- Integers >= 0
POSITIVE -- Integers > 0
REAL -- Floating-point
BIT -- '0','1'
BIT_VECTOR -- Array of bits
CHARACTER -- 7-bit ASCII
STRING -- Array of characters
TIME -- hr, min, sec, ms, us, ns, ps, fs
STD_LOGIC_1164
STD_ULOGIC -- 'U','X','0','1','Z','W','L','H','-'
STD_ULOGIC_VECTOR -- Array of STD_ULOGIC
STD_LOGIC -- Resolved STD_LOGIC
STD_LOGIC_VECTOR -- Array of STD_LOGIC
NUMERIC_STD, STD_LOGIC_ARITH (Never use both at once !!!)
UNSIGNED -- Array of STD_LOGIC
SIGNED -- Array of STD_LOGIC

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VHDL – data types

❑ BIT / BIT_VECTOR
TYPE bit IS ('0','1');
Simulation should run faster, than with STD_LOGIC

❑ BOOLEAN
TYPE boolean IS (false,true);
Argument of conditional statements

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VHDL – data types

❑ STD_ULOGIC / STD_ULOGIC_VECTOR
TYPE std_ulogic IS (
'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-'); -- Don’t care
TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;

ULOGIC = Unresolved Logic

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VHDL – data types

❑ STD_LOGIC / STD_LOGIC_VECTOR
Based on STD_ULOGIC
There is a "resolution function" defined over the type
❑ It is possible to interconnect outputs
'L' (Weak 0) connected to '1' (Forcing 1) results in '1'
❑ It is said to be slower in simulation (no benchmarks available)
❑ No difference in synthesis (same RTL)
❑ The whole world uses STD_LOGIC / STD_LOGIC_VECTOR

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VHDL – data types

❑ resolution function for STD_LOGIC

-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |

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VHDL – data types

❑ STD_LOGIC / STD_LOGIC_VECTOR
SIGNAL state : STD_LOGIC := '1';
SIGNAL counter : STD_LOGIC_VECTOR(1 TO 8);
SIGNAL data : STD_LOGIC_VECTOR(15 DOWNTO 0);
...
state <= '0'; -- SINGLE QUOTE MARKS for single bits
counter <= "00000000"; -- QUOTATION MARKS for vectors
counter <= "0000_0000"; -- separator of nibbles
counter <= X"00"; -- hexadecimal notation
-- set all members (bits) of a vector to '0'
data <= X"0000";
data <= (OTHERS => '0');
-- set selected members (bits) of a vector to '1', others to '0'
data <= "1111000001000000";
data <= (X"F" , 6 => '1', OTHERS => '0');

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VHDL – data types

❑ SIGNED / UNSIGNED
Data type for arithmetic functions.
The definition is identical to STD_LOGIC_VECTOR, but as it is a formally
different type, it is necessary to use conversion functions when dealing
with these types.
7 6 5 4 3 2 1 0
SIGNAL data_I : SIGNED(7 DOWNTO 0);
7 6 5 4 3 2 1 0
SIGNAL data_Q : SIGNED(7 DOWNTO 0);
SIGNAL data_out : STD_LOGIC_VECTOR(7 DOWNTO 0); 7 6 5 4 3 2 1 0

...
data_out <= STD_LOGIC_VECTOR (data_I + data_Q);

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VHDL – data types

Conversion functions
use IEEE.NUMERIC_STD.ALL;
...
SIGNAL a_VEC : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL a_UNS : UNSIGNED (7 DOWNTO 0);
SIGNAL a_INT : INTEGER RANGE 0 TO 255;
...

STD_LOGIC_VECTOR <= INTEGER a_VEC <= STD_LOGIC_VECTOR(TO_UNSIGNED(a_INT,xx));

STD_LOGIC_VECTOR <= UNSIGNED a_VEC <= STD_LOGIC_VECTOR(a_UNS);

UNSIGNED <= INTEGER a_UNS <= TO_UNSIGNED(a_INT,xx);

UNSIGNED <= STD_LOGIC_VECTOR a_UNS <= UNSIGNED(a_VEC);

INTEGER <= UNSIGNED a_INT <= TO_INTEGER(a_UNS);

INTEGER <= STD_LOGIC_VECTOR a_INT <= TO_INTEGER(UNSIGNED(a_VEC));

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VHDL – data types

VHDL is strongly typed. Is that a problem?

No!

❑ Strongly typed = strong control mechanism build in a

compiler
❑ In other languages (like Verilog) it is necessary to perform much
more thorough verification

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VHDL – data types

User data types

TYPE t_state IS (Idle, Run, Lap, Stop);
SIGNAL pres_state, next_state: t_state := Idle;

All the enumerated types are ordinal (including STD_LOGIC)

Idle < Run

Array declaration
TYPE RamType IS ARRAY(0 TO 15) of STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ram : RamType:= (OTHERS => X"00");

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VHDL

Operators

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VHDL – operators

Different priority (7 levels)

** exponent
<numeric> = <numeric> ** <integer>;

ABS absolute value

<numeric> = abs <numeric>;

NOT complement, negation

<logic> = NOT <logic>;
<boolean> = NOT <boolean>;

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VHDL – operators

* multiplication
<numeric> = <numeric> * <numeric>;

/ division
<numeric> = <numeric> / <numeric>;

MOD integer division

<integer> = <integer> MOD <ineger>;

REM reminder from integer division

<integer> = <integer> REM <ineger>;

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VHDL – operators

+ sign
<numeric> = + <numeric>;

- sign
<numeric> = - <numeric>;

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VHDL – operators

+ addition
<numeric> = <numeric> + <numeric>;

- difference
<numeric> = <numeric> - <numeric>;

& concatenate
<array> = <element> & <element>;
<array> = <element> & <array> ;
<array> = <array> & <element>;
<array> = <array> & <array> ;

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VHDL – operators

SLL shift left logical

SRL shift right logical
Warning! Not
SLA shift left arithmetic always
functional!
SRA shift right arithmetic
ROL rotate left
ROR rotate right
<logical array> = <logical array> xxx <integer>;

Most codes do not use these operators. Concatenation operator (&) is

used instead as it is better handled by implementation tools.

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VHDL – operators

Relation operators
= /= < <= > >=

<boolean> = <....> rel <....>

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VHDL – operators

Logic operators
AND, OR, NAND, NOR, XOR, XNOR

<logical array> = <logical array> xxx <logical array>

<boolean> = <boolean> xxx <boolean>

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VHDL – operators

Concatenate &
SIGNAL A,B: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL S,T,U,V: STD_LOGIC;
SIGNAL X,Y: STD_LOGIC_VECTOR(7 DOWNTO 0);
...
X(7) <= A(3);
X(6) <= A(2);
X(5) <= A(1);
X <= A & B; Equivalent X(4) <= A(0);
X(3) <= B(3);
X(2) <= B(2);
X(1) <= B(1);
X(0) <= B(0);
A 3 2 1 0 3 2 1 0 B

X 7 6 5 4 3 2 1 0

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VHDL – operators

Concatenate &
SIGNAL A,B: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL S,T,U,V: STD_LOGIC;
SIGNAL X,Y: STD_LOGIC_VECTOR(7 DOWNTO 0);
...
X(7) <= A(3);
X(6) <= A(2);
X(7 DOWNTO 4) <= A; X(5) <= A(1);
X(3 DOWNTO 0) <= S & T & U & V; X(4) <= A(0);
X(3) <= S;
X(2) <= T;
Equivalent
X(1) <= U;
X(0) <= V;

X <= A & S & T & U & V;

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VHDL – operators

Concatenate &
data_in : IN STD_LOGIC;
...

SIGNAL data_reg : STD_LOGIC_VECTOR(7 DOWNTO 0);

...
PROCESS (clk) BEGIN
IF rising_edge(clk) THEN
data_reg <= data_reg(6 DOWNTO 0) & data_in;
END IF;
END PROCESS;

data_buffer <= data_buffer(6 DOWNTO 0) & data_in;

data_reg 7 6 5 4 3 2 1 0

data_reg 7 6 5 4 3 2 1 0 data_in

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VHDL – operators

Concatenate &
data_in : IN STD_LOGIC;
...

SIGNAL data_reg : STD_LOGIC_VECTOR(7 DOWNTO 0);

...
PROCESS (clk) BEGIN
IF rising_edge(clk) THEN
data_reg <= data_reg(data_reg'HIGH-1 DOWNTO 0) & data_in;
END IF;
END PROCESS;

data_reg 7 6 5 4 3 2 1 0

data_reg 7 6 5 4 3 2 1 0 data_in

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VHDL

Statements
(commands)

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VHDL – statements
Concurrent statement:
• conditional statement WITH-SELECT-WHEN
• conditional statement WHEN-ELSE
• PROCESS as a whole
• component instantiation
• GENERATE statement

Sequential statement:
• variable assignment :=
• conditional statement IF-THEN-ELSIF-ELSE
• conditional statement CASE-WHEN
• loops (FOR, LOOP, NEXT, EXIT) and NULL statement

Concurrent/Sequential statement:
• signal assignment <= (expressions)
• function and procedure calls
• ASSERT-REPORT command

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VHDL – concurrent statements

Concurrent statements
❑ Each concurrent statement represents part of a digital circuitry.

❑ The sequence of concurrent statements in the source code is not

important.

❑ Used mostly for simple logic description.

❑ Each PROCESSS as a whole and each component instantiation is a

concurrent statement on its own.

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VHDL – concurrent statements

Connection of signals (wires)

Possible assignments:
PORT OUT <= PORT IN;
SIGNAL <= PORT IN;
SIGNAL <= SIGNAL;
PORT OUT <= SIGNAL;
SIGNAL <= PORT OUT; common mistake!!!
PORT OUT <= PORT OUT;

Each concurrent assignment outside of the PROCESS statement is represented

by a physical connection of the involved signals.

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 VHDL – concurrent statements

Connection of signals (wires)

ENTITY ALU IS
PORT (A,B : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
OpSel : IN STD_LOGIC;
SUM : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
sig_1 : INOUT STD_LOGIC; -- tri-state I/O
sig_2 : BUFFER STD_LOGIC); -- Do not use!!!
END ALU;
-----------------------------------------------
ARCHITECTURE Behavioral OF ALU IS
SIGNAL SUM_i : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL CARRY : STD_LOGIC;
BEGIN
ALU
... A SUM
SUM_i
B sig_1
OpSel CARRY sig_2

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 VHDL – concurrent statements

Concurrent statements
ARCHITECTURE Behavioral OF ALU IS
BEGIN
Z <= X + Y; 3 concurrent statements
X <= A;
Y <= B; Each statement has its
END Behavioral; physical image in
ALU implemented design
The sequence of
A X
statements has no effect
+ Z on implementation!
B Y

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 VHDL – concurrent statements

Concurrent statements
ARCHITECTURE Behavioral OF ALU IS
BEGIN
Z <= X + Y; 3 concurrent statements
X <= A + B;
Y <= C + D; Each statement has its
END Behavioral; physical image in
ALU implemented design
A The sequence of
+ X statements has no effect
B
+ Z on implementation!
C
+ Y
D

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VHDL – concurrent statements

Concurrent statements
WITH mux_sel SELECT
y <= a WHEN "00",
b WHEN "01" | "10",
c WHEN OTHERS;

y <= a WHEN mux_sel = "00" ELSE

b WHEN mux_sel = "01" OR mux_sel = "10" ELSE
c;

LED_green <= '1' WHEN (power_OK='1' AND reset='0') ELSE '0';

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VHDL – concurrent statements

Concurrent statements

PROCESS (A,B,C,D) BEGIN

X <= A + B;
Y <= C + D;
PROCESS = one concurrent
END PROCESS; statement

Adder_1 : Adder PORT MAP (

a => in_1a, Component instantiation =
b => in_1b,
sum => res_1, one concurrent statement
carry => carry_1);

page 56 kubicek@vutbr.cz
VHDL – concurrent statements

Concurrent statements

Value can be assigned to each signal only

using a single concurrent statement!
...
Z <= X + Y;
...
Z <= "0000" WHEN reset = '1';
...

...
Z <= "0000" WHEN reset = '1' ELSE (X + Y);
...

page 57 kubicek@vutbr.cz
VHDL – concurrent statements

Concurrent statements
❑ Sequence of the statements is not important

... ...
y <= a + b; x <= c + y;
x <= c + y; The same result and structure y <= a + b;
... ...

Resulting HW
A
+ Y
B + X
C

page 58 kubicek@vutbr.cz
VHDL – concurrent statements

Concurrent statements
❑ However, the manner of description is important, as well as implementation
options (resource sharing, optimization...)
... ...
y <= a + b; y <= a + b;
x <= y + c; Not always same structure x <= a + b + c;
... ...

Resulting HW

A
A A
+ Y
B
+ Y B + X
+ X B C
C

page 59 kubicek@vutbr.cz
VHDL

Sequential statements,
PROCESS

page 60 kubicek@vutbr.cz
VHDL – sequential statements

Sequential statement
❑ Used in processes, functions and procedures
❑ The order of the statements is important
❑ Can be used to describe both combinatorial and sequential logic

page 61 kubicek@vutbr.cz
VHDL – PROCESS

PROCESS – special VHDL construct

Commands within a process are interpreted sequentially (similar to microprocessor
program), the sequence of commands is important.
Each process as a whole represents one concurrent statement (a complex one).
There are two types of process:
❑ With a sensitivity list
❑ With a wait statement (use these only for simulation!)

page 62 kubicek@vutbr.cz
VHDL – PROCESS

Without "Wait;" command

runs again when completed (infinite loop)
With a
Wait Statement
With "Wait;" command
usually runs only once in each simulation

PROCESS
Combinatorial; the sensitivity list contains all
the signal from the right side of assignments and
from conditional statement arguments
With a
sensitivity list
Sequential; the sensitivity list contains only
clock signal and occasionally asynchronous
set/reset signal

page 63 kubicek@vutbr.cz
VHDL – PROCESS

Combinatorial process example

sensitivity list

PROCESS (a,b,reset) List of all the signals that affect the process
BEGIN results – "output" signals (signal x in this case).
IF reset = '1' THEN
x <= 0; The sensitivity list must contain:
ELSE • all the signals of the right side of all the
x <= a + b; assignments (a and b in this case)
END IF; • all the signals present in arguments of
END PROCESS; conditional statements (reset in this case)

page 64 kubicek@vutbr.cz
VHDL – PROCESS

PROCESS with a sensitivity list

❑ From simulator point of view: a process is executed whenever any signal in the sensitivity
changes its value.
❑ Once the process is triggered, time is stopped until the process is finished
❑ All the signal assignments are executed at the end of process execution (value of all the signals
affected by process is constant throughout execution of the whole process).
❑ On the other hand: synthesizer is trying to recognize typical structures in the code, not
taking the source code verbatim => possible mismatch in behavior between simulated and
implemented design (ex. when process sensitivity list is incomplete)

PROCESS (a) BEGIN [Synth 8-614] signal 'b' is read in the

y <= a + b; process but is not in the sensitivity list
END PROCESS;

Incomplete sensitivity list ➔ different behavior of a design in

simulation and after implementation in hardware!!!

page 65 kubicek@vutbr.cz
VHDL – PROCESS

Each concurrent statement can be described

using a process (sequential statement)

PROCESS (a,b,reset) BEGIN x <= 0 WHEN reset = '1' ELSE

IF reset = '1' THEN (a + b);
x <= 0;
ELSE
x <= a + b; equivalent
END IF;
END PROCESS;

sequential statement concurrent statement

page 66 kubicek@vutbr.cz
VHDL – PROCESS

PROCESS with a SENSITIVITY LIST

❑ DELAYED ASSIGNMENT: In process for each signal only the last
assignment found is considered (used), any previous assignments are
ignored. The assignment is actually made when the PROCESS is finished
(or stopped using a WAIT statement in simulation).

PROCESS (a,b) BEGIN PROCESS (a,b) BEGIN

y <= a + b; y <= a * b;
equivalent END PROCESS;
y <= a - b;
y <= a * b;
END PROCESS;

Combinatorial PROCESS

page 67 kubicek@vutbr.cz
VHDL – PROCESS

PROCESS with a SENSITIVITY LIST

❑ In process for each signal only the last assignment found is
considered (used), any previous assignments are ignored.
❑ Very often used for so called DEFAULT ASSIGNMENT

PROCESS (a,b,y) BEGIN PROCESS (a,b,y) BEGIN

IF y = X"8" THEN x <= a + b + y;
x <= 0; equivalent IF y = X"8" THEN
ELSE x <= 0;
x <= a + b + y; END IF;
END IF; END PROCESS;
END PROCESS;

Combinatorial PROCESS

page 68 kubicek@vutbr.cz
VHDL – PROCESS

Use of default assignment (PROCESS only)

CASE state IS
WHEN bit_0 => x <= D(0); DV <= '1'; busy <= '1';
WHEN bit_1 => x <= D(1); DV <= '1'; busy <= '1';
WHEN bit_2 => x <= D(2); DV <= '1'; busy <= '1';
...
WHEN stop => x <= '0'; DV <= '0'; busy <= '1';
WHEN idle => x <= '0'; DV <= '0'; busy <= '0';
END CASE;

x <= '0'; DV <= '1'; busy <= '1'; -- Default assignment

CASE state IS
WHEN bit_0 => x <= D(0);
WHEN bit_1 => x <= D(1);
WHEN bit_2 => x <= D(2);
...
WHEN stop => DV <= '0';
WHEN idle => DV <= '0'; busy <= '0';
END CASE;

page 69 kubicek@vutbr.cz
 VHDL – PROCESS

PROCESS with a SENSITIVITY LIST

Sequential process
PROCESS (clk) BEGIN
PROCESS (clk) BEGIN IF rising_edge(clk) THEN
IF rising_edge(clk) THEN ...
Q <= D; END IF;
nQ <= NOT D; END PROCESS;
D Q
END IF; _
END PROCESS; Q

IF clk'EVENT AND clk = '1' THEN equivalent IF rising_edge(clk) THEN

page 70 kubicek@vutbr.cz
VHDL – PROCESS

PROCESS with a SENSITIVITY LIST

Sequential process without a reset

PROCESS (clk) BEGIN

IF rising_edge(clk) THEN
... normal operation
END IF;
END PROCESS;

page 71 kubicek@vutbr.cz
VHDL – PROCESS

PROCESS with a SENSITIVITY LIST

Sequential process with an asynchronous reset

PROCESS (arst,clk) BEGIN

IF arst = '1' THEN
... asynchronous reset
ELSIF rising_edge(clk) THEN
... normal operation
END IF;
END PROCESS;

For Xilinx FPGA it is not recommended to use asynchronous set/reset in the design.
i
page 72 kubicek@vutbr.cz
VHDL – PROCESS

PROCESS with a SENSITIVITY LIST

Sequential process with an asynchronous and a synchronous reset

PROCESS (arst,clk) BEGIN

IF arst = '1' THEN
... asynchronous reset
ELSIF rising_edge(clk) THEN
IF srst = '1' THEN
... synchronous reset
ELSE
... normal operation
END IF;
END IF;
END PROCESS;

page 73 kubicek@vutbr.cz
VHDL – PROCESS

PROCESS with a SENSITIVITY LIST

Sequential process with a synchronous reset and a clock enable

PROCESS (clk) BEGIN

IF rising_edge(clk) THEN
IF srst = '1' THEN
... synchronous reset
ELSIF clock_enable = '1' THEN
... normal operation
END IF;
END IF;
END PROCESS;

page 74 kubicek@vutbr.cz
VHDL – PROCESS

PROCESS with a SENSITIVITY LIST

Example: 8-bit binary counter

SIGNAL cnt_reg : UNSIGNED(7 DOWNTO 0) <= (OTHERS => '0');

...
PROCESS (clk) BEGIN
IF rising_edge(clk) THEN
IF srst = '1' THEN
cnt_reg <= (OTHERS => '0'); -- synchronous reset
ELSIF clock_enable = '1' THEN
cnt_reg <= cnt_reg + 1; -- increment counter
END IF;
END IF;
END PROCESS;

page 75 kubicek@vutbr.cz
VHDL – PROCESS

PROCESS as a concurrent statements

It is allowed to assign a value to a signal
...
PROCESS (clk) BEGIN
only in a single concurrent statement. As
IF rising_edge(clk) THEN PROCESS is one concurrent statement
Z <= X + Y;
...
on its own, one signal can be assigned
END IF; only in a single PROCESS!!!
END PROCESS;
...

PROCESS (arst) BEGIN

IF arst = '1' THEN
Z <= "0000";
...
END IF;
END PROCESS;

page 76 kubicek@vutbr.cz
VHDL – PROCESS

PROCESS as a concurrent statements

It is allowed to assign a value to a signal
...
PROCESS (arst, clk) BEGIN
only in a single concurrent statement. As
IF arst = '1' THEN PROCESS is one concurrent statement
Z <= "0000";
...
on its own, one signal can be assigned
ELSIF rising_edge(clk) THEN only in a single PROCESS!!!
Z <= X + Y;
...
END IF;
END PROCESS;

page 77 kubicek@vutbr.cz
VHDL – PROCESS

PROCESS: delayed assignment

PROCESS (clk) BEGIN PROCESS (clk) BEGIN

IF rising_edge(clk) THEN IF rising_edge(clk) THEN
X <= X + 1; A <= X + 5;
A <= X + 5; equivalent X <= X + 1;
END IF; END IF;
END PROCESS; END PROCESS;

The signal assignment "<=" is also called delayed assignment,

especially in the context of signal assignments within a process.
Value of assigned signals are updated at the end of the process; during
process evaluation all the signals hold value that they had at the
initiation of the process.

page 78 kubicek@vutbr.cz
VHDL

Variables

page 79 kubicek@vutbr.cz
 VHDL – variables
ENTITY cnt_en_gen IS
PORT( clk : IN STD_LOGIC;

!
cnt_en_o : OUT STD_LOGIC);
END cnt_en_gen;
---------------------------------------------------------------
ARCHITECTURE Behavioral_1 OF cnt_en_gen IS
SIGNAL cnt_en : STD_LOGIC := '0';

---------------------------------------------------------------
BEGIN
PROCESS (clk)
VARIABLE cnt : UNSIGNED(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
IF rising_edge(clk) THEN
cnt_en <= '0'; -- default assignment
cnt := cnt + 1; Fully functional code, but some
IF cnt = X"FF" THEN
cnt_en <= '1'; simulators cannot monitor variables
END IF; ➔ very difficult to debug the code!
END IF;
END PROCESS;

cnt_en_o <= cnt_en;

page 80 kubicek@vutbr.cz
 VHDL – variables
ENTITY cnt_en_gen IS
PORT( clk : IN STD_LOGIC;
cnt_en_o : OUT STD_LOGIC);
END cnt_en_gen;
---------------------------------------------------------------
ARCHITECTURE Behavioral_2 OF cnt_en_gen IS
SIGNAL cnt_en : STD_LOGIC := '0';
SIGNAL cnt : UNSIGNED(7 DOWNTO 0) := (OTHERS => '0');
---------------------------------------------------------------
BEGIN
PROCESS (clk)

BEGIN
IF rising_edge(clk) THEN
cnt_en <= '0'; -- default assignment
cnt <= cnt + 1; The synthesis results in cnt signal
IF cnt = X"FF" THEN
cnt_en <= '1'; being output of a register, so it
END IF; makes perfect sense to define it as
END IF; a SIGNAL immediately in the code.
END PROCESS;

cnt_en_o <= cnt_en;

page 81 kubicek@vutbr.cz
VHDL – variables

If the synthesis of a VARIABLE results in a signal

(register), define it as a SIGNAL ➔ easier
verification
"Vivado Simulator does not yet support tracing of VHDL variables." (2019-02-26)

"In general, I would recommend that beginners avoid using

variables. They can cause a lot of confusion and often are hard to
synthesize by the tools." www.nandland.com (2019-02-26)

page 82 kubicek@vutbr.cz
VHDL – variables
-- sig_A, sig_B, sig_C: STD_LOGIC_VECTOR(3 DOWTNO 0);
-- At the moment of process start:
-- sig_A = 3, sig_B = 5, sig_C = 2

PROCESS (clk)
VARIABLE v_A, v_B, v_C: STD_LOGIC_VECTOR(3 DOWTNO 0):= X"0";
BEGIN
IF rising_edge(clk) THEN
v_A := sig_A + 1; -- v_A = 3 + 1 = 4
v_B := sig_B + v_A; -- v_B = 5 + 4 = 9
v_C := v_A + v_B; -- v_C = 4 + 9 = 13
sig_A <= v_A; sig_B <= v_B; sig_C <= v_C;
END IF;
END PROCESS;

-- After the process execution: sig_A = 4 sig_B = 9 sig_C = 13

In this PROCESS order of assignments matters.

page 83 kubicek@vutbr.cz
VHDL – variables
-- sig_A, sig_B, sig_C: STD_LOGIC_VECTOR(3 DOWTNO 0);
-- At the moment of process start:
-- sig_A = 3, sig_B = 5, sig_C = 2

PROCESS (clk)

BEGIN
IF rising_edge(clk) THEN
sig_A <= sig_A + 1; -- sig_A = 3 + 1 = 4
sig_B <= sig_B + sig_A; -- sig_B = 5 + 3 = 8
sig_C <= sig_A + sig_B; -- sig_C = 3 + 5 = 8

END IF;
END PROCESS;

-- After the process execution: sig_A = 4 sig_B = 8 sig_C = 8

In this PROCESS order of assignments is NOT important.

page 84 kubicek@vutbr.cz
VHDL

Conditional statements

page 85 kubicek@vutbr.cz
VHDL – conditional statements

Conditional statements
Concurrent statement
without PROCESS statement a 00
01
• WITH – SELECT – WHEN b
10
y
• WHEN – ELSE c 11

Sequential statement
select
inside PROCESS statement
• IF – THEN – ELSIF – ELSE
• CASE – WHEN

page 86 kubicek@vutbr.cz
VHDL – conditional statements

WITH – SELECT – WHEN

WHEN – ELSE
❑ Description of combinatorial logic
❑ Only out of PROCESS
❑ Only single target signal
(suitable only for simple algorithms/conditions)

page 87 kubicek@vutbr.cz
VHDL – conditional statements

IF – THEN – ELSIF – ELSE

CASE – WHEN
❑ Both combinatorial and sequential logic
❑ Can be used only within PROCESS block (function, procedure)
❑ Can be stacked to create complex conditions (but this can
negatively affect timing!!!)
CASE volba IS
WHEN "00" => IF counter_A = X"A1" THEN
IF btn_01 = '1' THEN
CASE SW(3 DOWNTO 0) IS
WHEN X"0" => ...

page 88 kubicek@vutbr.cz
VHDL – conditional statements

Entity description
ENTITY MUX_simple IS
PORT(
a,b,c : IN STD_LOGIC;
a 00
select : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 01
y : OUT STD_LOGIC b y
10
);
c 11
END MUX_simple;

ARCHITECTURE Behavioral OF MUX_simple IS

BEGIN select

-- function description (see next slides) There is no semicolon behind

the last port!
END Behavioral;

page 89 kubicek@vutbr.cz
VHDL – conditional statements

WITH – SELECT – WHEN

a 00
01
WITH select SELECT b y
10
y <= a WHEN "00",
c 11
b WHEN "01" | "10",
c WHEN OTHERS;
select

page 90 kubicek@vutbr.cz
VHDL – conditional statements

WHEN – ELSE

a 00
01
b y
10
y <= a WHEN select = "00" ELSE
c 11
b WHEN select = "01" OR select = "10" ELSE
c;
select

page 91 kubicek@vutbr.cz
VHDL – conditional statements

IF – THEN – ELSIF – ELSE

a 00
01
mux_4: PROCESS (select,a,b,c) b y
10
BEGIN
c 11
IF (select = "00") THEN
y <= a;
ELSIF (select = "01" OR select = "10") THEN
y <= b; select
ELSE
y <= c;
END IF;
END PROCESS mux_4;

page 92 kubicek@vutbr.cz
VHDL – conditional statements

CASE – WHEN

a 00
01
mux_4: PROCESS (select,a,b,c) b y
10
BEGIN
c 11
CASE select IS
WHEN "00" => y <= a;
WHEN "01" | "10" => y <= b;
WHEN OTHERS => y <= c; --"11" select
END CASE;
END PROCESS mux_4;

page 93 kubicek@vutbr.cz
VHDL

Loops

page 94 kubicek@vutbr.cz
VHDL - loops

Simple LOOP
LOOP

... <statements>

IF <condition> THEN
... <statements>
EXIT; -- termination of the loop at <condition>
END IF;

... <statements>

END LOOP;

❑ The loop must contain EXIT command if it is not meant to be infinite.

page 95 kubicek@vutbr.cz
VHDL - loops

Simple LOOP
LOOP_1: LOOP

... <statements>

IF <condition> THEN
... <statements>
EXIT LOOP_1; -- termination of the loop at <condition>
END IF;

... <statements>

END LOOP LOOP_1;

❑ Loop name (LOOP_1 in this case) is optional. Using loop names it is easier to read the
code and it is also possible to create nested loops.

page 96 kubicek@vutbr.cz
VHDL - loops

FOR LOOP
LOOP_1: FOR k IN 100 DOWNTO 1 LOOP
... <statements>
NEXT LOOP_1 WHEN <condition>;
EXIT LOOP_1 WHEN <condition>;
END LOOP LOOP_1;

❑ Iteration variable is defined implicitly as an INTEGER variable

❑ The iteration variable cannot be modified within the loop
❑ The iteration variable is implicitly incremented/decremented at each loop run
❑ The iteration variable cannot be accessed outside the loop ("local" variable)
❑ Loop condition is tested at the beginning of the loop
❑ Range of the loop can be dynamic
❑ The loop range can be TO or DOWNTO
❑ One loop iteration can be skipped using NEXT command
❑ The whole loop can be terminated with EXIT command
VHDL - loops

WHILE LOOP
LOOP_1: WHILE <condition> LOOP
... <statements>
NEXT LOOP_1 WHEN <condition>;
EXIT LOOP_1 WHEN <condition>;
END LOOP LOOP_1;

❑ Loop condition is tested at the beginning of the loop

❑ There is no implicitly defined loop variable
❑ One loop iteration can be skipped using NEXT command
❑ The whole loop can be terminated with EXIT command

page 98 kubicek@vutbr.cz
VHDL - loops

Loops: properties
❑ Not well supported by synthesis tools – algorithmic character of
descriptions does not suit well to digital circuitry
❑ Before using loops it is wise to learn abilities of your synthesizer
(ug901-vivado-synthesis.pdf)
❑ Loops are great tool for simulation – unlimited use, nested loops,
variable limits...

page 99 kubicek@vutbr.cz
VHDL - loops

Example: 8-bit shift register

PROCESS (clk) BEGIN
IF rising_edge(clk) THEN
shreg(0) <= SI;
shreg(1) <= shreg(0);
shreg(2) <= shreg(1);
shreg(3) <= shreg(2);
shreg(4) <= shreg(3);
SI
shreg(5) <= shreg(4); 7 6 5 4 3 2 1 0
shreg(6) <= shreg(5);
shreg(7) <= shreg(6); clk
END IF;
END PROCESS;

page 100 kubicek@vutbr.cz

VHDL - loops

Example: 8-bit shift register

PROCESS (clk) BEGIN
 Preferred way of description
IF rising_edge(clk) THEN
shreg <= shreg (6 DOWNTO 0) & SI;
END IF;
END PROCESS;

SI
PROCESS (clk) BEGIN
7 6 5 4 3 2 1 0
IF rising_edge(clk) THEN clk
for i in 0 to 6 loop
shreg(i+1) <= shreg(i);
end loop;
shreg(0) <= SI;
END IF;
END PROCESS;

page 101 kubicek@vutbr.cz

VHDL - loops

Example: change bit order in a vector

SIGNAL data_in, data_out : STD_LOGIC_VECTOR(7 DOWNTO 0);
...
PROCESS (data_in) BEGIN 7 7
data_out(7) <= data_in(0); 6 6
data_out(6) <= data_in(1);
5 5
...
data_out(1) <= data_in(6); 4 4
data_out(0) <= data_in(7); 3 3
END PROCESS; 2 2
1 1
0 0
data_in data_out

page 102 kubicek@vutbr.cz

VHDL - loops

Example: change bit order in a vector

SIGNAL data_in, data_out : STD_LOGIC_VECTOR(7 DOWNTO 0);
...
PROCESS (data_in) BEGIN 7 7
for i in 0 to 7 loop 6 6
data_out(7-i) <= data_in(i);
5 5
end loop;
END PROCESS; 4 4
3 3
2 2
1 1
0 0
data_in data_out

page 103 kubicek@vutbr.cz

VHDL - loops

Example: change bit order in a vector

SIGNAL data_in, data_out : STD_LOGIC_VECTOR(7 DOWNTO 0);
...
PROCESS (clk) BEGIN 7 7
IF rising_edge(clk) THEN 6 6
for i in 0 to 7 loop
5 5
data_out(7-i) <= data_in(i);
end loop; 4 4
8xD
END IF; 3 FlipFlop 3
END PROCESS; 2 2
1 1
0 0
data_in data_out

clk

page 104 kubicek@vutbr.cz

VHDL

Structural description

page 105 kubicek@vutbr.cz

VHDL – structural description

Textual description of a schematic interconnect

❑ Clear VHDL = design tool independent (portability)

❑ Often much easier to modify, possible automation

❑ Usually less readable

❑ Can be combined with other styles of description (processes...), but it is

not recommended as the resulting code tends to be hard to read.

page 106 kubicek@vutbr.cz

VHDL – structural description

Example: 4-input AND gate

AND_4in

I1
I2
Y
I3
I4

page 107 kubicek@vutbr.cz

VHDL – structural description

Example: 4-input AND gate

Basic cell: independent VHDL source code (AND_gate.vhd)

LIBRARY IEEE;
A Y
use IEEE.std_logic_1164.ALL;
-------------------------------------------- B
ENTITY AND_gate IS
PORT ( A : IN STD_LOGIC;
B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END AND_gate;
--------------------------------------------
ARCHITECTURE Behavioral OF AND_gate IS
BEGIN
Y <= '1' WHEN (A='1' AND B='1') ELSE '0';
END Behavioral;

page 108 kubicek@vutbr.cz

 VHDL – structural description
LIBRARY IEEE;
use IEEE.std_logic_1164.ALL;
-----------------------------------------
ENTITY AND_4in IS
PORT ( I1,I2,I3,I4 : IN STD_LOGIC;
AND_4in
Y : OUT STD_LOGIC);
END AND_4in; AND_1
----------------------------------------- I1
S1 AND_3
ARCHITECTURE Structural OF AND_4in I2
----------------------------------------- AND_2 Y
COMPONENT AND_gate I3
S2
PORT ( A,B : IN STD_LOGIC; I4
Y : OUT STD_LOGIC);
END COMPONENT;
---------------------------------------
SIGNAL S1,S2: STD_LOGIC;
-----------------------------------------
BEGIN
-----------------------------------------
AND_1: AND_gate PORT MAP ( A => I1, B => I2, Y => S1);
AND_2: AND_gate PORT MAP ( A => I3, B => I4, Y => S2);
AND_3: AND_gate PORT MAP ( A => S1, B => S2, Y => Y );
-----------------------------------------
END Structural;
 VHDL – structural description
LIBRARY IEEE;
use IEEE.std_logic_1164.ALL;
-----------------------------------------
ENTITY AND_4in IS
PORT ( I1,I2,I3,I4 : IN STD_LOGIC;
AND_4in
Y : OUT STD_LOGIC);
END AND_4in; AND_1
----------------------------------------- I1
S1 AND_3
ARCHITECTURE Structural OF AND_4in I2
----------------------------------------- AND_2 Y
COMPONENT AND_gate I3
S2
PORT ( A,B : IN STD_LOGIC; I4
Y : OUT STD_LOGIC);
END COMPONENT;
---------------------------------------
SIGNAL S1,S2: STD_LOGIC; Simplified component instantiation
----------------------------------------- (without port names)
BEGIN
----------------------------------------- Not recommended
AND_1: AND_gate PORT MAP (I1, I2, S1); (prone to error)
AND_2: AND_gate PORT MAP (I3, I4, S2);
AND_3: AND_gate PORT MAP (S1, S2, Y );
-----------------------------------------
END Structural;
VHDL – structural description

Order of instantiation is not important

BEGIN
AND_1: AND_gate PORT MAP ( A => I1, B => I2, Y => S1);
AND_2: AND_gate PORT MAP ( A => I3, B => I4, Y => S2);
AND_3: AND_gate PORT MAP ( A => S1, B => S2, Y => Y );
END Structural;

BEGIN
AND_3: AND_gate PORT MAP ( A => S1, B => S2, Y => Y );
AND_1: AND_gate PORT MAP ( A => I1, B => I2, Y => S1);
AND_2: AND_gate PORT MAP ( A => I3, B => I4, Y => S2);
END Structural;

page 111 kubicek@vutbr.cz

 VHDL – structural description
BEGIN
----------------------------------------- Correct code formating
AND_1: AND_gate
PORT MAP(
A => I1, AND_4in
B => I2,
Y => S1); AND_1
I1
S1 AND_3
AND_2: AND_gate I2
PORT MAP( AND_2 Y
I3
A => I3, S2
B => I4, I4
Y => S2);

AND_3: AND_gate
PORT MAP(
A => S1,
B => S2,
Y => Y );
-----------------------------------------
END Structural;

page 112 kubicek@vutbr.cz

 VHDL – structural description, no component declaration
... ...
ARCHITECTURE Structural OF AND_4in ARCHITECTURE Structural OF AND_4in
----------------------------------------- -----------------------------------------
COMPONENT AND_gate
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;
--------------------------------------- ---------------------------------------
SIGNAL S1,S2: STD_LOGIC; SIGNAL S1,S2: STD_LOGIC;
----------------------------------------- -----------------------------------------
BEGIN BEGIN
----------------------------------------- -----------------------------------------
AND_1: AND_gate AND_1: ENTITY work.AND_gate
PORT MAP( PORT MAP(
A => I1, A => I1,
B => I2, B => I2,
Y => S1); Y => S1);

AND_2: AND_gate AND_2: ENTITY work.AND_gate

PORT MAP( PORT MAP(
A => I3, A => I3,
B => I4, B => I4,
Y => S2); Y => S2);
... ...
VHDL

Final notes

page 114 kubicek@vutbr.cz

VHDL

Simulation versus synthesis

❑ It is possible to simulate any syntactically correct code.
❑ To synthesize (implement) the code can contain only selected VHDL statements
(synthesizable subset) that are supported by the selected synthesis tool.

Vivado Design Suite User Guide: Synthesis (UG901)

❑ Synthesizer is not interpreting the code exactly (as simulator does), it is trying to
recognize known structures
❑ For reliable design it is necessary to use standard design coding styles (especially
for synchronous sequence systems)

page 115 kubicek@vutbr.cz

VHDL

General rules for synthesis

❑ A value can be assigned to a signal
• once using a single concurrent statement
• several times in a single process (1 process = 1 concurrent statement)
❑ The rising_edge(<signal>) function can be used only for clock edge
detection (register description), not to detect button press!!!
❑ To describe registers, always use only one type of active edge of clock signal
(either rising_edge or falling_edge) in the whole design.
❑ Use as few different clock signals as possible.

page 116 kubicek@vutbr.cz

VHDL

General rules
❑ Each statement is terminated with semicolon
❑ Complex commands can be written on more lines; CR/LF, spaces and TABs
can be combined to create well-readable code
❑ Identifiers are not allowed to start with a number or underscore, end with
underscore, or contain two underscores in a row
❑ Never use spaces or special characters in filename, project name or
any directory (path) related to your project.

page 117 kubicek@vutbr.cz

VHDL

General rules
❑ Do not underestimate warnings, read and analyze them from the beginning,
use message filtering to suppress irrelevant warnings, Google the message if you are
not sure what does it mean (many other designers have had the same problem).

page 118 kubicek@vutbr.cz

VHDL
LIBRARY people, skills;
USE people.smart.all;
USE people.experienced.all;
USE people.motivated.all;
USE skills.vhdl.all;

ARCHITECTURE Brno OF hiring IS

SIGNAL link_to_company : OPEN_JOB_ARRAY(1 TO 5);
BEGIN
gen: FOR 1 TO 5 GENERATE
vhdl_designer: ENTITY work.Job_Offer
PORT MAP (
position => "FPGA/ASIC Designer – full time",
location => "Brno, Šumavská 31",
tasks => ("VHDL coding", "Verification"),
requirements => (VHDL, English),
nice_to_have => (DO_254, FPGA, ASIC, C, Python, Ethernet, PCIe, Amba, Avalon),
starting => ASAP,
scope => (AUTOMOTIVE, AEROSPACE & SPACE, INDUSTRIAL),
experience => (Junior, Senior),
respond_to => contact);
END GENERATE;

tttech_company: ENTITY work.company

GENERIC MAP (
name => "TTTech Computertechnik AG",
contact => "http://www.tttech.com/jobs-career/jobs",
keywords => "Reliability, Robustness, Safety, Networks")
PORT MAP (
open_positions => link_to_company);

END ARCHITECTURE Brno;

page 119 kubicek@vutbr.cz

 Combinatorial / sequential
synchronous / asynchronous
systems

page 120 kubicek@vutbr.cz

Digital systems - combinatorial

Combinatorial systems (circuits)

❑ Output signal values depend entirely on current values of input
signals.
❑ For each combination of input values of logical ZEROs and ONEs
there is an explicit (definit) value of output value.
❑ Combinatorial systems implement combinatorial functions

page 121 kubicek@vutbr.cz

Digital systems - combinatorial

Ways of combinatorial function description

O = ((I0 * I1 * !I2 * !I3) + (!I0 * !I1 * I2 * I3) + (I0 * I1 * I2 * I3) + (!I0 * !I1 * !I2
* !I3));

page 122 kubicek@vutbr.cz

Digital systems - sequential

Sequential systems (circuits)

❑ Output signal values depend not only on current values of input
signals but also on previous values (history).
❑ Always contain memory elements (registers)
❑ Systems that combine registers and combinatorial logic are usually
called sequential systems

D Q D Q

CLK CLK

page 123 kubicek@vutbr.cz

Digital systems - sequential

Asynchronous systems
❑ In case they contain a clock signal, it is not common for all its
sequential components (registers)
❑ They are able to respond immediately to an input stimulus
❑ They are usually less complex (in terms of utilized gates and
registers) than equivalent synchronous systems
❑ Very difficult to design and even more to verify
❑ Gradual signal propagation, risk of hazards

page 124 kubicek@vutbr.cz

Digital systems - sequential

Synchronous systems
❑ Can change its state only in certain moments defined by a single
control (clock) signal
❑ Much easier design and verification
❑ Much more reliable, less dependent on external conditions
❑ Perfectly suitable for CAD tools (design automation)
❑ Today almost all digital systems are synchronous

page 125 kubicek@vutbr.cz

Digital systems - sequential

Synchronous sequential system

❑ Today almost all digital systems are synchronous
❑ Well defined design methodology for reliable implementation using CAD tools

KČ3

KČ1 REG KČ2 REG

clk clk

page 126 kubicek@vutbr.cz

Digital systems - sequential

Synchronous sequential system

❑ Common clock signal
❑ In FPGAs all the registers are edge sensitive D-type Flip-Flops

KČ3

KČ1 REG KČ2 REG

clk clk

page 127 kubicek@vutbr.cz

Digital systems - sequential

Synchronous sequential system

CIC filter

page 128 kubicek@vutbr.cz

Digital systems - sequential

Synchronous sequential system

FIR filter

page 129 kubicek@vutbr.cz

Digital systems - sequential

Synchronous sequential system

Pipelined CPU

page 130 kubicek@vutbr.cz

Digital systems - sequential

Synchronous sequential system

page 131 kubicek@vutbr.cz

Digital systems - sequential

Globally asynchronous, locally synchronous

sequential systems
❑ Systems that are composed of more synchronous subsystems, of
which some are synchronized (clocked) by a different clock signal.

CIC FIR FIFO Procesor Ethernet

250 MHz 125 MHz

page 132 kubicek@vutbr.cz

 Counters
Simple synchronous
sequential systems

page 133 kubicek@vutbr.cz

Counters

Counters
Very simple Finite State Machines (FSMs)
❑ Binary
❑ Decimal
❑ Gray
❑ Johnson
❑ LFSR
❑ ...

page 134 kubicek@vutbr.cz

Counters

Binary counter
4-bit counter: 2N = 16 states (0 to (2N – 1) = 15)
State diagram (free-running counter)

0 1 2 ... 14 15

BIN

clk

page 135 kubicek@vutbr.cz

 Counters

Binary counter
Incremented with each rising edge of a clock signal (CLK)
4b counter: 2N = 16 states (0 to (2N – 1) = 15)
N bits ➔ N registers (flip-flops)

clk

b[0]
b[1]
b[2]
b[3]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 ....

page 136 kubicek@vutbr.cz

Counters

Binary counter - asynchronous

D Q D Q D Q D Q
_ _ _ _
Q Q Q Q

+ simple implementation => high FMAX

– asynchronous (gradual switching)
Not suitable for PLD (FPGA)!!!

page 137 kubicek@vutbr.cz

 Counters

Binary counter - asynchronous

b[0] b[1] b[2] b[3]

D Q D Q D Q D Q
_ _ _ _
clk Q Q Q Q

clk

b[0]
b[1]
b[2]
b[3]
TP TP TP TP 4·TP

page 138 kubicek@vutbr.cz

Counters

Binary counter - synchronous

Condition for incrementing counter value: a Nth bit is inverted when all lower bits are in
logical one. This description is not used in VHDL, we depend on synthesis tool to implement
the counter optimally and write a readable VHDL code (functional description) using +1.

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0000 0001...
Variants:
• Output inversion = down counting
• Bidirectional (up/down input)
• Synchronous/asynchronous set/reset
• Load a value
+1
REG

page 139 kubicek@vutbr.cz

Counters

Binary counter – VHDL description

SIGNAL cnt : UNSIGNED(3 DOWNTO 0):= X"0";
SIGNAL cnt_next : UNSIGNED(3 DOWNTO 0);

PROCESS (clk) BEGIN PROCESS (clk) BEGIN

IF rising_edge(clk) THEN IF rising_edge(clk) THEN
cnt <= cnt_next; cnt <= cnt + 1;
END IF; END IF;
END PROCESS; END PROCESS;

PROCESS (cit) BEGIN

cnt_next <= cnt + 1;
END PROCESS;

Vivado => Tools => Language Templates

VHDL => Synthesis Constructs => Coding examples => Counters => Binary

page 140 kubicek@vutbr.cz

Counters

Binary counter – VHDL description

asynchronous reset (not recommended for Xilinx FPGA)

PROCESS (arst, clk) BEGIN

IF arst = '1' THEN
cnt <= (OTHERS => '0');
ELSIF rising_edge(clk) THEN
cnt <= cnt + 1;
END IF;
END PROCESS;

page 141 kubicek@vutbr.cz

Counters

Binary counter – VHDL description

asynchronous and synchronous reset (not recommended)

PROCESS (arst, clk) BEGIN

IF arst = '1' THEN
cnt <= (OTHERS => '0');
ELSIF rising_edge(clk) THEN
IF srst = '1' THEN
cnt <= (OTHERS => '0');
ELSE
cnt <= cnt + 1;
END IF;
END IF;
END PROCESS;

page 142 kubicek@vutbr.cz

Counters

Binary counter – VHDL description

synchronously load a value

PROCESS (clk) BEGIN PROCESS (clk) BEGIN

IF rising_edge(clk) THEN IF rising_edge(clk) THEN
IF srst = '1' THEN IF srst = '1' THEN
cnt <= (OTHERS => '0'); cnt <= (OTHERS => '0');
ELSE ELSIF cnt_load = '1' THEN
IF cnt_load = '1' THEN cnt <= data_in;
cnt <= data_in; ELSE
ELSE cnt <= cnt + 1;
cnt <= cnt + 1; END IF;
END IF; END IF;
END IF; END PROCESS;
END IF;
END PROCESS;

Both codes are correct and equivalent

page 143 kubicek@vutbr.cz

Counters

Binary counter – VHDL description

clock enabling – slow down the counter

clk
System clock signal 125 MHz

clk_EN
1:5 => 1/5 * 125 MHz = 25 MHz

clk_EN_gen: PROCESS (clk) BEGIN slow_proc: PROCESS (clk_EN) BEGIN

IF rising_edge(clk) THEN IF rising_edge(clk_EN) THEN
IF cnt_div = MAX THEN cnt_SLOW <= cnt_SLOW + 1;
cnt_div <= (OTHERS => '0'); END IF;
clk_EN <= '1'; END PROCESS slow_proc;
ELSE
cnt_div <= cnt_div + 1;
clk_EN <= '0';
END IF;
END IF;
END PROCESS clk_EN_gen;
Counters

Binary counter – VHDL description

clock enabling – slow down the counter

clk
System clock signal 125 MHz

clk_EN
1:5 => 1/5 * 125 MHz = 25 MHz

clk_EN_gen: PROCESS (clk) BEGIN slow_proc: PROCESS (clk) BEGIN

IF rising_edge(clk) THEN IF rising_edge(clk) THEN
IF cnt_div = MAX THEN IF clk_EN = '1' THEN
cnt_div <= (OTHERS => '0'); cnt_SLOW <= cnt_SLOW + 1;
clk_EN <= '1'; END IF;
ELSE END IF;
cnt_div <= cnt_div + 1; END PROCESS slow_proc;
clk_EN <= '0';
END IF;
END IF;
END PROCESS clk_EN_gen;
Counters

Binary counter – VHDL description

synchronous reset + synchronous load + clock enable

PROCESS (clk) BEGIN

IF rising_edge(clk) THEN
IF srst = '1' THEN
cnt <= (OTHERS => '0');
ELSIF clk_en = '1' THEN
IF cnt_load = '1' THEN
cnt <= data_in;
ELSE
cnt <= cnt + 1;
END IF;
END IF;
END IF;
END PROCESS;

page 146 kubicek@vutbr.cz

Counters

Decimal counter
binary counter with shortened cycle
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001

0 1 2 ... 8 9

Cycle shortening condition:

From state 9 jump to state 0

Unused states 10-15

REG More decades:
• Cascading decimal counters
• BIN ➔ BCD conversion
page 147 kubicek@vutbr.cz
Counters

Decimal counter – VHDL description

SIGNAL cnt : UNSIGNED(3 DOWNTO 0):= X"0";
SIGNAL cnt_next : UNSIGNED(3 DOWNTO 0);

PROCESS (clk) BEGIN PROCESS (clk) BEGIN

IF rising_edge(clk) THEN IF rising_edge(clk) THEN
cnt <= cnt_next; IF cnt = X"9" THEN
END IF; cnt <= X"0";
END PROCESS; ELSE
cnt <= cnt + 1;
PROCESS (cit) BEGIN END IF;
IF cnt = X"9" THEN END IF;
cnt_next <= X"0"; END PROCESS;
ELSE
cnt_next <= cnt + 1;
END IF;
END PROCESS;

page 148 kubicek@vutbr.cz

Counters

Decimal counter – unused (illegal) states

PROCESS (clk) BEGIN PROCESS (clk) BEGIN
IF rising_edge(clk) THEN IF rising_edge(clk) THEN
IF cnt = X"9" THEN IF cnt >= X"9" THEN
cnt <= X"0"; cnt <= X"0";
ELSE ELSE
cnt <= cnt + 1; cnt <= cnt + 1;
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;

No treatment of unused states, counter is not User defined treatment of unused states; can
forced to return to a valid operating state. It consume more FPGA resources but behavior is
is possible to ask the implementation tool to explicitly defined. Be aware of optimization
take care of this automatically. setting of the synthesis tool, some can result in
complete removal of this unused state transition
logic!

page 149 kubicek@vutbr.cz

Counters

Decimal counter – unused (illegal) states

IF cnt = X"9" THEN User defined treatment of unused states; can
cnt <= X"0"; consume more FPGA resources but behavior is
ELSE explicitly defined. Be aware of optimization setting
cnt <= cnt + 1; of the synthesis tool, some can result in complete
... removal of this unused state transition logic!

0 1 2 ... 8 9

10 11 12 13 14 15

page 150 kubicek@vutbr.cz

Counters

Decimal counter – unused (illegal) states

IF cnt >= X"9" THEN User defined treatment of unused states; can
cnt <= X"0"; consume more FPGA resources but behavior is
ELSE explicitly defined. Be aware of optimization setting
cnt <= cnt + 1; of the synthesis tool, some can result in complete
... removal of this unused state transition logic!

0 1 2 ... 8 9

10 11 12 13 14 15

page 151 kubicek@vutbr.cz

Counters

Gray Counter
Only single bit changes when transitioning between adjacent states

N-bit counter has cycle of 2N states.

There are several different Gray codes; the most
common one is the reflected binary Gray code.
Usage of auxiliary bit (po; see the table) results in
lower hardware requirements.

Usage:
• FIFO addressing
• A/D converters
• Absolute position sensors

page 152 kubicek@vutbr.cz

Counters

Gray counter
Only single bit changes when transitioning between
adjacent states

page 153 kubicek@vutbr.cz

Counters

Binary counter versus Gray counter

12 13 14 15 0 1 2 3 4 5 14 15 13 12 8 9 11 10 2 3 1 0 4 5 7 6 14

b(0) g(0)

b(1) g(1)

b(2) g(2)

b(3) g(3)

b(0)
g(0)
b(1)
g(1)
b(2)
g(2)
b(3)
g(3)

15 14 10 2 0
10 2

page 154 kubicek@vutbr.cz

Counters

Gray counter
Recommended description in VHDL (Xilinx Vivado: Language Templates)
constant N : INTEGER := 8;
signal gray_cnt : UNSIGNED( N-1 downto 0 );
signal next_bin_cnt : UNSIGNED(gray_cnt'range);
signal next_bin_cnt : UNSIGNED(gray_cnt'range);
...
process (clk) begin
if rising_edge(clk) then
bin_cnt <= next_bin_cnt;
gray_cnt <= (('0' & next_bin_cnt(next_bin_cnt 'HIGH downto 1))
XOR next_bin_cnt);
end if;
end process;

next_bin_cnt <= bin_cnt + 1;

REG
page 155 kubicek@vutbr.cz
Counters

Gray counter
next_bin_cnt
The same code written in a different
way (strictly separated combinatorial bin_cnt

and sequential portion of the design). +1

REG
The system structure is obvious using
this style of description. gray_cnt

process (clk) begin

if rising_edge(clk) then B»G
bin_cnt <= next_bin_cnt; REG
gray_cnt <= next_gray_cnt;
next_gray_cnt
end if;
end process;

next_bin_cnt <= bin_cnt + 1;

next_gray_cnt <= (('0' & next_bin_cnt(next_bin_cnt'HIGH DOWNTO 1))
XOR next_bin_cnt);

page 156 kubicek@vutbr.cz

Counters

Gray counter Gray  Binary code conversion

Gray ➔ Binary Binary ➔ Gray

g(0) b(0)
XOR b(0) XOR g(0)

g(1) b(1)
XOR b(1) XOR g(1)

g(2) b(2)
XOR b(2) XOR g(2)

g(3) b(3) b(3) g(3)

page 157 kubicek@vutbr.cz

Counters

Johnson counter A B C D E Y
0 0 0 0 0 0
❑ Very simple implementation
1 0 0 0 0 1
❑ High maximum clock frequency 1 1 0 0 0 2
❑ The cycle length is only 2·N (compared to 2N in 1 1 1 0 0 3
case of binary or Gray counter) ➔ large number of
1 1 1 1 0 4
unused states
1 1 1 1 1 5
❑ Sometimes used as a decimal counter (with a
decoder on its output) in DA converters 0 1 1 1 1 6
0 0 1 1 1 7
0 0 0 1 1 8
0 0 0 0 1 9
REG N-bit

page 158 kubicek@vutbr.cz

Counters

LFSR counter
❑ Liner Feedback Shift Register
❑ Very simple implementation
❑ High maximum clock frequency
❑ The cycle length is 2N-1
❑ Generator of PRBS (Pseudo-Random Binary
Sequence, also called M-sekvence)

REG N-bit

page 159 kubicek@vutbr.cz

Counters
BITS TAPS BITS TAPS
3 3,2 30 30,6,4,1

LFSR counter - feedback 4

5
4,3
5,3
31
32
31,28
32,22,2,1
6 6,5 33 33,20

❑ Fibonacci and Galois version 7

8
7,6
8,6,5,4
34
35
34,27,2,1
35,33
9 9,5 36 36,25
10 10,7 37 37,5,4,3,2,1
11 11,9 38 38,6,5,1
12 12,6,4,1 39 39,35
13 13,4,3,1 40 40,38,21,19

REG N-bit 14
15
14,5,3,1
15,14
41
42
41,38
42,41,20,19
16 16,15,13,4 43 43,42,38,37
17 17,14 44 44,43,18,17
18 18,11 45 45,44,42,41
19 19,6,2,1 46 46,45,26,25
20 20,17 47 47,42
21 21,19 48 48,47,21,20
22 22,21 49 49,40
23 23,18 50 50,49,24,23
24 24,23,22,17 51 51,50,36,35
25 25,22 52 52,49
26 26,6,2,1 53 53,52,38,37
27 27,5,2,1 54 54,53,18,17
page 160 kubicek@vutbr.cz 28 28,25 55 55,31
29 29,27 56 56,55,35,34
Counters

LFSR described in VHDL

❑ Fibonacci version

SIGNAL ShReg : STD_LOGIC_VECTOR(23 DOWNTO 1):= (OTHERS => '1');

...

PROCESS (clk) BEGIN

IF rising_edge(clk) THEN
ShReg(23) <= ShReg(22);
ShReg(22) <= ShReg(21);
...
ShReg( 2) <= ShReg( 1);
ShReg( 1) <= ShReg(18) XOR ShReg(23);
END IF;
END PROCESS;

page 161 kubicek@vutbr.cz

Counters

LFSR described in VHDL

❑ Fibonacci version

SIGNAL ShReg : STD_LOGIC_VECTOR(23 DOWNTO 1):= (OTHERS => '1');

...

PROCESS (clk) BEGIN

IF rising_edge(clk) THEN
FOR i IN 23 DOWNTO 2 LOOP
ShReg(i) <= ShReg(i + 1);
END LOOP;

ShReg( 1) <= ShReg(18) XOR ShReg(23);

END IF;
END PROCESS;

page 162 kubicek@vutbr.cz

Counters

LFSR described in VHDL

❑ Fibonacci version

SIGNAL ShReg : STD_LOGIC_VECTOR(23 DOWNTO 1):= (OTHERS => '1');

...

PROCESS (clk) BEGIN

IF rising_edge(clk) THEN
ShReg <= ShReg(22 DOWNTO 1) & ( ShReg(23) XOR ShReg(18) );
END IF;
END PROCESS;

page 163 kubicek@vutbr.cz

Counters

LFSR described in VHDL

❑ Fibonacci version

SIGNAL ShReg : STD_LOGIC_VECTOR(23 DOWNTO 1):= (OTHERS => '1');

SIGNAL Feedback : STD_LOGIC;

...

PROCESS (clk) BEGIN

IF rising_edge(clk) THEN
ShReg <= ShReg(22 DOWNTO 1) & Feedback;
END IF;
END PROCESS;

Feedback <= ShReg(23) XOR ShReg(18);

page 164 kubicek@vutbr.cz

Counters

LFSR described in VHDL

❑ Fibonacci version

SIGNAL ShReg : STD_LOGIC_VECTOR(23 DOWNTO 1):= (OTHERS => '0');

SIGNAL Feedback : STD_LOGIC;

...

PROCESS (clk) BEGIN Using XNOR instead of XOR results

IF rising_edge(clk) THEN in inversion of the generated
ShReg <= ShReg(22 DOWNTO 1) & Feedback; sequence (same order, just
END IF;
END PROCESS; swapped ONEs and ZEROs).

Feedback <= ShReg(18) XNOR ShReg(23);

page 165 kubicek@vutbr.cz

Counters

LFSR described in VHDL

❑ Fibonacci version

CONSTANT Tap_1 : INTEGER := 23;

CONSTANT Tap_2 : INTEGER := 18;
SIGNAL ShReg : STD_LOGIC_VECTOR(Tap_1 DOWNTO 1):= (OTHERS => '1');
SIGNAL Feedback : STD_LOGIC;

...

PROCESS (clk) BEGIN

IF rising_edge(clk) THEN
ShReg <= ShReg(ShReg'HIGH-1 DOWNTO 1) & Feedback;
END IF;
END PROCESS;

Feedback <= ShReg(Tap_1) XOR ShReg(Tap_2);

page 166 kubicek@vutbr.cz

Čítače

LFSR described in VHDL

❑ Fibonacci version

ENTITY LFSR_gen IS
GENERIC( Tap_1 : INTEGER := 23; LFSR_gen
Tap_2 : INTEGER := 18)
PORT( clk : IN STD_LOGIC;
PRBS_o : OUT STD_LOGIC);
Tap_1 = 23
END LFSR_gen; Tap_2 = 18
...
clk PRBS_o
PROCESS (clk) BEGIN
IF rising_edge(clk) THEN
ShReg <= ShReg(ShReg'HIGH-1 DOWNTO 1) & Feedback;
END IF;
END PROCESS;

Feedback <= ShReg(Tap_1) XNOR ShReg(Tap_2);

PRBS_o <= ShReg(ShReg'HIGH);

page 167 kubicek@vutbr.cz

Čítače

LFSR described in VHDL

❑ Fibonacci version LFSR_gen_i1

LFSR_gen_i1 : ENTITY work.LFSR_gen Tap_1 = 23

PORT MAP( clk => clk,
PRBS_o => PRBS_1_o);
Tap_2 = 18
clk PRBS_1_o

LFSR_gen_i2 : ENTITY work.LFSR_gen LFSR_gen_i2

GENERIC MAP( Tap_1 => 31;
Tap_2 => 28) Tap_1 = 31
PORT MAP( clk => clk,
PRBS_o => PRBS_2_o); Tap_2 = 28
clk PRBS_2_o

page 168 kubicek@vutbr.cz

Thank you for your attention!

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(;;;;;;;;;;;;)
( ° ° )==\\
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( ° ° ) ||
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( ° ° ) ||
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\__________/
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PROCESS( ========================== ) BEGIN