Computer Architecture & Organization (YCS4001)

Module 4: Arithmetic Unit Design

Soumya Majumdar
Adder
● Most basic arithmetic operation that the ALU (arithmetic logic unit) of a computer performs is
addition of two or more binary numbers.
● Adder is used to perform the operation of addition.
● Classified into two types − 1. Half Adder 2. Full Adder
● Half-adder: combinational logic circuit that performs the addition of only two bits (binary
digits)
● Full-adder : combination circuit that performs three bits (binary digits), where two are
significant bits and one is carry from previous execution
Half-Adder
Half-Adder
Full-Adder
Full-Adder
Full-Adder
Subtractor

● Subtraction of two binary numbers can be performed by taking the 1’s or 2’s complement of the
inputs.
● Subtraction operation becomes addition operation by this method, and thus can be performed by
using adder circuits.
● Reduction of hardware and cost
● In subtraction operation, each subtrahend bit (B) of number is subtracted from its corresponding
significant minuend bit (A) to obtain a difference bit.
● Classified into two types - 1. Half-Subtractor 2. Full-Subtractor
Half-Subtractor

● Half-subtractor is a combinational logic circuit that have two inputs and two outputs (i.e.
difference and borrow).
● Half subtractor produces difference between two binary bits a tinput and also produces a borrow
output (if any).
● In the subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit.
Half-Subtractor
●
Half-Subtractor
●
Full-Subtractor
● Full-subtractor is a combinational circuit that has three inputs A, B, bin and two outputs d and b.
Where, A is the minuend, B is subtrahend, bin is borrow produced by the previous stage, d is the
difference output and b is the borrow output.
● Half subtractor can only be used to find the difference of LSBs (Least Significant Bits) of two
binary numbers. Thus, if there is any borrow during the subtraction of the LSBs, it will affect
the subtraction of the next bits of numbers.
● To overcome this problem of the half subtractor, a full subtractor is realized.
Full-Subtractor
●
Full-Subtractor
●
Half-Subtractor
●
Shift-and-add Multiplication
● Shift-and-add multiplication is similar to the multiplication performed by paper and pencil.
● This method adds the multiplicand X to itself Y times, where Y denotes the multiplier.
● To multiply two numbers by paper and pencil, the algorithm is to take the digits of the multiplier
one at a time from right to left, multiplying the multiplicand by a single digit of the multiplier
and placing the intermediate product in the appropriate positions to the left of the earlier results.
Shift-and-add Multiplication
● Consider the multiplication of two unsigned 4-bit numbers, 8 (1000) and 9 (1001).

● In the case of binary multiplication, since the digits are 0 and 1, each step of the multiplication
is simple. If the multiplier digit is 1, a copy of the multiplicand (1 × multiplicand) is placed in
the proper positions; if the multiplier digit is 0, a number of 0 digits (0 × multiplicand) are
placed in the proper positions.
Shift-and-add Multiplication
●
Shift-and-add Multiplication
●
Signed multiplication: Booth’s algorithm
● Booth algorithm gives a procedure for multiplying binary integers in signed 2’s complement
representation in efficient way, i.e., less number of additions/subtractions required.
● It operates on the fact that strings of 0’s in the multiplier require no addition but just shifting and a
string of 1’s in the multiplier from bit weight 2^k to weight 2^m can be treated as 2^(k+1 ) to 2^m.
● Booth algorithm requires examination of the multiplier bits and shifting of the partial product.
Prior to the shifting, the multiplicand may be added to the partial product, subtracted from the
partial product, or left unchanged according to some rules.
Signed multiplication: Booth’s algorithm
Signed multiplication: Booth’s algorithm
Example: Multiply the two numbers 7 and 3 by using the Booth's multiplication algorithm.

7 = (0111) => multiplicand (M)

3 = (0011) => multiplier (Q)

SC (Sequence Count) => number of bits so SC = 4.

Qn Qn + 1 M = (0111) AC Q Qn + 1 SC
M' + 1 = (1001) & Operation

1 0 Initial 0000 0011 0 4

Subtract (M' + 1) 1001

1001

Perform Arithmetic Right Shift operations (ashr) 1100 1001 1 3

1 1 Perform Arithmetic Right Shift operations (ashr) 1110 0100 1 2

0 1 Addition (A + M) 0111

0101 0100

Perform Arithmetic right shift operation 0010 1010 0 1

0 0 Perform Arithmetic right shift operation 0001 0101 0 0

M = 23 = (010111) and Q = -9 = (110111)

Qn Qn + 1 M = (0111) AC Q Qn + SC
1
M' + 1 = (1001) & Operation

Initially 000000 110111 0 6

1 0 Subtract M 101001

101001 5

Perform Arithmetic right shift operation 110100 111011 1 4

1 1 Perform Arithmetic right shift operation 111010 011101 1 3

M' + 1 = (1001) & Operation

1 1 Perform Arithmetic right shift operation 111101 001110 1

0 1 Addition (A + M) 010111

010111

Perform Arithmetic right shift operation 001010 000111 0 2

1 0 Subtract M 101001

101001

Perform Arithmetic right shift operation 111001 100011 1 1

1 1 Perform Arithmetic right shift operation 111100 110001 1 0

Qn + 1 = 1, it means the output is negative.

Hence, 23 * -9 = 2's complement of 111100110001 => (00001100111)