SUBJECT: DIGITAL ELECTRONIC

Dear Students

KINDLY NOTE: UNIT II will be updated soon…

 Unit 1: Chapter 1
Number System
Unit Structure
1.0 Objectives
1.1 Introduction
1.2 Analog system, digital system
1.3 Numbering system
1.4 Conversion from one number system to another
1.5 Floating point numbers
1.6 Weighted codes binary coded decimal
1.7 Non-weighted codes Excess 3 code
1.8 Gray code
1.9 Alphanumeric codes
1.10 Error detection and correction
1.11 Universal Product Code
1.12 Code conversion
1.14 Summary
1.15 Reference for further reading

1.0 Objectives: This chapter would make you understand the following concepts
 What is difference between analog and digital system?
 Different numbering system.
 Conversion from one number system to another
 Floating point numbers
 Weighted codes binary coded decimal
 Non-weighted codes Excess 3 code
 Gray code and Alphanumeric codes
 Error detection and correction
 Universal Product Code and Code conversion

1.1 Introduction
The study of number systems is important from the viewpoint of understanding how
data are represented before they can be processed by any digital system including a
digital computer. In this chapter we will discuss different number systems commonly
used to represent data such as the binary, octal and hexadecimal number systems.
1.2 Analog system, digital system
Digital as well as Analog System, both are used to transmit signals from one place to
another like audio/video. Digital system uses binary format as 0 and 1 whereas
analog system uses electronic pulses with varying magnitude to send data.
1.2.1 Analog system
A signal is defined as any physical quantity that varies with time, space, or any other
independent variable or variables. Mathematically signal can be function of one or
more independent variables, for example,
S1 (t) = 10 t
S2 (t) = 10 t2
Most of the signals find in science and engineering are analog in nature i.e. the
signals are functions of a continuous variable, such as time or space, and usually
take on values in continuous range. The most common example of analog signal is
sinusoidal waveform as shown Fig. 1.2.1
The expression for the signal can be written as

S(t) = A sin ( t + )
Where, A = Amplitude
 = Radian/sec
 = Phase
T = Time duration of one cycle
F = Frequency = 1/T
Fig. 1.2.1 Sine Wave

To measure an analog signal analog multimeter is used. The main problem with an
analog signal is continuously varying with respect to time; the person has to be
expert in Time domain analysis to find out perfect result.
1.2.2 Digital system
To overcome the problems of an analog system; the digital system developed.
Digital system requires digital information. Digital information can be represented by
fixed number of non – continuous or discrete symbols called as Digits. In digital
system binary system is used which has only two digits ‘0’ and ‘1’.
Binary system: as we are using binary in digital system which restricts the digital
signal to have only two distinct values.
Advantages of Binary system:
1. Most information processing systems are constructed by using switches (binary
devices).
2. Binary signal are more reliable.
3. The basic decision making processes required of digital systems are binary.
Bits: As binary quantities are encountered in many different physical forms, it is
convenient to have a common way of representing binary states by using digit
symbols ‘0’ and ‘1’ to represent two possible values of binary quantity at any time.
These symbols are called as ‘bits’, abbreviation of term ‘Binary digits’. Fig. 1.2.2
shows digital and analog signal. We use ‘1’ to denote ‘HIGH’ and ‘0’ to denote ‘LOW’
level of the signal. Binary voltage values VH and VL are represented as ‘1’ and ‘0’
respectively.

Fig.1.2.2 Digital and Analog signal.

Convention:
In binary system two states 1 and 0 are present. The voltage levels are predefined
by the manufactures of chip and user cannot change it. Generally
HIGH LOGIC = 1 = VCC = +5 volt and LOW LOGIC = 0 = GND = 0 volt
Currently we are in the digital world. The widest application of digital system is
computers and to learn inside of the computers digital system is the base also it is
easy to implement and in around 90% cases you will find that analog systems are
replaced by digital systems.
1.3 Numbering system
We will begin our discussion on various number systems by briefly describing the
parameters that are common to all number systems.
Positional Number:
A number system is defined by digits or numerals. We can combine digits as per our
requirement to represent full range. The number system with which we are normally
familiar is Arabic Numerals, consists of 10 digits such as 0, 1, 2,…, 9.
Decimal Number System:
The 10 Arabic digits can be combined in various ways to represent any number.
Fundamental way of constructing a number is to form a sequence or string of digits
in which consecutive digits represent consecutive power of 10. For example take 3
digit number 876. The 876 represent, from left to right, hundreds (8), tens (7) and
unit (6).
We can decompose the number as
876 = 8 x 102 + 7 x 101 + 6 x 100 … (1)
This system is decimal number system which is a good example of positional
number system. Here each digit of multi-digit number has fixed value (or weight)
determined by its position. The number is also called as weighted number system.
Presently in the above example we have considered only integer part. One may
require to represent fractional part also. Here fractional part is denoted by sequences
of digits whose weights are negative powers of 10. The integer part and fractional
part represents the full number for example 1.414, both integer and fractional part
are separated by special symbol ‘.’ called a decimal point.
The number can be decomposed as
1.414 = 1 x 100 + 4 x 10-1 + 1 x 10-2 + 4 x 10-3 … (2)

Number Base:
The decimal number notation can be written in generalized form where quantity 10 is
replaced by ‘r’ called as base or radix, of the number system. We will represent
number x2 x1 x0 . x-1 x-2 as
x2 x1 x0 . x-1 x-2 = x2 X r2 + x1 X r1 + x0 X r0. x-1 X r-1 + x-2 X r-2 … (3)
Following table shows various number systems of our interest.
System Name Base ‘r’ Digits / symbols used in the system
Decimal 10 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
 Binary 2 0, 1
Octal 8 0, 1, 2, 3, 4, 5, 6, 7
Hexadecimal 16 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F

1.3.1 Binary number system

We have already seen that binary number system has base / radix 2, which means it
has only two digits, namely ‘0’ and ‘1’. The weights for binary number can be given
by
Binary number 24 23 22 21 20 2-1 2-2 2-3 ………..
Equivalent decimal 16 8 4 2 1 0.5 0.25 0.125 ………..
By putting r = 2 in equation (3) we can get equation for binary as follows
x2 x 22 + x1 x 21 + x0 x 20 + x-1 x 2-1 + x-2 x 2-2 … (4)
Let’s have one example, If Binary number is (101)2, then x2 x1 x0 = 101
x2 x 2 2 + x 1 x 2 1 + x 0 x 2 0
= 1 x 2 2 + 0 x 2 1 + 1 x 20
= 4 + 0 + 1 = (5)10
 (101)2 = (5)10
1.3.2 Octal number system
The octal number system has a base 8 and consists of 8 different digits or symbols
such as 0 to 7. As there are 8 digits, 3 bits (23 = 8) are sufficient to represent any
octal number in binary format. Following table shows 3 bit binary equivalent for each
octal number.
3-bit binary equivalent Octal Number
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7

The weights for actual number system can be given by

Octal number 83 82 81 80 8-1 8-2 8-3 ………..
1/8 = 1/64 = 1/512 =
Equivalent decimal 512 64 8 1 ………..
0.125 0.01562 0.00195

By putting r = 8 in equation (4) we can get equation for octal as follows

x2 x 82 + x1 x 81 + x0 x 80 + x-1 x 8-1 + x-2 x 8-2 … (5)
Let’s have one example, If Octal number is (357)8, then x2 x1 x0 = 357
x2 x 8 2 + x 1 x 8 1 + x 0 x 8 0
= 3 x 8 2 + 5 x 8 1 + 7 x 80
= 192 + 40 + 7 = (239)10
 (357)8 = (239)10
1.3.3 Hexadecimal number system
The Hexadecimal number system has a base 16 and consists of 16 different digits or
symbols. First ten digits or symbols are from decimal number system i.e. 0, 1, 2, …,
9 and next six are A, B, C, D, E and F representing 10, 11, 12, 13, 14 and 15
respectively. As there are 16 digits or symbols, 4 bits (24 = 16) are sufficient to
represent any hexadecimal number in binary format. Following table shows 4 bit
binary equivalent for each hexadecimal number.
4-bit binary equivalent Hexadecimal Number
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10 = A
1 0 1 1 11 = B
1 1 0 0 12 = C
 1 1 0 1 13 = D
1 1 1 0 14 = E
1 1 1 1 15 = F

The weights for actual number system can be given by

Hexadecimal number 162 161 160 16-1 16-2 ………..

1 16 1/256 =
Equivalent decimal 256 16 1 ………..
. 625 0.00390

By putting r = 16 in equation (5) we can get equation for hexadecimal as follows

x2 x 162 + x1 x 161 + x0 x 160 + x-1 x 16-1 + x-2 x 16-2 … (6)
Let’s have one example, If Hexadecimal number is (1AF)16, then x2 x1 x0 = 1 A F
x2 x 162 + x1 x 161 + x0 x 160
= 1 x 162 + A x 161 + F x 160
= 256 + (10 x 16) + (15 x 1)
= 256 + 160 + 15 = (431)10
 (1AF)16 = (431)10
1.4 Conversion from one number system to another
In this section we are going to study conversion from one type of number system to
another i.e. decimal to binary / octal / hexadecimal or vice versa and hexadecimal to
octal, hexadecimal to binary, binary to octal etc.

There are many methods or techniques which can be used to convert numbers from
one base to another. In this chapter, we'll demonstrate the following −

 Decimal to Other Base System

 Other Base System to Decimal

 Other Base System to Non-Decimal

 Binary to Octal

 Octal to Binary

 Binary to Hexadecimal

 Hexadecimal to Binary
1.4.1 Decimal to Other Base System

Step 1 − Divide the decimal number to be converted by the value of the new base.

Step 2 − Get the remainder from Step 1 as the rightmost digit (least significant digit)
of the new base number.

Step 3 − Divide the quotient of the previous divide by the new base.

Step 4 − Record the remainder from Step 3 as the next digit (to the left) of the new
base number.

Repeat Steps 3 and 4, getting remainders from right to left, until the quotient
becomes zero in Step 3.

The last remainder thus obtained will be the Most Significant Digit (MSD) of the new
base number.

Example

Decimal Number: 2910

Calculating Binary Equivalent −

Step Operation Result Remainder

Step 1 29 / 2 14 1

Step 2 14 / 2 7 0

Step 3 7/2 3 1

Step 4 3/2 1 1

Step 5 1/2 0 1

As mentioned in Steps 2 and 4, the remainders have to be arranged in the reverse

order so that the first remainder becomes the Least Significant Digit (LSD) and the
last remainder becomes the Most Significant Digit (MSD).

Decimal Number : 2910 = Binary Number : 111012.

1.4.2 Other Base System to Decimal System

Step 1 − Determine the column (positional) value of each digit (this depends on the
position of the digit and the base of the number system).
Step 2 − Multiply the obtained column values (in Step 1) by the digits in the
corresponding columns.

Step 3 − Sum the products calculated in Step 2. The total is the equivalent value in
decimal.

Example

Binary Number: 111012

Calculating Decimal Equivalent −

Step Binary Number Decimal Number

Step 1 111012 ((1 x 24) + (1 x 23) + (1 x 22) + (0 x 21) + (1 x 20))10

Step 2 111012 (16 + 8 + 4 + 0 + 1)10

Step 3 111012 2910

Binary Number : 111012 = Decimal Number : 2910

1.4.3 Binary to Octal

Step 1 − Divide the binary digits into groups of three (starting from the right).

Step 2 − Convert each group of three binary digits to one octal digit.

Example

Binary Number : 101012

Calculating Octal Equivalent −

Step Binary Number Octal Number

Step 1 101012 010 101

Step 2 101012 28 58

Step 3 101012 258

Binary Number : 101012 = Octal Number : 258

1.4.4 Octal to Binary
Step 1 − Convert each octal digit to a 3-digit binary number (the octal digits may be
treated as decimal for this conversion).

Step 2 − Combine all the resulting binary groups (of 3 digits each) into a single
binary number.

Example

Octal Number : 258

Calculating Binary Equivalent −

Step Octal Number Binary Number

Step 1 258 210 510

Step 2 258 0102 1012

Step 3 258 0101012

Octal Number : 258 = Binary Number : 101012

1.4.5 Hexadecimal to Binary

Step 1 − Convert each hexadecimal digit to a 4-digit binary number (the

hexadecimal digits may be treated as decimal for this conversion).

Step 2 − Combine all the resulting binary groups (of 4 digits each) into a single
binary number.

Example

Hexadecimal Number : 1516

Calculating Binary Equivalent −

Step Hexadecimal Number Binary Number

Step 1 1516 110 510

Step 2 1516 00012 01012

Step 3 1516 000101012

Hexadecimal Number : 1516 = Binary Number : 101012

1.5 Floating point number
(https://lost-
contact.mit.edu/afs/cs.wisc.edu/sunx86_57/test_image/u/a/n/andrew/public/cs3
54/beyond354/arith.flpt.html )

Floating point numbers are used to represent non integer fractional numbers and are
used in technical calculations. E.g. 3.256, 2.1 and 0.0036.
The most commonly used floating point standard is the IEEE standard.
According to this standard, floating point numbers are represented with 32 bits
(single precision) or 64 bits (double precision).
It is an arithmetic operations consist of addition, subtraction, multiplication and
division.
These operations are done with algorithms similar to those used on sign magnitude
integers (because of the similarity of representation) example, only add numbers of
the same sign. If the numbers are of opposite sign, must do subtraction.

ADDITION:
Example on decimal value given in scientific notation:
3.25 x 10 ** 3
+ 2.63 x 10 ** -1
------------------------
First step: align decimal points
Second step: add
3.25 x 10 ** 3
+ 0.000263 x 10 ** 3
---------------------------
3.250263 x 10 ** 3
(presumes use of infinite precision, without regard for accuracy)
Third step: normalize the result (already normalized!)
Example on fl pt. value given in binary:
S E F
.25 = 0 01111101 00000000000000000000000
100 = 0 10000101 10010000000000000000000
to add these fl. pt. representations,
step 1: align radix points

shifting the mantissa LEFT by 1 bit DECREASES THE EXPONENT by 1

shifting the mantissa RIGHT by 1 bit INCREASES THE EXPONENT by 1
we want to shift the mantissa right, because the bits that fall off the end
should come from the least significant end of the mantissa

-> choose to shift the .25, since we want to increase it's exponent.
-> shift by 10000101
-01111101
---------------
00001000 (8) places.
with hidden bit and radix point shown, for clarity
0 01111101 00000000000000000000000 (original value)
0 01111110 10000000000000000000000 (shifted 1 place)
(note that hidden bit is shifted into msb of mantissa)
0 01111111 01000000000000000000000 (shifted 2 places)
0 10000000 00100000000000000000000 (shifted 3 places)
0 10000001 00010000000000000000000 (shifted 4 places)
0 10000010 00001000000000000000000 (shifted 5 places)
0 10000011 00000100000000000000000 (shifted 6 places)
0 10000100 00000010000000000000000 (shifted 7 places)
0 10000101 00000001000000000000000 (shifted 8 places)

step 2: add (don't forget the hidden bit for the 100)

0 10000101 1.10010000000000000000000 (100)

+ 0 10000101 0.00000001000000000000000 (.25)
---------------------------------------
0 10000101 1.10010001000000000000000
 step 3: normalize the result (get the "hidden bit" to be a 1)
it already is for this example.
result is
0 10000101 10010001000000000000000
suppose that the result of an addition of aligned mantissas gives
10.11110000000000000000000
and the exponent to go with this is 10000000.
We must put the mantissa back in the normalized form.
Shift the mantissa to the right by one place, and increase the exponent by 1.
The exponent and mantissa become
10000001 1.01111000000000000000000 0 (1 bit is lost off the least
significant end)

SUBTRACTION
Like addition as far as alignment of radix points then the algorithm for subtraction of
sign mag. numbers takes over.
Before subtracting,
 Compare magnitudes (don't forget the hidden bit!)
 Change sign bit if order of operands is changed.
Don't forget to normalize number afterward.
EXAMPLE:
0 10000001 10010001000000000000000 (the representations)
- 0 10000000 11100000000000000000000
---------------------------------------------------------
step 1: align radix points
0 10000000 11100000000000000000000
becomes
0 10000001 11110000000000000000000 (notice hidden bit shifted in)
0 10000001 1.10010001000000000000000
- 0 10000001 0.11110000000000000000000
--------------------------------------------------------------

step 2: subtract mantissa

 1.10010001000000000000000
- 0.11110000000000000000000
--------------------------------------------
0.10100001000000000000000
step 3: put result in normalized form
Shift mantissa left by 1 place, implying a subtraction of 1 from the exponent.
0 10000000 01000010000000000000000

MULTIPLICATION:
example on decimal values given in scientific notation:
3.0 x 10 ** 1
+ 0.5 x 10 ** 2
-----------------
algorithm: multiply mantissas
add exponents
3.0 x 10 ** 1
+ 0.5 x 10 ** 2
-----------------
1.50 x 10 ** 3

example in binary: use a mantissa that is only 4 bits so that

I don't spend all day just doing the multiplication
part.

0 10000100 0100
x 1 00111100 1100
--------------------------
mantissa multiplication: 1.0100
(don't forget hidden bit) x 1.1100
----------------
00000
00000
10100
10100
 10100
-----------
1000110000
becomes 10.00110000
add exponents: always add true exponents
(otherwise the bias gets added in twice)

biased:
10000100
+ 00111100
-------------------

10000100 01111111 (switch the order of the subtraction,

- 01111111 - 00111100 so that we can get a negative value)
---------- ----------
00000101 01000011
true exp true exp
is 5. is -67
add true exponents 5 + (-67) is -62.
re-bias exponent: -62 + 127 is 65.
unsigned representation for 65 is 01000001.
put the result back together (and add sign bit).
1 01000001 10.00110000
normalize the result:
(moving the radix point one place to the left increases
the exponent by 1.)
1 01000001 10.00110000
becomes
1 01000010 1.000110000
this is the value stored (not the hidden bit!):
1 01000010 000110000
DIVISION:
It is similar to multiplication.
true division:
 do unsigned division on the mantissas (don't forget the hidden bit)
 subtract TRUE exponents
The IEEE standard is very specific about how all this is done.
Unfortunately, the hardware to do all this is pretty slow.
Some comparisons of approximate times:
 2's complement integer add 1 time unit
 fl. pt add 4 time units
 fl. pt multiply 6 time units
 fl. pt. Divide 13 time units
There is a faster way to do division. It is called division by reciprocal approximation.
It takes about the same time as a fl. pt. multiply. Unfortunately, the results are not
always the same as with true division.
Division by reciprocal approximation:
instead of doing a/b
they do a x 1/b.
figure out a reciprocal for b, and then use the fl. pt.
multiplication hardware.
example of a result that isn't the same as with true division.
true division: 3/3 = 1 (exactly)
reciprocal approx: 1/3 = .33333333
3 x .33333333 = .99999999, not 1
It is not always possible to get a perfectly accurate reciprocal.

1.6 Weighted codes binary coded decimal, Non-weighted codes Excess 3

code
Binary code: The digital data is represented, stored and transmitted as group of
binary bits. This group is also called as binary code.
The binary code is represented by the number as well as alphanumeric letter.
The group of symbols is called as a code.
Binary Codes for Decimal digits:
The following table shows the various binary codes for decimal digits 0 to 9.

Decimal Digit 8421 Code 2421 Code 84-2-1 Code Excess 3 Code

0 0000 0000 0000 0011

1 0001 0001 0111 0100

2 0010 0010 0110 0101

3 0011 0011 0101 0110

4 0100 0100 0100 0111

5 0101 1011 1011 1000

6 0110 1100 1010 1001

7 0111 1101 1001 1010

8 1000 1110 1000 1011

9 1001 1111 1111 1100

We have 10 digits in decimal number system. To represent these 10 digits in binary,

we require minimum of 4 bits. But, with 4 bits there will be 16 unique combinations of
zeros and ones. Since, we have only 10 decimal digits, the other 6 combinations of
zeros and ones are not required.
8 4 2 1 code
• The weights of this code are 8, 4, 2 and 1.
• This code has all positive weights. So, it is a positively weighted code.
• This code is also called as natural BCD Binary Coded decimal code.
Example
Let us find the BCD equivalent of the decimal number 786. This number has 3
decimal digits 7, 8 and 6. From the table, we can write the BCD 84218421 codes of
7, 8 and 6 are 0111, 1000 and 0110 respectively.
∴ 78678610 = 011110000110011110000110BCD
There are 12 bits in BCD representation, since each BCD code of decimal digit has 4
bits.
2 4 2 1 code
• The weights of this code are 2, 4, 2 and 1.
• This code has all positive weights. So, it is a positively weighted code.
• It is an unnatural BCD code. Sum of weights of unnatural BCD codes is equal
to 9.
• It is a self-complementing code. Self-complementing codes provide the 9’s
complement of a decimal number, just by interchanging 1’s and 0’s in its equivalent
2421 representation.
Example
Let us find the 2421 equivalent of the decimal number 786. This number has 3
decimal digits 7, 8 and 6. From the table, we can write the 2421 codes of 7, 8 and 6
are 1101, 1110 and 1100 respectively.
Therefore, the 2421 equivalent of the decimal number 786 is 110111101100.
8 4 -2 -1 code
• The weights of this code are 8, 4, -2 and -1.
• This code has negative weights along with positive weights. So, it is a
negatively weighted code.
• It is an unnatural BCD code.
• It is a self-complementing code.
Example
Let us find the 8 4-2-1 equivalent of the decimal number 786. This number has 3
decimal digits 7, 8 and 6. From the table, we can write the 8 4 -2 -1 codes of 7, 8 and
6 are 1001, 1000 and 1010 respectively.
Therefore, the 8 4 -2 -1 equivalent of the decimal number 786 is 100110001010.
Excess 3 code
• This code doesn’t have any weights. So, it is an un-weighted code.
• We will get the Excess 3 code of a decimal number by adding three 00110011
to the binary equivalent of that decimal number. Hence, it is called as Excess 3 code.
• It is a self-complementing code.
Example
Let us find the Excess 3 equivalent of the decimal number 786. This number has 3
decimal digits 7, 8 and 6. From the table, we can write the Excess 3 codes of 7, 8
and 6 are 1010, 1011 and 1001 respectively.
Therefore, the Excess 3 equivalent of the decimal number 786 is 101010111001

1.7 Gray code

A binary code used to represent digits generated from a mechanical sensor that may
be prone to error. Used in telegraphy in the late 1800s, and also known as "reflected
binary code," Gray code was patented by Bell Labs researcher Frank Gray in 1947.
Only Change One Bit
In Gray code, there is only one bit location different between numeric increments,
which make mechanical transitions from one digit to the next less error prone.

The following table shows the 4-bit Gray codes corresponding to each 4-bit binary
code.

Decimal Number Binary Code Gray Code

0 0000 0000

1 0001 0001

2 0010 0011

3 0011 0010

4 0100 0110

5 0101 0111

6 0110 0101

7 0111 0100

8 1000 1100

9 1001 1101

10 1010 1111
 11 1011 1110

12 1100 1010

13 1101 1011

14 1110 1001

15 1111 1000

• This code doesn’t have any weights. So, it is an un-weighted code.

• In the above table, the successive Gray codes are differed in one bit position
only. Hence, this code is called as unit distance code.
Binary code to Gray Code Conversion:
Follow these steps for converting a binary code into its equivalent Gray code.
• Consider the given binary code and place a zero to the left of MSB.
• Compare the successive two bits starting from zero. If the 2 bits are same,
then the output is zero. Otherwise, output is one.
• Repeat the above step till the LSB of Gray code is obtained.
Example
From the table, we know that the Gray code corresponding to binary code 1000 is
1100. Now, let us verify it by using the above procedure.
Given, binary code is 1000.
Step 1 − By placing zero to the left of MSB, the binary code will be 01000.
Step 2 − By comparing successive two bits of new binary code, we will get the gray
code as 1100.

1.8 Alphanumeric codes

Alphanumeric codes are sometimes called character codes due to their certain
properties. Now these codes are basically binary codes. We can write alphanumeric
data, including data, letters of the alphabet, numbers, mathematical symbols and
punctuation marks by this code which can be easily understandable and can be
processed by the computers. Input output devices such as keyboards, monitors,
mouse can be interfaced using these codes. 12-bit Hollerith code is the better known
and perhaps the first effective code in the days of evolving computers in early days.
During this period punch cards were used as the inputting and outputting data. But
nowadays these codes are termed obsolete as many other modern codes have
evolved. The most common alphanumeric codes used these days are ASCII code,
EBCDIC code and Unicode. Now we will discuss about them briefly.
1.8.1 ASCII code
The full form of ASCII code is American Standard Code for Information Interchange.
It is a seven bit code based on the English alphabet.
In 1967 this code was first published and since then it is being modified and updated.
ASCII code has 128 characters some of which are enlisted below to get familiar with
the code.
DEC OCT HEX BIN Symbol Description
0 000 00 00000000 NUL Null char
1 001 01 00000001 SOH Start of Heading
2 002 02 00000010 STX Start of Text
3 003 03 00000011 ETX End of Text
4 004 04 00000100 EOT End of Transmission
5 005 05 00000101 ENQ Enquiry
6 006 06 00000110 ACK Acknowledgment
7 007 07 00000111 BEL Bell
8 010 08 00001000 BS Back Space
9 011 09 00001001 HT Horizontal Tab
10 012 0A 00001010 LF Line Feed
11 013 0B 00001011 VT Vertical Tab
12 014 0C 00001100 FF Form Feed
13 015 0D 00001101 CR Carriage Return
14 016 0E 00001110 SO Shift Out / X-On
15 017 0F 00001111 SI Shift In / X-O
There are many more codes which are not included here.

1.8.2 EBCDIC
The EBCDIC stands for Extended Binary Coded Decimal Interchange Code. IBM
invented this code to extend the Binary Coded Decimal which existed at that time. All
the IBM computers and peripherals use this code. It is an 8 bit code and therefore
can accommodate 256 characters. Below is given some characters of EBCDIC code
to get familiar with it.
Char EBCDIC HEX Char EBCDIC HEX Char EBCDIC HEX
A 1100 0001 C1 P 1101 0111 D7 4 1111 0100 F4
B 1100 0010 C2 Q 1101 1000 D8 5 1111 0101 F5
C 1100 0011 C3 R 1101 1001 D9 6 1111 0110 F6
D 1100 0100 C4 S 1110 0010 E2 7 1111 0111 F7
E 1100 0101 C5 T 1110 0011 E3 8 1111 1000 F8
F 1100 0110 C6 U 1110 0100 E4 9 1111 1001 F9
G 1100 0111 C7 V 1110 0101 E5 blank … …
H 1100 1000 C8 W 1110 0110 E6 . … …
I 1100 1001 C9 X 1110 0111 E7 ( … …
J 1101 0001 D1 Y 1110 1000 E8 + … …
K 1101 0010 D2 Z 1110 1001 E9 $ … …
L 1101 0011 D3 0 1111 0000 F0 * … …
M 1101 0100 D4 1 1111 0001 F1 ) … …
N 1101 0101 D5 2 1111 0010 F2 – … …
O 1101 0110 D6 3 1111 0011 F3 /

1.8.3 ISCII Code

ISCII stands for Indian Script Code for Information Interchange. IISCII was
developed to support Indian languages on computer. Language supported by IISCI
include Devanagari, Tamil, Bangla, Gujarati, Gurmukhi, Tamil, Telugu, etc. IISCI is
mostly used by government departments and before it could catch on, a new
universal encoding standard called Unicode was introduced.

1.8.4 Hollerith code

In 1896, Herman Hollerith formed a company called the Tabulating Machine
Company. This company developed a line of machines that used punched cards for
tabulation. After a number of mergers, this company was formed into the IBM, Inc.
We often refer to the punched-cards used in computer systems as Hollerith cards
and the 12-bit code used on a punched-card is called the Hollerith code.
A Hollerith string is a sequence of l2-bit characters; they are encoded as two ASCII
characters, containing 6 bits each. The first character contains punches 12,0,2,4,6,8
and the second character contains punches 11, 1,3,5, 7, 9. Interleaving the two
characters gives the original 12 bits. To make the characters printable on ASCII
terminals, bit 7 is always set to 0 and bit 6 is said to the complement of bit 5. These
two bits are ignored when reading Hollerith cards.
Today, as punched cards are mostly obsolete and replaced with other storage
medias so the Hollerith code is rendered obsolete.

1.8.5 Morse code

The Morse code, invented in 1837 by Samuel F.B. Morse, was the first alphanumeric
code used in telecommunication. It uses a standardized sequence of short and long
elements to represent letters, numerals and special characters of a given message.
The short and long elements can be formed by sounds, marks, pulses, on off keying
and are commonly known as dots and dashes. For example : The letter ‘A’ is formed
by a dot followed by a dash. The digit 5 is formed by 5 dots in succession. The
International Morse code treats a dash equal to three dots. To see the details of
Morse code table you can refer the Internet search engines.
Due to variable length of Morse code characters, the morse code could not adapt to
automated circuits. In most electronic communication, the Baudot code and ASCII
code are used.
Morse code has limited applications. It is used in communication using telegraph
lines, radio circuits. Pilots and air traffic controllers also use them to transmit their
identity and other information

1.8.6 Teletypewriter (TTY)

A teletypewriter (TTY) is an input device that allows alphanumeric character to be
typed in and sent, usually one at a time as they are typed, to a computer or a printer.
The Teletype Corporation developed the teletypewriter, which was an early interface
to computers. Teletype mode is the capability of a keyboard, computer, application,
printer, display, or modem to handle teletypewriter input and output. Basically, this is
a one-character-at-a-time mode of sending, receiving, or handling data, although it is
often modified to handle a line of characters at a time. Since this mode requires little
programming logic, it is often used where memory is limited. The Basic Input/Output
Operating System ( BIOS ) sends messages to a PC display using teletype mode.
Most printers offer a teletype mode. The simplest video display output format is text
in teletype mode. Many modems today continue to include support for a TTY
interface.
1.9 Error detection and correction
What is Error?
Error is a condition when the output information does not match with the input
information. During transmission, digital signals suffer from noise that can introduce
errors in the binary bits travelling from one system to other. That means a 0 bit may
change to 1 or a 1 bit may change to 0.

Error-Detecting codes
Whenever a message is transmitted, it may get scrambled by noise or data may get
corrupted. To avoid this, we use error-detecting codes which are additional data
added to a given digital message to help us detect if an error occurred during
transmission of the message. A simple example of error-detecting code is parity
check.
Error-Correcting codes
Along with error-detecting code, we can also pass some data to figure out the
original message from the corrupt message that we received. This type of code is
called an error-correcting code. Error-correcting codes also deploy the same strategy
as error-detecting codes but additionally, such codes also detect the exact location
of the corrupt bit.
In error-correcting codes, parity check has a simple way to detect errors along with a
sophisticated mechanism to determine the corrupt bit location. Once the corrupt bit is
located, its value is reverted (from 0 to 1 or 1 to 0) to get the original message
1.10 Universal Product Code
A UPC, short for universal product code, is a type of code printed on retail product
packaging to aid in identifying a particular item. It consists of two parts – the
machine-readable barcode, which is a series of unique black bars, and the unique
12-digit number beneath it.
The purpose of UPCs is to make it easy to identify product features, such as the
brand name, item, size, and color, when an item is scanned at checkout. In fact,
that’s why they were created in the first place – to speed up the checkout process at
grocery stores. UPCs are also helpful in tracking inventory within a store or
warehouse.
To obtain a UPC for use on a product a company has to first apply to become part of
the system. GS1 US, the Global Standards Organization, formerly known as the
Uniform Code Council, manages the assigning of UPCs within the US.
Parts of a UPC
After paying a fee to join, GS1 assigns a 6-digit manufacturer identification number,
which becomes the first six digits in the UPC on all the company’s products. That
number identifies the particular manufacturer of the item.
The next five digits of the UPC is called an item number. It refers to the actual
product itself. Within each company is a person responsible for issuing item
numbers, to ensure that the same number isn’t used more than once and that old
numbers referring to discontinued products are phased out.
Many consumer products have several variations, based on, for example, size,
flavor, or color. Each variety requires its own item number. So a box of 24 one-inch
nails has a different item number than a box of 24 two-inch nails, or a box of 50 one-
inch nails.
The last digit in the 12-digit UPC is called the check digit. It is the product of several
calculations – adding and multiplying several digits in the code – to confirm to the
checkout scanner that the UPC is valid. If the check digit code is incorrect, the UPC
won’t scan properly.
Advantages of UPCs
• UPCs have a number of advantages to businesses and consumers. Because
they make it possible for barcode scanners to immediately identify a product and its
associated price, UPCs improve speed.
• They improve efficiency and productivity, by eliminating the need to manually
enter product information.
• They also make it possible to track inventory much more accurately than hand
counting, to know when more product is needed on retail shelves or in warehouses.
Or when there is an issue with a particular product and consumers who purchased it
need to be alerted or a recall issued, UPCs allow products to be tracked through
production to distribution to retail stores and even into consumer homes.
1.11 Code conversion
1.11.1 Binary Arithmetic:
Binary arithmetic is essential part of all the digital computers and much other digital
system.
Binary Addition: It is a key for binary subtraction, multiplication, division. There are
four rules of binary addition.

In fourth case, a binary addition is creating a sum of (1 + 1 = 10) i.e. 0 is written in

the given column and a carry of 1 over to the next column.

Example − Addition

Binary Subtraction
Subtraction and Borrow, these two words will be used very frequently for the
binary subtraction. There are four rules of binary subtraction.
Example − Subtraction

Binary Multiplication
Binary multiplication is similar to decimal multiplication. It is simpler than decimal
multiplication because only 0s and 1s are involved. There are four rules of binary
multiplication.

Example − Multiplication

Binary Division
Binary division is similar to decimal division. It is called as the long division
procedure.
Example − Division

Octal Number System

Following are the characteristics of an octal number system.
 Uses eight digits, 0,1,2,3,4,5,6,7.
 Also called base 8 number system.
 Each position in an octal number represents a 0 power of the base (8).
Example: 80
 Last position in an octal number represents an x power of the base (8).
Example: 8x where x represents the last position - 1.
Example
Octal Number − 125708
Calculating Decimal Equivalent −

Step Octal Number Decimal Number

Step 1 125708 ((1 × 84) + (2 × 83) + (5 × 82) + (7 × 81) + (0 × 80))10

Step 2 125708 (4096 + 1024 + 320 + 56 + 0)10

Step 3 125708 549610

Note − 125708 is normally written as 12570.

Octal Addition
Following octal addition table will help you to handle octal addition.
To use this table, simply follow the directions used in this example: Add 6 8 and 58.
Locate 6 in the A column then locate the 5 in the B column. The point in 'sum' area
where these two columns intersect is the 'sum' of two numbers.
68 + 58 = 138.
Example − Addition

Octal Subtraction
The subtraction of octal numbers follows the same rules as the subtraction of
numbers in any other number system. The only variation is in borrowed number. In
the decimal system, you borrow a group of 10 10. In the binary system, you borrow a
group of 210. In the octal system you borrow a group of 810.
Example − Subtraction

Hexadecimal Number System

Following are the characteristics of a hexadecimal number system.
 Uses 10 digits and 6 letters, 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F.
  Letters represents numbers starting from 10. A = 10, B = 11, C = 12, D = 13,
E = 14, F = 15.
 Also called base 16 number system.
 Each position in a hexadecimal number represents a 0 power of the base
(16). Example − 160
 Last position in a hexadecimal number represents an x power of the base
(16). Example − 16x where x represents the last position - 1.
Example
Hexadecimal Number − 19FDE16
Calculating Decimal Equivalent −

Step Hexadecimal Decimal Number

Number

Step 1 19FDE16 ((1 × 164) + (9 × 163) + (F × 162) + (D × 161) + (E ×

160))10

Step 2 19FDE16 ((1 × 164) + (9 × 163) + (15 × 162) + (13 × 161) + (14 ×
160))10

Step 3 19FDE16 (65536 + 36864 + 3840 + 208 + 14)10

Step 4 19FDE16 10646210

Note − 19FDE16 is normally written as 19FDE.

Hexadecimal Addition
Following hexadecimal addition table will help you greatly to handle Hexadecimal
addition.
To use this table, simply follow the directions used in this example − Add A 16 and
516. Locate A in the X column then locate the 5 in the Y column. The point in 'sum'
area where these two columns intersect is the sum of two numbers.
A16 + 516 = F16.
Example − Addition

Hexadecimal Subtraction
The subtraction of hexadecimal numbers follow the same rules as the subtraction of
numbers in any other number system. The only variation is in borrowed number. In
the decimal system, you borrow a group of 10 10. In the binary system, you borrow a
group of 210. In the hexadecimal system you borrow a group of 1610.
Example - Subtraction

BCD and Excess -3:

There are many methods or techniques which can be used to convert code from
one format to another. We'll demonstrate here the following

 Binary to BCD Conversion

 BCD to Binary Conversion
 BCD to Excess-3
 Excess-3 to BCD
Binary to BCD Conversion
Steps
 Step 1 -- Convert the binary number to decimal.
 Step 2 -- Convert decimal number to BCD.
Example − convert (11101)2 to BCD.
Step 1 − Convert to Decimal
Binary Number − 111012
Calculating Decimal Equivalent −

Step Binary Number Decimal Number

Step 1 111012 ((1 × 24) + (1 × 23) + (1 × 22) + (0 × 21) + (1 × 20))10

Step 2 111012 (16 + 8 + 4 + 0 + 1)10

Step 3 111012 2910

Binary Number − 111012 = Decimal Number − 2910

Step 2 − Convert to BCD
Decimal Number − 2910
Calculating BCD Equivalent. Convert each digit into groups of four binary digits
equivalent.
 Step Decimal Number Conversion

Step 1 2910 00102 10012

Step 2 2910 00101001BCD

Result
(11101)2 = (00101001)BCD
BCD to Binary Conversion
Steps
 Step 1 -- Convert the BCD number to decimal.
 Step 2 -- Convert decimal to binary.
Example − convert (00101001)BCD to Binary.
Step 1 - Convert to BCD
BCD Number − (00101001)BCD
Calculating Decimal Equivalent. Convert each four digit into a group and get
decimal equivalent for each group.

Step BCD Number Conversion

Step 1 (00101001)BCD 00102 10012

Step 2 (00101001)BCD 210 910

Step 3 (00101001)BCD 2910

BCD Number − (00101001)BCD = Decimal Number − 2910

Step 2 - Convert to Binary
Used long division method for decimal to binary conversion.
Decimal Number − 2910
Calculating Binary Equivalent −

Step Operation Result Remainder

Step 1 29 / 2 14 1

Step 2 14 / 2 7 0
 Step 3 7 / 2 3 1

Step 4 3 / 2 1 1

Step 5 1 / 2 0 1

As mentioned in Steps 2 and 4, the remainders have to be arranged in the reverse

order so that the first remainder becomes the least significant digit (LSD) and the
last remainder becomes the most significant digit (MSD).
Decimal Number − 2910 = Binary Number − 111012
Result
(00101001)BCD = (11101)2
BCD to Excess-3
Steps
 Step 1 -- Convert BCD to decimal.
 Step 2 -- Add (3)10 to this decimal number.
 Step 3 -- Convert into binary to get excess-3 code.
Example − convert (0110)BCD to Excess-3.
Step 1 − Convert to decimal
(0110)BCD = 610
Step 2 − Add 3 to decimal
(6)10 + (3)10 = (9)10
Step 3 − Convert to Excess-3
(9)10 = (1001)2
Result
(0110)BCD = (1001)XS-3
Excess-3 to BCD Conversion
Steps
 Step 1 -- Subtract (0011)2 from each 4 bit of excess-3 digit to obtain the
corresponding BCD code.
Example − convert (10011010)XS-3 to BCD.
Given XS-3 number = 1 0 0 1 1 0 1 0
Subtract (0011)2 = 1 0 0 1 0 1 1 1
--------------------
BCD = 0 1 1 0 0 1 1 1
Result
(10011010)XS-3 = (01100111)BCD

1.12 Summary

1.13 Reference for further reading

 Unit III: Combinational Logic Circuits
Chapter-1
3.0 Introduction- Combinational Logic Circuits
3.1 Multi Input Combinational Circuit
3.2 Multi Output Combinational Circuit
3.3 Code Converters Design and Implementation
Chapter-2
3.4 Arithmetic Circuits
3.4.1 Introduction- Arithmetic Circuits
3.4.2 Adder
3.4.3 BCD Adder
3.4.4 Excess-3 Adder
3.4.5 Binary Subtrac
tors
3.4.6 BCD Subtractor
Chapter-3
3.5 Multiplier
3.6 Comparator
List of References

Chapter - 1

3.0 Introduction Combinational Logic Circuits

Combinational Logic Circuits are circuits designed by using different types of logic
gates. A logic gate is a fundamental building block of any electronic circuit. In other
word Combinational Logic Circuits are memoryless digital logic circuits whose output
at any instant in time depends only on the combination of its inputs. Means these
circuits do not make use of any memory or storage device.

The digital system consists of two types of circuits as -

a) Combinational circuits b) Sequential circuits

1
Combinational circuit consists of logic gates whose output at any time is determined
from the present combination of inputs. The logic gate is the most basic building
block of combinational logic circuit.

A combinational circuit consists of –

- Input variables
- Logic gates
- Output variables

The logic gates accept signals from inputs and output signals are generated
according to the logic circuits working in it. Binary information from the given data
transforms to preferred output data in this process. Both input and output are
apparently the binary signals, i.e. both the input and output signals are of two
probable states, logic ‘1’ and logic ‘0’. Logical function performed by a
combinational circuit is completely defined by a set of Boolean expressions.

The function implemented by combinational circuit is depend upon the Boolean

expressions. Below figure shown the combinational circuit having ‗n‘ inputs and
‗m‗outputs. The ‗n‘ number of inputs shows that there are 2 n possible combinations
of bits at the input.

Fig. : Combinational circuit having ‗n‘ inputs and ‗m‗ outputs

Combinational logic circuits may be very simple or very complicated and any
combinational circuit can be implemented with only NAND and NOR gates as these
are classified as universal gates.

Design Procedure

At all combinational circuit can be designed by the following steps of design process-

2
 1. Stated problem

2. Ascertainthe input and output variables

3. The input and output variables are allocated letter symbols

4. Construction of a truth table to encounter input -output requirements

5. Writing Boolean expressions for numerous output variables in relations of

input variables.

6. The basic Boolean expression is acquired by any method of minimization—

algebraic, or tabulation method. orKarnaugh map method.

7. A logic diagram is understood from the simplified Boolean expression using

logic gates.

The logic gates are combined in such a way that the output state depends
completely on the input states. Combinational logic circuits have no memory, timing
or feedback loops, there operation is prompt. A combinational logic circuit performs
an operation assigned logically by a Boolean expression or truth table.

The three main methods of specifying the function of a combinational logic circuit as-

1. Boolean Algebra – This forms the algebraic expression viewing the operation
of the logic circuit for each input variable whicheverTrue or False that results in a
logic ―1‖ output.

2. Truth Table – A truth table expresses the function of a logic gate by providing a
brief list that shows all the output states in tabular form for each possible
combination of input variable that the gate could meet.

3. Logic Diagram – This is a graphical representation of a logic circuit that

displays the wiring and connections of each individual logic gate, signified by a
specific graphical symbol that implements the logic circuit. These logic circuit
representations are shown as-

Logic Diagram Boolean Truth Table

Expression

3
Fig. : Combinational Circuit Diagram, Boolean Expression & truth Table

As combinational logic circuits are made up from discrete logic gates only, they can
also be considered as decision making circuits and combinational logic is nearby
combining logic gates together to process two or more signals in order to produce at
least one output signal according to the logical function of each logic gate. General
combinational circuits made up from individual logic gates that carry out a anticipated
application comprise Full and Half Adders Multiplexers, De-
multiplexers, Encoders, Decoders etc.

Classification of Combinational Logic

Fig. Classification of Combinational Logic

4
One of the greatest uses of combinational logic is in Multiplexer and De-multiplexer
type circuits. Here, multiple inputs or outputs are connected to a common signal
stripe and logic gates are used to decode an address to select a single data input or
output switch.

………………………………………………………………………………………………

3.1 Multi Input Combinational Circuit

In processor designs, transistors are protected down for specific functions. To

overcome the restriction of fixed structures of static architecture in the next
generation of computer is an important issue to the real-world applications. A
reconfigurable technique with dynamic architecture has made it possible to break
through the stable limitations of the current computer systems. In dynamic
architecture, systems can flexibly change their hardware configurations during the
course of computation according to the demands of various functions. Multi input
gates can be made by constructing gates of the same type with fewer inputs. The
figure below shown how a three input AND gate can be made out of
two input AND gates.The same logical standard applies - the output goes ―low‖ (0) if
any of the inputs are made ―high‖ (1).

Combinational Logic Circuits are made up from basic logic NAND, NOR or NOT
gates that are connected together to produce more complex switching circuits.
These logic gates are the building blocks of combinational logic circuits. An example
of a combinational circuit-Decoder, which converts the binary code data present at
its input into a number of diverse output lines, one at a time producing an equivalent
decimal code at its output.

Fig. Multi Input Combinational Circuit

The number of possible input states is equal to two to the power of the number of
inputs:

5
This increase in the number of possible input states obviously allows for more
complex gate performance. Instead of simply inverting a single ―high‖ or ―low‖ logic
level, the output of the gate will be determined by whatsoever combination of 1‘s and
0‘s is present at the input stations.

Since many combinations are possible with just a limited input stations, there are
many different types of multiple-input gates, unlike single-input gates which can
simply be inverters. Each basic gate type will be shown as its standard symbol, truth
table, andoperation.

Types of different Multi Input Combinational Circuit

a) AND Gate
b) NAND Gate
c) Negative AND Gate
d) OR Gate
e) NOR Gate
f) Negative OR Gate
g) Exclusive OR Gate
h) Encoder
i) Multiplexer

a) AND Gate

The simple multiple-input gates to recognize is the AND gate, the output of this gate
will be ―high‖ (1) if and only if all inputs are ―high‖ (1). If any input(s) is ―low‖ (0), the
output is certain to be in a ―low‖ state.

Two input AND gate Three input AND gate Truth Table

6
AND Gate Circuit Operation

The truth table means in practical terms is shown in the following sequence as, with
the 2-input AND gate exposed to all possibilities of input logic levels. An LED
provides visual signal of the output logic level.

Circuit Diagram

It is only with all inputs raised to ―high‖ logic levels that the AND gate‘s output goes
―high,‖ thus stimulating the LED for only one out of the four input combination states.

b) NAND Gate

A distinction on the idea of the AND gate is called the NAND gate. The term ―NAND‖
is a verbal contraction of the words NOT and AND. Fundamentally, a NAND gate
performs the same as an AND gate with a NOT gate connected to the output
terminal. To represent this output signal inversion, the NAND gate symbol has a
bubble on the output line.The truth table for a NAND gate is as one might expect,
preciselyopposite as that of an AND gate

NAND gate Truth Table

7
As with AND gates, NAND gates are made with more than two inputs. In such cases,
the same over-allstandardrelates: the output will be ―low‖ (0) if and only if all inputs
are ―high‖ (1). If any input is ―low‖ (0), the output will go ―high‖ (1).

c) Negative AND Gate

A Negative-AND gate purposes the same as an AND gate with all its inputs inverted
(connected through NOT gates). In trust with standard gate symbol convention,
these inverted inputs are showed by bubbles. Opposing to most publics‘ first nature,
the logical conduct of a Negative-AND gate is not the same as a NAND gate. Its truth
table, essentially, is matching to a NOR gate:

Negative AND gate Truth Table Circuit Diagram

d) OR Gate

Next gate to study is the OR gate, so-called because the output of this gate will be
―high‖ (1) if any of the inputs are ―high‖ (1). The output of an OR gate goes ―low‖ (0) if
and only if all inputs are ―low‖ (0).

Two input Three Input Truth Table

8
A two-input OR gate‘s truth table appearances like the following sequence of
drawingsproves the OR gate‘s function, with the 2-inputs undergoing all possible logic levels.
An LED delivers visual indication of the gate‘s output logic level

Circuit Diagram

A condition of any input being outstretched to a ―high‖ logic level makes the OR
gate‘s output go ―high,‖ thus stimulating the LED for three out of the four input
combination states.

e) NOR gate

The NOR gate is an OR gate with its output inverted, just like a NAND gate is an
AND gate with an inverted output.

NOR Gate Truth Table Circuit Diagram

9
NOR gates, like all the other multiple-input gates realized thus outlying, can be
synthetic with more than two inputs. Still, the same logical standard applies. The
output goes ―low‖ (0) if any of the inputs are made ―high‖ (1). The output is ―high‖ (1)
only when all inputs are ―low‖ (0

e) Negative-OR Gate

A Negative-OR gate functions the same as an OR gate with all its inputs inverted. In
possession with standard gate symbol convention, these inverted inputs are showed
by bubbles. The performance and truth table of a Negative-OR gate is the same as
for a NAND gate:

Negative OR gate Truth Table Circuit Diagram

e) Exclusive OR Gate

This gate is direct variations on three basic functions- AND, OR, and NOT. The
Exclusive-OR gate, however, is approximatelyfairly different. Exclusive-OR gates
output a ―high‖ (1) logic level if the inputs are at different logic levels, either 0 and 1

10
or 1 and 0. Contrariwise, the output a ―low‖ (0) logic level if the inputs are at the
same logic levels.

The Exclusive-OR ( XOR) gate has both a symbol and a truth table pattern that is
distinctive:

Exclusive OR Gate Truth table

There are corresponding circuits for an Exclusive-OR gate made up of AND, OR,
and NOT gates, just as there were for NAND, NOR, and the negative-input gates. A
slightly direct method to simulating an Exclusive-OR gate is to start with a regular
OR gate, then add additional gates to prevent the output from going ―high‖ (1) when
both inputs are ―high‖ (1):

h) Encoder

An encoder is a digital circuit that accomplishes the inverse operation of a decoder.

Hence, the opposite of the decoding process is called encoding. An encoder is a
combinational circuit that converts binary information from 2n input lines to a
maximum of ‘n‗ unique output lines.

11
It has 2n input lines, only one which ‗1‘ is active at any time and ‘n‗output lines. It
encodes one of the active inputs to a coded binary output with ‘n‗ bits. In an encoder,
the number of outputs is less than the number of inputs.

a) Octal-to-Binary Encoder
It has eight inputs and the three outputs that produce the equivalent binary number.
It is assumed that only one input has a value of ‗1‘ at any given time.

Table: Input / Output of Octal-to-‗Binary Encoder

The encoder can be implemented with OR gates whose inputs are determined
straight from the truth table. Output z is equal to 1, when the input octal digit is 1 or 3
or 5 or 7. Output y is 1 for octal digits 2, 3, 6, or 7 and the output is 1 for digits 4, 5, 6
or
7. These conditions can be expressed by the following output Boolean functions:
z= D1+ D3+ D5+ D7
y= D2+ D3+ D6+ D7
x= D4+ D5+ D6+ D7
The encoder can be implemented with three OR gates. The encoder defined in the
below table, has the limitation that only one input can be active at any given time. If
two inputs are active simultaneously, the output produces an approximate
combination.
For eg.if D3 and D6 are 1 concurrently, the output of the encoder may be 111. This
does not represent either D6 or D3. To resolve this problem, encoder circuits must
establish an input priority to ensure that only one input is encoded. If we establish a
higher priority for inputs with higher subscript numbers and if D3 and D6 are 1 at the
same time, the output will be 110 because D6 has higher priority than D3.

12
Fig. Circuit diagram of Octal-to-Binary Encoder
Alternative problem in the octal-to-binary encoder is that an output with all 0‗s is
generated when all the inputs are 0; this output is same as when D0 is equal to 1.
The discrepancy can be resolved by providing one more output to show that at least
one input is equal to 1.

i) Multiplexer: (Data Selector)

A multiplexer or MUX, is a combinational circuit with more than one input line, one
output line and more than one selection line. A multiplexer selects binary information
present from one of many input lines, depending upon the logic status of the
selection inputs, and directions it to the output line. Generally, there are 2n input
lines and n selection lines whose bit combinations determine which input is selected.
The multiplexer is labeled as MUX in block diagrams. A multiplexer is also called a
data selector, since it selects one of many inputs and directs the binary information
to the output line.

Fig. multiplexer

13
 j) 2-to-1- line Multiplexer
This circuit has two data input lines, one output line and one selection line. When S=
0, the upper AND gate is enabled and I0 has a path to the output.
When S=1, the lower AND gate is enabled and I1 has a path to the output.

Fig.Circuit diagram 2-to-1- line Multiplexer

The multiplexer acts like an electronic switch that selects one of the two sources.

Table: Truth table

ii) 4-to-1-line Multiplexer

A 4-to-1-line multiplexer has four (2n) input lines, two (n) select lines and one output
line. It is the multiplexer comprising of four input channels and information of one of
the station can be selected and transmitted to an output line according to the select
inputs combinations. Selection of one of the four input station is possible by two
selection inputs.
Each of the four inputs I0 through I3, is applied to one input of AND gate. Selection
lines S1 and S0 are decoded to select a particular AND gate. The outputs of the AND
gate are applied to a single OR gate that provides the 1-line output.

14
Fig. Circuit diagram of 4-to-1-line Multiplexer

Table: Truth table 4-to-1-line Multiplexer

To establish the circuit operation, consider the case when S1S0= 10. The AND gate
associated with input I2 has two of its inputs equal to 1 and the third input connected
to I2. The other three AND gates have at least one input equal to 0, which makes
their outputs equal to 0. The OR output is now equal to the value of I 2, providing a
path from the selected input to the output.

The data output is equal to I0 only if S1= 0 and S0= 0; Y= I0S1‗S0‗. The data output is
equal to I1 only if S1= 0 and S0= 1; Y= I1S1‗S0. The data output is equal to I2 only if
S1= 1 and S0= 0; Y= I2S1S0‗. The data output is equal to I3 only if S1= 1 and S0= 1; Y=
I3S1S0.
When these terms are ORed, the total expression for the data output is,
Y= I0S1‘S0‘+ I1S1‘S0 +I2S1S0‘+ I3S1S0.

15
As in decoder, multiplexers may have an enable input to control the operation of the
unit. When the enable input is in the inactive state, the outputs are disabled, and
when it is in the active state, the circuit functions as a usual multiplexer.

………………………………………………………………………………………….............
.

3.2 Multi Output Combinational Circuit

A combinational circuit has output values that depend only on the current input
values irrespective of presence or absence of responses.Circuits that implement
these functions may be combined into expensive single circuit with multiple outputs
by sharing some gates desirable in the implementation of the single functions.
Boolean expressions are used to output a Boolean function of number of variables.
There are circuits which have multiple outputs and multiple inputs. Conventional
combinational circuits are normally acyclic but these circuits can have feedbacks
(cycles) which will give more minimized expressions as compared to usual
combinational circuits. Thoughtfulintegration of such cycles or feedbacks in usual
combinational circuits eventually results in reduction in number of literals in the
expression of the combinational circuits. The reduction in literal counts decreases
the number of gates required to implement the expressions of the combinational
circuits. Hence, the decrease in number of gates leads to reduction in transistor
counts. A cyclic combinational circuit is defined as the circuit whose output depends
on present inputs only, but at the same time contains one or more feedbacks
(cycles)
Types of multiple-output circuits

i) Decoder a) 2 to 4 decoder b) 3- to-8 Line Decoder

ii) Demultiplexer a) 1 to 4 Demultiplexer b) 3 to 8 Demultiplxer

i) Decoder

A decoder is a combinational circuit that converts binary information from ‗‘n‗ input
lines to a maximum of ‗2n unique output lines. The general structure of decoder
circuit is

16
Fig. Decoder block diagram

The encoded information is presented as ‘n‗inputs producing 2n possible outputs.

The 2n output values are from 0 through 2n-1. A decoder is provided with enable
inputs to activate decoded output based on data inputs. When any one enable input
is unasserted, all outputs of decoder are disabled

a) Binary Decoder (2 to 4 decoder)

A binary decoder has ‘n‗ bit binary input and a one activated output out of 2 n outputs.
A binary decoder is used when it is necessary to activate exactly one of 2 n outputs
based on an n-bit input value.

Fig. 2 to 4 decoder circuit diagram

17
Here the 2 inputs are decoded into 4 outputs, each output signifying one of the
minterms of the two input variables.

Fig.Truth table 2 to 4 decoder circuit

As shown in the truth table, if enable input is 1 (EN= 1) only one of the outputs (Y 0 –
Y3), is active for a given input.
The output Y0 is active, i.e., Y0= 1 when inputs A= B= 0, Y1 is active when inputs, A=
0 and B= 1,
Y2 is active, when input A= 1 and B= 0, Y3 is active, when inputs A= B= 1.

b)3- to-8 Line Decoder

A 3-to-8 line decoder has three inputs (A, B, C) and eight outputs (Y0- Y7). Based on
the 3 inputs one of the eight outputs is selected.
The three inputs are decoded into eight outputs, each output signifying one of the
minterms of the 3-input variables. This decoder is used for binary-to-octal
conversion. The input variables may represent a binary number and the outputs will
signify the eight digits in the octal number system. The output variables are mutually
exclusive because only one output can be equal to 1 at any one time. The output line
whose value is equal to 1 signifies the minterm equivalent of the binary number
presently accessible in the input lines.

18
Fig.Truth table 3- to-8 Line Decoder

Fig. 3- to-8 Line Decoder:

ii) Demultiplexer

Demultiplex means one into many. Demultiplexing is the process of taking

information from one input and transmitting the same over one of several outputs. A
demultiplexer is a combinational logic circuit that receives information on a single
input and transmits the same information over one of several (2n) output lines.

19
Fig. Demultiplexer circuit
The block diagram of a demultiplexer which is opposite to a multiplexer in its
operation is shown above. The circuit has one input signal, ‘n‗ select signals and 2n
output signals. The select inputs determine to which output the data input will be
connected. As the serial data is changed to parallel data, i.e., the input produced to
appear on one of the n output lines, the demultiplexer is also called a ―data
distributer.

i) 1-to-4 Demultiplexer:
A 1-to-4 demultiplexer has a single input, Din, four outputs (Y0 to Y3) and two select
inputs (S1 and S0).

Fig. 1-to-4 Demultiplexer

The input variable Din has a path to all four outputs, but the input information is
directed to only one of the output lines. The truth table of the 1-to-4 demultiplexer is
shown below.

20
Table: Input /Output of 1-to-4 Demultiplexer

From the truth table, it is clear that the data input, Din is connected to the output Y 0,
when S1= 0 and S0= 0 and the data input is connected to output Y1 when S1= 0 and
S0= 1. Similarly, the data input is connected to output Y2 and Y3 when S1= 1 and S0=
0 and when S1= 1 and S0= 1, respectively. From the truth table, the expression for
outputs can be written as follows,
Y0= S1‘S0‘Din
Y1= S1‘S0Din
Y2= S1S0‘Din
Y3= S1S0Din

Fig. Circuit diagram 1-to-4 Demultiplexer

21
Now, using the above expressions, a 1-to-4 demultiplexer can be applied using four
3-input AND gates and two NOT gates. Here, the input data line Din, is connected to
all the AND gates. The two select lines S1, S0 enable only one gate at a time
and the data that appears on the input line passes through the selected gate to the
associated output line.

b)1-to-8 Demultiplexer
A 1-to-8 demultiplexer has a single input, Din, eight outputs (Y0 to Y7) and three
select inputs (S2, S1 and S0). It distributes one input line to eight output lines based
on the select inputs. The truth table of 1-to-8 demultiplexer is shown below.

Table: Input/output of 1-to-8 Demultiplexer

From the above truth table, it is clear that the data input is connected with one of the
eight outputs based on the select inputs. Now from this truth table, the expression for
eight outputs can be written as follows:
Y0= S2‗S1‗S0‗Din Y4= S2 S1‗S0‗Din
Y1= S2‗S1‗S0Din Y5= S2 S1‗S0Din
Y2= S2‗S1S0‗Din Y6= S2 S1S0‗Din
Y3= S2‗S1S0Din Y7= S2S1S0Din
Now using the above expressions, the logic diagram of a 1-to-8 demultiplexer can be
drawn as shown below. Here, the single data line, Din is connected to all the eight
AND gates, but only one of the eight AND gates will be enabled by the select input
lines. For example, if S2S1S0= 000, then only AND gate-0 will be enabled and
thereby the data input, Din will appear at Y0. Similarly, the different combinations of
the select inputs, the input Din will appear at the respective output.

22
Fig.Circuit diagram 1-to-8 Demultiplexer
………………………………………………………………………………………………

3.3 Code Converters Design and Implementation

Introduction

The converters, which convert one code to another code are called as code
converters. These code converters basically consist of Logic gates. The availability
of a large variety of codes for the same distinct elements of information outcomes in
the use of different codes by different digital systems. It is necessary to use the
output of one system as the input to the other. Thus a conversion circuit must be
introduced between the two systems if each uses different codes for the same
information. A code converter is a circuit that makes the two systems well-matched
even though each uses the different codes. Code converters are used for protecting
private information from detectives. They are also used to enhance data portability
and tractability. Code converters have found applications in algorithm generation
and communication. Some of the major codes are as follows:

23
Binary Code: A symbolic representation of data/information is called code. The
base or radix of the binary number is 2. Hence, it has two independent symbols.
The symbols used are 0 and 1. A binary digit is called a bit. A binary number
consists of sequence of bits, each of which is either a 0 or 1. Each bit carries a
weight based on its position comparative to the binary point. The weight of each bit
position is one power of 2 greater than the weight of the position to its immediate
right.

Code Converters Design and Implementation done with the help of following way as
below-

a) Binary code to Gray code converter

b) Parity Bit Generator

i) Even Parity Generator

ii) Odd Party Generator

c) Parity Checker

i) Even Parity Checker

ii) Odd Party Checker

a) Binary code to Gray code converter

Let us implement a converter, which converts a 4-bit binary code WXYZ into its
equivalent Gray code ABCD.

The following table shows the Truth table of a 4-bit binary code to Gray code
converter.

Binary code WXYZ Gray

WXYZ code ABCD

0000 0000
0001 0001
0010 0011

24
 0011 0010
0100 0110
0101 0111
0110 0101
0111 0100
1000 1100
1001 1101
1010 1111
1011 1110
1100 1010
1101 1011
1110 1001
1111 1000

Fig. -bit binary code to Gray code converter

Boolean Expression

From Truth table, we can write the Boolean functions for each output bit of Gray
code as below.

A=∑m(8,9,10,11,12,13,14,15)
B=∑m(4,5,6,7,8,9,10,11)
C=∑m(2,3,4,5,10,11,12,13)
D=∑m(1,2,5,6,9,10,13,14)

Let us simplify the above functions using 4 variable K-Maps.

K-Map

Let us simplify the above functions using 4 variable K-Maps.

The following figure shows the 4 variable K-Map for simplifying Boolean
function, A.

25
 Fig. 4 variable K-Maps

By grouping 8 adjacent ones, we got A=WA=W.

The following figure shows the 4 variable K-Map for simplifying Boolean function, B.

Fig.Simplification of 4 variable –K-Map

There are two groups of 4 adjacent ones. After grouping, we will get B as

B=W′X+WX′=W⊕XB=W′X+WX′=W⊕X

Similarly, we will get the following Boolean functions for C & D after simplifying.

C=X′Y+XY′=X⊕YC=X′Y+XY′=X⊕Y

D=Y′Z+YZ′=Y⊕ZD=Y′Z+YZ′=Y⊕Z

Circuit Diagram

The following figure shows the circuit diagram of 4-bit binary code to Gray code
converter.

26
 Fig. 4-bit binary code to Gray code converter.

Since the outputs depend only on the present inputs, this 4-bit Binary code to Gray
code converter is a combinational circuit. Similarly, you can implement other code
converters.

b) Parity Bit Generator

There are two types of parity bit generators based on the type of parity bit being
generated. Even parity generator generates an even parity bit. Similarly, odd parity
generator generates an odd parity bit.

i) Even Parity Generator ii) Odd Party Generator

i) Even Parity Generator

Let us implement an even parity generator for a 3-bit binary input, WXY. It
generates an even parity bit, P. If odd number of ones present in the input, then
even parity bit, P should be ‗1‘ so that the resultant word contains even number of
ones. For other combinations of input, even parity bit, P should be ‗0‘. The following
table shows the Truth table of even parity generator.

Binary Even
Input Parity
WXY bit P
000 0
001 1
010 1

27
 011 0
100 1
101 0
110 0
111 1

Table. Even parity generator

From the above Truth table, we can write the Boolean function for even parity bit as

P=W′X′Y+W′XY′+WX′Y′+WXYP=W′X′Y+W′XY′+WX′Y′+WXY

⇒P=W′(X′Y+XY′)+W(X′Y′+XY)⇒P=W′(X′Y+XY′)+W(X′Y′+XY)
⇒P=W′(X⊕Y)+W(X⊕Y)′=W⊕X⊕Y⇒P=W′(X⊕Y)+W(X⊕Y)′=W⊕X⊕Y

The following figure shows the circuit diagram of even parity generator.

Fig. circuit diagram of even parity generator

This circuit consists of two Exclusive-OR gates having two inputs each. First
Exclusive OR gate having two inputs W & X and produces an output W ⊕ X. This
output is given as one input of second Exclusive-OR gate. The other input of this
second Exclusive-OR gate is Y and produces an output of W ⊕ X ⊕ Y.

ii) Odd Parity Generator

If even number of ones present in the input, then odd parity bit, P should be ‗1‘ so
that the resultant word contains odd number of ones. For other combinations of
input, odd parity bit, P should be ‗0‘.Follow the same procedure of even parity
generator for implementing odd parity generator. The circuit diagram of odd parity
generator is shown in the following figure.

28
 Fig: circuit diagram of odd parity generator

The above circuit diagram consists of Ex-OR gate in first level and Ex-NOR gate in
second level. Since the odd parity is just opposite to even parity, we can place an
inverter at the output of even parity generator. In that case, the first and second
levels contain an Ex-OR gate in each level and third level consist of an inverter.

c) Parity Checker

There are two types of parity checkers based on the type of parity has to be
checked. Even parity checker checks error in the transmitted data, which contains
message bits along with even parity. Similarly, odd parity checker checks error in
the transmitted data, which contains message bits along with odd parity.

i) Even Parity Checker ii) Odd Party Checker

i) Even parity checker

Let us implement an even parity checker circuit. Consider a 3-bit binary input, WXY
is transmitted along with an even parity bit, P. So, the resultant word data contains 4
bits, which will be received as the input of even parity checker.

It generates an even parity check bit, E. This bit will be zero, if the received data
contains an even number of ones. That means, there is no error in the received
data. This even parity check bit will be one, if the received data contains an odd
number of ones. That means, there is an error in the received data.The following
table shows the Truth table of an even parity checker.

4-bit Received Even Parity

Data WXYP Check bit E

29
 0000 0

0001 1

0010 1

0011 0

0100 1

0101 0

0110 0

0111 1

1000 1

1001 0

1010 0

1011 1

1100 0

1101 1

1110 1

1111 0

Table: Truth table of an even parity checker.

30
From the above Truth table, we can perceive that the even parity check bit value is
‗1‘, when odd number of ones present in the received data. That means the Boolean
function of even parity check bit is an odd function. Exclusive-OR function satisfies
this condition. Hence, we can directly write the Boolean function of even parity
check bit as

E=W⊕X⊕Y⊕PE=W⊕X⊕Y⊕P

The following figure shows the circuit diagram of even parity checker.

Fig: circuit diagram of even parity checker

This circuit consists of three Exclusive-OR gates having two inputs each. The first
level gates produce outputs of W⊕XW⊕X & Y⊕PY⊕P. The Exclusive-OR gate,
which is in second level produces an output of W⊕X⊕Y⊕PW⊕X⊕Y⊕P

Odd Parity Checker

Consider a 3-bit binary input, WXY is transmitted along with odd parity bit, P. So,
the resultant word data contains 4 bits, which will be received as the input of odd
parity checker.

It generates an odd parity check bit, E. This bit will be zero, if the received data
contains an odd number of ones. That means, there is no error in the received data.
This odd parity check bit will be one, if the received data contains even number of
ones. That means, there is an error in the received data.Follow the same procedure
of an even parity checker for implementing an odd parity checker. The circuit
diagram of odd parity checker is shown in the following figure.

31
 Fig: circuit diagram of odd parity checker

The above circuit diagram consists of Ex-OR gates in first level and Ex-NOR gate in
second level. Since the odd parity is just opposite to even parity, we can place an
inverter at the output of even parity checker. In that case, the first, second and third
levels contain two Ex-OR gates, one Ex-OR gate and one inverter correspondingly.

…………………………………………………………………………………………………

32
 Chapter - 2

3.4 Arithmetic Circuits

3.4.1 Introduction to arithmetic circuits

3.4.2 Adder

3.4.3 BCD Adder

3.4.4 Excess-3 Adder

3.4.5 Binary Subtractors

3.4.6 BCD Subtractors

3.4.1 Introduction

Combinational circuit is a circuit in which we have to combine the different gates in

the circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of
the characteristics of combinational circuits are as below −

 The output of combinational circuit at any instant of time, depends only on the
stages present at input stations.

 The combinational circuit do not use any memory. The previous state of input
does not have any effect on the present state of the circuit.

 A combinational circuit can have an ‗n‘ number of inputs and ‗m‘ number of
outputs.

Following are the various types of arithmetic circuits –

Adder, BCDAdder, Binarysubtractor, BCDsubtractor etc.

3.4.2 Adder

Adder arithmetic circuit can classified into two main types as –

a) Half Adder b) Full Adder

a) Half Adder

33
Introduction

Half adder is a combinational logic circuit with two inputs and two outputs.
The half adder circuit is designed to add two single bit binary number A and
B. It is the basic building block for addition of two single bit numbers. This
circuit has two outputs carry and sum.

Block Diagram Truth Table Circuit diagram

b) Full Adder

Introduction

Full adder is designed to overcome the drawback of Half Adder circuit. It can
add two one-bit numbers A and B, and carry C. The full adder is a three input
and two output combinational circuit.

Block Diagram Truth Table Circuit diagram

34
N-Bit Parallel Adder

Introduction

The Full Adder is capable of adding only two single digit binary number along with a
carry input. But in practical we need to add binary numbers which are much longer
than just one bit. To add two n-bit binary numbers, we need to use the n-bit parallel
adder. It uses a number of full adders in cataract. The carry output of the previous
full adder is connected to carry input of the next full adder.

4 Bit Parallel Adder

Introduction

In the block diagram, A0 and B0 represent the Least Significant Bits(LSB) of the four
bit words A and B. Hence Full Adder-0 is the lowest stage. Hence its Cin has been
permanently made 0. The rest of the connections are precisely same as those of n-
bit parallel adder is shown in fig. The four bit parallel adder is a very common logic
circuit.

Block diagram

3.4.3 BCD Adder

Introduction

A 4-bit binary adder that is accomplished of adding two 4-bit words having
a BCD (binary-coded decimal) format. The result of the addition is a BCD-format 4-

35
bit output word, demonstrating the decimal sum of the addend and augend, and a
carry that is generated if this sum exceeds a decimal value of 9.

Use of BCD Adder

A BCD 1-digit adder is a circuit that adds two BCD digits in parallel and also
produces the Sum digit in BCD along with the essential correction logic. It can be
seen that a 4-bit binary adder is used originally to add two BCD digits with a carry-
input. When the binary sum is less than or equal to 9, it also correctly represents
the sum in BCD. When the binary sum is greater than 9, however, it does not
represent the correct BCD sum. The sum in BCD is to be attained by adding 6 to it.

In the BCD representation system each digit is encoded into its binary equivalent
with four (4) bits.

Decimal BCD

0 0000

1 0001

2 0010

3 0011

4 0100

5 0101

6 0110

7 0111

8 1000

9 1001

Table: BCD representation system

Observe that only 10 of the 16 possible bit-patterns are used in BCD. That means
the remaining 6 patterns could be treated as don't-care cases. For the arithmetic
addition of two decimal digits in BCD, the maximum value that may be produced as
the result is 9 + 9 + 1 = 19 (two largest operands plus the carry). If we try to add two
decimal digits in BCD with a 4-bit ripple-carry adder we will get a binary sum

36
extending from 0 to 19. When the binary sum is less than or equal to 9, it may
represents the sum in BCD. When the binary sum is greater than 9, however, it
does not represent the correct BCD sum. The sum in BCD is to be obtained by
adding 6 to it.

Perform the following addition in BCD as explained above:

1) 7 + 4
2) 3 + 2
3) 9 + 9

The above examples should benefit you realize when the conversion is necessary
and what should be done to perform the conversion correctly.

Here is a block diagram of a 1-digit BCD adder

Fig. Block diagram of a 1-digit BCD adder

Complete the truth table below.

Decimal
Inputs Binary Sum BCD Sum
Number
Cin X Y Cout Z Cout S
0 0000 0000 0 0000 0 0000 0
0 0000 0001 0 0001 0 0001 1

37
 0 0001 0001
0 0101 0100
0 0101 0101
0 0101 0110
0 1000 1000 1 0000 1 0110 16
0 1000 1001
0 1001 1001
1 1001 1001
Table: Truth table - 1-digit BCD adder

Upon an examination of the 1-digit BCD adder block diagram shown above, you
should notice that the only block you do not have a circuit for is the ―Sum >
9”? block. Having the circuit just excitingly appear on your circuit diagrams.

3.4.4 Excess-3 Adder

The excess-3 code is a non-weighted code used to express code used to express
decimal numbers. It is a self-complementary Binary Coded Decimal (BCD) code and
numerical system which has partial representation.

The primary benefit of excess-3 coding over non-biased coding is that a decimal
number can be nines' complemented as easily as a binary number can be ones'
complemented, just by inverting all bits.Excess-3 is a modified form of a BCD number.
The excess-3 code can be derived from the natural BCD code by adding 3 to each coded
number.

For example, decimal 12 can be represented in BCD as 0001 0010. Now adding 3 to
each digit we get excess-3 code as 0100 0101 (12 in decimal). With this information
the truth table for BCD to Excess-3 code converter can be determined as-

38
Table: Truth Table - Excess-3 Adder

From the truth table, the logic expression for the Excess-3 code outputs can be
written as,
E3= Σm (5, 6, 7, 8, 9) + Σd (10, 11, 12, 13, 14, 15)
E2= Σm (1, 2, 3, 4, 9) + Σd (10, 11, 12, 13, 14, 15)
E1= Σm (0, 3, 4, 7, 8) + Σd (10, 11, 12, 13, 14, 15)
E0= Σm (0, 2, 4, 6, 8) + Σd (10, 11, 12, 13, 14, 15)

K-map Simplification

39
Circuit Diagram

Fig.Excess-3 Adder circuit

3.4.5 Binary Subtractors

Introduction

The subtraction can be carried out by taking the 1's or 2's complement of the
number to be subtracted. For example we can perform the subtraction (A-B) by

40
adding either 1's or 2's complement of B to A. That means we can use a binary
adder to perform the binary subtraction.

4 Bit Parallel Subtractor

Introduction

The number to be subtracted (B) is first accepted through inverters to obtain its 1's
complement. The 4-bit adder then adds A and 2's complement of B to produce the
subtraction. S3 S2 S1 S0 represents the result of binary subtraction (A-B) and carry
output Cout represents the polarity of the result. If A > B then Cout = 0 and the result
of binary form (A-B) then Cout = 1 and the result is in the 2's complement form.

Block diagram

Fig. 4 Bit Parallel Subtractor

Types of Subtractors

Subtractors circuit can classified into two main category as-

a) Half Subtractor b) Full Subtractors

a) HalfSubtractors

Introduction

Half subtractor is a combination circuit with two inputs and two outputs. It produces
the difference between the two binary bits at the input and also produces an output
to indicate if a 1 has been borrowed. In the subtraction (A-B), A is called as
Minuend bit and B is called as Subtrahend bit.
41
 Truth Table Circuit Diagram

a) Full Subtractors
Introduction

The drawback of a half subtractor is overcome by full subtractor. The full subtractor
is a combinational circuit with three inputs A,B,C and two output D and C'. A is the
'minuend', B is 'subtrahend', C is the 'borrow' produced by the previous stage, D is
the difference output and C' is the borrow output.

Truth Table Circuit Diagram

5.4.6 BCD Subtractor

Introduction

42
A Binary Coded Decimal (BCD) adder is a circuit which adds two 4-bit BCD numbers
in parallel and produces a 4-bit BCD result. The block diagram of
conventional BCD adder. The circuit must include the correction logic to produce
valid BCD output.subtractor an electronic logic circuit for calculating the difference
between two binary numbers, the minuend and the number to be subtracted, the
subtrahend . A full subtractor performs this calculation with three inputs- subtrahend
bit, minuend bit, and borrow bit

BCD Subtraction:
Addition of signed BCD numbers can be accomplished by using 9‘s or 10‘s
complement methods. A negative BCD number can be expressed by taking the 9‘s
or 10‘s complement.The BCD Subtraction using 9‘s Complement and BCD
Subtraction using 10‘s Complement numbers and BCD Subtraction process using it.

9s Complement
The 9‘s complement of a decimal number is found by subtracting each digit in the
number from 9. The 9‘s complement of each of the decimal digits is as follows :

Table:9s Complement

BCD Subtraction using 9s Complement:

43
In 9s Complement subtraction when 9s Complement of smaller number is added to
the larger number carry is produced. It is essential to add this carry to the result.
When larger number is subtracted from smaller one, there is no carry, and the result
is in 9s complement form and negative. This is demonstrated in following ways as-

The 10‘s complement of a decimal number is equal to the 9’s complement plus 1.

BCD Subtraction using 10s Complement

The BCD Subtraction using 10s Complement can be used to accomplish subtraction
by adding the minuend to the 10s Complement of the subtrahend and dropping the
carry. This is demonstrated in following ways as-

44
 From the above examples we can review steps for 9s Complement BCD subtraction
as follows:

 Find the 9‘s complement of a negative number

 Add two numbers using BCD addition
 If carry is generated add carry to the result otherwise find the 9‘s complement of
the result.

45
Fig.4 bit BCD substractor using 9‘s complement

46
 Above figure demonstrate the logic diagram of the circuit to implement above stated
steps to perform BCD subtraction using 9s Complement method. First binary adder
finds the 9s Complement of the negative number. It does this by inverting each bit of
BCD number and adding 10 (1 0 1 02) to it. Let us find the 9‘s complement of 2

Next two 4-bit binary adders accomplish the BCD addition. The last adder finds the
9s Complement of the result if carry is not generated after BCD addition otherwise it
adds carry in the result.From the above examples we can summarize steps for 10s
complement BCD subtraction as -

 Find the 10‘s complement of a negative number

 Add two numbers using BCD addition
 If carry is not generated find the 10s Complement of the result.

47
Fig.4 bit BCD substractorusing 10‘s complement

48
The logic diagram of the circuit to implement above stated steps to perform
subtraction using 10s Complement method. First binary adder finds the 10s
Complement of the negative number (9‘s complement + 1). Next two 4-bit binary
adders perform the BCD addition. Lastly, last 4-bit binary adder finds the 10‘s
complement of the number if carry is not generated after BCD addition.

…………………………………………………………………………………………………

Chapter - 3

3.5 Multiplexer

Introduction

Multiplexer is a distinct type of combinational circuit. There are ‗n‘data inputs, one
output and ‗m‘ select inputs with 2m = ‗n‘. It is a digital circuit which selects one of
the ‗n‘ data inputs and routes it to the output. The selection of one of the ‗n‘ inputs is
done by the selected inputs. Depending on the digital code applied at the selected
inputs, one out of ‗n‘ data sources is selected and transmitted to the single output
‗Y‘. ‗E‘ is called the strobe or enable input which is useful for the cascading. It is
commonly an active low terminal that means it will complete the required operation
when it is low.

Block diagram

Fig: n:1 Multiplexer

Types of Multiplexer

49
Multiplexers come in multiple variations

a) 2 : 1 multiplexer

b) 4 : 1 multiplexer

c) 16 : 1 multiplexer

d) 32 : 1 multiplexer

a) 2 : 1 multiplexer

Block Diagram

Fig.2:1 multiplexer

Truth Table

Table: Truth Table

Demultiplexers

Introduction

50
A demultiplexer achieves the reverse operation of a multiplexer i.e. it receives one
input and distributes it over several outputs. It has only one input, n outputs, m
select input. At a time only one output line is selected by the select lines and the
input is transmitted to the selected output line.

Types of demultiplexer

Demultiplexers comes in multiple variations.

a) 1 : 2 demultiplexer

b) 1 : 4 demultiplexer

c) 1 : 16 demultiplexer

d) 1 : 32 demultiplexer

a) 1 : 2 demultiplexer

Block diagram

Fig. 1:2 Demux

Truth Table

51
 Table : 1:2 Demux truth table

…………………………………………………………………………………………………..
......

3.6 Comparator

Introduction

Comparator is a combinational logic circuit that compares the magnitudes of two

binary quantities to determine which one has the greater magnitude. In other word, a
comparator determines the association of two binary quantities. An ex-OR gate can
be used as a basic comparator. Digital comparators are also called as binary or logic
comparators..

Usage

This logic circuit is used for testing whether the binary number at one input is greater
than or less than or equal to another binary number. In other word, Comparator is a
very useful combinational circuit capable of comparing two numbers as input in
binary form and determines whether one number is greater than, less than or equal
to other number. Comparators can also be used as window detectors.
A comparator is used to compare two voltages and determine whether a given input
voltage is under voltage or over voltage. Comparators are used in central processing
unit (CPUs) and microcontrollers (MCUs).

Types of Comparators

There are two types of comparators:

52
 1. Equality or Identity Comparator

2. Magnitude or inequality comparator

1. Equality or Identity Comparator

Identity Comparator is a digital comparator that has only one output. The
circuit of the equality comparator is made up from an exclusive NOR gate
(XNOR) per pair of input bits. If the two inputs are equal (both logic 1 or both
logic 0) then a logic 1 is output

Consider two 4-bit binary numbers A and B so

Fig. Identity Comparator

Here each subscript represents one of the digits in the numbers.

Equality

The binary numbers A and B will be equal if all the pairs of significant digits of both
numbers are equal, i.e.,

53
Since the numbers are binary, the digits are either 0 or 1 and the Boolean function
for equality of any two digits Ai and Bi can be expressed as

we can also replace it by XNOR gate in digital electronics.

For the equality of A and B, all variables (for i=0,1,2,3) must be 1.

So the equality condition of A and B can be implemented using the AND operation
as

The binary variable (A=B) is 1 only if all pairs of digits of the two numbers are equal

2. Magnitude or inequality comparator

To manually determine the greater of two binary numbers, you have inspect the
relative magnitudes of pairs of significant digits, starting from the most significant bit,
gradually proceeding towards lower significant bits until an inequality is found. When
an inequality is found, if the corresponding bit of A is 1 and that of B is 0 then we
conclude that A>B.

This sequential comparison can be expressed logically as:

Fig.2 inequality comparator.

54
(A>B) and (A < B) are output binary variables, which are equal to 1 when A>B or
A<B respectively.

List of References

1. https://study.com/academy/lesson/basic-combinational-circuits-types-
examples.html
2. https://www.electronics-tutorials.ws/combination/comb_1.html
3. https://www.tutorialspoint.com/computer_logical_organization/combinational_
circuits.htm
4. https://www.tutorialspoint.com/digital_circuits/digital_arithmetic_circuits.htm
5. https://www.allaboutcircuits.com/textbook/digital/chpt-3/multiple-input-gates/

55
 UNIT IV
Chapter 1: Multiplexer and Demultiplexer

Unit Structure
9.0 Multiplexer
9.1 Demultiplexer
9.2 Decoder
9.3 Encoder
9.4 Arithmetic Logic Unit
9.5 Questions
9.6 Further Reading

9.0 Objective

This chapter takes a comprehensive look at another class of building blocks used to design
more complex combinational circuits, and covers building blocks such as multiplexers and
demultiplexers and other derived devices such as encoders and decoders. Particular
emphasis is given to the operational basics and use of these devices to design more
complex combinational circuits.

9.1 Multiplexer

 Multiplex means many into one.

 A digital multiplexer is a combinational circuit that selects binary information from one
of many input lines and directs it to a single output line.
 The selection of a particular input line is controlled by a set of selection lines.
 It is also called a data selector is a device that selects between
several analog or digital input signals and forwards it to a single output line
Block Diagram :

Select lines

Fig.1 Block Diagram

The circuit has n input signals, m select signals and 1 output signal.
Note that, m control signals can select at the most 2m input signals thus n <=2m
4x1 Multiplexer

D3

D2

D1

D0

Fig.2 4x1 multiplexer block diagram

The circuit diagram of a 4-to-l multiplexer is shown in Fig.

Depending on control inputs S1 & S0, one of the four inputs Do to D3 is steered to output Y.
Let us write the logic equation of this circuit. Clearly, it will give a SOP representation, each
AND gate generating a product term, which finally are summed by OR gate. Thus,
Y=S1′S0′D0 + S1′S0D1 + S1S0′D2 + S1S0D3
If S1=0 and S0= 0
Y=0′ 0′ D0 + 0′ 0 D1 + 0 0′ D2 + 0 0 D3
Y=1.1 D0 + 1.0 D1 + 0.1 D2 + 0.0 D3 (0’=1)
Y= D0

In other words, for S1S0 = 00, the first AND gate to which D0 is connected remains active
and equal to D0 and all other AND gate are inactive with output held at logic 0.
Thus, multiplexer output Y is same as D0.
If D0 =0, Y=0 and if D0 = 1, Y= 1.

Control Signals Output

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

A logic diagram of 4-line to 1-line multiplexer is shown in figure 3

Each of the four input lines, D0 to D3, is applied to one input of an AND gate. Selection lines
s1 and s0 are decoded to select a particular AND gate. The function table in the figure lists
the input-to-output path for each possible bit combination of the selection lines.
To demonstrate the circuit operation, consider the case when s1s0 = 10. The AND gate
associated with input D2 has two of its inputs equal to 1 and the third input connected to D2.
The other three AND gates have at least one input equal to 0, which makes their output
equal to 0.

The OR-gate output is now equal to the value of D2, thus providing a path from the selected
input to the output.
 S1 S0

Fig.3 logic diagram of 4 to 1 multiplexer

9.2Demultiplexer

 Demultiplex means one into many.

 A demultiplexer is a circuit that receives information on a single line and transmits
this information on one of 2n possible output lines.
 The selection of a specific output line is controlled by the bit values of n selection
lines.

Select lines
 Fig.4. Demultiplexer Block diagram

Demultiplexer has single data input (D) and n outputs (Y0 – Yn-1).
While number of Select lines depends on number of outputs.
If ‘n’ is number of outputs and ‘m’ is number of select lines then the relation between
them is given by n = 2m.

1 to 4 Demultiplexer

Fig. 5 Block diagram 1 to 4 Demultiplexer

The truth table of this type of demultiplexer is given below.

Input Control Signals Output

S1 S0 Y3 Y2 Y1 Y0
D 0 0 0 0 0 D
D 0 1 0 0 D 0
D 1 0 0 D 0 0
D 1 1 D 0 0 0

From the truth table it is clear that, when S1=0 and S0= 0, the data input is connected to
output Y0 and when S1= 0 and S0=1, then the data input is connected to output Y1.
Similarly, other outputs are connected to the input for other two combinations of select lines.
̅ ̅

̅
 S1 S0

Fig.6 Logic Diagram 1 to 4 Demultiplexer

Decoder

 A decoder is similar to a demultiplexer, with one exception-there is no data input.

 The only inputs are the Select signals.
 Decoder is a logic circuit that converts n-bit binary input code into m output lines.
 The decoders presented here are called n-to-m line decoders where m < 2n.
 Each output line will be activated for only one of the possible combination of inputs.
 m
m

Fig. 7 Block diagram

2 to 4 Decoder

Y0
S0
2 to 4 Y1
Decoder
S1 Y2

Y3

The two inputs are decoded into four outputs, each output representing one of the minterms
of the 2-input variables. The two inverters provide the complement of the inputs, and each
one of the four AND gates generates one of the minterms. A particular application of this
decoder would be a binary-to-octal conversion. The input variables may represent a binary
number, and the outputs will then represent the four digits. However, a 2-to-4 line decoder
can be used for decoding any 2-bit code to provide four outputs, one for each element of
the code.
̅ ̅

Inputs Outputs
S1 S0 Y3 Y2 Y1 Y0
 X X 0 0 0 0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

Y0

Y1

Y2

Y3

Encoder
An Encoder is a combinational circuit that performs the reverse operation of Decoder.
An encoder converts an active input signal into a coded output signal
There are n input lines, only one of which is active.
Internal logic within the encoder converts this active input to a coded binary output with m
bits.
Decimal-to-BCD Encoder
Figure shows a common type of encoder-the decimal-to-BCD encoder.
The switches are push-button switches like those of a pocket calculator.
When button 3 is pressed, the C and D OR gates have high inputs; therefore, the output is
ABCD=0011
If button 5 is pressed, the output becomes
ABCD=0101
When switch 9 is pressed,
ABCD= 1001
 A B C D

Encoders Decoders
Encoders may have more than one input Decoders may have more than one input
line active and may have more than one line active at any given time but only one
output line active at any given time output line will be active
Number of input lines is more than number Number of output lines is more than
of output lines number of input lines
Number of input lines = 2Number of output lines Number of output lines = 2Number of input lines
Encoder is logic device used to create Decoder is logic device used to decode
binary code for given decimal input binary input to give decimal output
Priority Encoder

A priority encoder is a practical form of an encoder. The encoders available in IC form are
all priority encoders. In this type of encoder, a priority is assigned to each input so that,
when more than one input is simultaneously active, the input with the highest priority is
encoded.
In previous cases we saw that if two or more input lines are activated then output code is
invalid. Therefore we have to modify the circuit. The modification is we have to define the
priority of given number. It means whenever two or more inputs are applied at a time,
internal hardware will check this condition and if priority is set such that higher input is to be
taken into account and remaining are considered as don’t care then output code that will
appear is of higher input.

Arithmetic Logic Unit (ALU)

The arithmetic logic unit (ALU) is a digital building block capable of performing both
arithmetic as well as logic operations. Arithmetic logic units that can perform a variety of
arithmetic operations such as addition, subtraction, etc., and logic functions such as
ANDing, ORing, EX-ORing, etc., on two four-bit numbers are usually available in IC form.
The function to be performed is selectable from function select pins. Functional details of
these ICs are given in the latter part of the chapter under the heading of Application-
Relevant Information.
More than one such IC can always be connected in cascade to perform arithmetic and logic
operations on larger bit numbers.

9.5 Questions
1. Define Multiplexer.
2. Write short note on 4 –to- 1 Channel Multiplexer.
3. Explain 4- to -2 Channel Multiplexer With help of suitable diagram.
4. What is De-Multiplexer?
5. What is Digital Encoder? Explain 4- to -2 Bit Binary Encoder with help of suitable
diagram.
6. What is Priority Encoder? Explain 8- to -3 Priority Encoder with the help of suitable
diagram.
7. List and Explain Applications of Encoder.
8. Explain in detail Binary Decoder.
 Chapter 2:
Flip-flops

2.0 Objective
2.1 Introduction to Sequential Circuits
2.2 SR Flip-Flop
2.3 D Flip-Flop
2.4 JK Flip-Flop
2.5 Race Around Condition
2.6 Master Slave JK Flip-Flop
2.7 T Flip-Flop
2.8 Conversion of flip-flop from one type to another
2.9 Applications of Flip-Flop

2.0 Objective:
After completing this chapter, you will be able to:
 Understand the basics of Sequential Logic Circuits.

 Learn different types of Flips –Flops, their working and applications with the help of
suitable diagrams.
2.1 Introduction to Sequential Circuits:
Sequential Circuits: Digital electronics is classified into combinational logic and sequential
logic. Combinational logic output depends on the inputs levels, whereas sequential logic
output depends on stored levels and also the input levels.

Sequential logic elements perform as many different functions as combinational logic

elements; however, they do carry out certain well-defined functions, which have been given
names.
Latch: A latch is a 1-bit memory element. You can capture a single bit in a latch at one
instant and then use it later; for example, when adding numbers, you can capture the carry-
out in a latch and use it as a carry-in in the next calculation.

Register: The register is just m latches in a row and is able to store an m-bit word; that is,
the register is a device that stores one memory word. A computer‟s memory is just a very
large array of registers.

Flip-flop:
In the electronics world, a flip-flop is a type of circuit that has two states (i.e., on or off, 1 or
0). These circuits are often used to store state information. By sending a signal to the flip-
flop, the state can be changed. Flip-flops are used in many electronics, including computers
and communications equipment.

Flip-flops and latches are used as data storage elements. Such data storage can be used
for storage of state, and such a circuit is described as sequential logic. When used in a
finite-state machine, the output and next state depend not only on its current input, but also
on its current state (and hence, previous inputs). It can also be used for counting of pulses,
and for synchronizing variably-timed input signals to some reference timing signal. A flip-
flop can be symbolically represented as shown below:

Generally, Set and Reset Pins are input pins; whereas Q and Q‟ are output pins.
When Set Pin= logic 1, the output Q is SET to 1. (Q‟= 0)
When Reset Pin=logic 1, the output Q is RESET to 0. (Q‟=1)
Note that Q‟ is complement of Q at all times.
2.2 SR Flip- flop:
The R-S flip-flop is the most basic of all flip-flops. The letters „R‟ and „S‟ here stand for
RESET
and SET.
It is constructed by feeding the outputs of two NOR gates back to the other NOR gates as
shown below:
RS Flip-Flop composed of two NOR
Gates.

To understand the operation of the RS-flip-flop (or RS-latch) consider the following
scenarios:
 S=1 and R=0:
o The output of the bottom NOR gate is equal to zero, Q'=0.
o Hence both inputs to the top NOR gate are equal to one, thus, Q=1.
o Hence, the input combination S=1 and R=0 leads to the flip-flop being set to
Q=1.
 S=0 and R=1:
o The output of the top NOR gate is equal to zero, Q=0.
o Hence, the inputs to the bottom NOR gate are equal to 1, thus Q‟=1
o We say that the flip-flop is reset, that is reset to Q=0.
 S=0 and R=0:
o Assume the flip-flop is set (Q=0 and Q'=1), then the output of the top NOR
gate remains at Q=1 and the bottom NOR gate stays at Q'=0.
o Similarly, when the flip-flop is in a reset state (Q=1 and Q'=0), it will remain
there with this input combination.
o Therefore, with inputs S=0 and R=0, the flip-flop remains in its state.
 S=1 and R=1:
 o This input combination must be avoided.

We can summarize the operation of the RS-flip-flop by the following truth table.

R S Q Q' Comment

0 0 Q Q' Hold state

0 1 1 0 Set

1 0 0 1 Reset

1 1 ? ? Avoid

Note, the output Q' is simply the inverse of Q.

An RS flip-flop can also be constructed from NAND gates.

S-R Flip-Flop Using NAND Gate:

A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its
opposing inputs. The term “Flip-flop” means that the output can be “flipped” into one logic
Set state or “flopped” back into the opposing logic Reset state.

The NAND Gate SR Flip-Flop

The Basic SR Flip-flop

The Set State

To understand the operation of the RS-flip-flop (or RS-latch) consider the following
scenarios:
 S’=1 and R’=0:
o In a NAND gate, if one of the input =0, then output of NAND gate=1.
Using this logic, the lower NAND gate Y will be Q‟=1, assuming B=0.
o Let us consider the upper NAND gate X now. A=0 since Q‟=1 from above, but
S‟=1. Therefore, output of X will be 0, that is Q=0. This is exactly what we had
assumed when we said let B=0.
o Thus, the SR flip-flop is said to be RESET to 1. Q=0. Q‟=1
 S’=0 and R’=1:
o Using the same logic, the upper NAND gate X will be Q=1, assuming A=0.
o Let us consider the lower NAND gate Y now. B=1 since Q=1 from above, but
R‟=1. Therefore, output of Y will be 0, that is Q‟=0. This is exactly what we had
assumed when we said let A=0.
o We say that the flip-flop is set, that is set to Q=1. Q‟=0.
 S’=0 and R’=0:
o S‟=0 and R‟=0 is not desired or invalid condition. This must be avoided. This
condition will cause both Q and Q‟ to go high together to logic 1. In such a
case, the flip-flop will become unstable.

 S’=1 and R’=1:

o When both S‟ and R‟ are equal to logic HIGH, the outputs Q and Q‟ can be at
1 or 0 logic level. This depends on the states of S‟ and R‟ before this input
condition existed. Thus, S‟=R‟=1 results in no change of state of the outputs.

Truth Table for this Set-Reset Function

S’ R’ Q Q’ State

1 1 Previous state Previous state No change

1 0 0 1 RESET

0 1 1 0 SET
0 0 ? ? Forbidden

2.3 D Flip-Flop:

The Delay Flip-Flop or D Flip-flop is easily formed from SR flip-flop by adding a NOT

gate(inverter) as shown in the logic diagram.

We have observed that S‟=0, R‟=0 is a forbidden condition in SR NAND gate flip-flop. We
can prevent this from happening by connecting a NOT gate between S and R inputs.
The D flip-flop ensures that S and R can never be simultaneously equal to each other.
The single input then is called the Data input or simply D input.

D-type Flip-Flop Circuit

If D=1, then S=1 in the above circuit resulting in Q=1 and Q‟=0
If D=0, then R=1 in the above circuit resulting in Q‟=1 and Q=0.
Thus, the D input condition is copied to the output Q when the clock input is active. Once
the clock input goes low, the output at Q and Q‟ will remain unchanged. We say that the
output is “latched” at logic 0 or logic 1.

Truth Table for the D-type Flip Flop

 Clk D Q Q‟ Description

Memory
↓»0 X Q Q‟
no change

↑»1 0 0 1 Reset Q » 0

↑»1 1 1 0 Set Q » 1

Note that: ↓ and ↑ indicates direction of clock pulse as it is assumed D-type flip flops are
edge triggered
2.4 JK Flip-Flop:

We have seen that S=0 and R=0 condition in SR NAND flip-flop is forbidden and should be
avoided. Also, while Enable input is HIGH, the correct latching may not occur, if S or R
changes state during this period. To overcome these two problems, the JK flip-flop was
developed. The inputs J and K are derived from its inventor Jack Kilby.

The operation of JK flip-flop is same as the SR flip-flop for same S and R inputs. The
difference is that it has no forbidden or invalid states of SR flip-flop.
The JK flip flop is obtained by adding two NAND gates to SR NAND gate flip-flop as shown
below:
The Basic JK Flip-flop

Both the S and the R inputs of the previous SR bi-stable have now been replaced by two
inputs called the J and K inputs. Thus, J = S and K = R.
The two 2-input AND gates of the gated SR bi-stable have now been replaced by two 3-
input NAND gates with the third input of each gate connected to the outputs at Q and Q‟.
This cross coupling of the SR flip-flop allows the previously invalid condition of S = “1”
and R = “1” state to be used to produce a “toggle action” as the two inputs are now
interlocked.
If the circuit is now “SET”, then the J input is inhibited by the “0” status of Q through the
lower NAND gate. If the circuit is “RESET” the K input is inhibited by the “0” status
of Q through the upper NAND gate. As Q and Q‟ are always different we can use them to
control the input. When both inputs J and K are equal to logic “1”, the JK flip flop toggles as
shown in the following truth table.

The Truth Table for the JK Function

Clock Input Output

Description
same as
for the Clk J K Q Q‟
SR Latch

X 0 0 1 0
Memory
 no change
X 0 0 0 1

↓ 0 1 1 0

Reset Q » 0

X 0 1 0 1

↓ 1 0 0 1

Set Q » 1

X 1 0 1 0

↓ 1 1 0 1
toggle
Toggle
action
↓ 1 1 1 0
2.5 Race-Around Condition:

Before getting into the race around condition, let us have a look at the JK flip-flop‟s truth
table.

Inputs Outputs

J K Q Q'

Same as Same as
0 X X No change
previous previous
Clock
Comments
Input Same as Same as
1 0 0 No change
previous previous

1 0 1 0 1 Reset

1 1 0 1 0 Set

Opposite of Opposite of
1 1 1 Toggle
previous previous

Here, Q is the present state and Q‟ is the next state. As you can see, when J, K and Clock
are equal to 1, toggling takes place, i.e. The next state will be equal to the complement of
the present state.

Now, let us look at the timing diagram of JK flip-flop.

Here, T is the time period of the clock whereas delta t is the propagation delay. The delay
between input and output is called a propagation delay.

This is what was expected, but the output may not be like this all the time. This is
where Race around condition comes into the play.

Let us look at the timing diagram of JK flip-flop when the race around condition is
considered.
When J, K and Clock are equal to 1, toggling takes place. Here, propagation delay has also
been reduced, so the output will be given out at the instant input is given. So there is a
toggling again. Therefore, whenever Clock is equal to 1 there are consecutive toggling. This
condition is called as Race around condition. To put it in words, “For JK flip-flop if J, K and
Clock are equal to 1 the state of flip-flop keeps on toggling which leads to uncertainty in
determining the output of the flip-flop. This problem is called Race around condition. “‟ This
condition also exists in T flip-flop since T flip-flop also has toggling options.

2.6 Master-Slave JK Flip-Flop:

 The master slave JK flip flop is a combination of a clocked JK flip-flop and a clocked
SR flip-flop. The clocked JK flip-flop acts as the master and the clocked SR flip-flop
acts as the slave.
 Master is positive level triggered and due to the presence of an inverter in the clock
line, the slave is negative level edge triggered. Hence when clock=1, the master is
active and slave is inactive. Vice versa happens when clock=0.

 The following is truth table of master slave flip flop.

  Operation:

Case I: When clock is not given, both master and slave are inactive and there will be no
change in outputs.
Case II: For clock=1, master is active, slave inactive. As J=K=0, output of master Q and Q'
will not change. As soon as clock goes to 0, slave becomes active, and master is inactive.
But since input to slave S and R is same, output of slave will also remain same.
Case III: For clock=1, master is active and slave is inactive. When J=0 and K=1, outputs of
master will be Q=0, Q'=1, which will be inputs to slave. When clock=0, slave becomes
active and takes inputs 0,1 to give output Q=0, Q'=1. This output will not change if clock is
again made 1and then 0. Hence we get a stable output from master and slave.
Case IV: For clock=1, master is active and slave is inactive. When J=1 and K=0, outputs of
master will be Q=1, Q'=0, which will be inputs to slave. When clock=0, slave becomes
active and takes inputs 1,0 to give output Q=1, Q'=0. This output will not change if clock is
again made 1 and then 0. Hence we get a stable output from master and slave.
Case V: When clock =1, J=K=1, master output will toggle. So S and R will invert. But slave
remains inactive all this time since clock is 1. As soon as clock becomes 0, slave becomes
active and master becomes inactive. So slave will also toggle. These changed outputs are
returned through feedback to the master, but master does not respond to them because
clock is now 0 and master is inactive. Thus, in one clock period, master and slave both
toggle only once, avoiding race condition caused by multiple toggling.

2.7 T Flip-Flop:
We can construct a T flip – flop by any of the following methods.

(1) Connecting the output feedback to the input, in SR flip – flop.

(2) Connecting the XOR of T input and Q PREVIOUS output to the Data input, in D flip –
flop.

(3) Wiring the J and K inputs together and connecting it to T input, in JK flip – flop. This is
illustrated in the figures below:
Figure (1) From SR flip flop.

Figure (2) From D Flip flop

Figure (3) From JK Flip flop

Working:

Toggle Flip flop changes its output whenever it is edge-triggered. What it means is that
whenever the clock changes its state from low to high or high to low.

Truth Table of T flip – flop

The disadvantage of T flip flop is that the state of the flip-flop at an applied trigger is known
only when read with the previous state.

T flip flops are not available as Integrated Circuits(ICs). But, they can be easily constructed
using SR flip-flop, JK flip-flop or D flip-flop as shown above.

2.8 Conversion of Flip-Flop from one type to another:

We have discussed four flip-flops-SR, D, JK and T flip-flops so far. It is possible to convert

one flip-flop from one type to another very easily. The steps required for such conversion
are:

1. Consider the truth table of the desired flip-flop.

 2. Fill in the excitation values of the flip-flop in hand for each combination of
present and next state.

3. Get a simplified expression for each input using Karnaugh Maps.

4. Draw the logic circuit diagram of the flip-flop to be formed according to the
simplified expression. Use flip-flop in hand and logic gates to achieve this.

Let us understand this with an example. Let us consider converting SR flip-flop to a D flip
flop.

Step 1. Prepare truth table of desired flip flop, that is D flip flop.

Input Present state Next state

D Q (t) Q (t+1)

0 0 1

0 1 0

1 0 1

1 1 1

Step 2. SR flip-flop has two inputs S and R. Write the excitation values of SR flip flop for
each combination of present state and next state. The above table will now be modified to

Input Present state Next state SR flip-flop inputs

D Q(t) Q(t+1) S R

0 0 1 0 X

0 1 0 0 1
1 0 1 1 0

1 1 1 X 0

Step 3.

From the above table, we can write the Boolean functions for each input as below.
S=m2+d3S=m2+d3
R=m1+d0R=m1+d0
We can use 2 variable K-Maps for getting simplified expressions for these inputs. The k-
Maps for S & R are shown below.

So, we got S = D & R = D' after simplifying.

Step 4.
The circuit diagram of D flip-flop is shown in the following figure.
This circuit contains a NOT gate connected in addition to SR flip-flop.

Other conversions can be similarly worked out.

2.9 Applications of Flip-Flop:

Flip-flops are used in numerous applications, such as

(1) Registers

(2) Counters

(3) Event Detectors

(4) Data Synchronizers

(5) Frequency Divider

(1) Registers
Registers are storage devices used to store memory. Each flip-flop can store a single bit.
Figure 1 shows cascading three D flip-flops to store 3-bit information.
The data can be shifted within registers in/out of the register by applying clock pulses.
These registers are called shift registers and can be pictorially represented as in Figure 2.

(2) Counters:
Counters are used for the purpose of counting. A series of flip –flops are cascaded to form
counters. These counters can be synchronous or asynchronous. They can be positive-edge
triggered or negative-edge triggered. Counters are used as up-counter, down counter, ring
counter, Johnson counter etc. Figure 3 shows a 3-bit asynchronous positive edge triggered
up-counter.
 (3) Event Detectors
These are circuits which are used to find occurrence of a particular event. Flip-flops do not
change their state unless triggered. This can be used to detect and store occurrence of an
event. Figure 4a shows one such event detector which detects the event of switching‟ ON‟
of light. The working is illustrated in Figure 4b.
 (4) Data Synchronizers:
Outputs of a particular combinational circuit should change their states simultaneously.
Using Data synchronizers, this can be easily achieved as illustrated in Figure 5 below:

(5) Frequency Divider:

Consider a positive edge triggered JK flip-flop as shown in Figure 6 below:
The output of JK flip-flop will toggle for each positive-edge of the clock. It is clearly seen
from the waveforms that if Tin is the input clock period, then Tout= 2Tin. In other words,
fout=fin/2. This is how frequency division takes place using flip-flops.

………………………………………………………X………………………………………………
 Unit 5: Chapter 9
Counters
Unit Structure
9.0 Objectives
9.1 Introduction
9.2 Asynchronous counter
9.3 Terms related to counters
9.4 IC 7493 (4-bit binary counter)
9.5 Synchronous counter
9.6 Bushing
9.7 Type T Design
9.8 Type JK Design
9.9 Presettable counter
9.10 IC 7490
9.11 IC 7492
9.12 Synchronous counter ICs
9.13 Analysis of counter circuits
9.14 Summary
9.15 Reference for further reading

9.0 Objectives: This chapter would make you understand the following concepts
 What is counter?
 Different types of counters – Asynchronous and synchronous counter.
 Terms related to counters.
 IC 7493 (4-bit binary counter)
 Synchronous counter, Bushing, Type T Design, Type JK Design.
 Presettable counter, IC 7490, IC 7492.
 Synchronous counter ICs, Analysis of counter circuits.
9.1 Introduction
In the design of counters and registers FFs (flip-flops) are most widely used. The FF is
the basic building block of any sequential logic system. FF and combinational circuit are
used in the design of any sequential system.
Counter is a sequential circuit. A counter is a device that stores the number of times a
particular event or process has occurred, often in relationship to CLK (a clock) pulse.
Counters are used in digital electronics for counting purpose, they can count specific
event happening in the circuit.
9.1.1 Definition
A digital circuit which is used for counting pulses is known counter. Counter is the
widest application of FFs. It is a group of FFs with a CLK pulse applied. Counter is a
register that goes through a prescribed series of states. Counter is a circuit which cycle
through state sequence.
9.1.2 Types of Counters
The number of FFs used and the way in which they are connected determines the
number of states and also the specific sequence of states that the counter goes through
during each complete cycle. Counters are classified according to the way they are
clocked: Asynchronous or ripple counters and Synchronous counters.
Asynchronous counter Synchronous counter
1. It is also called as serial counter. 1. It is also called as parallel counter.
2. Simple and straight forward in 2. Complex in operation as compared to
operation. asynchronous.
3. Slower than synchronous. 3. Faster than asynchronous.
4. Next FF is triggered by previous 4. All FFs are triggered simultaneously by
FF. external CLK.
5. Problem of glitch. 5. No problem of glitch.
6. Settling time is more. 6. Settling time is less.

Synchronous / asynchronous counter can be further divided in to following sub-type:

1. Regular Counter: FFs are used to build the regular counter, in which the number of
FFs determines the number of states means there is direct relation between number
of FFs used and number of states of counter.
 Suppose ‘N’ is number of States in counter and ‘m’ is number of FFs then the
relation is N (number of States) = 2 m (# of FFs)
Let‘s say m (# of FFs) = 3 then N = 2m = 23 = 8
 Number of States (N) in counter = 8
Consider one additional variable ‘n’, which indicates the number of actual states
of counter. In regular counter, number of actual states of counter (n) and number of
states of counter (N) are equal i.e. n = N.
2. Truncated counter: in this counter, number of actual states of counter (n) are
always less than number of states of counter (N) i.e. n < N.
If FFs are 3, then N = 2m = 8 but n < 8.
3. Sequential Counter: in this counter, states of counter are sequential i.e. 0, 1, 2, 3,
4, 5, 6, … so on.
4. Non-sequential Counter: in this counter, states of counter are not sequential
means states are irregular. e.g. 0, 3, 9, 8, 2, 1, 7.
9.2 Asynchronous or Ripple counters
Asynchronous counter is a cascaded arrangement of FFs where the output of one FF
drives the CLK input of the following FF. The number of FFs in the cascaded
arrangement depends upon the number of different logic states that it goes through
before it repeats the sequence, a parameter known as the modulus of the counter.
Asynchronous counter, also called ripple counter or a serial counter, the CLK input is
applied only to the first FF, also called the input FF, in the cascaded arrangement. The
CLK input to any subsequent FF comes from the output of its immediately preceding
FF. For instance, the output of the first FF acts as the CLK input to the second FF, the
output of the second FF feeds the CLK input of the third FF and so on. In general, in an
arrangement of ‗n‘ FFs, the CLK input to the nth FF comes from the output of the (n−1)th
FF for n>1.
Figure 9.2 shows the generalized block diagram of an n-bit binary ripple counter. As a
natural consequence of this, not all FFs change state at the same time. The second FF
can change state only after the output of the first FF has changed its state. That is, the
second FF would change state a certain time delay after the occurrence of the input
CLK pulse owing to the fact that it gets its own CLK input from the output of the first FF
and not from the input CLK. This time delay here equals the sum of propagation delays
of two FFs, the first and the second FFs. In general, the nth FF will change state only
after a delay equal to n times the propagation delay of one FF. The term ‗ripple counter‘
comes from the mode in which the CLK information ripples through the counter. It is
also called an ‗asynchronous counter‘ as different FFs comprising the counter do not
change state in synchronization with the input CLK. In a counter like this, after the
occurrence of each CLK input pulse, the counter has to wait for a time period equal to
the sum of propagation delays of all FFs before the next CLK pulse can be applied. The
propagation delay of each FF, of course, will depend upon the logic family to which it
belongs.

Figure 9.2: Block diagram of an n-bit binary ripple counter.

9.2 3 – Bit Ripple Counter:

A binary ripple counter can be constructed using clocked JK FFs. Figure 9.2.1(a) shows
three negative edge – triggered, JK FFs connected in cascade. The system clock, a
square wave, drives FF A. The output of A drives FF B, and the output of B drives FF C.
All the J and K inputs are tied to +VCC. This means that each FF will change state
(toggle) with a negative transition at its clock input.
When the output of a FF is used as the clock input for the next FF, we call the counter a
ripple counter, or asynchronous counter. The A FF must change state before it can
trigger the B FF, and the B FF has to change state before it can trigger the C FF. The
triggers move through the FFs like a ripple in water. Because of this, the overall
propagation delay time is the sum of the individual delays.
For instance, if each FF in this three- FF counter has a propagation delay time of 10 ns,
the overall propagation delay time for the counter is 30 ns.
 Figure 9.2.1: 3 - bit Ripple Counter

The waveforms given in Fig. 9.2.1(b) show the action of the counter as the clock runs.
Let's assume that the FFs are all initially reset to produce 0 outputs. If we consider A to
be the least-significant bit (LSB) and C the most-significant bit (MSB), we can say the
contents of the counter is CBA = 000.
Every time there is a clock NT (Negative Transition), FF A will change state. This is
indicated by the small arrows () on the time line. Thus at point a on the time line, A
goes high, at point b it goes back low, at c it goes back high, and so on. Notice that the
waveform at the output of FF A is one-half the clock frequency.
Since A acts as the clock for B, each time the waveform at A goes low, FF B will toggle.
Thus at point b on the time line, B goes high; it then goes low at point d and toggles
back high again at point f Notice that the waveform at the output of FF B is one-half the
frequency of A and one-fourth the clock frequency.
Since B acts as the clock for C, each time the waveform at B goes low, FF C will toggle.
Thus C goes high at point d on the time line and goes back low again at point h. The
frequency of the waveform at C is one-half that at B, but it is only one-eighth the clock
frequency.
9.3 Terms related to counters
Before we proceed further, we would like to study few things related to counter.
9.3.1 State Diagram:
State diagram means graphical representation of the states of counter circuit. For
example state diagram for 3 bit binary ripple up counter and 3 bit binary ripple down
counter can be as shown in Figures 9.3.1(a) and 9.3.1(b) respectively.

Figure 9.3.1(a): 3 bit binary ripple up counter Figure 9.3.1(b): 3 bit binary ripple down
Counter
9.3.2 Module N Counter:
If it is desired to have modulo N (mod – N) counter, the number of FFs required is
determined by,
N ≤ 2m where m = number of FFs
Let say m = 4, therefore N = 16. But if we require only 10 states out of 16, it is called as
modulus – 10 (Mod – 10) counter, but required FFs will be 4 only.
Mod – N can be achieved by resetting the FF. This should be done at the N state. In
Mod – 10, counter will count from 0 to 9, and at 10th state it will reset back to 0. Mod –
10 counter is also called as decade counter.
Up till now we have seen that counter is sequential and number of states provided are
N = 2m. Now let us take a case of truncated ripple counter when n (number of actual
state) < N.
Example 1: Design mod – 3 ripple counter.
Solution:
1) State diagram = 3 states → 0 to 2
2) No of actual states are n = 3
n < N = 2m 3 ≤ 2m therefore m=2
Hence 2 FFs are required.
3) Here FF used should have clear terminal for resetting or clearing.
4) Assumption: considering FF and gates are having 0 propagation delay.
5) Reset logic circuit required to terminate count after 2.
6) 2 FFs are used therefore N = 4

Figure 9.3.2.1(a): state diagram

Normally CLR terminal is ACTIVE LOW therefore Design a reset logic combinational
circuit such that output Y should be 1 when valid states are there and Y = 0 when
Invalid states are present.
Circuit Diagram:

Figure 9.3.2.1(b): mod – 3 ripple counter: circuit diagram

Counter is up counter, therefore FF should be –ve edge triggered, cascade Q O/P and
final O/P is taken from Q. The final circuit diagram is therefore shown in figure
9.3.2.1(b). Wave form for the same is shown in following figure 9.3.2.1(c).

Figure 9.3.2.1(c): mod – 3 ripple counter: wave form

Working: to check the working refer the figures 9.3.2.1(b) and 9.3.2.1(c) (QB QA = B A)
1) Initially all FFs are cleared.
 BA = 00;  Y = 1
2) When 1st negative CLK edge hits, A toggles
 A = 1,  BA = 01; Y = 1
3) At 2nd hit of CLK edge, A toggles from 1 → 0 (negative edge),
 B also toggles from 0 → 1.
 BA = 10  Y = 1
4) When 3rd CLK edge hits, A will toggle from 0 → 1(positive edge)
 B = unchanged  BA = 11
 Y = 0. As Y = 0, all FFs will be cleared.
and BA = 00. As BA = 00, Y = 1 again.
The sequence from BA = 11 to BA = 00, is so fast (as propagation delay is considered
0 ᶯ sec) that, it is not possible to observe 11 condition of waveform. Y waveform pulse is
also very sharp and of very, very small duration. Thus counter will run 0 → 1 → 2 → 0.

Example 2: Design mod – 6 ripple counter

Solution:
1) State diagram = 6 states → 0 to 5

Figure 9.3.2.2(a): state diagram

2) No. of states = 6 therefore n < N = 2m 6 < 2m therefore m = 3
3) Design of reset circuit.
Truth table is,
N = 2m = 23 = 8, but n = 6
Truth Table:

K-map:

Points:
1) Counter is up counter, therefore we have to cascade Q output, -ve edge
triggered FF and final output from Q.
2) FF should have ACTIVE LOW reset (clear) terminal.
3) Propagation delay presently assumed 0 n sec.
Circuit diagram:

Figure 9.3.2.2(b): mod – 6 ripple counter - circuit diagram

 Figure 9.3.2.2(c): mod – 6 ripple counter - wave form
9.3.3 Problems involved in Ripple Counter:
Mainly there are two problems involved in ripple counter.
1) Glitch operation – propagation delay of Reset logic.
2) Propagation delay – propagation delay of FF.
Glitch operation:
In example 1 assumption was made that propagation delay through FF and reset circuit
is 0 ᶯ sec. But practically this situation does not exist, therefore glitch operation occurs.
Let‘s consider propagation delay of reset logic. For analysis let‘s consider example 1 in
which states are 0, 1, 2. Redraw the waveforms considering propagation delay of reset
CLK.

Figure 9.3.3(a): mod – 3 ripple counter - wave form

Working: Refer Figure 9.3.3(a) and example 1 (QA = A QB = B)
1) Initially all FFs are reset  BA = 00  Y = 1
2) When 1st CLK edge hits, A will toggle  BA = 01,  Y = 1
3) At 2nd CLK edge, A will toggle from 1 → 0 (negative edge), B also toggles.
 BA = 10. Y = 1
4) When 3rd CLK edge hits, A will toggle from 0 → 1 (positive edge), B is
unchanged.  BA = 11
Reset circuit is designed in such a way that, when 11 occurs Y = 0. But appearing of
logic 11 at NAND input, getting settled, then propagates through NAND and appear at
output, then resetting the FF will take some time in ᶯ sec. During this period BA = 11.
This condition is invalid condition and as in Figure 9.3.3(a), QA produces unwanted
short duration pulse called glitch.
Propagation Delay in Ripple counter:
Basic principle of operation of a synchronous counter is, each FF is triggered by the
transition at the output of preceding FF. Each FF has internal propagation delay, means
second FF will not respond unless and until propagation delay time, after the first FF
receives an active clock transition.  Third FF will not respond until a time equal to
twice propagation delay (2 x tpd) after that clock transition.
Thus propagation delay of FF accumulates so that Nth cannot change state unless and
until, time equals to N x tpd after the CLK transition occurs. To understand this refers
waveforms in following figure 9.3.3(b).

Figure 9.3.3(b): mod – 3 ripple counter: wave form

Refer figure 9.3.3(b), (QA = A, QB = B) propagation delay of one FF = 10 ᶯ sec.
1) Initially both output BA = 00
2) When the first CLK edge hits, A changes from 0 → 1. As shown Q A changes
states 10 ᶯ sec after CLK edge hits. (Part (a)).

3) In Second CLK edge QA changes from 1 → 0. Transition occurs, 10 ᶯ sec after

CLK edge hits.
QA provides negative transition (1 → 0) to B FF.
 QB changes the state from 0 → 1, 10 ᶯ sec after the transition of QA.

With respect to CLK edge QB changes state after 20 ᶯ sec. (Part (b)).

i.e. 2 FF x 10 ᶯ sec = 20 ᶯ sec

This propagation delay causes limitation on CLK frequency input, so for ripple counter,
following equation provides relationship between CLK period, number of FFs used and
propagation delay of FF.
Time period of CLK (TCLK) ≥ N x tpd
Where, tpd= propagation delay
N = No. of FFs

9.3.4 Power on Reset Circuit:

Whenever counter working was discussed, it was assumed that initially everything is
reset. Whenever power supply is switched ON; one cannot predict the output state of
FF. Therefore clear terminal is provided. But clear terminal requires some external
circuitry to force it self ‗LOW‘ so that it can provide Q = 0 (some known state). This
external circuitry is nothing but power ON reset circuit. Refer following figure 9.3.4.
 Figure 9.3.4: mod – 3 counter with power ON Reset circuit
As shown in figure 9.3.4 (counter states are 0, 1, 2). In addition one RC n/w with AND
gate is used. So either of the input is LOW output of AND gate is LOW, FFs will be
cleared.

figure 9.3.4(a) figure 9.3.4(b)

Working:
Refer figure 9.3.4(a) and 9.3.4(b).
When power supply is switched ON, VCC will appear across RC n/w at time t0.
 Capacitor will start charging. The charging slope depends upon RC time constant.
When capacitor voltage (Voutput) reaches to level VTH (Threshold voltage), chip (IC) will
consider it HIGH logic. Below threshold it is considered as LOW logic.
 For duration t1 – t0 output of AND gate is ‗0‘  FFs are cleared.
When counter steps through states and AB = 11, output of NAND is equal to 0.
 . = 0, as AND output is ‘0’  FF will reset.
9.4 IC 7493 (4-bit binary counter):
Let‘s study TTC MSI circuit of 4 bit ripple counter implemented in IC 7493.

Figure 9.4.1: IC 7493

In IC 7493,
QD QC QB QA → Binary output of FF.
Input A → CLK IN of FFA
Input B → CLK IN of FFB
R0 (1), R0 (2) → Reset pin
When R0 (1) = R0 (2) = 1 Reset will occur
Figure 9.4.1 shows logic diagram of IC 7493, It shows that FFA is independent i.e.
output is not cascaded to next FF, But FF B, C and D are cascaded. Therefore we have
individual, internally two counters, ÷2 (Mod 2) and ÷ 8 (Mod 8). If we combine both
counters we get 2 x 8 = 16 state counter of mod 16 counter or ÷ 16 counter.
When we connect QA output to input B and CLK IN given to Input A only, it becomes
simple 4 bit binary ripple counter. Truth table is as follows

Example 3: Implement ÷ 9 counter using IC 7493.

Solution: Procedure is same as when we design mod – N ripple counter.
1) ÷ 9 means mod - 9,  required states are 9 (0 to 8)  FF used are 4.
2) Reset circuit should generate ‗0‘ output for valid states (0 to 8) and ‗1‘ output for
invalid states (9 to 15), because if R0 (1) and R0 (2) both are 1, then only IC 7493
resets.
3) Design reset circuit, Draw K-map.
4) Circuit diagram:

Figure 9.4.2: mod - 9 counter using IC 7493 - circuit diagram

9.5 Synchronous counters
In asynchronous counter mainly two problems were present, glitch and delay in counter.
To avoid this, synchronous counter came into picture. Synchronous counter is now most
widely used. Generalized block diagram of synchronous counter shown in figure 9.5
 Figure 9.5: Generalized block diagram of synchronous counter
Observation from block diagram of Synchronous counter:
1) CLK pin of all FFs are tied together, so that FF changes output in synchronism.
2) O/p Q given to combinational logic circuit. This circuit is designed in such a way
that GA GB GC generated from it, applies proper logic to input of FF, so that we
get correct next state.
3) O/p Q depends upon previous input of FF, when CLK edge hits.
Presently in block diagram, JK is tied together. But this will not be the case every time.
JK can be controlled separately by combinational circuit.

9.6 Bushing
If you observe examples solved up till now, in full sequence ‗0‘ is always present and
once counter enters in valid state, it will continue the chain unless and until power
supply is switched off. To enter in the chain we use power on reset circuit, therefore first
state is normally ‗0‘.
Problem:
1) In some of the applications we don‘t require ‗0‘ state at all.
2) Secondly due to power supply fluctuation (glitch of power supply),
Electromagnetic inference and RFI (radio frequency interference), it may happen
that counter will enter in invalid state.
If due to problem stated above it enters in to invalid condition then what will
happen?
Then here your luck factor counts
(1) LOCK OUT STATE (IF LUCK IS BAD).
It may happen that counter will lock itself in invalid states only. Let‘s say in above
case counter enters into state 1; because of logic circuit next state happens to be
6. After 6 next state happens to be 1. Then counter will toggle between two
states only, as shown in state diagram figure 9.6(a).

Figure 9.6(a): State diagram

(2) If you are lucky enough after entering into invalid state it may switch over to valid
state. But don‘t try to check your luck. Take precaution. As a precautionary step
we implement bushing to state diagram. Bushing means branches. We are
going to branch invalid state in such a way that even though it enters into invalid
state after one, two or three CLK ticks it will enter into valid state chain.
Following are some of the examples for implementing bushing in Example 5:

Figure 9.6 (b-e): Implementation of Bushing

Thus one can have ‗n‘ number of combinations. Choice depends upon designer.
9.7 Type T Design
Let‘s start designing synchronous counter using T FF.
Example 4: Design mod – 4 regular sequential synchronous up counter by using T FF.
Solution:
1. No. of states are 4, for mod – 4 counter.
2. Regular means n = N.
3. No. of FF required will be 4 ≤ 2m  m = 2
4. Sequential and up means 0, 1, 2, 3.
5. State design is Figure 9.7(a).
6. FF A and B are used. GA and GB are output from combinational circuit to provide
input to T FF.  Circuit will be as shown in Figure 9.7(b).
7. Design of combinational circuit to generate GA, GB.

Figure 9.7(a): State diagram

Figure 9.7(b): Circuit diagram

Step 1: For generation of truth table, depending upon number of bits (FF), write down
sequentially all states.
In our case 2 bits (FF) are used,  state are 4.

Here QA = A, QB = B for simplicity

Step 2: Now below this you write down required output.

Step 3: Now start from state of counter. Treat this state as previous state. Take next
state of counter from state diagram, and it will be obviously next state.
In our case 1st state = AB = 00 → Previous state.

2nd state = AB = 01→ Next state.

Step 4: Now refer excitation table of T FF, treat change of state for A and B individually
and write down GA and GB the step is explained as follows:

As A changes from 0 → 0  GA (TA) = 0

B changes from 0 → 1 GB (TB) = 1

Step 5: Now treat previously next as previous state. i.e. AB = 01 which was next state
previously, will be Now previous state. Refer state diagram and find next state. In our
case it will be AB = 10. Again the procedure is same as STEP 4.

As A changes from 0 → 1, GA (TA) = 1

B changes from 1 → 0,  GB (TB) = 1

Step 6: Now previous state = AB = 10 and Next state = AB = 11, again follow STEP4.
 As A changes from 1 → 1,  GA (TA) = 0

B changes from 0 → 1,  GB (TB) = 1

Step 7: Finally previous state = 11 and next state = 00. Next we are completing full
chain of counter. Follow step 4.

As A changes from 1→ 0, GA (TA) = 1

B changes from 1→ 0,  GB (TB) = 1.

Step 8: After filling truth table, next step is to draw K-Map.

Step 9: Draw final circuit diagram.

Already we have drawn half circuit as shown in Figure 9.7(b). Only this is to
replace combinational block by directly some connection.
 Figure 9.7(c): Final circuit diagram
Let us draw the waveforms and analyze the working of the circuit.

Figure 9.7(d): Waveforms

Working:
1. Initially counter is Reset,  AB = 00
2. At 1st CLK edge, TA = 0 as B = 0, TB = 1.
 A remains constant as QB toggles from 0 → 1.  AB = 01
3. At 2nd CLK edge, as TA = 1 (because B = 1) TB = 1,
A and B both will toggle, giving  AB = 10
4. At 3rd CLK edge, TA = 0 as B = 0 and TA = 1,
 A = unchanged, B = toggle  AB = 11
5. Finally at 4th CLK edge TA = 1 and B = 1, TB = 1
 A and B will toggle from 1 → 0  AB = 00
Now the point 2, 3, 4 and 5 will continue till CLK is present, and counter generates
required states.
If you compare the waveform in Figure 9.7(d) with waveforms of ripple counter. You will
find that falling edge is shown only on CLK, not on QA or QB output, because CLK is
synchronized. Counter changes state ONLY when CLK edge hits.

Example 5: Design synchronous, non-sequential counter

Solution:

Figure 9.7.1: State diagram

1. Counter is non sequential as well as truncated.
2. While designing non sequential counter, instead of number of state you should
consider maximum count of the state. In our case maximum count of the state is
7. To represent 7 in binary we require 3 bits (111) and therefore m = 3.
As m = 3, n = 23 = 8
3. While writing truth table as told in Example – 4 step 1, depending upon number
of bits (FF), write down states sequentially. In our case N = 8 as m = 3.
So we are supposed to write 0 to 7 sequentially, refer Figure 9.7.1(a) Truth table
4. Truth table.

Figure 9.7.1(a): Truth table

 5. K – map

6. Circuit diagram

Figure 9.7.1(b): Circuit diagram

Step 1: Write standard table A, B, C and GA, GB, GC.

Step 2: Write 0 – 7 states sequentially under A, B, C.
Step 3: Write down X (don‘t care) for invalid states. For our case invalid states are 1, 2,
4, 6,  for 1, 2, 6, GA, GB and GC are X (don‘t care).
Step 4: Now the steps are standard.
Start from 1st state of state diagram i.e. 0. Next state is 7. So the transition is shown in
Figure 9.7.1(a) by (a). Previous state of ABC = 000, Next state of ABC = 111.
 GA, GB and GC = 111, written under column ‗0 – 7‘ (shown in Figure 9.7.1(a)).
Step 5: 2nd transition is from 7 – 5 (shown by arrow (b)).
ABC changes from 111 to 101  GA = 0, GB = 1 and GC = 0. Written under column
‗7 – 5‘.
Step 6: 3rd transition is from ‗5 – 3‘ (shown by arrow (c)) ABC changes from 101 to 011
 GA = 1, GB = 1 and GC = 0, written under column ‗5 - 3‘.
Step 7: Final transition is from 3 to 0 (3 – 0) shown by arrow (d). ABC changes from
011 to 000  GA = 0, GB = 1 and GC = 1, written under column ‗3 – 0‘
Step 8: After going through one full cycle draw K – map.

Example 6: Design synchronous counter for state diagram shown in Figure 9.7.2.

Figure 9.7.2: state diagram.

Solution:
1. Counter is sequence but truncated.
2. Number of states n = 6.  n = 6 ≤ 2m ,  m = 3
As m = 3, 23 = 8 = N  n < N (truncated counter)
3. Up counter (observe from given state diagram)
4. Truth table for designing combinational logic circuit.

Figure 9.7.2(a): Truth table.

As shown in Figure 9.7.2(a) truth table, valid states are only 0, 1, 2, 3, 4 and 5.
Therefore, for invalid states i.e. 6 and 7, GA, GB and GC are takes don‘t care conditions
because we know that these states are not going to occur.
5. K – Map for GA , GB and Gc :

6. Circuit diagram

Figure 9.7.2(b): Circuit diagram.

7. Waveforms

Figure 9.7.2(c): Waveforms.

9.8 Type JK Design:
Counter design using JK-FF is most widely used. Here J and K terminals are controlled
separately. We have already generated excitation table for JK-FF.
As far as counter design goes, method is same as we followed up till now. Figure 9.8
shows generalized block diagram for counter using JK.

Figure 9.8: Generalized block diagram

As shown in Figure 9.8
1. CLK IN of all FFs is tied together. (synchronous counter)
2. QA, QB, QC output are fed to combinational circuit.
3. Depending upon next state combinational circuit generates proper J and K input for
A, B and C FF.
Example 7: Design a modulo – 6 counter using JK FF. Explain its action by writing a
truth table and draw waveforms for the outputs of the flip flops.
Solution:
1. State diagram, modulo 6 mean 0 to 5.

Figure 9.8.1(a): State diagram

2. Number of FFs required will be 3.  N=2m = 23 = 8.

3. Truth table

4. K-Map:
5. Circuit Diagram:

Figure 9.8.1(b): Circuit diagram

6. Waveforms:

Figure 9.8.1(c): Waveforms

Example 8: Implement synchronous counter using JK FF. for the state diagram shown
in Figure 9.8.2

Figure 9.8.2: State diagram

Solution:
1. Counter is with bushing
2. Number of FFs required will be 2.
3. Truth table:

4. K – Map:

5. Circuit diagram:

Figure 9.8.2(a): Circuit diagram

9.9 Presettable counter:

As we have discussed previously that sometime counter will not start from '0' state. It
will start from some predefined state. Let's say we want to down count from decimal 10.
So preset counter to start 10, apply CLK pulses, so it will count down to 9, 8, 7, ... to 0.
After that it will again start from 10.
Counters can be preset to any desired starting count either synchronously or
asynchronously. This can be done using PRESET and CLEAR terminals of FF.
Figure 9.9 shows 3 bit parallel presettable up counter.
1. Counter is synchronous.
2. Asynchronous inputs, preset and clear, are controlled through load signal.
3. Steps for 'Preset',
(a) Apply required count (step) to P2, P1, P0. Let's say P2, P1, P0 = 101
(b) Apply 'LOW' going signal to 'LOAD' pin
(c)  Output of NAND1, NAND3 = 0 and NAND2 = 1 at the same time NAND4,
NAND6 = 1 and NAND5 = 0.
 FF B will be reset and AC will be preset
 ABC = 101.
(d) CLK is not going to affect above action.
4. After presetting applies CLK pulse so that counter can start next count.

Figure 9.9: 3 bit parallel presettable up counter

9.10 IC 7490:
IC 7490 is TT1 MSI decade counter. It contains four M/S FF and additional gating to
provide divide by 2 counter (Mod-2) and three stage binary counter which provides
divide by 5 counter (Mod-5).
Figure 9.10 shows block diagram of IC 7490.
 Figure 9.10: Block diagram of IC 7490
7490 have gated zero reset (R0(1), R0(2)) and gated set to nine inputs R9(1), R9(2) for use
in BCD nine's complement applications.

Figure 9.10(a): Pin Configuration - IC 7490

Figure 9.10(b): Truth table - IC 7490

As shown in truth table when R0 (1) = R0 (2) = 1, IC 7490 Reset.
When R9 (1) = R9 (2) = IC 7490 sets to 1001 (9 decimal).
So one has to provide logic 1 to these input temporarily, set / reset it, and lower the
input terminals so IC 7490 can start counting as CLK pulses applied to it.

Example 9: Implement sequential decade counter using IC 7490 and write counter
states.
Solution: In IC 7490 mod-2 counter and mod-5 counter is available  2 x 5 = 10
 gives decade counter.
As mentioned in above example, requirement is sequential decade counter.  Apply
CLK IN to INPUT A pin. Output QA is connected to INPUT B i.e. input of mod-5 counter.
Output terminals are QD Qc QB QA, where QD = MSB, QB = LSB connections are shown
in Figure 9.10.1(a).

Figure 9.10.1(a): Sequential decade counter

Important point to be remembered is, now at each falling edge of QA O/P, mod 5 counter
will increment. And QA change at falling edge of CLK input.
The count sequence ca be written as,
 Figure 9.10.1(b): Count Sequence of Sequential decade counter
If you observe Figure 9.10.1(b), concentrate on QD, QB, Qc and QA separately initially
QD Qc QB = 000. When QA changed from 1 → QD Qc QB changed to 001. For 2nd CLK
period state of QD Qc QB remains unchanged.

9.11 IC 7492:
IC 7492 is TTL, MSI divide by 12 counter. IC 7492 is having 2 counter inside it. mod 2
(÷ 2) and mod 6 (÷ 6) counter.
 Combination of both gives 2 x 6 = 12  ÷ 12 counter.
Block diagram of IC 7492:

Figure 9.11: Block diagram of IC 7492

Figure 9.11 shows block diagram of IC 7492. For mod 6 counter IC 7492 counts from 0,
I, 2, 4, 5, 6, 0. (Observe sequence carefully, state 3 is absent).

Figure 9.11(a): Pin diagram of IC 7492

Example 10:
(a) Write down truth table for Mod 6 counter in IC 7492.
(b) Write down truth table for Mod 12 counter in IC 7492, if CLK IN is given to Input A
and Input B QA is shorted.
Solution:
(a) Truth table of IC 7492 for mod 6 counter. As we know that internally IC has mod 2
and mod 6 counter. So use only mod 6 counter. CLK IN gives to Input B and outputs
are QD QC QB only. States are as shown in Figure 9.11.1(a).

Figure 9.11.1(a): Truth table – IC 7492 mod 6 counter

(b) In this part,
(i) Give CLK IN to Input A
(ii) Conned Input B to QA.
 Circuit will be as shown in Figure 9.11.1(b)

Figure 9.11.1(b): Circuit diagram - IC 7492 mod 6 counter

Point to be remembered.
(1) QA toggles at each falling edge of CLK IN.
(2) QB QC QD will change state at each falling edge of QA.
Working:
Refer Figure 9.11.1(a)
(1) Initially QD QC QB QA (DCBA) = 0000
(2) At first CLK edge, a changes from 0 → 1 (rising edge.)
 = 000  DCBA = 0001.
(3) At 2nd CLK edge, A. toggles from 1 → 0 (falling edge.)
 DCB will change from 000 to 001. (From Figure 9.11.1(a)) DCBA = 0010.
(4) 3rd CLK edge, A changes from 0 → 1 (rising edge),  DCBA = 0011.
(5) 4th CLK edge, A changes from 1 → 0 (falling edge).
 DCB changes from 001 to 010  DCBA = 0100.
(6) At 5th CLK edge, A changes from 0 → 1 (rising edge),
 DCB = unchanged. DCBA = 0101.
(7) At 6th CLK edge, A changes from 1 → 0 (falling edge),
 DCB changes from 010 to 100 (Decimal count 011 is not present in mod 6 refer
 Figure 9.11.1(a)  DCBA = 1000
(8) At 7th CLK edge, A changes from 0 → 1,
 DCB = unchanged.  DCBA = 1001.
(9) At 8th CLK edge, A changes from 1 → 0,  DCB changes from 100 to 101.
 DCBA = 1010
(10) At 9th CLK edge, A changes from 0 → 1,
 DCB unchanged, DCBA = 1011.
(11) At 10th CLK edge, A changes from 1 → 0,  DCB changes from 101 to 110
 DCBA = 110
(12) Finally at 11th CLK edge, A changes from 0 → 1,
 DCB unchanged, DCBA = 1101.
Truth table is written as follows.

Figure 9.11.1(c): Truth table - IC 7492 mod 12 counter

9.12 Synchronous counter ICs:
Let's study some synchronous counter ICs.

IC 74190
IC 74190 is UP/DOWN decade counter with preset and ripple clock. It is a reversible
BCD (8421) decade counter featuring synchronous counting and asynchronous
presetting. Reversible BCD means it can count 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0 i.e. up and
9, 8, 7, 6, 5, 4, 3, 2, 1, 0. 9 i.e. down. Asynchronous presetting means parallel input data
can be loaded at any instant, it is not dependent upon CLK input.
Pin configuration and logic symbol is as shown in Figure 9.12 (a) & (b)

Figure 9.12: Pin configuration and logic symbol – IC 74190

Let us see the Pin names and functions
PIN NAMES DESCRIPTION
Count enable input (Active low)

Clock pulse input (Active rising edge)

Parallel data input
Asynchronous parallel load input (Active low)

Up / Down count control input

0 – up count
1 – down count
Flip Flop outputs

Ripple clock output (Active low)

Terminal count output (Active HIGH)

Basically 74190 is decade counter. Internally four JK FFs are used, output is 4 bit
Q0 – Q3. It may happen because of supply fluctuation or noise it may enter in invalid
state i.e. 10 – 15, then how 74190 behaves? This point can be explained by using state
diagram.
Refer figure 9.12(c)
1) When counter counts up (Shown by dark line)
Main loop is → …. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0 …
Bushing branches are
(1) 14, 15, 2
(2) 12, 13, 4
(3) 10, 11, 6
Where 2, 4 and 6 are valid states. Worst case counter will take maximum three CLK
Cycle to enter in main loop.
2) When counter counts down (shown by dotted line)
Main loop is → …. 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 9 …
Bushing branch is → 15, 14, 13, 12, 11, 9.
Here we have only one branch. In worst case situation counter will take maximum 7
CLK cycles to enter valid states.

Figure 9.12(c): State diagram

Different Modes of 74190:
74190 has different modes of operation. Modes are selected by , , /D pins

We will study all these modes step by step.

COUNT UP:

Figure 9.12(d): UP Counter using IC 74190

For counter counting up one has to tie = 1 and = /D = 0. Apply clock
pulse and counter counts up. The circuit is as shown in figure 9.12(d)
COUNT DOWN:
For counter counting down tie = 1 = Vcc and /D = 1 = Vcc, = 0. Apply clock
pulses and counter will start counting down.
The circuit is as shown in figure 9.12(e).
 Figure 9.12(e): Down Counter using IC 74190
PRESET MODE:
When you need programmable divider one should PRESET output Q0 – Q3 to the
required count and start counting.
The figure 9.12(f) shows experimental setup for studying presettable Up/down counter.
Case 1: Presettable Up counter.
Step 1: Close switch S2
Step 2: Apply the count to which you want to PRESET the counter to P0 – P3 input.
Step 3: Close switch S1. Moment switch is closed P0 – P3 contents will appear at
Q3 – Q0. You can see it as LED glows.
Step 4: Apply clock pulses. (The pulses should be of low frequency so that you can see
output LED changing)
Step 5: Release (open) S1 switch.
Step 6: Now counter will start counting from presetted count. Let's say Q3 – Q0 = 0101 =
(5)10.
Then it will count 5, 6, 7, 8, 9 and back to ‗0‘. It won‘t again preset to zero unless and
until S1 is closed again.
If we want that after 9, counter again preset to ‗5‘ (or presetted count) then we have to
add combinational circuit.
 Figure 9.12(f): Presettable up / down counter.

Case 2: Presettable down counter.

Step 1: Open switch S2.
Step 2: Steps written in case 1 from (2) to (5) is same here also.
Step 3: Now counter will, start counting from presetted count.
Let's say Q3 – Q0 = 0101 = (5)10.
Then counter will count 5, 4, 3, 2, 1, 0 and back to 9. It won't preset again to 5 in this
circuit unless and until S1 is closed again.
HOLD:
To HOLD or LATCH the count in the counter make = = 1 /D and CP, both pins
are treated as don‘t care.

IC 74191
IC 74191 is binary up/down counter with preset and ripple clock. If you compare it with
74190, IC 74190 is decade counter, whereas 74191 counts 0 to 15. This IC can count
up or down synchronously and has a synchronous preset. Preset feature allows the chip
to be used in dividers. The pin configuration and logic symbol is as shown in figure
9.12.1
 Figure 9.12.1: Pinout and Logic Symbol – IC 74191
Pin names are as follows
Pin Names Description
Count enable input (Active low)

Clock pulse input (Active rising edge)

Parallel data inputs
Asynchronous parallel load input (Active low)

Up/Down count control input

Flip Flop outputs

Ripple clock output (Active low)

Terminal count output (Active HIGH)

State diagram for chip is as shown in Figure 9.12.1(a)

74191 counts up from 0 to 15 (shown by dark line) and also counts down from 15 – 0
(shown by dotted line).
74191 can be operated in different modes
 Figure 9.12.1(a): State diagram – IC 74191
Following is the Mode select table for IC 74191.
INPUTS
MODE

1 0 0 Count Up

1 0 1 Count down

0 X X X Preset (Async)
1 1 X X No Change (HOLD)

Following is the RC Truth table

The modes are same as 74190, therefore the explanation given in 74190 holds for
74191 also.
For cascading or multistage counter, the configuration explained in 74190 holds for
74191 also. RC truth table is also similar.
9.13 Analysis of Counter Circuits:
Up till now we have solved some example based on T, D and JK FF design. This part
was designing the counter circuit or synthesis of counter, where we were given state
diagram and we have to find circuit for the same.
Now it is analysis, i.e. circuit will be given to you and we have to find state diagram, and
some time unused state will be given to us and we have to find how counter is going to
behave.
The method is very simple. Explained it point by point
(1) Firstly present state will be given to you e.g. say presently counter is in CBA = 010,
now next states.
By chance if the state is not given, you assume some state. The thumb rule is to
start from 000.
(2) This present state is now previous state for us.
(3) You have to now find out, I/ps to all the FFs, because of this previous state.
(4) After finding out inputs of all FFs. assume that CLK edge hits. Now you already
know the input, you know the truth table of each FF. So find out what will be Q
output of FF. This 'new' state will be next state of the FF.
(5) Now von assume the next state as previous and start from point 3.

This chain should be combined unless and until you get next state, which already exists
previously. For example, We started with slate 4. From 4 next state is 6. From 6 next is
8. From 8 next is 9 and from 9 next state is 4. Means '4' has occurred twice so chain is
complete. If you want you can draw state diagram as shown in Figure 9.13(a).

Figure 9.13(a): State diagram

In above example it may happen that you get 6, after 9. 6 is already present. But now
state diagram will be different. It is as shown in Figure 9.13(b).  4 is bushing.
 Figure 9.13(b): State diagram
Thus you go on trying different combination and find next states. To make analysis
simple, all 5 points can be combined in 'one' table. You keep the table standard now
onwards.
Previous State FF inputs  Next state Decimal
A B JA = KA = JB = KB = A B C Equivalent

9.14 Summary:
In this chapter we have studied in detail about counters which includes asynchronous,
synchronous counters, terms related to counters, IC 7493 (4-bit binary counter),
Bushing, Type T Design, Type JK Design, Presettable counter , IC 7490, IC 7492, and
Synchronous counter ICs with examples.
9.15 Reference for further reading:
For further detailed study following are books prescribed by the University
1. Digital Electronics and Logic Design by N. G. Palan
2. Modern Digital Electronics by R. P. Jain
3. Digital Principles and Applications by Malvino and Leach
 Unit 5: Chapter 10
Registers
Unit Structure
10.0 Objectives
10.1 Introduction
10.2 Parallel and Shift registers
10.3 Serial Shifting
10.4 Serial - in Serial - out (SISO)
10.5 Serial - in Parallel - out
10.6 Parallel - in Parallel - out
10.7 Ring counter
10.8 Johnson counter
10.9 Application of shift registers
10.10 Pseudo-random binary sequence generator
10.11 IC7495
10.12 Seven Segment displays
10.13 Analysis of shift counters.
10.14 Summary
10.15 Reference for further reading

10.0 Objectives: This chapter would make you understand the following concepts
 What is register?
 Different types of registers – Parallel and Shift registers.
 Serial Shifting,
 Ring counter, Johnson Counter.
 Applications of Shift Register.
 Pseudo-random binary sequence generator
 IC7495, Analysis of Shift Counter
10.1 Introduction
Till this point, we have studied different flip-flops and conversion from one to another.
Now let's concentrate on application part of flip-flops. The most common use of FF is a
simple Register (OR a n bit memory storage device). In this section, we will start with
basic definition of register and slowly move on to shift register.
Register is a group of memory element that works together as a unit. Register simply
stores a binary word. When register accepts parallel data and outputs parallel data, the
same is referred as Parallel register or buffer register. About shift register, it is nothing
but memory element with facility of shifting left and right, bit by bit. Before going deep
into shift register, let's see structure of buffer register.
10.2 Parallel and shift registers:
10.2.1 Buffer Register:
Buffer register is simplest kind of register and stores digital word. The structure of buffer
register, built with the edge triggered D type FF is shown in Figure 10.2

Figure 10.2: Buffer Register

Working:
(1) Initially, consider Q3 Q2 Q1 Q0 = 0 0 0 0
(2) Apply data to be stored at input terminals Y3 – Y0. Let's say Y3 Y2 Y1 Y0 = 1010.
(3) Apply clock pulse.
(4) When first clock edge arrives, Y3 Y2 Y1 Y0 = Q3 Q2 Q1 Q0 = 1010
(5) Even though if now Y3 Y2 Y1 Y0 = 0 0 0 0, Q3 Q2 Q1 Q0 = 1010 i.e. latched.
Conclusion:
From Fig. 10.2 and WORKING we conclude that,
(1) There must be one FF for each bit in binary number.  For 4 bit we require 4 FFs.
(2) Simultaneously Y3 – Y0 was applied and loaded to Q3 - Q0 by single clock pulse. i.e.
at a time Q3 to Q0 was loaded.
(3) Therefore, the way we applied input and taken output, is called parallel in - parallel
out (PIPO). The block schematic representation is shown in Figure 10.2.1.
This is also called as Parallel Shifting.

Figure 10.2.1: Parallel in – Parallel out (PIPO)

10.3 Serial shifting:

One more method of loading or shifting the data is called Serial Shifting. What do you
mean by serial?
Serial means bit by bit data flow, serially, on single line. Serial shifting has only single bit
data line, not 4 or 8 as in parallel loading. The serial shifting can be represented by
block schematically, as shown in Figure 10.3.
Single bit data is entered in register and serially single data bit is taken out, through
register. A group of flip-flops connected to provide serial out, when serial input is given,
is called as Shift register.

Figure 10.3: Serial Shifting

Basically if you see, loading parallel data is much faster than the serial. Secondly,
normally we work with 8 bit, 16 bit, and 32 bit parallel data bits.
So one can ask, why you think of serial data? The answer for the question is very
simple. If you see, up till now we are looking of loading the registers, but now think of
loading or transmitting data at distant end. Fig. 10.3.1 shows parallel and serial data
transmission.

Figure 10.3.1: Parallel and Serial data transmission

As shown in Figure 10.3.1 parallel transmission requires 8 lines, serial requires single
line. Now think of distance between A and B location is in meters and kilometers. At
such a large distance just increasing length of the wire is not the solutions because now
wire is Transmission line, so reflection, impedance matching, power required etc.
parameter, we have to consider. Increasing power will increase total power
consumption of the system. In parallel, power for 8 lines has to be increased;  power
consumed is much, in comparison with single line of serial.  Normally serial
transmission is preferred over parallel. At this point you must be eager to know how
serial data looks like. It is shown in figure 10.3.2

Figure 10.3.2: Format of Serial data

As shown in Figure 10.3.2, data is represented on time axis is bit by bit, not full 8 bit or
16 bit as in parallel. Time ‗t‘ for each bit is same. Data stream shown is, ..0, 1, 1, 0, 0,
1,…
Therefore serial communication has become common and most widely used media for
communication. But our systems are normally dealing with parallel (8 bit, 16 bit and so
on),  one has to convert parallel to serial. This function is also called as parallel input
and serial output (PISO).
Serial data is now transrnitted to location B. On receiving side (B side), one has to
convert serial data back to parallel. This function of conversion is called serial in and
parallel out (SIPO). Finally one may require serial in and serial out (SISO). Figure
10.3.3 shows generalized block schematic of four functions.

Figure 10.3.3: Generalized block schematic of four functions.

10.4 Serial in – Serial out (SISO):
In SISO, two main operations are performed, serial left shifting and serial right shifting;
Serial Left Shift:
Figure 10.4 shows serial operation, built using D Flip-Flop. To know data shifts left we
temporarily take output of Q2 Q1 and Q0 also.

Figure 10.4: Serial operation

Working:
(1) Initially all FFs are reset  Q3 Q2 Q1 Q0 = 0 0 0 0
(2) Make Data IN = 1.
(a) At 1st CLK edge, output will be Q3 Q2 Q1 Q0 = 0 0 0 1 (Refer truth table of D FF).
(b) At 2nd CLK edge, output will be Q3 Q2 Q1 Q0 = 0 0 1 1
(c) At 3rd CLK edge, output will be Q3 Q2 Q1 Q0 = 0 1 1 1
(d) At 4th CLK edge, output will be Q3 Q2 Q1 Q0 = 1 1 1 1
(3) Now the Data IN = 0.
(e) At 5th CLK edge, output will be Q3 Q2 Q1 Q0 = 1 1 1 0
(f) At 6th CLK edge, output will be Q3 Q2 Q1 Q0 = 1 1 0 0
(g) At 7th CLK edge, output will be Q3 Q2 Q1 Q0 = 1 0 0 0
(h) At 8th CLK edge, output will be Q3 Q2 Q1 Q0 = 0 0 0 0

Figure 10.4.1: Waveforms

If you observe, 1 or 0 travels from right hand to left hand,  called left shifting. Let's
observe waveforms for the same. Waveforms are self-explanatory. Refer Figure 10.4.1.
Shift Right:
Figure 10.4.2 shows serial right shift circuit, built using D FF.

Figure 10.4.2: Serial right shift circuit

Working:
(1) Initially all FFs are cleared  Q3 Q2 Q1 Q0 = 0 0 0 0
(2) Make Data In = 1
(a) 1st CLK edge, output will be, Q3 Q2 Q1 Q0 = 1 0 0 0
(b) 2nd CLK edge, output will be, Q3 Q2 Q1 Q0 = 1 1 0 0
(c) 3rd CLK edge, output will be, Q3 Q2 Q1 Q0 = 1 1 1 0
(d) 4th CLK edge, output will be, Q3 Q2 Q1 Q0 = 1 1 1 1
(3) Now apply Data In = 0.
(e) 5th CLK edge, output will be, Q3 Q2 Q1 Q0 = 0 1 1 1
(f) 6th CLK edge, output will be, Q3 Q2 Q1 Q0 = 0 0 1 1
(g) 7th CLK edge, output will be, Q3 Q2 Q1 Q0 = 0 0 0 1
(h) 8th CLK edge, output will be, Q3 Q2 Q1 Q0 = 0 0 0 0
Thus 1 and 0, travel from left to right,  right shifting.
10.5 Serial in - Parallel out:
In this function, data is entered serially and taken out in parallel. To take data parallel
out, it is necessary to have all data bits available as output, at the same time and
therefore output of each FF is taken.

Figure 10.5: Circuit diagram Serial in – Parallel out

If you observe the diagram carefully you will find that,
(1) Clock of all FFs are tied together, therefore all FF changes state at same time.
(2) Asynchronous input, CLEAR, is given to all FF. So that when CLEAR = 0, all FFs
 are resetted, output Q = 0000 0000.
(3) A and B are data inputs, either of the terminal can be used as control line.
When A = 0, irrespective of B, input to FF will be 0. At each CLOCK edge 0 travels
from left to right and after 8 CLOCK pulses. Q output = 0000 0000. It means if
B = Data In, data will get inhibited.
When A = 1, NAND gates enabled and data Input B passes through NAND gate
inverted. The input data shifted serially in the register.
(4) Output of all FFs are taken as final output. O/P is Q, not . Output appears at a
time,  It is parallel output.
(5) Data inputs may be changed while CLOCK is either low or high.

10.6 Parallel in – Parallel out:

This type we have already studied in section 10.2.1, buffer register. In that Y3 - Y0 was
inputted parallel and Q3 - Q0 taken out parallel.

10.7 Ring counter:

Refer figure 10.4 in that circuit if Q3 is connected to Serial Data In. then circuit is
going to circulate injected pulse. The way circuit behaves, it is named as 'Ring
Counter'.

Figure 10.7: Ring counter

Working:
Basically ring counter resembles shift register because the bits are shifted left one
position per positive clock edge. Only change is feedback line. i.e. output of Q3 given to
Q0.
(1) Initially CLOCK goes low then back to high. F3, F2, F1 will be reset and F0 is preset
giving output Q3 Q2 Q1 Q0 = 0 0 0 1.
(2) At 1st positive CLOCK edge, MSB moves to LSB, Q3 → Q0, Q2 → Q3, Q1 → Q2
and Q0 → Q1  output Q3 Q2 Q1 Q0 = 0 0 1 0
(3) At 2nd positive CLOCK edge, with respect to second point, bits will shift left.
 Output Q3 Q2 Q1 Q0 = 0 1 0 0.
(4) At 3rd positive CLOCK edge, with respect to 3rd point, bits will shift left.
 Output Q3 Q2 Q1 Q0 = 1 0 0 0
(5) At 4th positive CLOCK edge, with respect to 4th point, bits will shift left.
 Output Q3 Q2 Q1 Q0 = 0 0 0 1
Thus presetted '1' follows circular path or makes ring.  It is called as ring counter.
Observe waveform for the same. Refer Fig. 10.7 (a)

Figure 10.7 (a): Waveform – Ring counter

Conclusion:
(1) Number of FFs used are 4.
(2) Number of states for ring counter is also 4. i.e. 0001, 0010, 0100, 1000 and chain
repeats.
(3) Number of 1‘s s is single.
Let's write output Q for 8 bit. So for 8 bit, 8 FFs will be used.
Initially Q = 0000 0010
1st clock edges, Q = 0000 0010
2nd clock edges, Q = 0000 0100
3rd clock edges, Q = 0000 1000
 4th clock edges, Q = 0001 0000
5th clock edges, Q = 0010 0000
6th clock edges, Q = 0100 0000
7th clock edges, Q = 1000 0000
8th clock edges, Q = 0000 0001 → Repeat,
If you require you can also take output from ,  For 4 bit Refer Figure 10.7
Initially when = 0, Q = 0001  = 1110
1st CLOCK edge = 1101
2nd CLOCK edge = 1011
3rd CLOCK edge = 0111
4th CLOCK edge = 1110

Application:
Ring counters are invaluable when it is necessary to control sequence of operation.
Mainly ring counters are used in microprocessor.
Relationship of number of states and FFs:
In ring counter number of FFs and number of states are equal. Ring counter using JK
FF is shown in Figure 10.7.1.
The working of circuit is same as that of, when D FF is used.

Figure 10.7.1: Ring counter using JK FF

10.8 Johnson Counter (Twisted Ring Counter):

In ring counter output shift register was fed back to input of first FF, that technique was
referred as direct feedback. But if outputs of last FF are crossed and then connected to
inputs of first FF. the technique is called inverse feedback. The counter we get from this
technique is called Johnson counter or twisted ring counter.
Circuit:
Let's draw circuit of Johnson counter using positive edge triggered JK FF.

Figure 10.8: 4 bit Johnson counter

CLOCK QD QC QB QA State Decimal Equivalent

Initially 0 0 0 0 1 0
1 0 0 0 1 1 1
2 0 0 1 1 3 3
3 0 1 1 1 4 7
4 1 1 1 1 5 15
5 1 1 1 0 6 14
6 1 1 0 0 7 12
7 1 0 0 0 8 8
8 0 0 0 0 1 0

Figure 10.8(a): Truth table

Working:
Refer Figures 10.8 and 10.8(a).
(1) Initially is made low and then high after some time.
 all FFs will be cleared and output QD QC QB QA = DCBA = 0000.
(2) Now Inputs JD = JC = JB = 0, KD = KC = KB = 1 and JA = 1, KA = 0. So CLOCK
edge hits. A will change from 0  1 BCD are unchanged  DCBA = 0001.
(3) Inputs JD = JC = 0, KD = KC = 1. But JA = JB = 1, KA = KB = 0.  the moment
 CLOCK edge hits D and C are unchanged. A is also unchanged. But B changes
from 0  1.  DCBA = 0011.
(4) Inputs JD = 0 KD = 0, JA = JB = JC = 1 and KA = KB = KC = 0 and  the CLOCK
edge will change output C from 0  1, A, B and D are unchanged.  DCBA = 0111.
(5) Inputs JD = JC = JB = JA and KD = KC = KB = KA = 0
 next CLOCK edge changes D from 0  1,  DCBA = 1111
(6) Because of change of state of D from 0  1. Now I/P to JA = 0 and KA = 1, JD = JC =
JB = 1 and KD = KC = KB = 0.  next CLOCK edge changes A from 1  0
 DCBA = 1110.
(7) Now input to JA = JB = 0 and KA = KB = 1 and JD = JC =1 and KD = KC= 1
 next CLOCK edge changes B from 1  0.  DCBA = 1100 means A, D, C are
unchanged.
(8) At this stage input to JA = JB = JC = 0 and KA = KB = KC = 1, JD = 1 and KD = 0.
 next CLOCK edge keeps A, B and D unchanged, C changes from 1  0.
 DCBA = 1000.
(9) Finally input to JA = JB = JC = JD = 0 and KA = KB = KC = KD = 1  at next CLOCK
edge D changes from 1  0.  DCBA = 0000, Now cycle will repeat from point 2
onwards.
As we have seen in working of Johnson counter and observing truth table, we conclude
that number of states of Johnson counter are double of number of FFs. Therefore for 4
FFs states will be 8. 5 FFs states will be 10 and for 8 FFs states will be 16.
Johnson counter using D FF

Figure 10.8(b): Johnson counter using D FF

The working of the circuit is same as what we have seen.
10.9 Applications of Shift Registers:

Shift registers can be used for:

(1) Generating sequence (pulse generator)
(2) Counters
(3) Random bit generator.
(1) Sequence Generator (Pulse Generator):
Block schematic structure is shown in Figure 10.9

Figure 10.9: Block diagram – Sequence generator

Basically shift register sequence generator contains basic two blocks:
(1) 'N' bit shift register (SIPO type).
(2) Combination logic circuit.
Combinational logic circuit has input QN-1 to Q0. From this it will decide, what should be
the next serial input for shift register block, should be generated, so that new state or
sequence will appear. Now we will take an example to design sequence generator.
Example 1: The following pulse train is to be generated by using a shift register.
Explain the steps in designing and draw logic diagram.
pulse train ... 1011010110 ...
Solution:
(1) Observe the pulse train carefully and you will find that main pulse train, which is
repeating, is 10110.
i.e … ⏟ ⏟ …

(2) Calculate number of distinct timing intervals. In short you calculate number of bits of
pulse train. In our case it is
(3) Number of FFs can be given by equation,

Where N = Number of FFs.

S = Number of distinct timing intervals.
 S ≤ 2N – 1
 6 ≤ 2N  N = 3
 3 FFs are required.
(4) Preparing state table for sequence generator
Make table, containing number of states, decimal equivalent and 3 output of FF (N = 3)

Figure 10.9(a): State table

Procedure for preparing State table:
(a) Write the format of table as shown in Figure 10.9(a). i.e. states, output of 'N' number
of FF and decimal equivalent.
(b) Under column 1st (Normally MSB is selected) write down sequence 'vertically'.
(c) Now just imagine that sequence is having ring structure and shift the full sequence
by y one bit.  If sequence is 10110, rotate it left by one bit so we will get 01101.
Write down shifted version under column 2.
(d) Again shift the sequence by one bit. Therefore with respect to original it will be
shifted twice. Sequence under column 2 is 01101. Shift left by one bit.  Sequence
is 11010. Write it under column 3.
(e) Continue shifting of sequence unless you reach to LSB column. After shifting
(Rolling) sequence now find out decimal equivalent of binary sequence. For our case
we got 5, 3, 6, 5, 2.
In this decimal sequence, decimal number 5 is repeated twice,  states are not distinct,
 we have to increase number of FFs to get distinct states. Therefore make state table
again with four FFs.

Figure 10.9(b): State table

Procedure for making truth table is same as we discussed just now. If we observe the
decimal equivalent, it is coming out to be 11, 6, 13, 10, 5. All states are distinct.
(5) Design of Combinational circuit:
Here we have to find out O/P Y of combinational circuit, given to shift register, so that
state changes from previous to next.
For example let's say DCBA = 1011 (1 decimal), what should be input to shift register,
so that DCBA will be 0110. Means we have to apply '0' to input of shift register or in
short Y should be 0. Same way you find Y for each state. The format of table is shown
in Figure 10.9(c) State table

Figure 10.9(c): State table

As shown in Figure 10.9 (c). Output Y of combinational circuit is again nothing but 1 bit
shifted version of LSB column.
(6) K-Map:
Valid states are 11, 6, 13, 10, 5, remaining states are don‘t care. States reached to 13,
four variable K-Map should be used.

Figure 10.9(d): K – Map

(7) Logic diagram:

Figure 10.9(e): Logic diagram

10.10 Pseudo – Random Binary Sequence (PRBS) Generator:

One important application of shift register is pseudo-random generator. It is basically
used to generate random sequence. Due to random sequence generation the same can
be used for generating noise, as well as used for data encryption. By generating
random noise, one can test immunity given by his / her design to the noise. By
encrypting data, it becomes difficult job for a person who hacks the data in between.
Basically, the sequence generated is not truly random because it cycles through all
possible combinations once every 2n — 1 clock cycles (n= number of FFs).
Generation of pseudo random sequence is based on feedback given to shift register
through Combinational logic circuit. Figure 10.10 depicts noise generator based on
pseudo-random sequence. The combinational circuit used is simple EX-OR gate.

Figure 10.10: Noise generator based on pseudo-random sequence

It uses, 31 stage shift register provided with linear feedback to produce maximum length
pseudo-random bit sequence. One of the significant features of pseudo-random
sequence is that the noise produced from there is repeatable. The spectral density of
the noise output of this circuit is uniform to within ±1 dB over the frequency range 20Hz
to 20 kHZ.
The maximum length of sequence (MLS) generated will be 2n – 1
2n – 1 = 231 – 1, sufficient length to encrypt the data.

10.11 IC7495:
We are going to study now TTL MSI Chip 7495. 4 bit shift register with serial and
parallel synchronous operating mode.
Features of the chip are:
(1) Synchronous shift left capability.
(2) Synchronous parallel load.
(3) Separate shift and load clock inputs.
(4) Synchronous expandable shift right. Let's see internal block of IC 7495 and Pin
configuration.

Figure 10.11(a): Pin Configuration – IC 7495

Figure 10.11(b): Logic diagram (Universal Shift Register)

We are going to perform basically three functions using 7495:
(1) Parallel load
(2) Shift left
(3) Shift right
1. Parallel Load:
(a) Make mode control = 1, therefore AND gate 2, 4, 6, 8 will get enabled.
(b) Apply input ABCD.
(c) In this case clock 2 input (pin number 8) is enabled. Therefore a HIGH to LOW
transition on clock and input will transfer parallel data ABCD inputs to Q0 – Q3.
(d) Here clock 1 input is don‘t case. DS is also don‘t care.
2. Shift Right:
(a) Make mode control = 0, therefore AND gate 1, 3, 5, 7 will be enabled and AND
gate 2, 4, 6, 8 will get disabled.
(b) The data input to FF QA is now at serial input (DS).
(c) Clock and input is don‘t care. ABCD inputs are don‘t care.
(d) Apply CLOCK input to clock 1.
(e) A HIGH to LOW transition on enabled clock 1 input transfers data serially from
DS to QA, QA to QB, QB to QC and QC to QD respectively (right shift).
3. Shift Left:
(a) For shift left operation external connection are to be performed.
Connect QD to C, QC to B and QB to A. as shown in figure 10.11.1

Figure 10.11.1: Three functions using 7495

10.12 Seven Segment displays:
7 Segment display is one of the oldest methods of displaying values in electronic
devices. The combination of 7 LEDs makes the whole display. Every time a single pin
gets the power of a specific range it starts glowing. The pattern and drawing of LED
make the decimal digit 8. Then turning on/off the specific pins make the 7-segment to
show the other decimal numbers. The LED has a total of 10 input pins. It also comes in
two types; one is the cathode and the other one is the anode. In both types, one gives
the common anode and the other has a common cathode. The 7-segment is useable
directly by any low voltage device.
As 7-segment displays are very common components of digital devices, it is good to be
familiar with the ―driving‖ circuits behind them, and the 4511 is a good example of a
typical driver IC.
Its operating principle is to input a four-bit BCD (Binary-Coded Decimal) value and
energize the proper output lines to form the corresponding decimal digit on the 7-
segment LED display. The BCD inputs are designated A, B, C, and D in order from
least-significant to most-significant. Outputs are labeled a, b, c, d, e, f, and g, each letter
corresponding to a standardized segment designation for 7-segment displays. Of
course, since each LED segment requires its own dropping resistor, we must use seven
470 Ω resistors placed in series between the 4511‘s output terminals and the
corresponding terminals of the display unit.
Most 7-segment displays also provide for a decimal point (sometimes two), a separate
LED and terminal designated for its operation. All LEDs inside the display unit are made
common to each other on one side, either cathode or anode. The 4511 display driver IC
requires a common-cathode 7-segment display unit, and so that is what is used here.
After building the circuit and applying power, operate the four switches in a binary
counting sequence (0000 to 1111), noting the 7-segment display. A 0000 input should
result in a decimal ―0‖ display, a 0001 input should result in a decimal ―1‖ display, and
so on through 1001 (decimal ―9‖). What happens for the binary numbers 1010 (10)
through 1111 (15)? Read the data sheet on the 4511 IC and see what the manufacturer
specifies for operation above an input value of 9.
In the BCD code, there is no real meaning for 1010, 1011, 1100, 1101, 1110, or 1111.
These are binary values beyond the range of a single decimal digit, and so have no
function in a BCD system. The 4511 IC is built to recognize this, and output (or not
output accordingly.
Three inputs on the 4511 chip have been permanently connected to either Vdd or
ground: the ―Lamp Test,‖ ―Blanking Input,‖ and ―Latch Enable.‖ To learn what these
inputs do, remove the short jumpers connecting them to either power supply rail (one at
a time!), and replace the short jumper with a longer one that can reach the other power
supply rail.
For example, remove the short jumper connecting the ―Latch Enable‖ input (pin #5) to
ground, and replace it with a long jumper wire that can reach all the way to the
Vdd power supply rail. Experiment with making this input ―high‖ and ―low,‖ observing the
results on the 7-segment display as you alter the BCD code with the four input switches.
After you have learned what the input‘s function is, connect it to the power supply rail
enabling normal operation, and proceed to experiment with the next input (either ―Lamp
Test‖ or ―Blanking Input‖).
Once again, the manufacturer‘s datasheet will be informative as to the purpose of each
of these three inputs. Note that the ―Lamp Test‖ (LT) and ―Blanking Input‖ (BI) input
labels are written with Boolean complementation bars over the abbreviations.
Bar symbols designate these inputs as active-low, meaning that you must make each
one ―low‖ in order to invoke its particular function. Making an active-low input ―high‖
places that particular input into a ―passive‖ state where its function will not be invoked.
Conversely, the ―Latch Enable‖ (LE) input has no complementation bar written over its
abbreviation, and correspondingly it is shown connected to ground (―low‖) in the
schematic so as to not invoke that function.
The ―Latch Enable‖ input is an active-high input, which means it must be made ―high‖
(connected to Vdd) in order to invoke its function.
 Figure 10.12 Schematic diagram of Seven Segment display with display driver

10.13 Analysis of shift Counters:

In this circuit will be given and one has to find states through which shift register passes.
To understand this let's solve example.
Example 2: A shift register with associated combinational logic circuit is shown in
Figure 10.13. Explain its action by drawing waveforms for the outputs of shift register
(ABCD). Assume that initially shift register is in state ABCD = 1111.

Figure 10.13: circuit diagram

Solution:
(1) Write equation for output Y.
(2) Basically output Y is serial in for shift register, shift is left shift,  serial in placed in
LSB i.e. D. So make table.
 Figure 10.13(a): truth table
Explanation:
(Refer Figure 10.13(b))
Initially ABCD = 1111,  Y = (1 ⊕ 1) + =0+0=0
 Y = serial in = 0,  when 1st CLOCK edge hits, ABCD = 1110 (Legit shift)
Now ABCD = 1110,  Y = (1 ⊕ 1) + =0+0=0
 Y = serial in = 0,  when 2nd CLOCK edge hits, ABCD = 1100
Thus you proceed till you get initial condition ABCD = 1111.
From table (Figure 10.13(a)) we found that counter, counts through 15, 14, 12, 9, 3, 6,
13, 10, 5, 11, 7 and 15.
Thus generates sequence → 111100110101 Waveforms (Waveforms are as shown in
Figure 10.13(b)).

Figure 10.13(b): waveform

10.14 Summary:
In this chapter we have studied in detail about registers which includes parallel and shift
registers, serial shifting, serial-in serial-out, serial-in parallel-out, parallel-in parallel-out,
Ring counter, Johnson counter, Application of shift registers, Pseudo-random binary
sequence generator, IC7495, Seven Segment displays and analysis of shift counters
with examples.
9.15 Reference for further reading:
For further detailed study following are books prescribed by the University
1. Digital Electronics and Logic Design by N. G. Palan
2. Modern Digital Electronics by R. P. Jain
3. Digital Principles and Applications by Malvino and Leach