Module III

EMBEDDED SYSTEMS
MODULE-III: ARM INSTRUCTION

SET AND ASSEMBLY LANGUAGE
Mr. M Naresh Kumar

Asst.Prof., Dept.of EECE,
GITAM (Deemed to be University)
CONTENTS
Catagories of ARM Instructions

Data Processing Units
Arithmetic Instructions
• Unsigned numbers are defined as data in which all the bits are used
to represent data and no bits are set aside for the positive or
negative sign.
Affecting flags in ARM instructions

• A unique feature of the execution of ARM arithmetic instructions is
that it does not affect (updates) the flags unless we specify it.
• This is different from other microcontrollers and CPUs such as 8051
and x86. In the x86 and 8051 the arithmetic instructions
automatically change the Z and C flags regardless of we want it or
Department of EECE-19ECS431-EMBEDDED SYSTEMS 5
not.
• The default for the ARM instruction is not to affect these flags after the
execution of arithmetic instructions such as ADD and SUB.
• We override the default by having letter S in the instruction
• For example, we must use SUBS instead of SUB

6

Addition of unsigned numbers
The form of the ADD instruction is

ADD Rd,Rn,Op2 ;Rd = Rn + Op2
The destination operand must be a register.

The Op2 operand can be a register or immediate.
Memory-to-register or memory-to-memory arithmetic and logic

operations are never allowed in ARM Assembly language since it is a
RISC processor.
The effect of the ADDS instruction on the overflow (V) and N (negative)
flags they are used in signed number operations
8
a) LDR R2,=0xFFFFFFF5 ;R2=0xFFFFFFF5 (notice the = sign)
MOV R3,#0x0B
ADDS R1,R2,R3 ;R1=R2 + R3 and update the flags
b) LDR R2,=0xFFFFFFFF
ADDS R1,R2,#0x95 ;R1=R2 + 95 and update the flags
No increment instruction in ARM

• There is no increment instruction in the ARM processor.
• we use ADD to perform this action.
• The instruction “ADDS R4,R4,#1” will increment the R4
and places the result in R4 register.

9
ADC (add with carry)
• This instruction is used for multiword (data larger than 32-bit) numbers. The form of
the ADC instruction is
• ADC Rd,Rn,Op2 ;Rd = Rn + Op2 + C
In discussing addition, the following two cases will be examined:
1. Addition of individual word data
2. Addition of multiword data
CASE 1: Addition of individual word data

• LDR R2,=0xFFFFFFF1 ;R2 = 0xFFFFFFF1
• MOV R3,#0x0F
• ADDS R3,R3,R2 ;R3 = R3 + R2 and update the flags
• ADD R3,R3,#0x7 ;R3 = R3 + 0x7 and flags unchanged

10
CASE 2: Addition of multiword numbers
Analyze the following program which adds 0x35F62562FA to 0x21F412963B:
• LDR R0,=0xF62562FA ;R0 = 0xF62562FA
• LDR R1,=0xF412963B ;R1 = 0xF412963B
• MOV R2,#0x35 ;R2 = 0x35
• MOV R3,#0x21 ;R3 = 0x21
• ADDS R5,R1,R0 ;R5 = 0xF62562FA + 0xF412963B
;now C = 1
• ADC R6,R2,R3 ;R6 = R2 + R3 + C
; = 0x35 + 21 + 1 = 0x57

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Subtraction of unsigned numbers

SUB Rd,Rn,Op2 ;Rd = Rn - Op2
• In subtraction, the ARM microprocessors use the 2’s
complement method.
• Although every CPU contains adder circuitry, it would be too
cumbersome (and take too many logic gates) to design separate
subtractor circuitry.
1. Take the 2’s complement of the subtrahend (Op2 operand).
2. Add it to the minuend (Rn operand).
3. Place the result in destination Rd.
4. Set the carry flag if there is a carry.

12
Show the steps involved for the following cases:

a)
MOV R2,#0x4F ;R2 = 0x4F
MOV R3,#0x39 ;R3 = 0x39
SUBS R4,R2,R3 ;R4 = R2 – R3
Solution:
0x4F 0000004F
– 0x39 + FFFFFFC7 2’s complement of 0x39
________ ________________
16 1 00000016 (C = 1 step 4)
The flags would be set as follows: C = 1, and Z = 0. The programmer

must look at the carry flag (not the sign flag) to determine if the
result is positive or negative.
13
• Notice that, unlike x86 CPUs, ARM does not invert the carry flag after
SUBS so C=0 when there is borrow and C=1 when there is no borrow.
• It means that after the execution of SUBS, if C=1, the result is positive;
if C = 0, the result is negative and the destination has the 2’s
complement of the result.
• Analyze the following instructions:

MOV R1,#0x4C ;R1 = 0x4C
MOV R2,#0x6E ;R2 = 0x6E
SUBS R0,R1,R2 ;R0 = R1 – R2
• Following are the steps for “SUB R0,R1,R2”:
4C 0000004C
–6E + FFFFFF92 (2’s complement of 0x6E)
______________ ____________
– 22 FFFFFFDE (C = 0 step 4) result is negative, fins the 2’s complement of
this number to get the result

14
SBC (subtract with borrow)
SBC Rd,Rn,Op2 ;Rd = Rn – Op2 – 1 + C
• This instruction is used for subtraction of multiword (data larger than

32-bit) numbers.
• ARM the carry flag is not inverted after subtraction and carry flag is
invert of borrow.
• To invert the carry flag while running the subtract with borrow
instruction it is implemented as
“Rd = Rn – Op2 – 1 + C”

15
• Analyze the following program which subtracts 0x21F62562FA from 0x35F412963B:

• LDR R0,=0xF62562FA ;R0 = 0xF62562FA,
• LDR R1,=0xF412963B ;R1 = 0xF412963B
• MOV R2,#0x21 ;R2 = 0x21
• MOV R3,#0x35 ;R3 = 0x35
• SUBS R5,R1,R0 ;R5 = R1 – R0
; = 0xF412963B – 0xF62562FA, and C = 0
• SBC R6,R3,R2 ;R6 = R3 – R2 – 1 + C
; = 0x35 – 0x21 – 1 + 0 = 0x13

16
No decrement instruction in ARM

• Instead we use SUB to perform the action. The instruction “SUB
R4,R4,#1” will decrement one from R4 and places the result in R4
register.
RSB (reverse subtract)
The format for the RSB instruction is
RSB Rd,Rn,Op2 ;Rd = Op2 – Rn
• Notice the difference between the RSB and SUB instruction.
• They are essentially the same except the way the source operands
are subtracted is reversed.
• This instruction can be used to get 2’s complement of a 32-bit
operand
• Ex: MOV R1,#0x6E ;R1=0x6E
RSB R0,R1,#0 ;R0= 0 – R1
RSC (reverse subtract with carry)

• The form of the RSC instruction is
• RSC Rd,Rn,Op2 ;Rd = Op2 – Rn – 1 + C
• Notice the difference between the RSB and RSC instructions.
• They are essentially the same except the way the source operands
are subtracted is reversed.
• This instruction can be used to get the 2’s complement of the 64-bit
operand

Classification of embedded system

• Show how to create 2’s complement of a 64-bit data in R0 and R1 register. The R0 hold
the lower 32-bit.
Solution:
• LDR R0,=0xF62562FA ;R0 = 0xF62562FA
• LDR R1,=0xF812963B ;R1 = 0xF812963B
• RSB R5,R0,#0 ;R5 = 0 – R0
; = 0 – 0xF62562FA = 9DA9D06 and C = 0
• RSC R6,R1,#0 ;R6 = 0 – R1 – 1 + C
; = 0 – 0xF812963B – 1 + 0 = 7ED69C4

Classification
Multiplication of embedded
and division system
of unsigned numbers
• Not all CPUs have instructions for multiplication and division.
• All the ARM processors have a multiplication instruction but not the
division.
• Some family members such as ARM Cortex have both the division
and multiplication instructions.
Multiplication of unsigned numbers in ARM
• normal multiply - MUL is used when the result is less than 32-bit
• long multiply-MULL must be used when the result is greater than 32-
bit.


MUL (multiply)
MUL Rd,Rn,Op2 ;Rd = Rn × Op2
• The operands must be in registers
UMULL (unsigned multiply long)
UMULL RdLo,RdHi,Rn,Op2 ;RdHi:RdLoRd = Rn × Op2
LDR R1,=0x54000000 ;R1 = 0x54000000
LDR R2,=0x10000002 ;R2 = 0x10000002
UMULL R3,R4,R2,R1 ;0x54000000 × 0x10000002
; = 0x054000000A8000000
;R3 = 0xA800000, the lower 32 bits
;R4 = 0x05400000, the higher 32 bits

Multiply and Accumulate Instructions in ARM
• In some application such as digital signal processing (DSP) we need
to multiply two registers and add the result with another register.
• The format of MLA (multiply and add) instruction is as follows:
MLA Rd,Rm,Rs,Rn ;Rd = Rm × Rs + Rn
UMLAL (unsigned multiply and add long)
UMLAL RdLo,RdHi,Rn,Op2 ;RdHi:RdLo = Rn × Op2 + RdHi:RdLo
Division of unsigned numbers in ARM

• Some ARM families do not have an instruction for division of
unsigned numbers since it takes too many gates to implement it.
• We can use SUB instruction to perform the division.
Logic Instructions
AND
AND Rd, Rn, Op2 ;Rd = Rn ANDed Op2
The destination and the first source operands are registers.
Op2 -can be a register or an immediate value of less than 0xFF
ORR
ORR Rd, Rn, Op2 ;Rd = Rn ORed Op2

Logic Instructions

Logic Instructions
EORClassification of embedded system
EOR Rd,Rn,Op2 ;Rd = Rn Ex-ORed with Op2
EOR can also be used to see if two registers have the same value.
make Z = 1 if both registers have the same value
Another widely used application of EOR is to toggle bits of an
operand
EOR R2,R2,#0x04 ;EOR R2 with 0000 0100
BIC (bit clear)
BIC Rd,Rn,Op2 ;clear certain bits of Rn specified by the Op2
and place the result in Rd
• The bits that are HIGH in Op2 will be cleared and bits with LOW will
be left unchanged.
• For example, assuming that R3 = 00001000 the instruction “BIC
R2,R2,R3” will clear bit 3 of R2 and leaves the rest of the bits
unchanged. Department of EECE-19ECS431-EMBEDDED SYSTEMS 25
Logic Instructions
MVN (move negative)
MVN Rd, Rn ;move negative of Rn to Rd
• The MVN (move negative) instruction is used to generate one’s
complement of an operand.
• Ex-OR instruction to generate one’s complement of an operand.
• Ex-ORing an operand with 0xFFFFFFFF will generate the 1’s
complement
LDR R2,=0xAAAAAAAA ;R2 = 0xAAAAAAAA
MVN R0,#0 ;R0 = 0xFFFFFFFF
EOR R2,R2,R0 ;R2 = R2 ExORed with 0xFFFFFFFF
; = 0x55555555



Barrel Shifter
➢The barrel shifter is a functional unit.
➢It provides five types of shifts and rotates which can be
applied to Operand2.

Using the Barrel Shifter: The Second Operand

Operan Operan • Register, optionally with shift
operation applied.
d1 d2 • Shift value can be either be:
• 5 bit unsigned integer
Barrel • Specified in bottom byte of
another register.
Shifter
• Register, optionally with shift
operation applied.
• Shift value can be either be:
ALU • 5 bit unsigned integer
• Specified in bottom byte of
another register.
Result

Operand 2 and the barrel shifter
• The first operand for all data processing operations must
always be a register.
• The second operand is much more flexible and can be
either an immediate value (#x), a register (Rm), or a register
shifted by an immediate value or register "Rm, shift #x" or
"Rm, shift Rs".
• five shift operations:
LSL(Left Shift),LSR(Logical Right Shift),ASR(Arithmetic Right
Shift),ROR(Rotate Right),RRX(Rotate Right Extended)



Rotate and Barrel Shifter
• Although ARM Cortex has shift and rotate instructions
• ARM7 we can perform the shift and rotate operations as part of
other instructions such as MOV.
Barrel Shifter
• There are two kinds of shifts: logical and arithmetic.
• The logical shift is for unsigned operands and the arithmetic shift is
for signed operands.
LSR (logical shift right)
• The operand is shifted right bit by bit, and for every shift the LSB
(least significant bit) will go to the carry flag (C) and the MSB (most
significant bit) is filled with 0.
One can use an immediate operand or a register to hold
the number of times it is to be shifted.
MOV R0,#0x9A ;R0 = 0x9A
MOVS R1,R0,LSR #3 ;shift R0 to right 3 times and then
move (copy) the result to R1
Another way
MOV R0,#0x9A
MOV R2,#0x03
MOV R1,R0,LSR R2 ;shift R0 to right R2 times and move the result
to R1
LDR R0,=0x88 ;R0=0x88

MOVS R1,R0,LSR #3 ;shift R0 right three times (R1 = 0x11)
LSL (Logical Shift Left)
• Shift left is also a logical shift
• After every shift, the LSB is filled with 0 and the MSB goes to C.
LDR R1,=0x0F000006
MOVS R2,R1,LSL #8
ASR (arithmetic shift right)

MOV Rn,Op2, ASR count

Rotating the bits of an operand right and left
• There are two types of rotations. One is a simple rotation of the

bits of the operand, and the other is a rotation through the carry.
ROR (rotate right)
• In rotate right, as bits are shifted from left to right they exit from the
right end (LSB) and enter the left end (MSB).
• In addition, as each bit exits the LSB, a copy of it is given to the carry
flag.
• In other words, in ROR the LSB is moved to the MSB and is also
copied to C flag, as shown in the diagram.
MOV R1,#0x36 ;R1 = 0000 0000 0000 0000 0000 0000 0011 0110
MOVS R1,R1,ROR #1 ;R1 = 0000 0000 0000 0000 0000 0000 0001 1011 C=0
MOVS R1,R1,ROR #1 ;R1 = 1000 0000 0000 0000 0000 0000 0000 1101 C=1
MOVS R1,R1,ROR #1 ;R1 = 1100 0000 0000 0000 0000 0000 0000 0110 C=1
Rotate left
• There is no rotate left option in ARM7
• since one can use the rotate right (ROR) to do the job.
• That means instead of rotating left n bits we can use rotate right
32–n bits to do the job of rotate left.
• Using this method does not give us the proper carry if actual
instruction of ROL was available

• RRXClassification of embedded
rotate right through carry system
• In RRX, as bits are shifted from left to right, they exit from the right
end (LSB) to
• the carry flag, and the carry flag enters the left end (MSB).
• In other words, in RRX the LSB is moved to C and C is moved to the
MSB.
• C flag acts as if it is part of the operand.
• That means the RRX is like 33-bit register since the C flag is 33th bit.
• The RRX takes no arguments and the number of times an operand to
be rotated is fixed at one.
MOV R2,#0x26
MOVSDepartment
R2,R2,RRXof EECE-19ECS431-EMBEDDED SYSTEMS 39

Branch, Call, and Looping in ARM
•
In the sequence of instructions to be executed, it is often
necessary to transfer program control to a different location.
• Examples: when a function is called, execution of a loop is
repeated, or an instruction executes conditionally
Looping and Branch Instructions:
Looping in ARM
Repeating a sequence of instructions or an operation a certain
number of times is called a loop.
Using instruction BNE for looping

BNE (branch if not equal) instruction uses the zero flag in the status
register
The Classification
BNE instruction is of embedded
used as follows: system
BACK ……… ;start of the loop
……… ;body of the loop
……… ;body of the loop
SUBS Rn,Rn,#1 ;Rn = Rn - 1, set the flag Z = 1 if Rn = 0
BNE BACK ;branch if Z = 0
• The Rn (e.g. R2 or R3) is decremented; if it is not zero, it branches

(jumps) back to the target address referred to by the label
• BNE instruction refers to the Z flag of the status register affected

by the previous instruction, SUBS.

Write a program to (a) clear R0, (b) add 9 to R0 a thousand times, then
(c) place the sum in R4.
Use the zero flag and BNE instruction.
AREA EXAMPLE4_1, CODE, READONLY

ENTRY
LDR R2,=1000 ;R2 = 1000 (decimal) for counter
MOV R0,#0 ;R0 = 0 (sum)
AGAIN ADD R0,R0,#9 ;R0 = R0 + 9 (add 09 to R1, R1 = sum)
SUBS R2,R2,#1 ;R2 = R2 - 1 and set the flags. Decrement counter
BNE AGAIN ;repeat until COUNT = 0 (when Z = 1)
MOV R4,R0 ;store the sum in R4
HERE B HERE ;stay here
END
Looping a trillion times with loop inside a loop

we use a loop inside a loop, which is called a nested loop. In a nested
loop, we use two registers to hold the count.
Other conditional Branches

Comparison of unsigned numbers
CMP Rn,Op2
Classification of ;compare
embeddedRn with Op2 and set the flags
system
• The CMP instruction compares two operands and changes the flags
according to the result of the comparison.
• The operands themselves remain unchanged.
• There is no destination register and the second source operands
can be a register or an immediate value not larger than 0xFF

• Although BCS (branch carry set) and BCC (branch carry clear)
check the carry flag and can be used after a compare instruction, it
is recommended that BHS (branch higher or same) and BLO
(branch below) be used for two reasons.
• One reason is that assemblers will unassemble BCS as BLO, and BCC
as BHS, which may be confusing to beginner programmers.
• Another reason is that “branch higher” and “branch below” are
easier to understand

Division of unsigned numbers in ARM
• The older ARM family members do not have an instruction for division of
unsigned Numbers
• In ARMs with no divide instructions, we can use SUB instruction to
perform the division
AREA PROG_4_2, CODE, READONLY ;Division by subtractions

ENTRY
LDR R0,=2012 ;R0 = 2012 (numerator )
MOV R1,#10 ;R1 = 10 ( denominator )
MOV R2,#0 ;R2 = 0 ( quotient )
L1 CMP R0,R1 ;Compare R0 with R1 to see if less than 10
BLO FINISH ;if R0 < R1 jump to finish
SUB R0,R0,R1 ;R0 = R0 - R1 (division by subtraction)
ADD R2,R2,#1 ;R2 = R2 + 1 (quotient is incremented)
B L1 ;goto L1 (B is discussed in the next section)
FINISH B FINISH

TST (Test)
TST Rn,Op2 of ;Rn

Classification AND with Op2
embedded and flag bits are updated
system
• The TST instruction is used to test the contents of register to see if
any bit is set to HIGH.
• After the operands are ANDed together the flags are updated
• if result is zero, then Z flag is raised and one can use BEQ (branch
equal) to make decision.
MOV R0,#0x04 ;R0=00000100 in binary

LDR R1,=myport ;port address
OVER LDRB R2,[R1] ;load R2 from myport
TST R2,R0 ;is bit 2 HIGH?
BEQ OVER ;keep checking
TEQ (test equal)
TEQ Rn,Op2 of ;Rn

Classification EX-ORed with
embedded Op2 and flag bits are set
system
• The TEQ instruction is used to test to see if the contents of two
registers are equal.
• The source operands are Ex-ORed together the flag bits are set
according to the result. if result is 0, then Z flag is raised and one
can use BEQ (branch zero) to make decision.
TEMP EQU 100

MOV R0,#TEMP ;R0 = Temp
LDR R1,=myport ;port address
OVER LDRB R2,[R1] ;load R2 from myport
TEQ R2,R0 ;is it 100?
BNE OVER ;keep checking
Unconditional branch (jump) instruction
• The unconditional branch is a jump in which control is transferred

unconditionally to the target location.
• In the ARM there are two unconditional branches: B (branch) and BX
(branch and exchange).
B (Branch): B (branch) is an unconditional jump that can go to any memory

location in the 32M byte address space of the ARM.
CMP R1,R2
BHS L1
MOV R3,#2
B OVER
L1 MOV R3,#5
OVER
HERE B HERE ;stay here

HERE BAL HERE ;stay here
Calling Subroutine with BL
• Another control transfer instruction is the BL (branch and link)
instruction, which is used to call a subroutine.
• Classification
Subroutines are of embedded
often systemtasks that need to be
used to perform
performed frequently. This makes a program more structured in
addition to saving memory space.
• In the ARM there is only one instruction for call and that is BL
(branch and link).
• To use BL instruction for call, we must leave the R14 register
unused since that is where the ARM CPU stores the address of the
next instruction where it returns to resume executing the
program.

BL (Branch and Link) instruction and calling subroutine
• Classification of embedded
In the 32-bit instruction system
BL, 8 bits are used for the opcode and the
other 24 bits, k23–k0, are used for the address of the target
subroutine
• BL can be used to call subroutines located anywhere within the
32M address space of the ARM
• To make sure that the ARM knows where to come back to after
execution of the called subroutine, the ARM automatically saves in
the link register (LR), the R14, the address of the instruction
immediately below the BL.

• When a subroutine is called by the BL instruction, control is
transferred to that subroutine, and the processor saves the PC
Classification
(program counter) of embedded
in the R14 system
register and begins to fetch
instructions from the new location.
• After finishing execution of the subroutine, we must use “BX LR“
instruction to transfer control back to the caller.
• Every subroutine needs “BX LR” as the last instruction for return
address.

Write a program to toggle all the bits of address 0x40000000 by sending to it
the values 0x55 and 0xAA continuously. Put a time delay between each
issuing of data to address
Classification of location.
embedded system
Solution:
AREA EXAMPLE4_8, CODE, READONLY
ENTRY
RAM_ADDR EQU 0x40000000 ;change the address for your ARM
LDR R1,=RAM_ADDR ;R1 = RAM address
AGAIN MOV R0,#0x55 ;R0 = 0x55
STRB R0,[R1] ;send it to RAM
BL DELAY ;call delay (R14 = PC of next instruction)
MOV R0,#0xAA ;R0 = 0xAA
STRB R0,[R1] ;send it to RAM
BL DELAY ;call delay
B AGAIN ;keep doing it
;––––––—DELAY SUBROUTINE
DELAY LDR R3,=5 ;R3 =5, modify this value for different size delay
L1 SUBS R3,R3,#1 ;R3 = R3 - 1
Classification
BNE L1 of embedded system
BX LR ;return to caller
;––––––—end of DELAY subroutine
END ;notice the place for END directive
In above program, in place of “BX LR” for return, we could have used
“BX R14”, “MOV R15,R14”, or “MOV PC, LR” instructions. All of them
do the same thing; but it is recommended to use the “BX LR”
instruction.

ALP for Factorial
AREA factorial, CODE, Readonly ;program to find factorial
MOV R0,#5 ;int c =1
Classification
MOV R1,#1 of embedded
;int n=1 system
CMP R0,#0
BEQ STOP
MOV R1,R0
NEXT SUBS R0,#01
CMP R0,#01
BEQ STOP
MUL R2,R1,R0
MOV R1,R2
B NEXT
STOP NOP
L BL
END Department of EECE-19ECS431-EMBEDDED SYSTEMS 57
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EMBEDDED SYSTEMS

MODULE-III: ARM INSTRUCTION

Mr. M Naresh Kumar

Catagories of ARM Instructions

Affecting flags in ARM instructions

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Addition of unsigned numbers

The form of the ADD instruction is

The destination operand must be a register.

Memory-to-register or memory-to-memory arithmetic and logic

No increment instruction in ARM

Department of EECE-19ECS431-EMBEDDED SYSTEMS 9

CASE 1: Addition of individual word data

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Subtraction of unsigned numbers

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Show the steps involved for the following cases:

The flags would be set as follows: C = 1, and Z = 0. The programmer

• Analyze the following instructions:

Department of EECE-19ECS431-EMBEDDED SYSTEMS 14

SBC (subtract with borrow)

SBC Rd,Rn,Op2 ;Rd = Rn – Op2 – 1 + C

• This instruction is used for subtraction of multiword (data larger than

Department of EECE-19ECS431-EMBEDDED SYSTEMS 15

• Analyze the following program which subtracts 0x21F62562FA from 0x35F412963B:

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No decrement instruction in ARM

RSC (reverse subtract with carry)

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Classification of embedded system

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Classification of embedded system

Classification of embedded system

Division of unsigned numbers in ARM

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Classification of embedded system

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LDR R0,=0x88 ;R0=0x88

ASR (arithmetic shift right)

Department of EECE-19ECS431-EMBEDDED SYSTEMS 36

• There are two types of rotations. One is a simple rotation of the

ROR (rotate right)

Department of EECE-19ECS431-EMBEDDED SYSTEMS 38

Department of EECE-19ECS431-EMBEDDED SYSTEMS 40

Looping and Branch Instructions:

Using instruction BNE for looping

• The Rn (e.g. R2 or R3) is decremented; if it is not zero, it branches

• BNE instruction refers to the Z flag of the status register affected

Department of EECE-19ECS431-EMBEDDED SYSTEMS 42