FSFR1800US
FSFR1800US
FSFR1800US
May 2010
Related Resources
AN4151 — Half-bridge LLC Resonant Converter Design
TM
using FSFR-Series Fairchild Power Switch (FPS )
Ordering Information
Operating Maximum Output Power Maximum Output
Part Number Package Junction RDS(ON_MAX) without Heatsink Power with Heatsink
(1,2) (1,2)
Temperature (VIN=350~400V) (VIN=350~400V)
Block Diagram
Pin Definitions
Pin # Name Description
1 VDL This is the drain of the high-side MOSFET, typically connected to the input DC link voltage.
This pin is for discharging the external soft-start capacitor when any protections are
2 AR triggered. When the voltage of this pin drops to 0.2, all protections are reset and the
controller starts to operate again.
This pin programs the switching frequency. Typically, an opto-coupler is connected to control
3 RT
the switching frequency for the output voltage regulation.
This pin senses the current flowing through the low-side MOSFET. Typically, negative
4 CS
voltage is applied on this pin.
5 SG This pin is the control ground.
6 PG This pin is the power ground. This pin is connected to the source of the low-side MOSFET.
7 LVCC This pin is the supply voltage of the control IC.
8 NC No connection.
9 HVCC This is the supply voltage of the high-side gate-drive circuit IC.
10 VCTR This is the drain of the low-side MOSFET. Typically, a transformer is connected to this pin.
Thermal Impedance
TA=25°C unless otherwise specified.
Specifications
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
MOSFET Section
ID=200μA, TA=25°C 500
BVDSS Drain-to-Source Breakdown Voltage V
ID=200μA, TA=125°C 540
FSFR2100US/L VGS=10V, ID=6.0A 0.41 0.51
RDS(ON) On-State Resistance FSFR1800US/L VGS=10V, ID=3.0A 0.77 0.95 Ω
FSFR1700US/L VGS=10V, ID=2.0A 1.00 1.25
VGS=0V, IDiode=12.0A,
FSFR2100US/L 120
dIDiode/dt=100A/μs
Body Diode Reverse V =0V, IDiode=7.0A,
trr (6) FSFR1800US/L GS 160 ns
Recovery Time dIDiode/dt=100A/μs
VGS=0V, IDiode=6.0A,
FSFR1700US/L 160
dIDiode/dt=100A/μs
Supply Section
ILK Offset Supply Leakage Current H-VCC=VCTR=500V 50 μA
IQHVCC Quiescent HVCC Supply Current (HVCCUV+) - 0.1V 50 120 μA
IQLVCC Quiescent LVCC Supply Current (LVCCUV+) - 0.1V 100 200 μA
Specifications Unit
Symbol Parameter Test Conditions
Min Typ Max
Oscillator & Feedback Section
VRT V-I Converter Threshold Voltage 1.5 2.0 2.5 V
fOSC Output Oscillation Frequency RT=5.2KΩ 94 100 106 KHz
DC Output Duty Cycle 48 50 52 %
fSS=fOSC+40kHz,
fSS Internal Soft-Start Initial Frequency 140 KHz
RT=5.2KΩ
tSS Internal Soft-Start Time 2 3 4 ms
Protection Section
VCssH Beginning Voltage to Discharge CSS 0.9 1.0 1.1 V
VCssL Beginning Voltage to Charge CSS and Restart 0.16 0.20 0.24 V
VOVP LVCC Over-Voltage Protection L-VCC > 21V 21 23 25 V
VAOCP AOCP Threshold Voltage ΔV/Δt=-0.1V/µs -1.0 -0.9 -0.8 V
1.1 1.1
1.05 1.05
Normalized at 25OC
Normalized at 25OC
1 1
0.95 0.95
0.9 0.9
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temp (OC) Temp (OC)
Figure 4. Low-Side MOSFET Duty Cycle Figure 5. Switching Frequency vs. Temperature
vs. Temperature
1.1 1.1
1.05 1.05
Normalized at 25OC
Normalized at 25OC
1 1
0.95 0.95
0.9 0.9
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temp (OC) Temp (OC)
Figure 6. High-Side VCC (HVCC) Start vs. Temperature Figure 7. High-Side VCC (HVCC) Stop vs. Temperature
1.1 1.1
1.05 1.05
Normalized at 25OC
Normalized at 25OC
1 1
0.95 0.95
0.9 0.9
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Figure 8. Low-Side VCC (LVCC) Start vs. Temperature Figure 9. Low-Side VCC (LVCC) Stop vs. Temperature
1.1 1.1
1.05 1.05
Normalized at 25OC
Normalized at 25OC
1 1
0.95 0.95
0.9 0.9
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temp (OC) Temp (OC)
Figure 10. LVCC OVP Voltage vs. Temperature Figure 11. RT Voltage vs. Temperature
1.10 1.10
1.05 1.05
Normalized at 25Ԩ
Normalized at 25Ԩ
1.00 1.00
0.95 0.95
0.90 0.90
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temp(Ԩ) Temp(Ԩ)
Figure 12. VCssL vs. Temperature Figure 13. VCssH vs. Temperature
1.1
1.05
Normalized at 25OC
0.95
0.9
-50 -25 0 25 50 75 100
Temp (OC)
FSFR-US
Figure 16. Current Controlled Oscillator Figure 18. Frequency Control Circuit
3. Frequency Setting: Figure 17 shows the typical To prevent excessive inrush current and overshoot of
voltage gain curve of a resonant converter, where the output voltage during startup, increase the voltage gain
gain is inversely proportional to the switching frequency of the resonant converter progressively. Since the
in the ZVS region. The output voltage can be regulated voltage gain of the resonant converter is inversely
by modulating the switching frequency. Figure 18 shows proportional to the switching frequency, the soft-start is
the typical circuit configuration for the RT pin, where the implemented by sweeping down the switching frequency
ISS
opto-coupler transistor is connected to the RT pin to from an initial high frequency (f ) until the output
modulate the switching frequency. voltage is established. The soft-start circuit is made by
connecting R-C series network on the RT pin, as shown
The minimum switching frequency is determined as: in Figure 18. FSFR-US series also has an internal soft-
start for 3ms to reduce the current overshoot during the
5.2k Ω
f min = × 100(kHz) (1) initial cycles, which adds 40kHz to the initial frequency of
Rmin the external soft-start circuit, as shown in Figure 19. The
Assuming the saturation voltage of opto-coupler initial frequency of the soft-start is given as:
transistor is 0.2V, the maximum switching frequency is
determined as: 5.2k Ω 5.2k Ω
f ISS = ( + ) × 100 + 40 (kHz ) (3)
Rmin RSS
5.2 k Ω 4.68k Ω
f max =( + ) × 100(kHz ) (2)
Rmin Rmax
ICr
t stop tS /S
Np Ns
Ns
Control
IC
VCS
Ids
CS
SG PG
Rsense
VCS
Ids
Ids
VCS
Cr
Control
IC
VCS
Np Ns
CS
SG PG
Rsense Ns
Ids
26.20
25.80 3.4 0
3.0 0
23.10
22.90 (1.7 0) (1.2 0)
(R0.5 0)
5.35
5.15
10 .70
10 .30 (1 1.0 0)
1 4.50
(0 .7 0) 1 3.50
(0.5 0) 1 8.50
R0 .55 1 7.50
R0 .55
8.00
7.00 M AX 1.30 (7 .0 0)
1.3 0
1.1 0
(5 .0 8)
0.60
1 .27 MAX 0.80 0.40
0.7 0
0.5 0 3.4 8
2 .88
1 5.24
(R0.5 0)
3.4 0
3.0 0
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.