OR3C80 LatticeSemiconductor

Data Sheet
March 2002
ORCA® Series 3C and 3T

Field-Programmable Gate Arrays
Features ble logic cell (PLC), with over 50% speed improvement
typical.
■ High-performance, cost-effective, 0.35 µm (OR3C) and ■ Abundant hierarchical routing resources based on rout-
0.3 µm (OR3T) 4-level metal technology, (4- or 5-input ing two data nibbles and two control lines per set provide
look-up table delay of 1.1 ns with -7 speed grade in for faster place and route implementations and less rout-
0.3 µm). ing delay.
■ Same basic architecture as lower-voltage, advanced ■ TTL or CMOS input levels programmable per pin for the
process technology Series 3 architectures. (See ORCA OR3Cxx (5.0 V) devices.
Series 3L FPGA documentation.) ■ Individually programmable drive capability:
■ Up to 186,000 usable gates. 12 mA sink/6 mA source or 6 mA sink/3 mA source.
■ Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to ■ Built-in boundary scan (IEEE † 1149.1 JTAG) and
allow interconnection to both 3.3 V and 5 V devices, TS_ALL testability function to 3-state all I/O pins.
selectable on a per-pin basis.) ■ Enhanced system clock routing for low skew, high-speed
■ Pin selectable I/O clamping diodes provide 5 V or 3.3 V clocks originating on-chip or at any I/O.
PCI compliance and 5 V tolerance on OR3Txxx devices. ■ Up to four ExpressCLK inputs allow extremely fast clock-
■ Twin-quad programmable function unit (PFU) architec- ing of signals on- and off-chip plus access to internal
ture with eight 16-bit look-up tables (LUTs) per PFU, general clock routing.
organized in two nibbles for use in nibble- or byte-wide ■ StopCLK feature to glitchlessly stop/start ExpressCLKs
functions. Allows for mixed arithmetic and logic functions independently by user command.
in a single PFU.
■ Programmable I/O (PIO) has:
■ Nine user registers per PFU, one following each LUT, — Fast-capture input latch and input flip-flop (FF) latch
plus one extra. All have programmable clock enable and for reduced input setup time and zero hold time.
local set/reset, plus a global set/reset that can be dis- — Capability to (de)multiplex I/O signals.
abled per PFU. — Fast access to SLIC for decodes and PAL-like
■ Flexible input structure (FINS) of the PFUs provides a functions.
routability enhancement for LUTs with shared inputs and — Output FF and two-signal function generator to
the logic flexibility of LUTs with independent inputs. reduce CLK to output propagation delay.
— Fast open-drain dive capability
■ Fast-carry logic and routing to adjacent PFUs for nibble-, — Capability to register 3-state enable signal.
byte-wide, or longer arithmetic functions, with the option
to register the PFU carry-out. ■ Baseline FPGA family used in Series 3+ FPSCs (field
programmable system chips) which combine FPGA logic
■ Softwired LUTs (SWL) allow fast cascading of up to and standard cell logic on one device.
three levels of LUT logic in a single PFU for up to 40%
speed improvement.
■ Supplemental logic and interconnect cell (SLIC) pro- * PAL is a trademark of Advanced Micro Devices, Inc.
vides 3-statable buffers, up to 10-bit decoder, and PAL*- † IEEE is a registered trademark of The Institute of Electrical and
like AND-OR with optional INVERT in each programma- Electronics Engineers, Inc.
Table 1. ORCA Series 3 (3C and 3T) FPGAs
System Process
Device LUTs Registers Max User RAM User I/Os Array Size
Gates‡ Technology
OR3T20 36K 1152 1872 18K 196 12 x 12 0.3 µm/4 LM
OR3T30 48K 1568 2436 25K 228 14 x 14 0.3 µm/4 LM
OR3T55 80K 2592 3780 42K 292 18 x 18 0.3 µm/4 LM
OR3C/3T80 116K 3872 5412 62K 356 22 x 22 0.3 µm/4 LM
OR3T125 186K 6272 8400 100K 452 28 x 28 0.3 µm/4 LM
‡ The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per
PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch,
output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing
a 32 x 4 RAM (or 512 gates) per PFU.
Data Sheet
ispORCA Series 3C and 3T FPGAs March 2002
Table of Contents
Contents Page Contents Page
Features ......................................................................1 PCM Cautions ........................................................ 84

System-Level Features................................................6 FPGA States of Operation........................................ 85
Description...................................................................7 Initialization ............................................................. 85
FPGA Overview ........................................................7 Configuration .......................................................... 86
PLC Logic ..................................................................7 Start-Up .................................................................. 87
PIC Logic ...................................................................8 Reconfiguration ...................................................... 88
System Features .......................................................8 Partial Reconfiguration ........................................... 88
Routing ......................................................................8 Other Configuration Options ................................... 88
Configuration .............................................................8 Configuration Data Format ...................................... 89
ORCA Foundry Development System ......................9 Using ORCA Foundry to Generate
Architecture .................................................................9 Configuration RAM Data ....................................... 89
Programmable Logic Cells ........................................11 Configuration Data Frame ...................................... 89
Programmable Function Unit ..................................11 Bit Stream Error Checking ...................................... 91
Look-Up Table Operating Modes ............................13 FPGA Configuration Modes...................................... 92
Supplemental Logic and Interconnect Cell (SLIC) ..21 Master Parallel Mode ............................................. 92
PLC Latches/Flip-Flops ...........................................25 Master Serial Mode ................................................ 93
PLC Routing Resources ..........................................27 Asynchronous Peripheral Mode ............................. 94
PLC Architectural Description .................................34 Microprocessor Interface (MPI) Mode .................... 94
Programmable Input/Output Cells .............................36 Slave Serial Mode .................................................. 97
5 V Tolerant I/O .......................................................37 Slave Parallel Mode ............................................... 97
PCI Compliant I/O ...................................................37 Daisy-Chaining ....................................................... 98
Inputs ......................................................................38 Daisy-Chaining with Boundary Scan ...................... 99
Outputs ....................................................................41 Absolute Maximum Ratings.................................... 100
PIC Routing Resources ...........................................44 Recommended Operating Conditions .................. 100
PIC Architectural Description ..................................45 Electrical Characteristics ........................................ 101
High-Level Routing Resources..................................47 Timing Characteristics ............................................ 103
Interquad Routing ....................................................47 Description ........................................................... 103
Programmable Corner Cell Routing ........................48 PFU Timing ......................................................... 104
PIC Interquad (MID) Routing ...................................49 PLC Timing ........................................................... 111
Clock Distribution Network ........................................50 SLIC Timing .......................................................... 111
PFU Clock Sources .................................................50 PIO Timing ........................................................... 112
Clock Distribution in the PLC Array .........................51 Special Function Blocks Timing ........................... 115
Clock Sources to the PLC Array .............................52 Clock Timing ......................................................... 123
Clocks in the PICs ...................................................52 Configuration Timing ............................................ 133
ExpressCLK Inputs .................................................53 Readback Timing ................................................. 142
Selecting Clock Input Pins ......................................53 Input/Output Buffer Measurement Conditions ........ 143
Special Function Blocks ............................................54 Output Buffer Characteristics ................................. 144
Single Function Blocks ............................................54 OR3Cxx ................................................................ 144
Boundary Scan ........................................................57 OR3Txxx .............................................................. 145
Microprocessor Interface (MPI) .................................64 Estimating Power Dissipation ................................. 146
PowerPC System ....................................................65 OR3Cxx ................................................................ 146
i960 System ............................................................66 OR3Txxx (Preliminary Information) ...................... 147
MPI Interface to FPGA ............................................67 Pin Information ....................................................... 149
MPI Setup and Control ............................................68 Pin Descriptions ................................................... 149
Programmable Clock Manager (PCM) ......................72 Package Compatibility .......................................... 153
PCM Registers ........................................................73 Compatibility with OR2C/TxxA Series .................. 154
Delay-Locked Loop (DLL) Mode .............................75 Package Thermal Characteristics........................... 194
Phase-Locked Loop (PLL) Mode ............................76 ΘJA ....................................................................... 194
PCM/FPGA Internal Interface .................................79 ψJC ...................................................................... 194
PCM Operation .......................................................79 ΘJC ...................................................................... 194
PCM Detailed Programming ...................................80 ΘJB ...................................................................... 194
PCM Applications ....................................................83 FPGA Maximum Junction Temperature ............... 195
2 Lattice Semiconductor
Data Sheet
March 2002 ORCA Series 3C and 3T FPGAs
Table of Contents
Package Coplanarity ...............................................196 Table 32. Configuration Frame Format and
Package Parasitics ..................................................196 Contents .................................................................. 90
Package Outline Diagrams......................................197 Table 33. Configuration Frame Size ......................... 91
Terms and Definitions ...........................................197 Table 34. Configuration Modes ................................ 92
208-Pin SQFP .......................................................198 Table 35. Absolute Maximum Ratings ....................100
208-Pin SQFP2 .....................................................199 Table 36. Recommended Operating Conditions ....100
240-Pin SQFP .......................................................200 Table 37. Electrical Characteristics ........................101
240-Pin SQFP2 .....................................................201 Table 38. Derating for Commercial Devices
256-Pin PBGA .......................................................202 (OR3Cxx) ..............................................................103
352-Pin PBGA .......................................................203 Table 39. Derating for Industrial Devices (OR3Cxx) ....
432-Pin EBGA .......................................................204 103
600-Pin EBGA .......................................................205 Table 40. Derating for Commercial/Industrial
Ordering Information................................................206 Devices (OR3Txxx) ...............................................103
Index........................................................................207 Table 41. Combinatorial PFU Timing
Tables Characteristics .......................................................104
Table 42. Sequential PFU Timing Characteristics ..106
Table 1. ORCA Series 3 (3C and 3T) FPGAs ............ 2 Table 43. Ripple Mode PFU Timing
Table 2. ORCA Series 3 System Performance .......... 6 Characteristics .......................................................107
Table 3. Look-Up Table Operating Modes ............... 13 Table 44. Synchronous Memory Write
Table 4. Control Input Functionality .......................... 14 Characteristics .......................................................109
Table 5. Ripple Mode Equality Comparator Table 45. Synchronous Memory Read
Functions and Outputs ............................................ 18 Characteristics .......................................................110
Table 6. SLIC Modes ................................................ 21 Table 46. PFU Output MUX and Direct Routing
Table 7. Configuration RAM Controlled Timing Characteristics ...........................................111
Latch/Flip-Flop Operation ........................................ 25 Table 47. Supplemental Logic and Interconnect
Table 8. Inter-PLC Routing Resources ..................... 31 Cell (SLIC) Timing Characteristics ........................111
Table 9. PIO Options ................................................ 37 Table 48. Programmable I/O (PIO) Timing
Table 10. PIO Logic Options .................................... 43 Characteristics .......................................................112
Table 11. PIO Register Control Signals .................... 43 Table 49. Microprocessor Interface (MPI) Timing
Table 12. Readback Options .................................... 54 Characteristics .......................................................115
Table 13. Boundary-Scan Instructions ..................... 58 Table 50. Programmable Clock Manager (PCM)
Table 14. Boundary-Scan ID Code ........................... 59 Timing Characteristics (Preliminary Information) ..121
Table 15. TAP Controller Input/Outputs ................... 61 Table 51. Boundary-Scan Timing Characteristics ..122
Table 16. PowerPC/MPI Configuration ..................... 65 Table 52. ExpressCLK (ECLK) and Fast Clock
Table 17. i960/MPI Configuration ............................. 66 (FCLK) Timing Characteristics ..............................123
Table 18. MPI Internal Interface Signals .................. 67 Table 53. General-Purpose Clock Timing
Table 19. MPI Setup and Control Registers ............. 68 Characteristics (Internally Generated Clock) .........124
Table 20. MPI Setup and Control Registers Table 54. OR3Cxx ExpressCLK to Output Delay
Description ............................................................... 68 (Pin-to-Pin) ............................................................125
Table 21. MPI Control Register 2 ............................. 69 Table 55. OR3Cxx Fast Clock (FCLK) to Output
Table 22. Status Register ......................................... 70 Delay (Pin-to-Pin) ..................................................126
Table 23. Device ID Code ........................................ 71 Table 56. OR3Cxx General System Clock (SCLK)
Table 24. Series 3 Family and Device ID Values ..... 71 to Output Delay (Pin-to-Pin) ..................................127
Table 25. ORCA Series 3 Device ID Descriptions .... 71 Table 57. OR3C/Txxx Input to ExpressCLK (ECLK)
Table 26. PCM Registers ......................................... 73 Fast-Capture Setup/Hold Time (Pin-to-Pin) ..........128
Table 27. DLL Mode Delay/1x Duty Cycle Table 58. OR3C/Txxx Input to Fast Clock
Programming Values ............................................... 75 Setup/Hold Time (Pin-to-Pin) ................................130
Table 28. DLL Mode Delay/2x Duty Cycle Table 59. OR3C/Txxx Input to General System
Programming Values ............................................... 76 Clock (SCLK) Setup/Hold Time (Pin-to-Pin) ..........132
Table 29. PCM Oscillator Frequency Range 3Txxx . 78 Table 60. General Configuration Mode Timing
Table 30. PCM Oscillator Frequency Range 3Cxx ... 78 Characteristics .......................................................133
Table 31. PCM Control Registers ............................. 80
Lattice Semiconductor 3
Data Sheet
Table of Contents
Table 61. Master Serial Configuration Mode Timing Figure 13. Buffer-Buffer-Decoder Mode ................... 23
Characteristics ...................................................... 136 Figure 14. Buffer-Decoder-Buffer Mode ................... 23
Table 62. Master Parallel Configuration Mode Timing Figure 15. Buffer-Decoder-Decoder Mode ............... 24
Characteristics ...................................................... 137 Figure 16. Decoder Mode ......................................... 24
Table 63. Asynchronous Peripheral Configuration Mode Figure 17. Latch/FF Set/Reset Configurations ......... 26
Timing Characteristics ........................................... 138 Figure 18. Configurable Interconnect Point .............. 27
Table 64. Slave Serial Configuration Mode Timing Figure 19. Single PLC View of Inter-PLC Route
Characteristics ...................................................... 139 Segments ................................................................ 28
Table 65. Slave Parallel Configuration Mode Figure 20. Multiple PLC View of Inter-PLC Routing . 32
Timing Characteristics ........................................... 140 Figure 21. PLC Architecture ..................................... 35
Table 66. Readback Timing Characteristics ........... 142 Figure 22. OR3C/Txxx Programmable Input/Output
Table 67. Pin Descriptions ...................................... 149 (PIO) Image from ORCA Foundry ........................... 36
Table 68. ORCA I/Os Summary ............................. 153 Figure 23. Fast-Capture Latch and Timing ............... 39
Table 69. Series 3 ExpressCLK Pins ..................... 154 Figure 24. PIO Input Demultiplexing ......................... 40
Table 70. OR3T20, OR3T30, OR3T55, Figure 25. Output Multiplexing (OUT1OUT2 Mode) . 42
OR3C/T80, and OR3T125 208-Pin Figure 26. Output Multiplexing
SQFP/SQFP2 Pinout ............................................ 155 (OUT2OUTREG Mode) ........................................... 42
Table 71. OR3T20, OR3T30, OR3T55, Figure 27. PIC Architecture ...................................... 46
OR3C/T80, and OR3T125 240-Pin Figure 28. Interquad Routing .................................... 47
SQFP/SQFP2 Pinout ............................................ 161 Figure 29. hIQ Block Detail ....................................... 48
Table 72. OR3T20, OR3T30, and OR3T55 Figure 30. Top (TMID) Routing ................................. 49
256-Pin PBGA Pinout ............................................ 168 Figure 31. PFU Clock Sources ................................. 50
Table 73. OR3T20, OR3T30, OR3T55, Figure 32. ORCA Series 3 System Clock
OR3C/T80, and OR3T125 352-Pin PBGA Pinout . 172 Distribution Overview .............................................. 51
Table 74. OR3C/T80 and OR3T125 432-Pin Figure 33. PIC System Clock Spine Generation ...... 52
EBGA Pinout ......................................................... 182 Figure 34. ExpressCLK and Fast Clock Distribution 53
Table 75. OR3T125 600-Pin EBGA Pinout ............ 187 Figure 35. Top CLKCNTRL Function Block .............. 56
Table 76. Plastic Package Thermal Figure 36. Printed-Circuit Board with Boundary-
Characteristics for the ORCA Series ..................... 195 Scan Circuitry .......................................................... 57
Table 77. Package Coplanarity .............................. 196 Figure 37. Boundary-Scan Interface ......................... 58
Table 78. Package Parasitics ................................. 196 Figure 38. ORCA Series Boundary-Scan Circuitry
Table 79. Voltage Options ...................................... 206 Functional Diagram ................................................. 60
Table 80. Temperature Options ............................. 206 Figure 39. TAP Controller State Transition Diagram 61
Table 81. Package Options .................................... 206 Figure 40. Boundary-Scan Cell ................................ 62
Table 82. ORCA Series 3 Package Matrix ............. 206 Figure 41. Instruction Register Scan Timing
Table 83. Speed Grade Options ............................. 206 Diagram ................................................................... 63
Figure 42. MPI Block Diagram .................................. 64
Figures
Figure 43. PowerPC/MPI .......................................... 65
Figure 1. OR3T55 Array ........................................... 10 Figure 44. i960/MPI .................................................. 66
Figure 2. PFU Ports .................................................. 11 Figure 45. PCM Block Diagram ................................ 72
Figure 3. Simplified PFU Diagram ............................ 12 Figure 46. PCM Functional Block Diagram .............. 74
Figure 4. Simplified F4 and F5 Logic Modes ............ 14 Figure 47. ExpressCLK Delay Minimization Using
Figure 5. Softwired LUT Topology Examples ........... 15 the PCM .................................................................. 76
Figure 6. Ripple Mode .............................................. 16 Figure 48. Clock Phase Adjustment Using the PCM 83
Figure 7. Counter Submode ..................................... 17 Figure 49. FPGA States of Operation ....................... 85
Figure 8. Multiplier Submode .................................... 18 Figure 50. Initialization/Configuration/Start-Up
Figure 9. Memory Mode ........................................... 19 Waveforms .............................................................. 86
Figure 10. Memory Mode Expansion Example— Figure 51. Start-Up Waveforms ................................ 88
128 x 8 RAM ........................................................... 20 Figure 52. Serial Configuration Data Format—
Figure 11. SLIC All Modes Diagram ......................... 22 Autoincrement Mode ............................................... 90
Figure 12. Buffer Mode ............................................. 22
Data Sheet
Table of Contents
Figure 53. Serial Configuration Data Format— Figure 79. Input to ExpressCLK Setup/Hold Time ..129
Explicit Mode ........................................................... 90 Figure 80. Input to Fast Clock Setup/Hold Time .....131
Figure 54. Master Parallel Configuration Schematic 92 Figure 81. Input to System Clock Setup/Hold Time 132
Figure 55. Master Serial Configuration Schematic ... 93 Figure 82. General Configuration Mode Timing
Figure 56. Asynchronous Peripheral Configuration .. 94 Diagram .................................................................135
Figure 57. PowerPC/MPI Configuration Schematic .. 95 Figure 83. Master Serial Configuration Mode
Figure 58. i960/MPI Configuration Schematic .......... 95 Timing Diagram .....................................................136
Figure 59. Configuration Through MPI ..................... 95 Figure 84. Master Parallel Configuration Mode
Figure 60. Readback Through MPI .......................... 96 Timing Diagram .....................................................137
Figure 61. Slave Serial Configuration Schematic ..... 97 Figure 85. Asynchronous Peripheral Configuration
Figure 62. Slave Parallel Configuration Schematic .. 97 Mode Timing Diagram ...........................................138
Figure 63. Daisy-Chain Configuration Schematic ..... 98 Figure 86. Slave Serial Configuration Mode
Figure 64. Combinatorial PFU Timing .................... 105 Timing Diagram .....................................................139
Figure 65. Synchronous Memory Write Figure 87. Slave Parallel Configuration Mode
Characteristics ...................................................... 109 Timing Diagram .....................................................140
Figure 66. Synchronous Memory Read Cycle ........ 110 Figure 88. Readback Timing Diagram ....................142
Figure 67. MPI PowerPC User Space Read Timing ..... Figure 89. ac Test Loads ........................................143
117 Figure 90. Output Buffer Delays .............................143
Figure 68. MPI PowerPC User Space Write Timing ..... Figure 91. Input Buffer Delays ................................143
117 Figure 92. Sinklim (TJ = 25 °C, VDD = 5.0 V) ..........144
Figure 69. MPI PowerPC Internal Read Timing ..... 118 Figure 93. Slewlim (TJ = 25 °C, VDD = 5.0 V) .........144
Figure 70. MPI PowerPC Internal Write Timing ...... 118 Figure 94. Fast (TJ °C, VDD = 5.0 V) ......................144
Figure 71. MPI i960 User Space Read Timing ....... 119 Figure 95. Sinklim (TJ = 125 °C, VDD = 4.5 V) ........144
Figure 72. MPI i960 User Space Write Timing ....... 119 Figure 96. Slewlim (TJ = 125 °C, VDD = 4.5 V) .......144
Figure 73. MPI i960 Internal Read Timing .............. 120 Figure 97. Fast (TJ = 125 °C, VDD = 4.5 V) ............144
Figure 74. MPI i960 Internal Write Timing .............. 120 Figure 98. Sinklim (TJ = 25 °C, VDD = 3.3 V) ..........145
Figure 75. Boundary-Scan Timing Diagram ........... 122 Figure 99. Slewlim (TJ = 25 °C, VDD = 3.3 V) .........145
Figure 76. ExpressCLK to Output Delay ................ 125 Figure 100. Fast (TJ = 25 °C, VDD = 3.3 V) ............145
Figure 77. Fast Clock to Output Delay ................... 126 Figure 101. Sinklim (TJ = 125 °C, VDD = 3.0 V) ......145
Figure 78. System Clock to Output Delay .............. 127 Figure 102. Slewlim (TJ = 125 °C, VDD = 3.0 V) .....145
Data Sheet
System-Level Features phase and duty cycle for input clock rates from
5 MHz to 120 MHz. The PCM may be combined with
System-level features reduce glue logic requirements FPGA logic to create complex functions, such as dig-
and make a system on a chip possible. These features ital phase-locked loops (DPLL), frequency counters,
in the ORCA Series 3 include: and frequency synthesizers or clock doublers. Two
PCMs are provided per device.
■ Full PCI local bus compliance.
■ True, internal, 3-state, bidirectional buses with simple
■ Dual-use microprocessor interface (MPI) can be control provided by the SLIC.
used for configuration, readback, device control, and
device status, as well as for a general-purpose inter- ■ 32 x 4 RAM per PFU, configurable as single- or dual-
face to the FPGA. Glueless interface to i960 * and port at >176 MHz. Create large, fast RAM/ROM
PowerPC† processors with user-configurable blocks (128 x 8 in only eight PFUs) using the SLIC
address space provided. decoders as bank drivers.
■ Parallel readback of configuration data capability with

the built-in microprocessor interface. * i960 is a registered trademark of Intel Corporation.
† PowerPC is a registered trademark of International Business
■ Programmable clock manager (PCM) adjusts clock Machines Corporation.
Table 2. ORCA Series 3 System Performance

Speed
Parameter # PFUs Unit
-4 -5 -6 -7
16-bit Loadable Up/Down Counter 2 78 102 131 168 MHz
16-bit Accumulator 2 78 102 131 168 MHz
8 x 8 Parallel Multiplier:
Multiplier Mode, Unpipelined1 11.5 19 25 30 38 MHz
ROM Mode, Unpipelined2 8 51 66 80 102 MHz
Multiplier Mode, Pipelined3 15 76 104 127 166 MHz
32 x 16 RAM (synchronous):
Single-port, 3-state Bus4 4 97 127 151 192 MHz
Dual-port5 4 127 166 203 253 MHz
128 x 8 RAM (synchronous):
Single-port, 3-state Bus4 8 88 116 139 176 MHz
Dual-port5 8 88 116 139 176 MHz
8-bit Address Decode (internal):
Using Softwired LUTs 0.25 4.87 3.66 2.58 2.03 ns
Using SLICs6 0 2.35 1.82 1.23 0.99 ns
32-bit Address Decode (internal):
Using Softwired LUTs 2 16.06 12.07 9.01 7.03 ns
Using SLICs7 0 6.91 5.41 4.21 3.37 ns
36-bit Parity Check (internal) 2 16.06 12.07 9.01 7.03 ns
1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 PFUs contain only pipelining registers).
4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 x 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
Data Sheet
Description PLC Logic

Each PFU within a PLC contains eight 4-input (16-bit)
FPGA Overview
look-up tables (LUTs), eight latches/flip-flops (FFs),
The ORCA Series 3 FPGAs are a new generation of and one additional flip-flop that may be used indepen-
SRAM-based FPGAs built on the successful OR2C/ dently or with arithmetic functions.
TxxA FPGA Series, with enhancements and innova- The PFU is organized in a twin-quad fashion: two sets
tions geared toward today’s high-speed designs and of four LUTs and FFs that can be controlled indepen-
tomorrow’s systems on a single chip. Designed from dently. LUTs may also be combined for use in arith-
the start to be synthesis friendly and to reduce place metic functions using fast-carry chain logic in either
and route times while maintaining the complete 4-bit or 8-bit modes. The carry-out of either mode may
routability of the ORCA 2C/2T devices, Series 3 more be registered in the ninth FF for pipelining. Each PFU
than doubles the logic available in each logic block and may also be configured as a synchronous 32 x 4 sin-
incorporates system-level features that can further gle- or dual-port RAM or ROM. The FFs (or latches)
reduce logic requirements and increase system speed. may obtain input from LUT outputs or directly from
ORCA Series 3 devices contain many new patented invertible PFU inputs, or they can be tied high or tied
enhancements and are offered in a variety of pack- low. The FFs also have programmable clock polarity,
ages, speed grades, and temperature ranges. clock enables, and local set/reset.
The ORCA Series 3 FPGAs consist of three basic ele- The SLIC is connected to PLC routing resources and to
ments: programmable logic cells (PLCs), programma- the outputs of the PFU. It contains 3-state, bidirectional
ble input/output cells (PICs), and system-level features. buffers and logic to perform up to a 10-bit AND function
An array of PLCs is surrounded by PICs. Each PLC for decoding, or an AND-OR with optional INVERT
contains a programmable function unit (PFU), a sup- (AOI) to perform PAL-like functions. The 3-state drivers
plemental logic and interconnect cell (SLIC), local rout- in the SLIC and their direct connections to the PFU out-
ing resources, and configuration RAM. Most of the puts make fast, true 3-state buses possible within the
FPGA logic is performed in the PFU, but decoders, FPGA, reducing required routing and allowing for real-
PAL-like functions, and 3-state buffering can be per- world system performance.
formed in the SLIC. The PICs provide device inputs and
outputs and can be used to register signals and to per-
form input demultiplexing, output multiplexing, and
other functions on two output signals. Some of the sys-
tem-level functions include the new microprocessor
interface (MPI) and the programmable clock manager
(PCM).
Data Sheet
ORCA Series 3C and 3T FPGAs March 2002
Description (continued) innovative programmable clock manager. These func-

tional blocks allow for easy glueless system interfacing
PIC Logic and the capability to adjust to varying conditions in
today’s high-speed systems.
Series 3 PIC addresses the demand for ever-increas-
ing system clock speeds. Each PIC contains four pro-
grammable inputs/outputs (PIOs) and routing Routing
resources. On the input side, each PIO contains a fast-
The abundant routing resources of the ORCA Series 3
capture latch that is clocked by an ExpressCLK. This
FPGAs are organized to route signals individually or as
latch is followed by a latch/FF that is clocked by a sys-
buses with related control signals. Clocks are routed on
tem clock from the internal general clock routing. The
a low-skew, high-speed distribution network and may
combination provides for very low setup requirements
and zero hold times for signals coming on-chip. It may be sourced from PLC logic, externally from any I/O
also be used to demultiplex an input signal, such as a pad, or from the very fast ExpressCLK pins. Express-
multiplexed address/data signal, and register the sig- CLKs may be glitchlessly and independently enabled
nals without explicitly building a demultiplexer. Two and disabled with a programmable control signal using
input signals are available to the PLC array from each the new StopCLK feature. The improved PIC routing
PIO, and the ORCA 2C/2T capability to use any input resources are now similar to the patented intra-PLC
pin as a clock or other global input is maintained. routing resources and provide great flexibility in moving
signals to and from the PIOs. This flexibility translates
On the output side of each PIO, two outputs from the into an improved capability to route designs at the
PLC array can be routed to each output flip-flop, and required speeds when the I/O signals have been
logic can be associated with each I/O pad. The output locked to specific pins.
logic associated with each pad allows for multiplexing
of output signals and other functions of two output sig-
nals. Configuration
The output FF in combination with output signal multi- The FPGA’s functionality is determined by internal
plexing, is particularly useful for registering address configuration RAM. The FPGA’s internal initialization/
signals to be multiplexed with data, allowing a full clock configuration circuitry loads the configuration data at
cycle for the data to propagate to the output. The I/O powerup or under system control. The RAM is loaded
buffer associated with each pad is very similar to the by using one of several configuration modes. The con-
ORCA 2C/2T Series buffer with a new, fast, open-drain figuration data resides externally in an EEPROM or any
option for ease of use on system buses. other storage media. Serial EEPROMs provide a sim-
ple, low pin count method for configuring FPGAs. A
new, easy method for configuring the devices is
System Features through the microprocessor interface.
Series 3 also provides system-level functionality by
means of its dual-use microprocessor interface and its
Data Sheet
Description (continued) The OR3T55 array in Figure 1 has PLCs arranged in

an array of 18 rows and 18 columns. The location of a
ORCA Foundry Development System PLC is indicated by its row and column so that a PLC in
the second row and the third column is R2C3. PICs are
The ORCA Foundry Development System is used to located on all four sides of the FPGA between the
process a design from a netlist to a configured FPGA. PLCs and the device edge. PICs are indicated using
This system is used to map a design onto the ORCA PT and PB to designate PICs on the top and bottom
architecture and then place and route it using ORCA sides of the array, respectively, and PL and PR to des-
Foundry’s timing-driven tools. The development system ignate PICs along the left and right sides of the array,
also includes interfaces to, and libraries for, other popu- respectively. The position of a PIC on an edge of the
lar CAE tools for design entry, synthesis, simulation, array is indicated by a number, counting from left to
and timing analysis. right for PT and PB and top to bottom for PL and PR
PICs.
The ORCA Foundry Development System interfaces to
front-end design entry tools and provides the tools to Each PIC contains routing resources and four program-
produce a configured FPGA. In the design flow, the mable I/Os (PIOs). Each PIO contains the necessary
user defines the functionality of the FPGA at two points I/O buffers to interface to bond pads. PIOs in Series 3
in the design flow: at design entry and at the bit stream FPGAs also contain input and output FFs, fast open-
generation stage. drain capability on output buffers, special output logic
functions, and signal multiplexing/demultiplexing capa-
Following design entry, the development system’s map, bilities.
place, and route tools translate the netlist into a routed
FPGA. A static timing analysis tool is provided to deter- PLCs comprise a programmable function unit (PFU), a
mine device speed and a back-annotated netlist can be supplemental logic and interconnect cell (SLIC), and
created to allow simulation. Timing and simulation out- routing resources. The PFU is the main logic element
put files from ORCA Foundry are also compatible with of the PLC, containing elements for both combinatorial
many third-party analysis tools. Its bit stream generator and sequential logic. Combinatorial logic is done in
is then used to generate the configuration data which is look-up tables (LUTs) located in the PFU. The PFU can
loaded into the FPGA’s internal configuration RAM. be used in different modes to meet different logic
When using the bit stream generator, the user selects requirements. The LUT’s twin-quad architecture pro-
options that affect the functionality of the FPGA. Com- vides a configurable medium-/large-grain architecture
bined with the front-end tools, ORCA Foundry pro- that can be used to implement from one to eight inde-
duces configuration data that implements the various pendent combinatorial logic functions or a large num-
logic and routing options discussed in this data sheet. ber of complex logic functions using multiple LUTs. The
flexibility of the LUT to handle wide input functions, as
well as multiple smaller input functions, maximizes the
Architecture gate count per PFU while increasing system speed.
The LUTs can be programmed to operate in one of
The ORCA Series 3 FPGA comprises three basic ele- three modes: combinatorial, ripple, or memory. In com-
ments: PLCs, PICs, and system-level functions. Figure binatorial mode, the LUTs can realize any 4- or 5-input
1 shows an array of programmable logic cells (PLCs) logic function and many multilevel logic functions using
surrounded by programmable input/output cells (PICs). ORCA’s softwired LUT (SWL) connections. In ripple
Also shown are the interquad routing blocks (hIQ, vIQ) mode, the high-speed carry logic is used for arithmetic
present in Series 3. System-level functions (located in functions, comparator functions, or enhanced data path
the corners of the array) and the routing resources and functions. In memory mode, the LUTs can be used as a
configuration RAM are not shown in Figure 1. 32 x 4 synchronous read/write or read-only memory, in
either single- or dual-port mode.
Data Sheet
Architecture (continued)
VI
PT1 PT2 PT3 PT4 PT5 PT6 PT7 PT8 PT9 TMID PT10 PT11 PT12 PT13 PT14 PT15 PT16 PT17 PT18
PL1
PR1
PL2 R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 R1C10 R1C11 R1C12 R1C13 R1C14 R1C15 R1C16 R1C17 R1C18
PR2
R2C1 R2C2 R2C3 R2C4 R2C5 R2C6 R2C7 R2C8 R2C9 R2C10 R2C11 R2C12 R2C13 R2C14 R2C15 R2C16 R2C17 R2C18
vIQ
PR3
PL3
PR4
PL4
PL5
PR5
PR6
PL6
PL7
PR7
PL8
PR8
PR9
PL9
PR10
LMID
hIQ
RMID
PL10
PR11
PL11
PR12
PL12
PR13
PL13
PR14
PL14
PR15
PL15
PR16
PL16
PR17
PL17
PR18
PL18
PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 BMID PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18
5-4489(F)
Figure 1. OR3T55 Array
Data Sheet
Programmable Logic Cells

F5D
The programmable logic cell (PLC) consists of a pro- K7_0
grammable function unit (PFU), a supplemental logic K7_1
K7_2
and interconnect cell (SLIC), and routing resources. All K7_3
PLCs in the array are functionally identical with only
K6_0
minor differences in routing connectivity for improved K6_1
routability. The PFU, which contains eight 4-input LUTs, K6_2
K6_3
eight latches/FFs, and one FF for logic implementation,
is discussed in the next section, followed by discus- K5_0
K5_1
sions of the SLIC and PLC routing resources. K5_2
K5_3
K4_0
Programmable Function Unit K4_1
K4_2
K4_3 Q7
The PFUs are used for logic. Each PFU has 50 external Q6
inputs and 18 outputs and can operate in several F5C Q5
Q4
modes. The functionality of the inputs and outputs DIN7 Q3
depends on the operating mode. DIN6 Q2
DIN5 Q1
DIN4 Q0
The PFU uses 36 data input lines for the LUTs, eight DIN3 PROGRAMMABLE
data input lines for the latches/FFs, five control inputs DIN2 FUNCTION UNIT
DIN1 (PFU) COUT
(ASWE, CLK, CE, LSR, SEL), and a carry input (CIN) DIN0 REGCOUT
for fast arithmetic functions and general-purpose data
CIN
input for the ninth FF. There are eight combinatorial data F7
outputs (one from each LUT), eight latched/registered F5B F6
F5
outputs (one from each latch/FF), a carry-out (COUT), K3_0 F4
and a registered carry-out (REGCOUT) that comes from K3_1 F3
K3_2 F2
the ninth FF. The carry-out signals are used principally K3_3 F1
for fast arithmetic functions. F0
K2_0
K2_1
Figure 2 and Figure 3 show high-level and detailed K2_2
views of the ports in the PFU, respectively. The eight K2_3
sets of LUT inputs are labeled as K0 through K7 with K1_0
each of the four inputs to each LUT having a suffix of K1_1
K1_2
_x, where x is a number from 0 to 3. There are four F5 K1_3
inputs labeled A through D. These inputs are used for a
K0_0
fifth LUT input for 5-input LUTs or as a selector for multi- K0_1
plexing two 4-input LUTs. The eight direct data inputs to K0_2
K0_3
the latches/FFs are labeled as DIN[7:0]. Registered LUT
outputs are shown as Q[7:0], and combinatorial LUT F5A
LSR CLK CE SEL ASWE
outputs are labeled as F[7:0].
The PFU implements combinatorial logic in the LUTs 5-5752(F)
and sequential logic in the latches/FFs. The LUTs are 5-5752(F)
static random access memory (SRAM) and can be used

for read/write or read-only memory. Figure 2. PFU Ports
Each latch/FF can accept data from its associated LUT.

Alternatively, the latches/FFs can accept direct data The PFU can be configured to operate in four modes:
from DIN[7:0], eliminating the LUT delay if no combina- logic mode, half-logic mode, ripple mode, and memory
torial function is needed. Additionally, the CIN input can (RAM/ROM) mode. In addition, ripple mode has four
be used as a direct data source for the ninth FF. The submodes and RAM mode can be used in either a
LUT outputs can bypass the latches/FFs, which reduces single- or dual-port memory fashion. These submodes
the delay out of the PFU. It is possible to use the LUTs of operation are discussed in the following sections.
and latches/FFs more or less independently, allowing,
for instance, a comparator function in the LUTs simulta-
neously with a shift register in the FFs.
Data Sheet
Programmable Logic Cells (continued)
F7
F5D REG7
0 Q7
D0
K7_0 K7 DIN7 D1
A DSEL
K7_1 0 CE
K7_2 B CK
S/R
C F6
K7_3 D
REG6 Q6
K6_0 K6 DIN6
D0
A 0 D1
K6_1 DSEL
K6_2 B 1 CE
C 0 CK
K6_3 S/R
D F5MODE67 F5
K5 REG5
K5_0 DIN5 Q5
A D0
K5_1 0 D1
B DSEL
K5_2
C CE
K5_3 CK
D
S/R
K4
K4_0
A
K4_1
B 1 F4
K4_2
C 0
K4_3
D REG4
DIN4 Q4
D0
F5C 0 D1
F5MODE45 DSEL
0 CE
CK
CLK S/R
0
SEL
0
CIN COUT
0
CE
1
1 FF8
REGCOUT
D
ASWE CE
CK
1 S/R
1
0
LSR 0
0
0
F3
F5B REG3
0 D0 Q3
K3_0 K3 DIN3 D1
A DSEL
K3_1 0 CE
K3_2 B CK
C S/R
F2
K3_3 D
REG2
K2_0 K2 DIN2 Q2
D0
A 0 D1
K2_1 DSEL
K2_2 B 1 CE
C 0 CK
K2_3 S/R
D F5MODE23
F1
K1 REG1
K1_0 DIN1 Q1
A D0
K1_1 0 D1
B DSEL
K1_2
C CE
K1_3 CK
D
S/R
K0
K0_0
A
K0_1 1
B F0
K0_2 0
C
K0_3
D REG0
DIN0 Q0
D0
F5A 0 D1
F5MODE01 DSEL
0 CE
CK
S/R
5-5743(F)
Note: All multiplexers without select inputs are configuration selector multiplexers.
Figure 3. Simplified PFU Diagram
Data Sheet
March 2002 ispORCA Series 3C and 3T FPGAs
Look-Up Table Operating Modes

The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For exam-
ple, in some operating modes, the DIN[7:0] inputs are direct data inputs to the PFU latches/FFs. In memory mode,
the same DIN[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into LUT
memory.
Table 3 lists the basic operating modes of the LUT. Figure 4—Figure 10 show block diagrams of the LUT operating
modes. The accompanying descriptions demonstrate each mode’s use for generating logic.
Table 3. Look-Up Table Operating Modes
Mode Function
Logic 4- and 5-input LUTs; softwired LUTs; latches/FFs with direct input or LUT input; CIN as direct input to
ninth FF or as pass through to COUT.
Half Logic/ Upper four LUTs and latches/FFs in logic mode; lower four LUTs and latches/FFs in ripple mode; CIN
Half Rip- and ninth FF for logic or ripple functions.
ple
Ripple All LUTs combined to perform ripple-through data functions. Eight LUT registers available for direct-in
use or to register ripple output. Ninth FF dedicated to ripple out, if used. The submodes of ripple mode
are adder/subtractor, counter, multiplier, and comparator.
Memory All LUTs and latches/FFs used to create a 32 x 4 synchronous dual-port RAM. Can be used as single-
port or as ROM.
PFU Control Inputs

Each PFU has five routable control inputs and an active-low, asynchronous global set/reset (GSRN) signal that
affects all latches and FFs in the device. The five control inputs are CLK, LSR, CE, ASWE, and SEL, and their
functionality for each logic mode of the PFU (discussed subsequently) is shown in Table 4. The clock signal to the
PFU is CLK, CE stands for clock enable, which is its primary function. LSR is the local set/reset signal that can be
configured as synchronous or asynchronous. The selection of set or reset is made for each latch/FF and is not a
function of the signal itself. ASWE stands for add/subtract/write enable, which are its functions, along with being an
optional clock enable, and SEL is used to dynamically select between direct PFU input and LUT output data as the
input to the latches/FFs.
All of the control signals can be disabled and/or inverted via the configuration logic. A disabled clock enable indi-
cates that the clock is always enabled. A disabled LSR indicates that the latch/FF never sets/resets (except from
GSRN). A disabled SEL input indicates that DIN[7:0] PFU inputs are routed to the latches/FFs. For logic and ripple
modes of the PFU, the LSR, CE, and ASWE (as a clock enable) inputs can be disabled individually for each nibble
(latch/FF[3:0], latch/FF[7:4]) and for the ninth FF.
Data Sheet

Table 4. Control Input Functionality
Mode CLK LSR CE ASWE SEL

Logic CLK to all latches/ LSR to all latches/ CE to all latches/FFs, CE to all latches/FFs, Select between LUT
FFs FFs, enabled per nib- selectable per nibble selectable per nibble input and direct input
ble and for ninth FF and for ninth FF and for ninth FF for eight latches/FFs
Half Logic/ CLK to all latches/ LSR to all latches/FF, CE to all latches/FFs, Ripple logic control Select between LUT
Half Ripple FFs enabled per nibble selectable per nibble input input and direct input
and for ninth FF and for ninth FF for eight latches/FFs
Ripple CLK to all latches/ LSR to all latches/ CE to all latches/FFs, Ripple logic control Select between LUT
FFs FFs, enabled per nib- selectable per nibble input input and direct input
ble and for ninth FF and for ninth FF for eight latches/FFs
Memory CLK to RAM Port enable 2 Port enable 1 Write enable Not used
(RAM)
Memory Optional for sync. Not used Not used Not used Not used
(ROM) outputs
Logic Mode
F5D
The PFU diagram of Figure 3 represents the logic
mode of operation. In logic mode, the eight LUTs are
K7 F7 K7
used individually or in flexible groups to implement user
logic functions. The latches/FFs may be used in con-
F6
junction with the LUTs or separately with the direct
PFU data inputs. There are three basic submodes of K6
K6 F6
LUT operation in PFU logic mode: F4 mode, F5 mode,
and softwired LUT (SWL) mode. Combinations of these K7/K6 F6
submodes are possible in each PFU.
F4 mode, shown simplified in Figure 4, illustrates the K5 F5 K5
uses of the basic 4-input LUTs in the PFU. The output
of an F4 LUT can be passed out of the PFU, captured F4 K5/K4 F4
at the LUTs associated latch/FF, or multiplexed with the

K4 F4 K4
adjacent F4 LUT output using one of the F5[A:D] inputs
to the PFU. Only adjacent LUT pairs (K0 and K1, K2 F5C
K3/K2 F2
and K3, K4 and K5, K6 and K7) can be multiplexed, and F5B
the output always goes to the even-numbered output of K3 F3
the pair. K3
The F5 submode of the LUT operation, shown simpli- K1/K0 F0
fied in Figure 4, indicates the use of 5-input LUTs to F2
K2 F2
implement logic. 5-input LUTs are created from two
K2
4-input LUTs and a multiplexer. The F5 LUT is the F5 MODE
same as the multiplexing of two F4 LUTs described
previously with the constraint that the inputs to the F4
K1 F1 K1
LUTs be the same. The F5[A:D] input is then used as
the fifth LUT input. The equations for the two F4 LUTs F0
will differ by the assumed value for the F5[A:D] input,
one F4 LUT assuming that the F5[A:D] input is zero, K0 F0 K0
and the other assuming it is a one. The selection of the
appropriate F4 LUT output in the F5 MUX by the F5A
F5[A:D] signal creates a 5-input LUT. Any combination F4 MODE MULTIPLEXED F4 MODE
of F4 and F5 LUTs is allowed per PFU using the eight
16-bit LUTs. Examples are eight F4 LUTs, four F5 5-5970(F)
LUTs, and a combination of four F4 plus two F5 LUTs.
Figure 4. Simplified F4 and F5 Logic Modes
Data Sheet

Softwired LUT submode uses F4 and F5 LUTs and internal PFU feedback routing to generate complex logic func-
tions up to three LUT-levels deep. Figure 3 shows multiplexers between the KZ[3:0] inputs to the PFU and the
LUTs. These multiplexers can be independently configured to route certain LUT outputs to the input of other LUTs.
In this manner, very complex logic functions, some of up to 21 inputs, can be implemented in a single PFU at
greatly enhanced speeds.
Figure 5 shows several softwired LUT topologies. In this figure, each circle represents either an F4 or F5 LUT. It is
important to note that an LUT output that is fed back for softwired use is still available to be registered or output
from the PFU. This means, for instance, that a logic equation that is needed by itself and as a term in a larger equa-
tion need only be generated once and PLC routing resources will not be required to use it in the larger equation.
F4 F4 F4 F4 F5 F5
F4 F4 F4 F4 F5 F5
FOUR 7-INPUT FUNCTIONS IN ONE PFU TWO 9-INPUT FUNCTIONS IN ONE PFU
F5 F4 F4 F4 F4
F5 F5 F5
F5 F5
ONE 17-INPUT FUNCTION IN ONE PFU ONE 21-INPUT FUNCTION IN ONE PFU
5-5753(F)
F4 3 F4
F4 F4
F4 F4
F4 F4
TWO OF FOUR 10-INPUT FUNCTIONS IN ONE PFU ONE OF TWO 12-INPUT FUNCTIONS IN ONE PFU
5-5754(F)
KEY:
F4 4-INPUT LUT F5 5-INPUT LUT
Figure 5. Softwired LUT Topology Examples
Data Sheet
Programmable Logic Cells (continued) with half-logic ripple connections shown as dashed
lines.
Half-Logic Mode The result output and ripple output are calculated by
Series 3 FPGAs are based upon a twin-quad architec- using generate/propagate circuitry. In ripple mode, the
ture in the PFUs. The byte-wide nature (eight LUTs, two operands are input into KZ[1] and KZ[0] of each
eight latches/FFs) may just as easily be viewed as two LUT. The result bits, one per LUT, are F[7:0]/F[3:0] (see
nibbles (two sets of four LUTs, four latches/FFs). The Figure 6). The ripple output from LUT K7/K3 can be
two nibbles of the PFU are organized so that any nib- routed on dedicated carry circuitry into any of four adja-
ble-wide feature (excluding some softwired LUT topolo- cent PLCs, and it can be placed on the PFU COUT/
gies) can be swapped with any other nibble-wide FCOUT outputs. This allows the PLCs to be cascaded
feature in another PFU. This provides for very flexible in the ripple mode so that nibble-wide ripple functions
use of logic and for extremely flexible routing. The half- can be expanded easily to any length.
logic mode of the PFU takes advantage of the twin- Result outputs and the carry-out may optionally be reg-
quad architecture and allows half of a PFU, K[7:4] and istered within the PFU. The capability to register the rip-
associated latches/FFs, to be used in logic mode while ple results, including the carry output, provides for
the other half of the PFU, K[3:0] and associated latches/ improved counter performance and simplified pipelin-
FFs, is used in ripple mode. In half-logic mode, the ing in arithmetic functions.
ninth FF may be used as a general-purpose FF or as a
register in the ripple mode carry chain.
Ripple Mode
D Q REGCOUT
C
The PFU LUTs can be combined to do byte-wide ripple
FCOUT
functions with high-speed carry logic. Each LUT has a
dedicated carry-out net to route the carry to/from any C COUT
adjacent LUT. Using the internal carry circuits, fast
F7
arithmetic, counter, and comparison functions can be K7[1]
K7 D
implemented in one PFU. Similarly, each PFU has K7[0] Q Q7
carry-in (CIN, FCIN) and carry-out (COUT, FCOUT) F6
ports for fast-carry routing between adjacent PFUs. K6[1]
K6 D
K6[0] Q Q6
The ripple mode is generally used in operations on two
F5
data buses. A single PFU can support an 8-bit ripple K5[1] D
K5 Q Q5
function. Data buses of 4 bits and less can use the K5[0]
nibble-wide ripple chain that is available in half-logic F4
mode. This nibble-wide ripple chain is also useful for K4[1] D
K4 Q Q4
K4[0]
longer ripple chains where the length modulo 8 is four
or less. For example, a 12-bit adder (12 modulo 8 = 4) F3
K3[1] D
can be implemented in one PFU in ripple mode (8 bits) K3[0]
K3 Q Q3
and one PFU in half-logic mode (4 bits), freeing half of
F2
a PFU for general logic mode functions. K2[1] D
K2 Q Q2
K2[0]
Each LUT has two operands and a ripple (generally
carry) input, and provides a result and ripple (generally F1
K1[1] D
carry) output. A single bit is rippled from the previous K1 Q Q1
K1[0]
LUT and is used as input into the current LUT. For LUT F0
K0, the ripple input is from the PFU CIN or FCIN port. K0[1] D
K0 Q Q0
The CIN/FCIN data can come from either the fast-carry K0[0]
routing (FCIN) or the PFU input (CIN), or it can be tied
CIN/FCIN
to logic 1 or logic 0. 5-5755(F)
In the following discussions, the notations LUT K7/K3

and F[7:0]/F[3:0] are used to denote the LUT that pro- Figure 6. Ripple Mode
vides the carry-out and the data outputs for full PFU
ripple operation (K7, F[7:0]) and half-logic ripple
operation (K3, F[3:0]), respectively. The ripple mode
diagram in Figure 6 shows full PFU ripple operation,
Data Sheet

D Q REGCOUT
The ripple mode can be used in one of four submodes. C
The first of these is adder-subtractor submode. In FCOUT
this submode, each LUT generates three separate out-
puts. One of the three outputs selects whether the C COUT
carry-in is to be propagated to the carry-out of the cur- F7

K7[0]
rent LUT or if the carry-out needs to be generated. If K7 D
Q Q7
the carry-out needs to be generated, this is provided by
the second LUT output. The result of this selection is K6[0] F6
placed on the carry-out signal, which is connected to K6 D
Q Q6
the next LUT carry-in or the COUT/FCOUT signal, if it
F5
is the last LUT (K7/K3). Both of these outputs can be K5[0]
D
any equation created from KZ[1] and KZ[0], but in this K5 Q Q5
case, they have been set to the propagate and gener- F4
K4[0]
ate functions. D
K4 Q Q4
The third LUT output creates the result bit for each LUT
F3
output connected to F[7:0]/F[3:0]. If an adder/subtrac- K3[0]
K3 D Q
tor is needed, the control signal to select addition or Q3
subtraction is input on ASWE, with a logic 0 indicating F2
K2[0]
subtraction and a logic 1 indicating addition. The result D
K2 Q Q2
bit is created in one-half of the LUT from a single bit
from each input bus KZ[1:0], along with the ripple input K1[0] F1
bit. K1 D Q Q1
The second submode is the counter submode (see F0
K0[0]
Figure 7). The present count, which may be initialized D
K0 Q Q0
via the PFU DIN inputs to the latches/FFs, is supplied
to input KZ[0], and then output F[7:0]/F[3:0] will either CIN/FCIN
be incremented by one for an up counter or decre- 5-5756(F)
mented by one for a down counter. If an up/down

counter is needed, the control signal to select the direc- Figure 7. Counter Submode
tion (up or down) is input on ASWE with a logic 1 indi-
cating an up counter and a logic 0 indicating a down
counter. Generally, the latches/FFs in the same PFU
are used to hold the present count value.
Data Sheet

D Q REGCOUT
In the third submode, multiplier submode, a single C
PFU can affect an 8 x 1 bit (4 x 1 for half-ripple mode)

multiply and sum with a partial product (see Figure 8). ASWE
C COUT
The multiplier bit is input at ASWE, and the multiplicand K7[1] 1 F7
bits are input at KZ[1], where K7[1] is the most signifi- 0 0 + D Q
Q7
cant bit (MSB). KZ[0] contains the partial product (or K7[0]
K7
other input to be summed) from a previous stage. If K6[1] 1 F6
ASWE is logical 1, the multiplicand is added to the par- 0 0 + D Q Q6
K6[0]
tial product. If ASWE is logical 0, 0 is added to the par- K6
K5[1] 1 F5
tial product, which is the same as passing the partial 0 0 + D Q
product. CIN/FCIN can bring the carry-in from the less K5[0] Q5
K5
significant PFUs if the multiplicand is wider than 8 bits, K4[1] 1 F4
and COUT/FCOUT holds any carry-out from the multi- 0 0 + D Q Q4
K4[0]
plication, which may then be used as part of the prod- K4
K3[1] 1 F3
uct or routed to another PFU in multiplier mode for
0 0 + D Q
multiplicand width expansion. K3[0]
Q3
K3
K2[1] F2
Ripple mode’s fourth submode features equality 1
0 0 + D Q
comparators. The functions that are explicitly available Q2
K2[0]
K2
are A > B, A ≠ B, and A < B, where the value for A is K1[1] F1
1
input on KZ[0], and the value for B is input on KZ[1]. A 0 0 + D Q Q1
value of 1 on the carry-out signals valid argument. For K1[0]
K1
example, a carry-out equal to 1 in AB submode indi- K0[1] 1 F0
0 0 + D Q
cates that the value on KZ[0] is greater than or equal to K0[0]
Q0
the value on KZ[1]. Conversely, the functions A < B, A + K0
B, and A > B are available using the same functions but 5-5757(F)
with a 0 output expected. For example, A > B with a 0 Key: C = configuration data.
output indicates A < B. Table 5 shows each function
and the output expected. Figure 8. Multiplier Submode
If larger than 8 bits, the carry-out signal can be cas-

caded using fast-carry logic to the carry-in of any adja-
cent PFU. The use of this submode could be shown
using Figure 6, except that the CIN/FCIN input for the
least significant PFU is controlled via configuration.
Table 5. Ripple Mode Equality Comparator

Functions and Outputs
Equality ORCA Foundry True, if

Function Submode Carry-Out Is:
A>B A>B 1
A<B A<B 1
A ≠B A≠B 1
A<B A>B 0
A>B A<B 0
A=B A≠B 0
Data Sheet

Memory Mode
The Series 3 PFU can be used to implement a 32 x 4 (128-bit) synchronous, dual-port random access memory
(RAM). A block diagram of a PFU in memory mode is shown in Figure 9. This RAM can also be configured to work
as a single-port memory and because initial values can be loaded into the RAM during configuration, it can also be
used as a read-only memory (ROM).
F5[A:D]
READ
KZ[3:0] 4 ADDRESS[4:0]
CIN(WA4) 5 WRITE
D Q
ADDRESS[4:0]
DIN7(WA3) D Q
F6
F4
F2
DIN5(WA2) D Q F0
D Q Q6
DIN3(WA1) D Q
D Q Q4
READ 4
DIN1(WA0) D Q DATA[3:0]
D Q Q2
DIN6(WD3) 4 WRITE
D Q DATA[3:0]
D Q Q0
DIN4(WD2) D Q
DIN2(WD1) D Q
DIN0(WD0) D Q
ASWE(WREN) WRITE
D Q ENABLE
CE(WPE1) EN
RAM CLOCK
S/R
LSR(WPE2)
CLK 5-5969(F)
Figure 9. Memory Mode
The PFU memory mode uses all LUTs and latches/FFs including the ninth FF in its implementation as shown in
Figure 9. The read address is input at the KZ[3:0] and F5[A:D] inputs where KZ[0] is the LSB and F5[A:D] is the
MSB, and the write address is input on CIN (MSB) and DIN[7, 5, 3, 1], with DIN[1] being the LSB. Write data is
input on DIN[6, 4, 2, 0], where DIN[6] is the MSB, and read data is available combinatorially on F[6, 4, 2, 0] and
registered on Q[6, 4, 2, 0] with F[6] and Q[6] being the MSB. The write enable signal is input at ASWE, and two
write port enables are input on CE and LSR. The PFU CLK signal is used to synchronously write the data. The
polarities of the clock, write enable, and port enables are all programmable. Write-port enables may be disabled if
they are not to be used.
Data Sheet
Programmable Logic Cells (continued) 8-bit data path. Depth expansion is applied to achieve
128 words deep using the 32-word deep PFU memo-
Data is written to the write data, write address, and ries. In addition to the PFU in each PLC, the SLIC
write enable registers on the active edge of the clock, (described in the next section) in each PLC is used for
but data is not written into the RAM until the next clock read address decodes and 3-state drivers. The 128 x 8
edge one-half cycle later. The read port is actually RAM shown could be made to operate as a single-port
asynchronous, providing the user with read data very RAM by tying (bit-for-bit) the read and write addresses.
quickly after setting the read address, but timing is also To achieve depth expansion, one or two of the write
provided so that the read port may be treated as fully address bits (generally the MSBs) are routed to the
synchronous for write then read applications. If the write port enables as in Figure 10. For 2 bits, the bits
read and write address lines are tied together (main- select which 32-word bank of RAM of the four available
taining MSB to MSB, etc.), then the dual-port RAM from a decode of two WPE inputs is to be written. Simi-
operates as a synchronous single-port RAM. If the larly, 2 bits of the read address are decoded in the
write enable is disabled, and an initial memory contents SLIC and are used to control the 3-state buffers
is provided at configuration time, the memory acts as a through which the read data passes. The write data bus
ROM (the write data and write address ports and write is common, with separate nibbles for width expansion,
port enables are not used). across all PLCs, and the read data bus is common
Wider memories can be created by operating two or (again, with separate nibbles) to all PLCs at the output
more memory mode PFUs in parallel, all with the same of the 3-state buffers.
address and control signals, but each with a different Figure 10 also shows a new optional capability to pro-
nibble of data. To increase memory word depth above vide a read enable for RAMs/ROMs in Series 3 using
32, two or more PLCs can be used. Figure 10 shows a the SLIC cell. The read enable will 3-state the read
128 x 8 dual-port RAM that is implemented in eight data bus when inactive, allowing the write data and
PLCs. This figure demonstrates data path width expan- read data buses to be tied together if desired.
sion by placing two memories in parallel to achieve an
8
WD[7:0]
4 4 4 4
PLC PLC PLC PLC
PFU PFU PFU PFU

WD[7:4] WD[3:0] WD[7:4] WD[3:0]
5 5 5 5 5 5 5 5
WA RA WA RA WA RA WA RA
WPE0 WPE0 WPE0 WPE0
WPE1 WPE1 WPE1 WPE1
WE WE WE WE
RD[7:4] RD[3:0] RD[7:4] RD[3:0]
SLIC SLIC SLIC SLIC
4 4 4 4
8
RD[7:0]
WE
7
WA[6:0]
7
RA[6:0]
CLK
RE
5-5749(F)
Figure 10. Memory Mode Expansion Example—128 x 8 RAM
Data Sheet
Programmable Logic Cells (continued) The SLIC may also be used to generate PAL-like AND-
OR with optional INVERT (AOI) functions or a decoder
Supplemental Logic and Interconnect Cell of up to 10 bits. Each group of buffers can feed into an
(SLIC) AND gate (4-input AND for the nibble groups and 2-
input AND for the other two buffers). These AND gates
Each PLC contains a supplemental logic and intercon- then feed into a 3-input gate that can be configured as
nect cell (SLIC) embedded within the PLC routing, out- either an AND gate or an OR gate. The output of the 3-
side of the PFU. As its name indicates, the SLIC input gate is invertible and is output at the DEC output
performs both logic and interconnect (routing) func- of the SLIC. Figure 16 shows the SLIC in full decoder
tions. Its main features are 3-statable, bidirectional mode.
buffers, and a PAL-like decoder capability. Figure 11 The functionality of the SLIC is parsed by the two
shows a diagram of a SLIC with all of its features nibble-wide groups and the 2-bit buffer group. Each of
shown. All modes of the SLIC are not available at one these groups may operate independently as BIDI buff-
time. ers (with or without 3-state capability for the nibble-
Each SLIC contains ten bidirectional (BIDI) buffers, wide groups) or as a PAL/decoder.
each buffer capable of driving left and/or right out of the As discussed in the memory mode section, if the SLIC
SLIC. These BIDI buffers are twin-quad in nature and is placed into one of the modes where it contains both
are segregated into two groups of four (nibbles) and a buffers and a decode or AOI function (e.g.,
third group of two for control. Each of these groups of BUF_BUF_DEC mode), the DEC output can be gated
BIDIs can drive from the left (BLI[9:0]) to the right with the 3-state input signal. This allows up to a 6-input
(BRO[9:0]), the right (BRI[9:0]) to the left (BLO[9:0]), or decode (e.g., BUF_DEC_DEC mode) plus the 3-state
from the central input (I[9:0]) to the left and/or right. input to control the enable/disable of up to four buffers
This central input comes directly from the PFU outputs per SLIC. Figure 12—Figure 16 show several configu-
(O[9:0]). Each of the BIDIs in the nibble-wide groups rations of the SLIC, while Table 6 shows all of the pos-
also has a 3-state buffer capability, but not the third sible modes.
group.
There is one 3-state control (TRI) for each SLIC, with Table 6. SLIC Modes
the capability to invert or disable the 3-state control for
Mode BUF BUF BUF
each group of four BIDIs. Separate 3-state control for Mode
# [3:0] [7:4] [9:8]
each nibble-wide group is achievable by using the
SLIC’s decoder (DEC) output, driven by the group of 1 BUFFER Buffer Buffer Buffer
two BIDIs, to control the 3-state of one BIDI nibble 2 BUF_BUF_DEC Buffer Buffer Decoder
while using the TRI signal to control the 3-state of the 3 BUF_DEC_BUF Buffer Decoder Buffer
other BIDI nibble. Figure 12 and Figure 13 show the
4 BUF_DEC_DEC Buffer Decoder Decoder
SLIC in buffer mode with available 3-state control from
the TRI and DEC signals. If the entire SLIC is acting in 5 DEC_BUF_BUF Decoder Buffer Buffer
a buffer capacity, the DEC output may be used to gen- 6 DEC_BUF_DEC Decoder Buffer Decoder
erate a constant logic 1 (VHI) or logic 0 (VLO) signal for 7 DEC_DEC_BUF Decoder Decoder Buffer
general use. 8 DECODER Decoder Decoder Decoder
Data Sheet
BRI9 BL09
I9
BRI9 BL09 BR09
I9
BLI9
BR09
BLI9
BRI8 BL08
BRI8 BL08 I8
I8
BR08
BR08 BLI8
BLI8
BRI7 BRI7 BL07

BL07
I7 I7
BR07 BR07
BLI7 BLI7
BRI6 BL06 BRI6 BL06

I6
BR06 I6
BLI6 BR06
BLI6
BRI5 BL05
I5 BRI5
BR05 BL05
BLI5
I5
DEC BR05
BRI4 BLI5
BL04
I4
BR04
BLI4 BRI4 BL04
I4
TRI BR04
BLI4
0/1 0/1
TRI
DEC
HIGH Z WHEN LOW
0/1 1 DEC
0/1
HIGH Z WHEN LOW 0
0/1 THIS CAN BE USED
BRI3 BL03 TO GENERATE
I3 A VHI OR VLO
BR03 0/1
BLI3
BRI2 BL02 BRI3 BL03

I2
BR02 I3
BLI2 BR03
BLI3
BRI1 BL01
I1 BRI2 BL02
BR01
BLI1 I2
BR02
BLI2
BRI0 BL00
I0
BR00 BRI1
BLI0 BL01
5-5744(F)
I1
BR01
BLI1
Figure 11. SLIC All Modes Diagram
BRI0 BL00
I0
BR00
BLI0
5-5745(F)
Figure 12. Buffer Mode
Data Sheet
BRI9 BL09
I9
BRI9 BR09
BLI9
BLI9 BRI8 BL08

I8
BRI8 BR08
BLI8
BLI8
BRI7
BRI7 BL07
I7 BLI7
BR07
BLI7
BRI6
BRI6 BL06
I6 BLI6
BR06
BLI6
BRI5
BRI5 BL05
I5 BLI5
BR05
BLI5
BRI4
BRI4 BL04
I4
BR04 BLI4
BLI4
1
DEC DEC
HIGH Z TRI
TRI WHEN LOW
1
1 1
HIGH Z
WHEN LOW HIGH Z WHEN LOW
1 1
BRI3 BL03 BRI3 BL03

I3 I3
BR03 BR03
BLI3 BLI3
BRI2 BL02 BRI2 BL02

I2 I2
BR02 BR02
BLI2 BLI2
BRI1 BL01 BRI1 BL01

I1
BR01 I1
BLI1 BR01
BLI1
BRI0 BL00 BRI0 BL00

I0
BR00 I0
BLI0 BR00
5-5746(F) BLI0
5-5747(F)
Figure 13. Buffer-Buffer-Decoder Mode

Figure 14. Buffer-Decoder-Buffer Mode
Data Sheet
BRI9 BRI9
BLI9 BLI9
BRI8 BRI8
BLI8 BLI8
BRI7 BRI7
BLI7
BLI7
BRI6
BRI6
BLI6
BLI6
BRI5
BRI5
BLI5
BLI5
BRI4
BRI4
BLI4
BLI4
DEC
TRI DEC
HIGH Z WHEN LOW

1
BRI3 BL03
I3
BR03 BRI3
BLI3
BRI2 BLI3
BL02
I2
BR02 BRI2
BLI2
BRI1 BL01 BLI2

I1
BR01
BLI1 BRI1
BRI0 BL00 BLI1

I0
BR00
BLI0 BRI0
5-5750(F)
BLI0 5-5748(F)
Figure 15. Buffer-Decoder-Decoder Mode
Figure 16. Decoder Mode
Data Sheet
Programmable Logic Cells (continued) The eight latches/FFs in a PFU share the clock (CLK)
and options for clock enable (CE), local set/reset (LSR),
PLC Latches/Flip-Flops and front-end data select (SEL) inputs. When CE is dis-
abled, each latch/FF retains its previous value when
The eight general-purpose latches/FFs in the PFU can clocked. The clock enable, LSR, and SEL inputs can be
be used in a variety of configurations. In some cases, inverted to be active-low.
the configuration options apply to all eight latches/FFs in The set/reset operation of the latch/FF is controlled by
the PFU and some apply to the latches/FFs on a nib- two parameters: reset mode and set/reset value. When
ble-wide basis where the ninth FF is considered inde- the global set/reset (GSRN) and local set/reset (LSR)
pendently. For other options, each latch/FF is signals are not asserted, the latch/FF operates normally.
independently programmable. In addition, the ninth FF The reset mode is used to select a synchronous or
can be used for a variety of functions. asynchronous LSR operation. If synchronous, LSR has
Table 7 summarizes these latch/FF options. The the option to be enabled only if clock enable (CE or
latches/FFs can be configured as either positive- or ASWE) is active or for LSR to have priority over the
negative-level sensitive latches, or positive or negative clock enable input, thereby setting/resetting the FF inde-
edge-triggered flip-flops (the ninth register can only be pendent of the state of the clock enable. The clock
FF). All latches/FFs in a given PFU share the same enable is supported on FFs, not latches. It is imple-
clock, and the clock to these latches/FFs can be mented by using a 2-input multiplexer on the FF input,
inverted. The input into each latch/FF is from either the with one input being the previous state of the FF and the
corresponding LUT output (F[7:0]) or the direct data other input being the new data applied to the FF. The
input (DIN[7:0]). The latch/FF input can also be tied to select of this 2-input multiplexer is clock enable (CE or
logic 1 or to logic 0, which is the default. ASWE), which selects either the new data or the previ-
ous state. When the clock enable is inactive, the FF out-
Table 7. Configuration RAM Controlled Latch/ put does not change when the clock edge arrives.
Flip-Flop Operation
Function Options
Common to All Latches/FFs in PFU
LSR Operation Asynchronous or synchronous
Clock Polarity Noninverted or inverted
Front-end Select* Direct (DIN[7:0]) or from LUT
(F[7:0])
LSR Priority Either LSR or CE has priority
Latch/FF Mode Latch or flip-flop
Enable GSRN GSRN enabled or has no effect on
PFU latches/FFs
Set Individually in Each Latch/FF in PFU
Set/Reset Mode Set or reset
By Group (Latch/FF[3:0], Latch/FF[7:4], and FF[8])
Clock Enable CE or ASWE or none
LSR Control LSR or none
* Not available for FF[8].
Data Sheet
Programmable Logic Cells (continued) The latches/FFs can be configured in three basic
modes:
The GSRN signal is only asynchronous, and it sets/ 1. Local synchronous set/reset: the input into the
resets all latches/FFs in the FPGA based upon the set/ PFU’s LSR port is used to synchronously set or
reset configuration bit for each latch/FF. The set/reset reset each latch/FF.
value determines whether GSRN and LSR are set or
2. Local asynchronous set/reset: the input into LSR
reset inputs. The set/reset value is independent for
asynchronously sets or resets each latch/FF.
each latch/FF. A new option is available to disable the
GSRN function per PFU after initial device configura- 3. Latch/FF with front-end select, LSR either synchro-
tion. nous or asynchronous: the data select signal
selects the input into the latches/FFs between the
The latch/FF can be configured to have a data front- LUT output and direct data in.
end select. Two data inputs are possible in the front-
For all three modes, each latch/FF can be indepen-
end select mode, with the SEL signal used to select
dently programmed as either set or reset. Figure 17
which data input is used. The data input into each
provides the logic functionality of the front-end select,
latch/FF is from the output of its associated LUT, F[7:0],
global set/reset, and local set/reset operations.
or direct from DIN[7:0], bypassing the LUT. In the front-
end data select mode, both signals are available to the The ninth PFU FF, which is generally associated with
latches/FFs. registering the carry-out signal in ripple mode func-
tions, can be used as a general-purpose FF. It is only
If either or both of these inputs is unused or is unavail-
an FF and is not capable of being configured as a latch.
able, the latch/FF data input can be tied to a logic 0 or
Because the ninth FF is not associated with an LUT,
logic 1 instead (the default is logic 0).
there is no front-end data select. The data input to the
ninth FF is limited to the CIN input, logic 1, logic 0, or
the carry-out in ripple and half-logic modes.
CE/ASWE SEL CE/ASWE

CE/ASWE
F
DIN
F CE F CE LOGIC 1 CE
DIN D Q DIN D Q LOGIC 0 D Q
LOGIC 1 LOGIC 1 DIN
LOGIC 0 LOGIC 0
s_set
LSR
s_reset
GSRN GSRN
CLK CLK CLK
LSR LSR
SET RESET SET RESET SET RESET
GSRN
CD CD CD
Key: C = configuration data.

Figure 17. Latch/FF Set/Reset Configurations
Data Sheet
PLC Routing Resources INDEPENDENT CIP

B
Generally, the ORCA Foundry Development System is
used to automatically route interconnections. Interac- CD
A =
tive routing with the ORCA Foundry design editor
(EPIC) is also available for design optimization. To use A B
EPIC for interactive layout, an understanding of the
routing resources is needed and is provided in this sec-
tion. MULTIPLEXED CIP
The routing resources consist of switching circuitry and CD

metal interconnect segments. Generally, the metal O
2
lines which carry the signals are designated as routing A
segments. The switching circuitry connects the routing A
segments, providing one or more of three basic func-
B B O
tions: signal switching, amplification, and isolation. A
net running from a PFU or PIC output (source) to a C
C
PLC or PIC input (destination) consists of one or more
routing segments, connected by switching circuitry
called configurable interconnect points (CIPs).
The following sections discuss PLC, PIC, and interquad
routing resources. This section discusses the PLC Key: C = configuration data.
5-5973(C)
switching circuitry, intra-PLC routing, inter-PLC routing,
and clock distribution. Figure 18. Configurable Interconnect Point
Configurable Interconnect Points
The process of connecting routing segments uses 3-Statable Bidirectional Buffers
three basic types of switching circuits: two types of con- Bidirectional buffers, previously described in the SLIC
figurable interconnect points (CIPs) and bidirectional section of the programmable logic cell discussion, pro-
buffers (BIDIs). The basic element in CIPs is one or vide isolation as well as amplification for signals routed
more pass transistors, each controlled by a configura- a long distance. Bidirectional buffers are also used to
tion RAM bit. The two types of CIPs are the mutually route signals diagonally in the PLC (described later in
exclusive (or multiplexed) CIP and the independent the subsection entitled Intra-PLC Routing), and BIDIs
CIP. can be used to indirectly route signals through the
A mutually exclusive set of CIPs contains two or more switching routing (xSW) segments. Any number from
CIPs, only one of which can be on at a time. An inde- zero to ten BIDIs can be used in a given PLC.
pendent CIP has no such restrictions and can be on
independent of the state of other CIPs. Figure 18
shows an example of both types of CIPs.
Data Sheet

General Routing Structure
Routing resources in Series 3 FPGAs generally consist of routing segments in groups of ten, with varying lengths
and connectivity to logic and other routing resources. The varying lengths of routing segments provides a hierarchy
of routing capability from chip-length routes to routes within a PLC. The hierarchical nature of the routing provides
the ORCA Foundry development tools with the necessary resources to route a design completely and to optimize
the routing for system speed while reducing the overall power required by the device.
Within each group of ten routing segments there is an equivalency of connectivity between pairs of segments.
These pairs are segments: [0, 4] and [1, 5] and [2, 6] and [3, 7] and [8, 9]. The equivalency in connectivity ensures
that signals on either segment in a pair have the same capability to get to a given destination. This, in turn, allows
for signal distribution from a source to varying destinations without using special routing. It also provides for routing
flexibility by ensuring that one segment position will not become so congested as to preclude routing a bus or group
of signals and allows easy connectivity from either of the twin quads in a source PFU to either of the twin quads in
any destination PFU.
Having ten segments in a group is significant in that it provides for routing a byte of data and two control signals or
parity. Due to the equivalent pairs of segments, this can also be viewed as routing two nibbles each with a control
signal. Figure 19 is an overview of the routing for a single PLC.
vx1R[9:0]
vx1L[9:0]
SUL[9:0]
vxL[9:0]
vxH[9:0]
vx5[9:0]
LCK
BL[9:0]
BL[9:0]
VCK
FC
hxH[9:0]
hx1U[9:0]
hCK
FC FC
SLL[9:0]
SLL[9:0]
FINS PFU
5
2 SLR[9:0]
SLIC
OUTPUT
SWITCHING
SUR[9:0]
LCK
hx1B[9:0]
2
hx5[9:0]
5
hxL[9:0]
BR[9:0] BR[9:0]
SUL[9:0]
SUL[9:0] FC BL[9:0]
KEY: CONFIGURABLE SIGNAL LINE BREAKS
LINE-BY-LINE
2
2 OF 5
5
5-5766(F)
Figure 19. Single PLC View of Inter-PLC Route Segments
Data Sheet
Programmable Logic Cells (continued) ally labeled for the upper-left, upper-right, lower-left,
and lower-right sections of the PFUs, respectively. The
Intra-PLC Routing xSW routing segments connect to the PFU inputs and
outputs as well as the BIDI routing segments, to be
The function of the intra-PLC routing resources is to described later. They also connect to both the horizon-
connect the PFU’s input and output ports to the routing tal and vertical x1 and x5 routing segments (inter-PLC
resources used for entry to and exit from the PLC. This routing resources, described later) in their specific cor-
routing provides PFU feedback, corner turning, or ner. xSW segments can be used for fast connections
switching from one type of routing resource to another. between adjacent PLCs or PICs without requiring the
use of inter-PLC routing resources. This capability not
Flexible Input Structure (FINS) only increases signal speed on adjacent PLC routing,
The flexible input switching structure (FINS) in each but also reduces routing congestion on the principal
PLC of the ORCA Series 3 provides for the flexibility of inter-PLC routing resources. The SLL and SUR seg-
a crossbar switch from the routing resources to the ments combine to provide connectivity to the PLCs to
PFU inputs while taking advantage of the routability of the left and right of the current PLC; the SLR and SUL
shared inputs. Connectivity between the PLC routing segments combine to provide connectivity to the PLCs
resources and the PFU inputs is provided in two above and below the current PLC.
stages. The primary FINS switch has 50 inputs that Fast routes on switching segments to diagonally adja-
connect the PLC routing to the 35 inputs on the sec- cent PLCs/PICs are possible using the BIDI routing
ondary switch. The outputs of the second switch con- segments (discussed below) and the SLL and SLR
nect to the 50 PFU inputs. The switches are switching segments. The BR BIDI routing segments
implemented to provide connectivity for bused signals combine with the SUL switching segments of the PLC
and individual connections. below and to the right of the current PLC to connect to
that PLC. The BL BIDI routing segments combine with
PFU Output Switching the SLL switching segments of the PLC above and to
The PFU outputs are switched onto PLC routing the right of the current PLC to connect to that PLC.
resources via the PFU output multiplexer (OMUX). The These fast diagonal connections provide a great
PFU output switching segments from the output multi- amount of flexibility in routing congested areas of logic
plexer provide ten connections to the PLC routing out and in shifting data on a per-PLC basis such as per-
of 18 possible PFU outputs (F[7:0], Q[7:0], DOUT, forming implicit multiplications/divisions in routing
REGCOUT). These output switching segments connect between functional logic elements.
segment for segment to the SUR, SUL, SLR, and SLL Switching routing segments are also the chief means
switching segments described below (e.g., O4 con- by which signals are transferred between the inter-PLC
nects only to SUR4, not SUR5). The output switching routing resources and the PFU. Each set of switching
segments also feed directly into the SLIC on a seg- segments has connectivity to the x1 routing segments,
ment-by-segment basis. This connectivity is also and there is varying connectivity to the x5, xH, and xL
described below. inter-PLC routing segments. Detailed information on
switching segment/inter-PLC routing connectivity is
Switching Routing Segments (xSW) provided later in this section in the Inter-PLC Routing
There are four sets of switching routing segments in Resources subsection.
each PLC. Each set consists of ten switching elements:
SUL[9:0], SUR[9:0], SLL[9:0], and SLR[9:0], tradition-
Data Sheet
Programmable Logic Cells (continued) Control Signal and Fast-Carry Routing

PFU control signal and the fast-carry routing are per-
BIDI Routing and SLIC Connectivity formed using the FINS structure and several dedicated
The SLIC is connected to the rest of the PLC by the routing paths. The fast-carry (FC) routing resources
bidirectional (BIDI) routing segments and the PFU out- consist of a dedicated bidirectional segment between
put switching segments coming from the PFU output each orthogonal pair of PLCs. This means that a fast-
multiplexer. The BIDI routing segments (xBID) are carry can go to or come from each PLC to the right or
labeled as BL for BIDI-left and BR for BIDI-right. Each left, above or below the subject PLC. The FINS struc-
set of BR and BL xBID segments is composed of ten ture is used to control the switching of these fast-carry
bidirectional lines (note that these lines are diagramed paths between the fast-carry input (FCIN) and fast-
as ten input lines to the SLIC and ten output lines from carry output (FCOUT) ports of the PFU.
the SLIC that can be used in a mutually exclusive fash- The PFU control inputs (CE, SEL, LSR, ASWE) and
ion). Because the SLIC is connected directly to the out- CIN can be reached via the FINS by two special routing
puts of the PFU, it provides great flexibility in routing via segments, E1 and E2. The E1 routing segment pro-
the xBID segments. The PFU routing segments, O[9:0], vides connectivity between all of the xBID routing seg-
only connect to their respective line in the SLL, SUL, ments and the FINS. It is unidirectional from the BIDI
SUR, and SLR switching segment groups. That is, O9 routing to the FINS. E1 also provides connectivity to the
only connects to SLL9, SUL9, SUR9, and SLR9. The PFU clock input via FINS for a local clock signal. The
BIDI lines provide the capability to connect to the other E2 segment connects the SLIC DEC output to the FINS
member of the routing set. That means, for example, and to a group of CIPS that provide bidirectional con-
that O9 can be routed to BR8 or BL8. This connectivity nectivity with all of the BIDI routing segments. This
can be used as a means to distribute or gather signals allows the DEC signal to be used in the PFU and/or
on intra-PLC routing without disturbing inter-PLC routed on the BIDI segments. It also allows signals to
resources. As described in the Switching Routing Seg- be routed to the PFU on the xBID segments if the SLIC
ments subsection, the BIDI routing segments are also DEC output is not used.
used for routes to a diagonally adjacent PFU.
There is also a dedicated routing segment from the
In addition to the intra-PLC connections, the xBID and FINS to the SLIC TRI input used for BIDI buffer 3-state
output switching segments also have connectivity to control.
the x1, x5, and xL inter-PLC routing resources, provid-
ing an alternate routing path rather than using PLC
xSW segments. These connections also provide a path
to the 3-state buffers in the SLIC without encumbering
the xSW segments. In this manner, buffering or 3-state
control can be added to inter-PLC routing without dis-
turbing local functionality within a PFU.
Data Sheet
Programmable Logic Cells (continued) x1 Routing Segments. There are a total of 40 x1 rout-
ing segments per PLC: 20 vertical and 20 horizontal.
Inter-PLC Routing Resources Each of these are subdivided into two, 10-bit wide
buses: hx1T[9:0], hx1B[9:0], vx1L[9:0], and vx1R[9:0].
The inter-PLC routing is used to route signals between An x1 segment is one PLC long. If a signal net is longer
PLCs. The routing segments occur in groups of ten, than one PLC, an x1 segment can be lengthened to n
and differ in the numbers of PLCs spanned. The x1 times its length by turning on n – 1 CIPs. A signal is
routing segments span one PLC, the x5 routing seg- routed onto an x1 route segment via the switching rout-
ments span five PLCs, the xH routing segments span ing segments or BIDI routing segments which also
one-half the width (height) of the PLC array, and the xL allows the x1 route segment to be connected to other
routing segments span the width (height) of the PLC inter-PLC segments of different lengths. Corner turning
array. All types of routing segments run in both horizon- between x1 segments is provided through direct con-
tal and vertical directions. nections, xSW segments, and xBID segments.
Table 8 shows the groups of inter-PLC routing seg-
ments in each PLC. In the table, there are two rows/col- x5 Routing Segments. There are two sets of ten x5
umns for x1 lines. They are differentiated by a T for top, routing segments per PLC. One set (vx5[9:0]) runs ver-
B for bottom, L for left, and R for right. In the ORCA tically, and the other (hx5[9:0]) runs horizontally. Each
Foundry design editor representation, the horizontal x1 x5 segment traverses five PLCs before it is broken by a
routing segments are located above and below the CIP. Two x5 segments in each group break in each
PFU. The two groups of vertical segments are located PLC. The two that break are in an equivalent pair; for
on the left side of the PFU. The xL and x5 routing seg- example, x5[0] and x5[4]. The x5 segments that break
ments only run below and to the left of the PFU, while shift by one at the next PLC. For example, if hx5[0] and
the xH segments only run above and to the right of the hx5[4] are broken at the current PLC, hx5[1] and hx5[5]
PFU. The indexes specify individual routing segments will be broken at the PLC to the right of the current
within a group. For example, the vx5[2] segment runs PLC. There are direct connections to the BIDI routing
vertically to the left of the PFU, spans five PLCs, and is segments in the PLC at which the x5 segments break,
the third line in the 10-bit wide group. on both sides of the break. Signal corner turning is
enabled by CIPs in each PLC that allow the broken x5
PLCs are arranged like tiles on the ORCA device. segments to directly connect to the broken x5 seg-
Breaks in routing occur at the middle of the tile (e.g., x1 ments that run in the orthogonal direction. x5 corner
lines break in the middle of each PLC) and run across turning can also be accomplished via the xSW and
tiles until the next break. xBID segments in a PLC. In addition, the x5 segments
are connected to the FINS and PFU outputs on a bit-
Table 8. Inter-PLC Routing Resources by-bit basis by the xSW segments. x5 segments can be
Horizontal Vertical connected for signal runs in multiples of five PLCs, or
Distance they can be combined with x1 and xH routing segments
Routing Routing
Spanned for runs of varying distances.
Segments Segments
hx1U[9:0] vx1R[9:0] One PLC
hx1B[9:0] vx1L[9:0] One PLC
hx5[9:0] vx5[9:0] Five PLCs
hx5[9:0] vx5[9:0] Five PLCs
hxL[9:0] vxL[9:0] PLC Array
hxH[9:0] vxH[9:0] 1/2 PLC Array
hCLK vCLK PLC Array
Figure 20 provides a global view of inter-PLC routing

resources across multiple PLCs.
Data Sheet
vx1L[9:0]
vxH[9:0]
vxH[9:0]
vx1[9:0]
vxH[9:0]
vx5[9:0]
vx1[9:0]
vx1[9:0]
vxL[9:0]
vx5[9:0]
vx1[9:0]
vx1[9:0]
vxL[9:0]
vx5[9:0]
vx1[9:0]
vCLK
vCLK
vCLK
hxH[9:0]
hx1[9:0]
hCLK
10 10 10
PFU PFU PFU
2 2 2
SLIC SLIC SLIC
hx1[9:0]
2 2 2
hx5[9:0]
10 10 10
hxL[9:0]
hxH[9:0]
hx1[9:0]
hCLK
10 10 10
PFU PFU PFU
2 2 2
SLIC SLIC SLIC
hx1[9:0]
2 2 2
hx5[9:0]
10 10 10
hxL[9:0]
hxH[9:0]
hx1[9:0]
hCLK
10 10 10
PFU PFU PFU
2 2 2
SLIC SLIC SLIC
hx1[9:0]
2 2 2
hx5[9:0]
10 10 10
hxL[9:0]
KEY: CONFIGURABLE SIGNAL-LINE BREAKS:
LINE-BY-LINE
2
2 OF 10
10
PLC BOUNDARY
5-5767(F)
Figure 20. Multiple PLC View of Inter-PLC Routing
Data Sheet
Programmable Logic Cells (continued) The clock routing segments are designed to be a clock
spine. In each PLC, there is a fast connection available
xL Routing Lines. The xL routing lines run vertically from the clock segment to a long-line driver (described
and horizontally the height and width of the array, earlier). With this connection, one of the clock routing
respectively. There are a total of 20 xL routing lines per segments in each PLC can be used to drive one of the
PLC: ten horizontal (hxL[9:0]) and ten vertical ten xL routing segments perpendicular to it, which, in
(vxL[9:0]). Each of the xL lines connects to the PIC turn, creates a clock spine tree. This feature is dis-
routing at either end. The xL lines are intended prima- cussed in detail in the Clock Distribution Network sec-
rily for global signals that must travel long distances tion.
and require minimum delay and/or skew, such as Special connectivity is provided in each PLC to connect
clocks or 3-state buses. the clock enable signals (CE and ASWE) and the LSR
Each xL line (also called a long line) drives a buffer in signal to the clock network for fast global control signal
each PLC that can drive onto the horizontal and verti- distribution. CE and ASWE have a special connection
cal local clock routing segments (lCLK) in the PLC. to the horizontal clock spine, and LSR has a special
Also, two out of each group of ten xL segments in each connection to the vertical clock spine. This allows both
PLC can be driven by a buffer attached to a clock spine signals to be routed globally within the same PLC, if
(described later) allowing local distribution of global desired; however, this will consume some of the
clock signals. More general-purpose connections to the resources available for clock signal routing.
long lines can be made through the xBID segments in a If using these spines, the clock enable signal must
PLC. Each long line is connected to an xBID segment come from the right or left edge of the device, and the
on a bit-by-bit basis. These BIDI connections allow cor- LSR signal must come from the top or bottom of the
ner turning from horizontal to vertical long lines, and device due to their horizontal and vertical connectivity,
connection between long lines and x1 or x5 segments. respectively, to the clock network.
xH Routing Segments. Ten by-half (xH) routing seg- Minimizing Routing Delay
ments run horizontally (hxH[9:0]) and ten xH routing
segments run vertically (vxH[9:0]) in each row and col- The CIP is an active element used to connect two rout-
umn in the array. These routing segments travel a dis- ing segments. As an active element, it adds signifi-
tance of one-half the PLC array before being broken in cantly to the resistance and capacitance of a routing
the middle of the array in the interquad area (discussed network (net), thus increasing the net’s delay. The
later). They also connect at the periphery of the FPGA advantage of the x1 segment over an x5 segment is
to the PICs, like the xL lines. xH routing segments con- routing flexibility. A net from one PLC to the next is eas-
nect to the PLCs only by switching segments. They are ily routed by using x1 routing segments. As more CIPs
intended for fast signal interconnect. are added to a net, the delay increases. To increase
speed, routes that are greater than two PLCs away are
Clock (and Global CE and LSR) Routing Segments. routed on the x5 routing segments because a CIP is
For a very fast and low-skew clock (or other global sig- located only in every fifth PLC. A net that spans eight
nal tree), clock routing segments run the entire height PLCs requires seven x1 routing segments and six
and width of the PLC array. There are two clock routing CIPs. Using x5 routing segments, the same net uses
segments per PLC: one horizontal (hCLK) and one ver- two routing segments and one CIP.
tical (vCLK). The source for these clock routing seg-
ments can be any of the I/O buffers in the PIC, the
Series 3 ExpressCLK inputs, user logic, or the pro-
grammable clock manager (PCM). The horizontal clock
routing segments (hCLK) are alternately driven by the
left and right PICs. The vertical clock routing segments
(vCLK) are alternately driven by the top and bottom
PICs.
Data Sheet
Programmable Logic Cells (continued) J. These are the ten switched output routing segments
from the PFU. They connect to the PLC switching
segments and are input to the SLIC.
PLC Architectural Description
K. These lines deliver the auxiliary signals clock enable
Figure 21 is an architectural drawing of the PLC (as (CE), local set/reset (LSR), front-end select (SEL),
seen in ORCA Foundry) that reflects the PFU, the rout- add/subtract/write enable (ASWE), as well as the
ing segments, and the CIPs. A discussion of each of carry signals (CIN and FCIN) to the latches/FFs.
the letters in the drawing follows. L. This is the local clock buffer. Any of the horizontal
and vertical xL lines can drive the clock input of the
A. These are switching routing segments (xSW) that
PLC latches/FFs. The clock routing segments (vCLK
give the router flexibility. In general switching theory,
and hCLK) and multiplexers/drivers are used to con-
the more levels of indirection there are in the routing,
nect to the xL routing segments for low-skew, low-
the more routable the network is. The xSW seg-
delay global signals.
ments can also connect to the xSW lines in adjacent
PLCs. M. These routing segments are used to route the fast-
carry signal to/from the neighboring four PLCs. The
B. These CIPs connect the x1 routing. These are
carry-out (COUT) and registered carry-out (REG-
located in the middle of the PLC to allow the block to
COUT) can also be routed out of the PFU.
connect to either the left end of the horizontal x1
segment from the right or the right end of the hori- N. This is the E2 control routing segment. It runs from
zontal x1 segment from the left, or both. By symme- the SLIC DEC output to the FINS and also provides
try, the same principle is used in the vertical connectivity to all xBID segments.
direction. O. The xH routing segments run one-half the length
C. This set of CIPs is used to connect the x1 and x5 (width) of the array before being broken by a CIP.
nets to the xSW segments or to other x1 and x5 P. These CIPs connect the xH segments to the xSW
nets. The CIPs on the major diagonal allow data to segments.
be transmitted on a bit-by-bit basis from x1 nets to Q. The xBID segments are used to connect the SLIC to
the xSW segments and between the x1 and x5 nets. the xSW segments, x1 segments, x5 segments, and
D. This structure is the supplemental logic and inter- xL lines, as well as providing for diagonal PLC to
connect cell, or SLIC. It contains 3-statable bidirec- PLC connections.
tional buffers and logic for building decoders and R. These CIPs provide connections from the xBID seg-
AND-OR-INVERT type structures. ments to the E1/E2 routing segments that feed PFU
E. These are the primary and secondary elements of control inputs CE, LSR, CIN, ASWE, SEL, and the
the flexible input structure or FINS. FINS is a switch clock input. Alternatively, these CIPs connect the
matrix that provides high connectivity while retaining BIDI lines to the decoder (DEC) output of the SLIC,
routing capability. FINS also includes feedback for routing the DEC signal.
paths for softwired LUT implementation. S. These are clock spines (vCLK and hCLK) with the
F. This is the PFU output switch matrix. It is a complex multiplexers and drivers to connect to the xL routing
switch network which, like the FINS at the input, pro- segments.
vides high connectivity and maintains routability. T. These CIPs connect xBID segments to switching
G. This set of CIPs allows an xBID segment to transfer segments in diagonally and orthogonally adjacent
a signal to/from xSW segments on each side. The PFUs.
BIDIs can access the PFU through the xSW seg- U. These CIPs connect xSW segments to the PFU out-
ments. These CIPs allow data to be routed through put segments.
the BIDIs for amplification or 3-state control and con-
V. These CIPS connect xSW segments in orthogonally
tinue to another PLC. They also provide an alterna-
adjacent PFUs.
tive routing resource to improve routability.
W.This is the SLIC 3-state control routing segment
H. These CIPs are used to transfer data from/to the
from the FINS to the SLIC 3-state control.
xBID segments to/from the x1 and xL routing seg-
ments. These CIPs have been optimized to allow the X. This is the E1 control routing segment. It provides a
BIDI buffers to drive the loads usually seen when PFU input path from all xBID segments.
using each type of routing segment. Y. These CIPs are used to select which xBID segments
I. Clock input to PFU. are connected to the E1/E2 signal as described in
(R).
Data Sheet
P A M
H B
C C C
S
Q
M M
E E
A O
G A
PRIMARY FINS
C C
SECONDARY FINS
A A A
B
PFU
A
C
C
Q A
B
D
N
K
W
H H SLIC
U U U J OUTPUT F
SWITCHING
P V
C
X
R R Y
A
L
C C
C
H B T
C
H G L
Q Q
Q Q
T A M S
5-5758(F)
Figure 21. PLC Architecture
Data Sheet
Programmable Input/Output Cells PICs in the Series 3 FPGAs have significant local rout-
ing resources, similar to routing in the PLCs. This new
The programmable input/output cells (PICs) are routing increases the ability to fix user pinouts prior to
located along the perimeter of the device. The PIC’s placement and routing of a design and still maintain
name is represented by a two-letter designation to indi- routability. The flexibility provided by the routing also
cate on which side of the device it is located followed provides for increased signal speed due to a greater
by a number to indicate in which row or column it is variety of signal paths possible.
located. The first letter, P, designates that the cell is a Included in the PIC routing is a fast path from the input
PIC and not a PLC. The second letter indicates the side pins to the SLICs in each of the three adjacent PLCs
of the array where the PIC is located. The four sides (one orthogonal and two diagonal). This feature allows
are left (L), right (R), top (T), and bottom (B). The indi- for input signals to be very quickly processed by the
vidual I/O pad is indicated by a single letter (either A, B, SLIC decoder function and used on-chip or sent back
C, or D) placed at the end of the PIC name. As an off of the FPGA. Also new to the Series 3 PIOs are
example, PL10A indicates a pad located on the left latches and FFs and options for using fast, dedicated
side of the array in the tenth row. clocks called ExpressCLKs. These features will all be
Each PIC interfaces to four bond pads and contains the discussed in subsequent sections.
necessary routing resources to provide an interface A diagram of a single PIO (one of four in a PIC) is
between I/O pads and the PLCs. Each PIC is com- shown in Figure 22. Table 9 provides an overview of
posed of four programmable I/Os (PIOs) and significant the programmable functions in an I/O cell.
routing resources. Each PIO contains input buffers,
output buffers, routing resources, latches/FFs, and
logic and can be configured as an input, output, or
bidirectional I/O.
PIO LOGIC
AND
NAND
OR
NOR
XOR
XNOR
PMUX PULL-MODE
OUT1OUTREG UP
OUT2OUTREG DOWN CLKIN
OUT1 OUT1OUT2 NONE
D0
0 PD D Q D1 Q IN1
TO ROUTING
PAD
FROM ROUTING
OUT2 ECLK NORMAL CK

SCLK INVERTED CK
0 1 LEVEL MODE
ECLK TS SP
D Q TTL SD
SCLK CK RESET BUFFER CMOS 1 INREGMODE LSR
SP SET MODE
CE D0 Q LATCHFF
LSR RESET
FAST LATCH
1 CK FF SET
SLEW
LSR IN2
CE_OVER_LSR LSR SINK
LSR_OVER_CE
0 ASYNC
ENABLE_GSR
DISABLE_GSR
5-5805(F).c
Figure 22. OR3C/Txxx Programmable Input/Output (PIO) Image from ORCA Foundry
Data Sheet
Programmable Input/Output Cells 5 V Tolerant I/O

(continued)
The I/O on the OR3Txxx Series devices allow intercon-
nection to both 3.3 V and 5 V devices (selectable on a
Table 9. PIO Options
per-pin basis).
Input Option The OR3Txxx devices will drive the pin to the 3.3 V lev-
Input Level TTL, OR3Cxx only els when the output buffer is enabled. If the other
CMOS, OR3Cxx or OR3Txxx device being driven by the OR3Txxx device has TTL-
3.3 V PCI Compliant, OR3Txxx compatible inputs, then the device will not dissipate
5 V PCI Compliant, OR3Txxx much input buffer power. This is because the OR3Txxx
output is being driven to a higher level than the TTL
Input Speed Fast, Delayed
level required. If the other device has a CMOS-compat-
Float Value Pull-up, Pull-down, None ible input, the amount of input buffer power will also be
Register Mode Latch, FF, Fast Zero Hold FF, small. Both of these power values are dependent upon
None (direct input) the input buffer characteristics of the other device when
Clock Sense Inverted, Noninverted driven at the OR3Txxx output buffer voltage levels.
Input Selection Input 1, Input 2, Clock Input The OR3Txxx device has internal programmable pull-
Output Option ups on the I/O buffers. These pull-up voltages are
always referenced to VDD and are always sufficient to
Output Drive 12 mA/6 mA or 6 mA/3 mA pull the input buffer of the OR3Txxx device to a high
Current state. The pin on the OR3Txxx device will be at a level
Output Function Normal, Fast Open Drain 1.0 V below VDD (minimum of 2.0 V with a minimum
Output Speed Fast, Slewlim, Sinklim VDD of 3.0 V). This voltage is sufficient to pull the exter-
nal pin up to a 3.3 V CMOS high input level (1.8 V, min)
Output Source FF Direct-out, General Routing
or a TTL high input level (2.0 V, min) in a 5 V tolerant
Output Sense Active-high, Active-low system. Therefore, in a 5 V tolerant system using 5 V
3-State Sense Active-high, Active-low (3-state) CMOS parts, care must be taken to evaluate the use of
FF Clocking ExpressCLK, System Clock these pull-ups to pull the pin of the OR3Txxx device to
a typical 5 V CMOS high input level (2.2 V, min).
Clock Sense Inverted, Noninverted
Logic Options See Table 10.
I/O Controls Option PCI Compliant I/O
Clock Enable Active-high, Active-low, The I/O on the OR3Txxx Series devices allows compli-
Always Enabled ance with PCI Local Bus (Rev. 2.2) 5 V and 3.3 V sig-
Set/Reset Level Active-high, Active-low, naling environments. The signaling environment used
No Local Reset for each input buffer can be selected on a per-pin
basis. The selection provides the appropriate I/O
Set/Reset Type Synchronous, Asynchronous
clamping diodes for PCI compliance. Choosing an IBT
Set/Reset Priority CE over LSR, LSR over CE input buffer will provide PCI compliance in OR3Txxx
GSR Control Enable GSR, Disable GSR devices. OR3Cxx devices have PCI Local Bus compli-
ant I/Os for 5 V signaling.
Data Sheet
Programmable Input/Output Cells Warning: During configuration, all OR3Txxx inputs

have internal pull-ups enabled. If these inputs are
(continued)
driven to 5 V, they will draw substantial current
(≅ 5 mA). This is due to the fact that the inputs are
Inputs pulled up to 3 V.
As outlined earlier in Table 9, there are six major Floating inputs increase power consumption, produce
options on the PIO inputs that can be selected in the oscillations, and increase system noise. The OR3Cxx
ORCA Foundry tools. For OR3Cxx devices, the inputs inputs have a typical hysteresis of approximately 280
and bidirectional buffers can be configured as either mV (200 mV for the OR3Txxx) to reduce sensitivity to
TTL or CMOS compatible. OR3Txxx devices support input noise. The PIC contains input circuitry which pro-
CMOS levels only for input or bidirectional buffers, have vides protection against latch-up and electrostatic dis-
5 V tolerant I/Os as previously explained, but can charge.
optionally be selected on a pin-by-pin basis to be PCI
bus 3.3 V signaling compliant (PCI bus 5 V signaling The other features of the PIO inputs relate to the new
compliance occurs in 5 V tolerant operation). The latch/FF structure in the input path. As shown in
default buffer upon powerup for the unused sites is 5 V Figure 23, the input is optionally passed to a register or
tolerant/5 V PCI compliant. Consult the ORCA macro latch/register pair. These structures can operate in the
library, Series 3 I/O cells, for the appropriate buffers. modes listed in Table 9. In latch mode, the input signal
Inputs may have a pull-up or pull-down resistor is fed to a latch that is clocked by a system clock signal.
selected on an input for signal stabilization and power The clock may be inverted or noninverted from its
management. Input signals in a PIO can be passed to sense in the PIC routing. There is also a local set/reset
PIC routing on any of three paths, two general signal signal to the latch from the PIC routing. The senses of
paths into PIC routing, and/or a fast route into the clock these signals are also programmable as well as the
routing system. capability to enable or disable the global set/reset sig-
nal and select the set/reset priority. The same control
There is also a programmable delay available on the signals may also be used to control the input latch/FF
input. When enabled, this delay affects the IN1 and IN2 when it is configured as a FF instead of a latch, with the
signals of each PIO, but not the clock input. The delay addition of another control signal used as a clock
allows any signal to have a guaranteed zero hold time enable.
when input. This feature is discussed subsequently.
Inputs should have transition times of less than 500 ns
and should not be left floating. If any pin is not used, it
is 3-stated with an internal pull-up resistor enabled
automatically after configuration.
Data Sheet
Programmable Input/Output Cells (continued)

Zero-Hold Input
There are two options for zero-hold input capture in the PIO. If input delay mode is selected to delay the signal from
the input pin, data can be either registered or latched with guaranteed zero-hold time in the PIO using a system
clock.
To guarantee zero hold, the system clock spine structure must be used for clocking, as will be discussed later. The
fast zero-hold mode of the PIO input takes advantage of the latch/FF combination and sources the input FF data
from a dedicated latch that is clocked by the ExpressCLK from the PIC. The ExpressCLK is a clock from a dedi-
cated input pin designed for fast, low-skew operation at the I/Os and is described more fully in the Clock Distribu-
tion Network and PIC Interquad (MID) Routing sections that follow. The combination of ExpressCLK latch and
system clock FF guarantees a zero-hold capture of input data in the PIO FF, while at the same time reducing input
setup time. Figure 23 shows a schematic of the fast-capture latch/FF and a sample timing diagram.
LATCH FF
INPUT DATA D Q DATA OUT

D Q TO PIC ROUTING
O
EXPRESSCLK CLK CE
I
CD = 1 S/R
O
SYSTEM CLK
I
CLOCK ENABLE
LOCAL SET/RESET
EXPRESSCLK
SYSTEM CLK
INPUT DATA A B C D E
QLATCH A B C D E
QFF A B C D
5-5974(F)
Note: CE and LSR signals not shown.
Figure 23. Fast-Capture Latch and Timing
Data Sheet

Input Demultiplexing
The combination of input register capability and the two inputs, IN1 and IN2, from each PIO to the internal routing
provides for input signal demultiplexing without any additional resources. Figure 24 shows the input configuration
and general timing for demultiplexing a multiplexed address and data signal. The PIO input signal is sent to both
the input latch and directly to IN2. The signal is latched on the falling edge of the clock and output to routing at IN1.
The address and data are then both available at the rising edge of the system clock. These signals may be regis-
tered or otherwise processed in the PLCs at that clock edge. Figure 24 also shows the possible use of the SLIC
decoder to perform an address decode to enable which registers are to receive the input data. Although the timing
shown is for using the input register as a latch, it may also be used in the same way as an FF. Also note that the
signals found in PIO inputs IN1 and IN2 can be interchanged.
OTHER ADDRESS
LINES
PIO PLC
IN1 DEC
PAD D Q SLIC
SCLK
IN2
D Q
CE
SCLK
PIO INPUT DATA1 ADDR2 DATA2 ADDR3 DATA3 ADDR4 DATA4 ADDR5
PIO LATCH
OUTPUT ADDR1 ADDR2 ADDR3 ADDR4 ADDR5
PLC FF
OUTPUT DATA0 DATA1 DATA2 DATA3 DATA4
5-5798(F)
Figure 24. PIO Input Demultiplexing
Data Sheet
Programmable Input/Output Cells An FF has been added to the output path of the PIO.
The register has a local set/reset and clock enable. The
(continued)
LSR has the option to be synchronous or asynchro-
nous and have priority set as clock enable over LSR or
Outputs LSR over clock enable. Clocking to the output FF can
The PIC’s output drivers have programmable drive come from either the system clock or the ExpressCLK
capability and slew rates. Three propagation delays associated with the PIC. The input to the FF can come
(fast, slewlim, sinklim) are available on output drivers. from either OUT1 or OUT2, or it can be tied to VDD or
The sinklim mode has the longest propagation delay GND. Additionally, the input to the FF can be inverted.
and is used to minimize system noise and minimize
power consumption. The fast and slewlim modes allow Output Multiplexing
critical timing to be met. The Series 3 PIO output FF can be combined with the
The drive current is 12 mA sink/6 mA source for the new PIO logic block to perform output data multiplexing
slewlim and fast output speed selections and with no PLC resources required. The PIO logic block
6 mA sink/3 mA source for the sinklim output. Two adja- has three multiplexing modes: OUT1OUTREG,
cent outputs can be interconnected to increase the out- OUT2OUTREG, and OUT1OUT2. OUT1OUTREG and
put sink/source current to 24 mA/12 mA. OUT2OUTREG are equivalent except that either OUT1
or OUT2 is MUXed with the FF, where the FF data is
All outputs that are not speed critical should be config- output on the clock phase after the active edge. The
ured as sinklim to minimize power and noise. The num- simplest multiplexing mode is OUT1OUT2. In this
ber of outputs that switch simultaneously in the same mode, the signal at OUT1 is output to the pad while the
direction should be limited to minimize ground bounce. clock is low, and the signal on OUT2 is output to the
To minimize ground bounce problems, locate heavily pad when the clock is high. Figure 25 shows a simple
loaded output buffers near the ground pads. Ground schematic of a PIO in OUT1OUT2 mode and a general
bounce is generally a function of the driving circuits, timing diagram for multiplexing an address and data
traces on the printed-circuit board, and loads and is signal.
best determined with a circuit simulation.
Often an address will be used to generate or read a
At powerup, the output drivers are in slewlim mode, data sample from memory with the goal of multiplexing
and the input buffers are configured as TTL-level com- the data onto a single line. In this case, the address
patible (CMOS for OR3Txxx) with a pull-up. If an output often precedes the data by one clock cycle.
is not to be driven in the selected configuration mode, it OUT1OUTREG and OUT2OUTREG modes of the PIO
is 3-stated. logic can be used to address this situation.
The output buffer signal can be inverted, and the Because OUT1OUTREG mode is equivalent to
3-state control signal can be made active-high, active- OUT2OUTREG, only OUT2OUTREG mode is
low, or always enabled. In addition, this 3-state signal described here. Figure 26 shows a simple PIO sche-
can be registered or nonregistered. Additionally, there matic in OUT2OUTREG mode and general timing for
is a fast, open-drain output option that directly connects multiplexing data with a leading address. The address
the output signal to the 3-state control, allowing the out- signal on OUT1 is registered in the PIO FF. This delays
put buffer to either drive to a logic 0 or 3-state, but the address so that it aligns with the data signal. The
never to drive to a logic 1. Because there is no explicit PIO logic block then sends the OUTREG signal
route required to create the open-drain output, its (address) to the pad when the clock is high and the
response is very fast. Like the input side of the PIO, OUT2 signal (data) to the pad when the clock is low,
there are two output connections from PIC routing to resulting in an aligned, multiplexed signal.
the output side of the PIO, OUT1, and OUT2. These
connections provide for flexible routing and can be
used in data manipulation in the PIO as described in
subsequent paragraphs.
Data Sheet
PLC PIC
ADDRESS OUT1
FROM
ROUTING
DATA OUT2
PIO
FROM PAD
ROUTING LOGIC
CLK
CLK
OUT1 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5
OUT2 DATA1 DATA2 DATA3 DATA4 DATA5
PIC OUTPUT ADDR1 DATA1 ADDR2 DATA2 ADDR3 DATA3 ADDR4 DATA4
NOTE: PIO LOGIC MODE, OUT1OUT2

5-5799(F)
Figure 25. Output Multiplexing (OUT1OUT2 Mode)
PLC PIC
ADDRESS OUT1
FROM D Q
ROUTING
CLK
P/O
LOGIC PAD
DATA OUT2
FROM
ROUTING
CLK
ADDR ADDR1 ADDR2 ADDR3 ADDR4 ADDR5
DATA DATA1 DATA2 DATA3 DATA4
REG ADDRESS ADDR1 ADDR2 ADDR3 ADDR4
PAD ADDR1 DATA1 ADDR2 DATA2 ADDR3 DATA3 ADDR4
NOTE: PIO LOGIC MODE, OUT1OUT2

5-5797(F)
Figure 26. Output Multiplexing (OUT2OUTREG Mode)

Data Sheet
Programmable Input/Output Cells PIO Register Control Signals

(continued) As discussed in the Inputs and Outputs subsections,
the PIO latches/FFs have various clock, clock enable
PIO Logic Function Generator (CE), local set/reset (LSR), and global set/reset
(GSRN) controls. Table 11 provides a summary of
The PIO logic block can also generate logic functions
these control signals and their effect on the PIO
based on the signals on the OUT2 and CLK ports of
latches/FFs. Note that all control signals are optionally
the PIO. The functions are AND, NAND, OR, NOR,
invertible.
XOR, and XNOR. Table 10 is provided as a summary
of the PIO logic options. Table 11. PIO Register Control Signals
Table 10. PIO Logic Options Control Signal Effect/Functionality
Option Description ExpressCLK Clocks input fast-capture latch;
optionally clocks output FF, or
OUT1OUTREG Data at OUT1 output when clock
3-state FF.
low, data at FF out when clock
high. System Clock Clocks input latch/FF; optionally
(SCLK) clocks output FF, or 3-state FF.
OUT2OUTREG Data at OUT2 output when clock
low, data at FF out when clock Clock Enable Optionally enables/disables input
high. (CE) FF (not available for input latch
mode); optionally enables/dis-
OUT1OUT2 Data at OUT1 output when clock
ables output FF; separate CE
low, data at OUT2 when clock
inversion capability for input and
high.
output.
AND Output logical AND of signals on
Local Set/Reset Option to disable; affects input
OUT2 and clock.
(LSR) latch/FF, output FF, and 3-state FF
NAND Output logical NAND of signals if enabled.
on OUT2 and clock.
Global Set/Reset Option to enable or disable per
OR Output logical OR of signals on (GSRN) PIO after initial configuration.
OUT2 and clock.
Set/Reset Mode The input latch/FF, output FF, and
NOR Output logical NOR of signals on 3-state FF are individually set or
OUT2 and clock. reset by both the LSR and GSRN
XOR Output logical XOR of signals on inputs.
OUT2 and clock.
XNOR Output logical XNOR of signals
on OUT2 and clock.
Data Sheet
Programmable Input/Output Cells switching segments of the PIC to the right (below). This
(continued) means of connectivity between PICs using staggered
connections of groups of switching segments allows a
given PIC to route signals to both adjacent PICs and all
PIC Routing Resources adjacent PLCs efficiently. This provides single signal
The PIC routing borrows many of the concepts and routing flexibility and routing of multiple buses on
constructs from the PLC routing. It is designed to be groups of I/Os without tying up global routing
able to gather an 8-bit bidirectional bus from any eight resources.
consecutive I/O pads and route them to either or both
of the two adjacent PLCs. The eight I/O bits do not px1 Routing Segments. There are five px1 routing
need to start at a PIC boundary; that is, they may start segments in each PIC that run parallel to the edge of
at one of the middle two PIOs in a PIC and span three the chip on which the PIC resides, each broken by a
PICs. CIP in each PIC. The px1 segments have connectivity
to the pSW segments and to the x1 routing segments
Substantial routing has been added to the PIC to off- of the two adjacent PLCs.
load PLC routing from being used to move signals
around the PLC array perimeter. This saves PLC rout- px2 Routing Segments. There are five px2 routing
ing for logic purposes and provides greater flexibility for segments in each PIC that run parallel to the edge of
locking design pinouts prior to final placement and rout- the chip on which the PIC resides. To provide greater
ing of the device, or allowing a change in the pinout late routing flexibility, the CIPs that break the px2 segments
in the design cycle. The PIC routing has also been every two PICs are staggered across the two PICs in a
increased substantially to allow routing to the complex pair. One PIC of the pair has break CIPs on the even-
PIO cells that now allow multiple inputs and outputs per numbered px2 segments, and the other has them on
device pin, along with new sequential control signals, the odd-numbered px2 segments. The px2 segments
such as clock enable, LSR, and clock. have connectivity to the pSW segments and to the x1
PICs are grouped in pairs for purposes of discussing routing segments of the two adjacent PLCs.
PIC routing. On the sides of a device, the PICs in a pair
are referred to as top and bottom. On the top or bottom px5 Routing Segments. There are ten px5 routing
of a device, the PICs in a pair are referred to as left or segments in each PIC that run parallel to the edge of
right. For example, on the top edge of the device, the the chip on which the PIC resides. Two of the ten seg-
leftmost PIC, PT1, is the left PIC of a pair, and PIC PT2 ments are broken in each PIC so that each segment is
is the right PIC of that pair. The next PIC to the right, broken every five PICs. All ten px5 segments break at
PT3, is the left PIC of the next pair, and so on. the corners of the chip, allowing independent px5 rout-
ing on each edge of the chip. The px5 routing seg-
The need for PIC pairs stems from the routing of ments connect to the pSW segments and the x5 and
switching segments and PLC half- and long-line driv- xH routing segments of the two adjacent PLCs.
ers. As described below, the connectivity for these
types of routing is grouped across pairs of PICs to pro- pxH Routing Segments. Each PIC contains eight pxH
vide complete and fast routing of I/O signals between a routing segments that run parallel to the edge of the
given PIC and the three adjacent PLCs: one orthogo- chip on which the PIC resides. The pxH segments have
nal and two diagonal. connectivity with the xL, xH, and one set of xBID rout-
PIC routing segments use the same terminology as ing segments in the immediately adjacent PLC.
PLC routing segments, but are prefixed with a p to dis-
tinguish them as belonging to the PICs. pxL Routing Segments. There are ten pxL routing
segments in each PIC that run parallel to the edge of
PIC Switching Segments. Each PIC has two groups the chip on which the PIC resides. Each of the xL lines
of switching segments (pSW), each group having eight makes a connection to an xL line from the adjacent
lines with connectivity to the PIOs in groups of four. PLC. PIC long lines (xL) can be used for global signal
One set of switching segments connects to the PIC to distribution just as PLC xL lines can.
the left (above), and the other set connects to the
Data Sheet
Programmable Input/Output Cells O. xH routing segments from the adjacent PLC routing.
(continued) P. BIDI routing segments from the adjacent PLC rout-
ing.
PIC Architectural Description Q. These are the IN2 routing segments. There is one
IN2 line from each PIO, and all eight IN2 lines from
The PIC architecture as seen in ORCA Foundry is
each PIC pair are present in both PICs of a pair.
shown in Figure 27. The figure is the left PIC of a PIC
pair on the top edge of a Series 3 array. Both PICs in a R. These CIPs connect the IN1 and IN2 routing seg-
pair are similar, with the differences mainly lying in the ments from the PIOs to the PIC switching seg-
connections between the PIC switching segments ments.
(pSW), the IN2 connections across PIC boundaries, S. These CIPs break the PIC switching segments at
and the system clock spine driver residing in only one the interface between a PIC pair.
PIC of a pair.
T. These CIPs connect adjacent PLC routing
A. This is a programmable input/output (PIO). There resources to the PIC switching segments.
are four PIOs per PIC. The PIOs contain the PIC
logic and I/O buffers. U. These CIPs connect inter-PIC routing with the PIC
switching segments.
B. This is the PIC output switching block. It connects
the PIC switching segments and local clock lines to V. These CIPs break the px1, px2, and px5 routing at
the PIO output and control signals. the middle of a PIC. The px2 and px5 CIP place-
ment varies depending on the PLC.
C. This is the system clock spine switching block and
buffer. There is only one system clock spine per pair W. These mutually exclusive buffers can drive one long
of PICs. Its inputs can come from the PIC switching line signal onto a PIC local clock routing segment.
segments or any of the eight PIO inputs in a PIC X. These mutually exclusive buffers can select a
pair. source from one of the local system clock routes to
D. PIC switching segments (pSW). These routing seg- drive the PIO 3-state control signal.
ments are used to interconnect routing resources Y. These are the four local system clock routing seg-
within the PIC and to a lesser degree, between ments. Two come from connections within the PIC,
PICs. one from the other PIC in the pair, and one from the
E. px1 routing segments. The PIC x1 routing segments adjacent PLC.
traverse one PIC and break at a CIP in the middle of Z. These mutually exclusive buffers allow a signal on
each PIC. the PIC switching segments to be routed to a sys-
F. px2 routing segments. The PICs have routing that tem clock spine or to a PIO system clock.
traverses two PICs between breaks. The breaks are AA. ExpressCLK routing line.
staggered among the five px2 segments.
AB. System clock spine.
G. px5 routing segments. Each of the ten PIC x5 rout-
ing segments traverses five PICs in between breaks AC. These various groups of CIPs connect routing
at a CIP. Two px5 segments break in each PIC. resources from the adjacent PLC to the inter-PIC
routing resources.
H. pxH routing segments. The eight PIC xH routing
segments traverse half of the array and break at AD. These buffers provide connectivity between the
CIPs in the interquad routing region that is in the PLC xL (xH) lines and the PIC xL (xH) lines or
middle of the array. connectivity between one of the IN2 routing seg-
ments and the PIC and/or PLC xL (xH) routing
I. (Not used intentionally for clarity.) segments.
J. pxL routing segments. The PIC long lines run the AE. These mutually exclusive buffers and CIPs provide
entire length of the side of the array. connectivity to the PLC xL and xH lines from one
K. x5 routing segments from the adjacent PLC routing. of the IN2 input segments.
L. xL routing segments from the adjacent PLC routing. AF. These buffers allow the IN2 signals to drive onto
the BIDI routing of the adjacent PLC, or the BIDI
M. x1 routing segments from the adjacent PLC routing. routing of the adjacent PLC, and the PIC switching
N. Switching segments from the adjacent PLC routing. segments and/or PIC half lines may be connected.
Data Sheet
AF
T
P
AE
AC
O
AB
AD
AA
W
A
Q
R
A
M
AC
G
H
D
X
E
J
F
U
Z
Y
V
B
N
A
M
AE
K
A
L
J
AD
T
AC
5-5823(F)
Figure 27. PIC Architecture
Data Sheet
High-Level Routing Resources

The high-level routing resources in the ORCA Series 3 devices are interquad routing, corner cell routing, and PIC
interquad routing. These resources and their related structures are discussed in the following subsections.
Interquad Routing
In the ORCA Series 3 devices, the PLC array is split into four equal quadrants. In between these quadrants, routing
has been added to route signals between the quadrants and distribute clocks. In addition to general routing, there
are four specialized clock routing spines. The general routing is discussed below, followed by the special clock rout-
ing.
One of the main purposes of interquad routing is to distribute internally generated signals, such as clocks and con-
trol signals. There are two types of interquad blocks: vertical and horizontal. Vertical interquad blocks (vIQ) run
between quadrants on the left and right, while horizontal interquad blocks (hIQ) run between top and bottom quad-
rants. Interquad lines begin and end in the MID cells that are discussed later. Since hIQ and vIQ blocks have the
same logic, only the hIQ block is described below. The interquad routing connects to x5 and xH segments. It does
not affect other local routing (xsw, x1, fast carry), so local routing is the same, whether PLC-PLC connections cross
quadrants or not. Figure 28 presents a (not to scale) view of interquad routing.
TMID
5 5 5 5 5
FAST CLOCK T
vIQ8[4:0]
vIQ0[4:0]
vIQ6[4:0]
vIQ4[4:0]
vIQ2[4:0]
FAST CLOCK L
5 hIQ9[4:0]
hIQ8[4:0] 5
5 hIQ7[4:0] 5
5 hIQ6[4:0]
LMID hIQ5[4:0] 5 RMID
5 hIQ4[4:0]
hIQ3[4:0] 5
5 hIQ2[4:0]
hIQ1[4:0] 5
hIQ0[4:0]
FAST CLOCK R
FAST CLOCK B
vIQ9[4:0]
vIQ1[4:0]
vIQ7[4:0]
vIQ5[4:0]
vIQ3[4:0]
5 5 5 5 5
BMID
5-4538(F)
Figure 28. Interquad Routing

Data Sheet
High-Level Routing Resources (continued) device. Fast clocks and other clock resources are dis-
cussed in the Clock Distribution Network section.
Figure 29 shows the connections from the interquad
routing to the inter-PLC routing for a block of the hori- Programmable Corner Cell Routing
zontal interquad. The vertical interquad has similar
connections. The connections shown in Figure 29 are Programmable Routing
made with PLCs located above and below the routing The programmable corner cell (PCC) contains the cir-
shown in the figure. The interquad routing segments, cuitry to connect the routing of the two PICs in each
prefixed IH for interquad horizontal, are in ten groups of corner of the device. The PIC px1 and px2 segments
five lines. Any one line from each group can be routed and eight PIC switching segments are directly con-
to one of the xH segments from the top of the device nected together from one PIC to another. The px5 lines
(left for vertical interquad), one of the xH segments are all broken with CIPs and the PIC pxL and pxH
from the bottom of the device (right for vertical inter- segments are connected from one block to another
quad), and one of the x5 segments crossing the inter- through programmable buffers.
quad.
Figure 28 shows four fast middle clock (fast clock) sig- Corner Cell Special Functions
nals with the suffixes T (top), B (bottom), R (right), and In addition to routing functions, special-purpose func-
L (left), respectively. Figure 29 also shows the fast tions are located in each FPGA corner. The upper-left
clock R and fast clock L lines; these are dedicated PCC contains connections to the boundary-scan logic
interquad clock spines. They originate in the CLKCN- and microprocessor interface. The upper-right PCC
TRL special function blocks in the middle of each edge contains connections to the readback logic, connectiv-
of the device, with the name referencing the edge of ity to the global 3-state signal (TS_ALL), and a pro-
origin. For example, fast clock R originates in the grammable clock manager. The lower-left PCC
CLKCNTRL block on the right edge of a device. Fast contains connections to the internal oscillator and a
clock spines traverse the entire PLC array but do not programmable clock manager. The lower-right PCC
connect to the PICs on the edge of the device opposite contains connections to the start-up and global reset
to the source. Each fast clock line connects to two of logic. These functions are all more completely
the xL lines in each PLC that run orthogonally to the described in the Special Function Blocks section of this
fast clock. These connections allow the fast clock lines data sheet.
to generate a clock tree that can reach any PLC in the
IH0[4:0]
IH1[4:0]
IH2[4:0]
IH3[4:0]
IH4[4:0]
FAST CLOCK R
FAST CLOCK L
IH5[4:0]
IH6[4:0]
IH7[4:0]
IH8[4:0]
IH9[4:0]
BL[9:0] vxL[9:0] vx5[9:0] vx1[9:0] SUL[9:0] vx1[9:0] FAST vck vxH[9:0] BL[9:0]
CARRY
5-5821(F)
Figure 29. hIQ Block Detail
Data Sheet
High-Level Routing Resources (continued) The pxH segments from the one quadrant can be con-
nected through a CIP to its counterpart in the opposite
PIC Interquad (MID) Routing quadrant, providing a path that spans the array of
PICs. Since a passive CIP is used to connect the two
There is also connectivity between the PICs in each pxH segments, a 3-state signal can be routed on the
quadrant, as well as a clock control (CLKCNTRL) mod- two pxH segments in the opposite quadrants, and then
ule (discussed in the Special Function Blocks section) connected through this CIP. As with the hIQ and vIQ
between the PIC routing and the interquad routing. blocks, CIPs and buffers allow nibble-wide connections
These blocks are called LMID (left), TMID (top), RMID between the interquad segments, the xH segments,
(right), and BMID (bottom). The TMID routing is shown and the x5 segments.
in Figure 30. As with the hIQ and vIQ blocks, the only
connectivity to the PIC routing is to the global pxH and
px5 segments.
SHUTOFF
EXPRESSCLK LEFT
EXPRESSCLK RIGHT
PIC LOCAL CLOCKS

FROM RIGHT
PIC LOCAL CLOCKS
FROM LEFT
pxL[9:0]
pxH[7:0]
px5[9:0]
px2[4:0]
px1[4:0]
pSW[7:4]
pSW[3:0]
pSW[7:4]
pSW[3:0]
in2[A:D] FROM LEFT
in[A:D] FROM RIGHT
CORNER ExpressCLK
FAST CLOCK
1v9xL[4]
1v8xL[3]
Iv7xL[2]
Iv7xL[0]
Iv6xL[3]
Iv6xL[1]
Iv5xL[2]
Iv5xL[0]
Iv4xL[3]
Iv4xL1]
Iv3xL[3]
Iv3xL[1]
Iv2xL[2]
Iv2xL[0]
Iv1xL[3]
Iv1xL[1]
1v0xL[2]
1v0xL[0]
5-5822(F)
Figure 30. Top (TMID) Routing
Data Sheet
Clock Distribution Network is generated from the PLC to the left or right of the cur-
rent PLC, and one is generated from the PLC above or
The Series 3 FPGAs provide three types of high- below the current PLC. The selection decision as to
speed, low-skew clock distributions: system clock, fast where these signals come from, above/below and left/
middle clock (fast clock), and ExpressCLK. Because of right, is based on the position of the PLC in the array
the great variety of sources and distribution for clock and has to do with the alternating nature of the source
signals in the ORCA Series 3, the clock mechanisms of the system clock spines (discussed later). The last of
will be described here from the inside out. The clock the five clock sources is also generated within the PLC.
connections to the PFU will be described, followed by The E1 control signal, described in the PLC Routing
clock distribution to the PLC array, clock sources to the Resources section, can drive the PFU clock. The E1
PLC array, and finally ending with clock sources and signal can come from any xBID routing resource in the
distribution in the PICs. The ExpressCLK inputs are PLC. The selection and switching of clock signals in a
new, dedicated clock inputs in Series 3 FPGAs. They PLC is performed in the FINS. Figure 31 shows the
are mentioned in several of the clock network descrip- PFU clock sources for a set of four adjacent PLCs.
tions and are described fully later in this section.
Global Control Signals
The four clock signals in each PLC that are generated
PFU Clock Sources from the long lines (xL) in the current PLC or an adja-
cent PLC can also be used to drive the PFU clock
Within a PLC there are five sources for the clock signal
enable (CE), local set/reset (LSR) and add/subtract/
of the latches/FFs in the PFU. Two of the signals are
write enable (ASWE) signals. The clock signals gener-
generated off of the long lines (xL) within the PLC: one
ated from vertical long lines can drive CE and ASWE,
from the set of vertical long lines and one from the set
and the clocks generated from horizontal long lines can
of horizontal long lines. For each of these signals, any
drive LSR. This allows for low-skew global distribution
one of the ten long lines of each set, vertical or horizon-
of two of these three control signals with the clock rout-
tal, can generate the clock signal. Two of the five PFU
ing while still allowing a global clock route to occur.
clock sources come from neighboring PLCs. One clock
vxL[9:0] vxL[9:0]
PLC PLC
PFU PFU
E1 E1
hxL[9:0]
PLC PLC
PFU PFU
E1 E1
hxL[9:0]
5-6054(F)
Figure 31. PFU Clock Sources
Data Sheet
Clock Distribution Network (continued) The clock spine structure previously described pro-
vides for complete distribution of a clock from any I/O
Clock Distribution in the PLC Array pin to the entire PLC array by means of a single clock
spine and long lines (xL). This distribution system also
System Clock (SCLK) provides a means to have many different clocks routed
to many different and dispersed locations in the PLC
The clock distribution network, or clock spine network,
array. Each spine can carry a different clock signal, so
within the PLC array is designed to minimize clock
for the OR3T55 (which has an 18 x 18 array of PLCs,
skew while maximizing clock flexibility. Clock flexibility is
implying nine clock spines per side), 36 input clock sig-
expressed in two ways: the ease with which a single
nals can be supported using the system clock network.
clock is routed to the entire array, and the capability to
provide multiple clocks to the PLC array.
Fast Clock
There is one horizontal and one vertical clock spine
Fast clocks are high-speed, low-skew clock spines that
passing through each PLC. The horizontal clock spine
originate from the CLKCNTRL special function blocks
is sourced from the PIC in the same row on either the
(described later). There are four fast clock spines—one
left- or right-hand side of the array, with the source side
originating on the middle of each edge of the array. The
(left or right) alternating for each row. The vertical clock
spines run in the interquad region of the PLC array
spines are similarly sourced from the PICs alternating
from their source side of the device to the last row or
from the top or bottom of a column. Each clock spine is
column on the opposite side of the device. The fast
capable of driving one of the ten xL routing segments
clocks connect to two long lines, xL[8] and xL[9], that
that run orthogonal to it within each PLC. Full connec-
run orthogonal to the spine direction in each PLC.
tivity to all PFUs is maintained due to the connectivity
These long lines can then be connected to the PFU
from the xL lines to the PFU clock signals described in
clock input in the same manner as the general system
the previous section; however, only an xL line in every
clocks, and, like the system clock connections, xL lines
other row (column) needs to be driven to allow the
are only needed in every other row (column) to distrib-
given clock signal to be distributed to every PFU.
ute a clock to every PFU. The limited number of long-
Figure 32 is a high-level diagram of the Series 3 system
line connections and the low skew of the CLKCNTRL
clock spine network with sample xL line
source combine to make the fast clocks a very robust,
connections for a 4 x 4 array of PLCs.
low-skew clock source.
UNUSED VERTICAL UNUSED

SCLK SPINE SCLK SPINE SCLK SPINE
UNUSED
SCLK SPINE (xL)
HORIZONTAL
SCLK SPINE
UNUSED (xL)
SCLK SPINE
UNUSED
SCLK SPINE
(xL)
UNUSED (xL) (xL)
SCLK SPINE
UNUSED UNUSED
SCLK SPINE SCLK SPINE
5-5801(F).a
Figure 32. ORCA Series 3 System Clock Distribution Overview

Data Sheet
Clock Distribution Network (continued) Clocks in the PICs
Clock Sources to the PLC Array Because the Series 3 FPGAs have latches and FFs in
the I/Os, it is necessary to have clock signal distribution
The source of a clock that is globally available to the to the PIOs as well as in the PLC array. The system
PLC array can be from any user I/O pad, any of the clock, the fast clock, and the ExpressCLK are available
ExpressCLK pads, or an internally generated source. for PIO clocking.
System Clock PIC System Clock

As described in the Programmable Input/Output Cells There are five local system clock lines in each PIC.
section, PICs are grouped in adjacent pairs. Any one of Much like the sources for a clock in the PFU, two of the
the eight pads in a PIC pair can drive a clock spine in a local PIC clocks are generated within the PIC from long
row or column. For PIC pairs on the top of the chip, the lines. One is generated from the set of ten PIC long
column associated with the left PIC has the clock lines (pxL) that runs parallel to the PICs on a side, and
spine, for pairs on the bottom, the right PIC column has the other is generated from the set of ten long lines (xL)
the spine. The top PIC of the pair sources the spine from the PLC array that terminate in the PIC. Another
from the left side of the array, and the bottom PIC of the local PIC system clock route comes from the set of ten
pair sources the spine from the right side of the array. xL lines in the adjacent PLC that is parallel to the side
Clock delay and skew are minimized by having a single of the array on which the PIC resides. The fourth local
clock buffer per pair of PICs. The clock spine for each PIC system clock route comes from the set of ten long
pair can also be driven by one of the four PIC switching lines (xL) from the PLC array that terminate in the adja-
segments (pSW) in each PIC of the pair. This allows a cent PIC that is not part of the same PIC pair. Much like
signal generated in the PLC array to be routed onto the the E1 signals in the PLCs that are used to distribute a
global clock spine network. The system clock output of local clock to the PFU source, the fifth local clock line in
the programmable clock manager (PCM) may also be each PIC comes from local pSW signals. This clock
routed to the global system clock spines via the pSW signal for each PIC is shown in Figure 33. One of these
segments. Figure 33 shows the clock spine multiplex- five local PIC system clocks is selected for the system
ing structure for a pair of PICs on the top of the array. clock signal in the PIO. It is used as the PIO system
clock for both input and output clocking as selected
Fast Clock
within the PIO. All PIOs in a PIC share the same sys-
The fast clock spines are sourced to the PLC array tem clock.
from each side of the device by the ExpressCLK pads
via the CLKCNTRL function block (described in the PIC ExpressCLK
Special Function Blocks section). The ExpressCLK and
fast clock source from the pads is shown in Figure 34 The ExpressCLK signal used at the PIC latches/FFs
and will be described further in the ExpressCLK Inputs comes from the CLKCNTRL function block that resides
subsection. in the middle of the side on which the PIC resides. A
single signal comes from the CLKCNTRL and is driven
by separate buffers onto two ExpressCLK long wires.
One of these ExpressCLK signals goes to the PICs on
the right of (above) the CLKCNTRL block, and the
pSW[4]
pSW[5]
pSW[6]
pSW[7]
PAD C
PAD D
PAD A
PAD B
other ExpressCLK signal goes to the PICs on the left of

(below) the CLKCNTRL block on that side.
PAD A
PAD B
PAD C
PAD D
pSW[4]
pSW[5]
pSW[6]
pSW[7]
TO LOCAL CLOCKS TO LOCAL CLOCKS
SPINE
TPICL TPICR
5-5800(F)
Figure 33. PIC System Clock Spine Generation

Data Sheet
Clock Distribution Network (continued) pin is completely arbitrary, but using a pin that is near
the center of an edge of the device will provide the low-
ExpressCLK Inputs est skew system clock network. The pin-to-pin timing
numbers in the Timing Characteristics section assume
There are four dedicated ExpressCLK pads on each that the clock pin is in one of the PICs at the center of
Series 3 device: one in the middle of each side. Two any side of the device next to an ExpressCLK pad. For
other user I/O pads can also be used as corner actual timing characteristics for a given clock pin, use
ExpressCLK inputs, one on the lower-left corner, and the timing analyzer results from ORCA Foundry.
one on the upper-right corner. The corner ExpressCLK To select subsequent clock pins, certain rules should
pads feed the ExpressCLK to the two sides of the array be followed. As discussed in the Programmable Input/
that are adjacent to that corner, always driving the Output Cells section, PICs are grouped into adjacent
same signal in both directions. The ExpressCLK route pairs. Each of these pairs contains eight I/Os, but only
from the middle pad and from the corner pad associ- one of the eight I/Os in a PIC pair can be routed directly
ated with that side are multiplexed and can be glitch- onto a system clock spine. Therefore, to achieve top
lessly stopped/started under user control using the performance, the next clock input chosen should not be
StopCLK feature of the CLKCNTRL function block one of the pins from a PIC pair previously used for a
(described under Special Function Blocks) on that side. clock input. If it is necessary to have a second input in
The ExpressCLK output of the programmable clock the same PIC pair route onto global system clock rout-
manager (PCM) is programmably connected to the cor- ing, the input can be routed to a free clock spine using
ner ExpressCLK routes. PCM blocks are found in the the PIC switching segment (pSW) connections to the
same corners as the corner ExpressCLK signals and clock spine network at some small sacrifice in speed.
are described in the Special Function Blocks section. Alternatively, if global distribution of the secondary
The ExpressCLK structure is shown in Figure 34 (PCM clock is not required, the signal can be routed on long
blocks are not shown). lines (xL) and input to the PFU clock input without
using a clock spine.
Another rule for choosing clock pins has to do with the
CLKCNTRL alternating nature of clock spine connections to the xL
BLOCK EXPRESSCLK PADS
and pxL routing segments. Starting at the left side of
the device, the first vertical clock spine from the top
connects to hxL[0] (horizontal xL[0]), and the first verti-
cal clock spine from the bottom connects to hxL[5] in all
PLC rows. The next vertical clock spine from the top
connects to hxL[1], and the next one from the bottom
connects to hxL[6]. This progression continues across
FAST CLOCKS the device, and after a spine connects to hxL[9], the
next spine connects to hxL[0] again. Similar connec-
tions are made from horizontal clock spines to vxL (ver-
EXPRESSCLKS TO PIOs tical xL) lines from the top to the bottom of the device.
Because the ORCA Series 3 clock routing only
requires the use of an xL line in every other row or col-
5-5802(F)
umn, even two inputs chosen 20 PLCs apart on the
Note: All multiplexers are set during configuration. same xL line will not conflict, but it is always better to
avoid these choices, if possible. The fast clock spines in
Figure 34. ExpressCLK and Fast Clock Distribution the interquad routing region also connect to xL[8] and
xL[9] for each set of xL lines, so it is better to avoid user
I/Os that connect to xL[8] or xL[9] when a fast clock is
Selecting Clock Input Pins used that might share one of these connections.
Another reason to use the fast clock spines is that
Any user I/O pin on an ORCA FPGA can be used as a
since they use only the xL[9:8] lines, they will not con-
fast, low-skew system clock input. Since the four dedi-
flict with internal data buses which typically use xL[7:0].
cated ExpressCLK inputs can only be used to distribute
For more details on clock selection, refer to application
global signals into the FPGA, these pins should be
notes on clock distribution in ORCA Series 3 devices.
selected first as clock pins. Within the interquad region
of the device, these clocks sourced by the ExpressCLK
inputs are called fast clocks. Choosing the next clock
Data Sheet
Special Function Blocks Readback can be performed via the Series 3 micropro-
cessor interface (MPI) or by using dedicated FPGA
Special function blocks in the Series 3 provide extra readback controls. If the MPI is enabled, readback via
capabilities beyond general FPGA operation. These the dedicated FPGA readback logic is disabled. Read-
blocks reside in the corners and MIDs (middle inter- back using the MPI is discussed in the Microprocessor
quad areas) of the FPGA array. Interface (MPI) section.
The pins used for dedicated readback are readback
data (RD_DATA), read configuration (RD_CFG), and
Single Function Blocks configuration clock (CCLK). A readback operation is
initiated by a high-to-low transition on RD_CFG. The
Most of the special function blocks perform a specific
RD_CFG input must remain low during the readback
dedicated function. These functions are data/configura-
operation. The readback operation can be restarted at
tion readback control, global 3-state control (TS_ALL),
frame 0 by driving the RD_CFG pin high, applying at
internal oscillator generation, global set/reset (GSRN),
least two rising edges of CCLK, and then driving
and start-up logic.
RD_CFG low again. One bit of data is shifted out on
RD_DATA at the rising edge of CCLK. The first start bit
Readback Logic
of the readback frame is transmitted out several cycles
The readback logic is located in the upper right corner after the first rising edge of CCLK after RD_CFG is input
of the FPGA and can be enabled via a bit stream option low (see the Readback Timing Characteristics table in
or by instantiation of a library readback component. the Timing Characteristics section). To be certain of the
start of the readback frame, the data can be monitored
Readback is used to read back the configuration data
for the 01 frame start bit pair.
and, optionally, the state of the PFU outputs. A read-
back operation can be done while the FPGA is in nor- Readback can be initiated at an address other than
mal system operation. The readback operation cannot frame 0 via the new microprocessor interface (MPI)
be daisy-chained. To use readback, the user selects control registers (see the Microprocessor Interface
options in the bit stream generator in the ORCA (MPI) section for more information). In all cases, read-
Foundry Development System. back is performed at sequential addresses from the
start address.
Table 12 provides readback options selected in the bit
stream generator tool. The table provides the number It should be noted that the RD_DATA output pin is also
of times that the configuration data can be read back. used as the dedicated boundary-scan output pin, TDO.
This is intended primarily to give the user control over If this pin is being used as TDO, the RD_DATA output
the security of the FPGA’s configuration program. The from readback can be routed internally to any other pin
user can prohibit readback (0), allow a single readback desired. The RD_CFG input pin is also used to control
(1), or allow unrestricted readback (U). the global 3-state (TS_ALL) function. Before and during
configuration, the TS_ALL signal is always driven by
Table 12. Readback Options the RD_CFG input and readback is disabled. After con-
figuration, the selection as to whether this input drives
Option Function the readback or global 3-state function is determined
0 Prohibit Readback by a set of bit stream options. If used as the RD_CFG
input for readback, the internal TS_ALL input can be
1 Allow One Readback Only
routed internally to be driven by any input pin.
U Allow Unrestricted Number of Readbacks
Data Sheet
Special Function Blocks (continued) The following occur when TS_ALL is activated:
1. All of the user I/O output buffers are 3-stated, the
The readback frame contains the configuration data user I/O input buffers are pulled up (with the pull-
and the state of the internal logic. During readback, the down disabled), and the input buffers are configured
value of all registered PFU and PIC outputs can be with TTL input thresholds (OR3Cxx only).
captured. The following options are allowed when
2. The TDO/RD_DATA output buffer is 3-stated.
doing a capture of the PFU outputs.
3. The RD_CFG, RESET, and PRGM input buffers remain
1. Do not capture data (the data written to the RAMs, active with a pull-up.
usually 0, will be read back).
4. The DONE output buffer is 3-stated, and the input
2. Capture data upon entering readback. buffer is pulled up.
3. Capture data based upon a configurable signal
internal to the FPGA. If this signal is tied to Internal Oscillator
logic 0, capture RAMs are written continuously.
The internal oscillator resides in the lower left corner of
4. Capture data on either options 2 or 3 above. the FPGA array. It has output clock frequencies of
The readback frame has an identical format to that of 1.25 MHz and 10 MHz. The internal oscillator is the
the configuration data frame, which is discussed later source of the internal CCLK used for configuration. It
in the Configuration Data Format section. If LUT mem- may also be used after configuration as a general-
ory is not used as RAM and there is no data capture, purpose clock signal.
the readback data (not just the format) will be identical
to the configuration data for the same frame. This Global Set/Reset (GSRN)
eases a bitwise comparison between the configuration The GSRN logic resides in the lower right corner of the
and readback data. The configuration header, including FPGA. GSRN is an invertible, default, active-low signal
the length count field, is not part of the readback frame. that is used to reset all of the user-accessible latches/
The readback frame contains bits in locations not used FFs on the device. GSRN is automatically asserted at
in the configuration. These locations need to be powerup and during configuration of the device.
masked out when comparing the configuration and
readback frames. The development system optionally The timing of the release of GSRN at the end of config-
provides a readback bit stream to compare to readback uration can be programmed in the start-up logic
data from the FPGA. Also note that if any of the LUTs described below. Following configuration, GSRN may
are used as RAM and new data is written to them, be connected to the RESET pin via dedicated routing, or
these bits will not have the same values as the original it may be connected to any signal via normal routing.
configuration data frame either. Within each PFU and PIO, individual FFs and latches
can be programmed to either be set or reset when
Global 3-State Control (TS_ALL) GSRN is asserted. A new option in Series 3 allows
individual PFUs and PIOs to turn off the GSRN signal
To increase the testability of the ORCA Series FPGAs, to its latches/FFs after configuration.
the global 3-state function (TS_ALL) disables the
device. The TS_ALL signal is driven from either an The RESET input pad has a special relationship to
external pin or an internal signal. Before and during GSRN. During configuration, the RESET input pad
configuration, the TS_ALL signal is driven by the input always initiates a configuration abort, as described in
pad RD_CFG. After configuration, the TS_ALL signal the FPGA States of Operation section. After configura-
can be disabled, driven from the RD_CFG input pad, or tion, the global set/reset signal (GSRN) can either be
driven by a general routing signal in the upper right cor- disabled (the default), directly connected to the RESET
ner. Before configuration, TS_ALL is active-low; after input pad, or sourced by a lower-right corner signal. If
configuration, the sense of TS_ALL can be inverted. the RESET input pad is not used as a global reset after
configuration, this pad can be used as a normal input
pad.
Data Sheet
Special Function Blocks (continued) The source clock for the CLKCNTRL block comes
either from the ExpressCLK pad at the middle of the
Start-Up Logic side of the FPGA or from the corner ExpressCLK route
that comes from the corner ExpressCLK pad (at the
The start-up logic block is located in the lower right cor- lower left or upper right of the device, whichever is
ner of the FPGA. This block can be configured to coor- closer). The programmable clock manager ExpressCLK
dinate the relative timing of the release of GSRN, the output can also be sourced to this corner routing for
activation of all user I/Os, and the assertion of the distribution at the two closest CLKCNTRL blocks.
DONE signal at the end of configuration. If a start-up
clock is used to time these events, the start-up clock Each CLKCNTRL block also features an invertible
can come from CCLK, or it can be routed into the start- StopCLK shutoff input that is available from local rout-
up block using lower right corner routing resources. ing. This feature may be used to glitchlessly stop and
These signals are described in the Start-Up subsection start the clock at the three outputs of each CLKCNTRL
of the FPGA States of Operation section. block and has the option of doing so on either the rising
or falling edge of the clock. When the clock is halted
Clock Control (CLKCNTRL) and StopCLK based on its rising edge, it stops and stays at VDD.
When it is stopped based on its falling edge, it stops
There is one CLKCNTRL block in the MID section of and stays at GND. If the StopCLK shutoff signal meets
the interquad routing on each side of the FPGA. This the CLKCNTRL setup and hold times, the clock is
block is used to selectively distribute the fast clock to stopped on the second clock cycle after the shutoff sig-
the PLC array and the left (top) and right (bottom) nal. A diagram of the bottom CLKCNTRL block and
ExpressCLKs (ECKL and ECKR) to the side of the StopCLK timing is shown in Figure 35.
array on which the CLKCNTRL block resides.
CORNER EXPRESSCLK
CLOCK SHUTOFF
EXPRESSCLK LEFT EXPRESSCLK RIGHT
FAST CLOCK
OFF_SET
OFF_SET OFF_HLD
OFF_HLD
CLOCK SHUTOFF
CLKCNTRL OUTPUT
CLOCKS
5-5981(F)
Notes:
CLKCNTRL output clocks are ExpressCLK left and right and fast clock.
Clock shutoff shown active-high acting on clock falling edge.
Figure 35. Top CLKCNTRL Function Block
Data Sheet
Special Function Blocks (continued)

s
TMS TDI TMS TDI
Boundary Scan TCK
TDO net a
TCK
TDO
net b
U2 U2
The increasing complexity of integrated circuits (ICs) net c
and IC packages has increased the difficulty of testing TDI

TMS
printed-circuit boards (PCBs). To address this testing TCK
problem, the IEEE standard 1149.1/D1 (IEEE Standard TDO
Test Access Port and Boundary-Scan Architecture) is TMS TDI

TCK
TMS TDI
TCK
implemented in the ORCA series of FPGAs. It allows TDO TDO
U3 U4
users to efficiently test the interconnection between
integrated circuits on a PCB as well as test the inte-
grated circuit itself. The IEEE 1149.1/D1 standard is a
well-defined protocol that ensures interoperability
among boundary-scan (BSCAN) equipped devices SEE ENLARGED VIEW BELOW
from different vendors.

The IEEE 1149.1/D1 standard defines a test access
port (TAP) that consists of a four-pin interface with an TDO TCK TMS TDI
optional reset pin for boundary-scan testing of inte- PT[ij]
grated circuits in a system. The ORCA Series FPGA TAPC

SCAN BSC SCAN
provides four interface pins: test data in (TDI), test BYPASS
REGISTER
IN BDC DCC OUT
mode select (TMS), test clock (TCK), and test data out INSTRUCTION p_in p_ts
REGISTER
(TDO). The PRGM pin used to reconfigure the device SCAN
p_out
SCAN
also resets the boundary-scan logic. OUT IN
BSC p_ts p_in PR[ij]

The user test host serially loads test commands and DCC
BSC
PLC BDC
test data into the FPGA through these pins to drive out- BDC
p_out
ARRAY
p_out
DCC
puts and examine inputs. In the configuration shown in PL[ij] p_in p_ts
Figure 36, where boundary scan is used to test ICs, SCAN SCAN
IN
test data is transmitted serially into TDI of the first p_out
OUT
p_ts p_in
BSCAN device (U1), through TDO/TDI connections
between BSCAN devices (U2 and U3), and out TDO of SCAN BSC SCAN
OUT DCC BDC IN
the last BSCAN device (U4). In this configuration, the
TMS and TCK signals are routed to all boundary-scan PB[ij]
ICs in parallel so that all boundary-scan components 5-5972(F)
operate in the same state. In other configurations, mul- Key: BSC = boundary-scan cell, BDC = bidirectional data cell,
tiple scan paths are used instead of a single ring. When and DCC = data control cell.
multiple scan paths are used, each ring is indepen-
dently controlled by its own TMS and TCK signals. Figure 36. Printed-Circuit Board with Boundary-
Figure 37 provides a system interface for components Scan Circuitry
used in the boundary-scan testing of PCBs. The three
major components shown are the test host, boundary-
scan support circuit, and the devices under test
(DUTs). The DUTs shown here are ORCA Series
FPGAs with dedicated boundary-scan circuitry. The
test host is normally one of the following: automatic test
equipment (ATE), a workstation, a PC, or a micropro-
cessor.
Data Sheet
D[7:0] D[7:0] TDO TDI TDO TDI TDO

ORCA ORCA
SERIES SERIES
BOUNDARY-
FPGA FPGA
SCAN
MASTER
MICRO- CE TMS0 TMS (DUT) TMS (DUT)
PROCESSOR RA TCK TCK TCK
R/W
DAV
(BSM) TDI
INTR INT
SP
TDI TDO
ORCA
SERIES
FPGA
TMS (DUT)
TCK
5-6765(F)
Figure 37. Boundary-Scan Interface

The boundary-scan support circuit shown in Figure 37 Table 13. Boundary-Scan Instructions
is the 497AA Boundary-Scan Master (BSM). The BSM Code Instruction
off-loads tasks from the test host to increase test
000 EXTEST
throughput. To interface between the test host and the
DUTs, the BSM has a general microprocessor interface 001 PLC Scan Ring 1 (PSR1)/USERCODE
and provides parallel-to-serial/serial-to-parallel conver- 010 RAM Write (RAM_W)
sion, as well as three 8K data buffers. The BSM also 011 IDCODE
increases test throughput with a dedicated automatic 100 SAMPLE/PRELOAD
test-pattern generator and with compression of the test 101 PLC Scan Ring 2 (PSR2)
response with a signature analysis register. The PC-
110 RAM Read (RAM_R)
based boundary-scan test card/software allows a user
to quickly prototype a boundary-scan test setup. 111 BYPASS
Boundary-Scan Instructions
The ORCA Series boundary-scan circuitry is used for
three mandatory IEEE 1149.1/D1 tests (EXTEST,
SAMPLE/PRELOAD, BYPASS), the optional IEEE
1149.1/D1 IDCODE instruction, and five ORCA-defined
instructions. The 3-bit wide instruction register supports
the nine instructions listed in Table 13, where the use of
PSR1 or USERCODE is selectable by a bit stream
option.
Data Sheet
Special Function Blocks (continued) operation or written during test operation. The data for
all of the I/Os is captured simultaneously into the BSR,
The external test (EXTEST) instruction allows the inter- allowing them to be shifted-out TDO to the test host.
connections between ICs in a system to be tested for Since each I/O buffer in the PICs is bidirectional, two
opens and stuck-at faults. If an EXTEST instruction is pieces of data are captured for each I/O pad: the value
performed for the system shown in Figure 36, the con- at the I/O pad and the value of the 3-state control sig-
nections between U1 and U2 (shown by nets a, b, and nal. For preload operation, data is written from the BSR
c) can be tested by driving a value onto the given nets to all of the I/Os simultaneously.
from one device and then determining whether the There are five ORCA-defined instructions. The PLC
same value is seen at the other device. This is deter- scan rings 1 and 2 (PSR1, PSR2) allow user-defined
mined by shifting 2 bits of data for each pin (one for the internal scan paths using the PLC latches/FFs. The
output value and one for the 3-state value) through the RAM_Write Enable (RAM_W) instruction allows the
BSR until each one aligns to the appropriate pin. Then, user to serially configure the FPGA through TDI. The
based upon the value of the 3-state signal, either the RAM_Read Enable (RAM_R) allows the user to read
I/O pad is driven to the value given in the BSR, or the back RAM contents on TDO after configuration. The
BSR is updated with the input value from the I/O pad, IDCODE instruction allows the user to capture a 32-bit
which allows it to be shifted out TDO. identification code that is unique to each device and
The SAMPLE/PRELOAD instruction is useful for sys- serially output it at TDO. The IDCODE format is shown
tem debugging and fault diagnosis by allowing the data in Table 14.
at the FPGA’s I/Os to be observed during normal
Table 14. Boundary-Scan ID Code
Version Part* Family Manufacturer LSB

Device
(4 bits) (10 bits) (6 bits) (11 bits) (1 bit)
OR3T20 0000 0011000000 110000 00000011101 1
OR3T30 0000 0111000000 110000 00000011101 1
OR3T55 0000 0100100000 110000 00000011101 1
OR3C/T80 0000 0110100000 110000 00000011101 1
OR3T125 0000 0011100000 110000 00000011101 1
OR3T165 0000 0000010000 110000 00000011101 1
* PLC array size of FPGA, reverse bit order.

Note: Table assumes version 0.
Data Sheet
Special Function Blocks (continued) the BSR (which requires a two FF delay for each pad)
is bypassed, test throughput is increased when devices
ORCA Boundary-Scan Circuitry that are not part of a test operation are bypassed.
The ORCA Series boundary-scan circuitry includes a The boundary-scan logic is enabled before and during
test access port controller (TAPC), instruction register configuration. After configuration, a configuration
(IR), boundary-scan register (BSR), and bypass regis- option determines whether or not boundary-scan logic
ter. It also includes circuitry to support the four pre- is used.
defined instructions. The 32-bit boundary-scan identification register con-
Figure 38 shows a functional diagram of the boundary- tains the manufacturer’s ID number, unique part num-
scan circuitry that is implemented in the ORCA Series. ber, and version (as described earlier). The
The input pins’ (TMS, TCK, and TDI) locations vary identification register is the default source for data on
depending on the part, and the output pin is the dedi- TDO after RESET if the TAP controller selects the shift-
cated TDO/RD_DATA output pad. Test data in (TDI) is data-register (SHIFT-DR) instruction. If boundary scan
the serial input data. Test mode select (TMS) controls is not used, TMS, TDI, and TCK become user I/Os, and
the boundary-scan test access port controller (TAPC). TDO is 3-stated or used in the readback operation.
Test clock (TCK) is the test clock on the board. An optional USERCODE is available if the boundary-
The BSR is a series connection of boundary-scan cells scan PSR1 instruction is not used. The selection
(BSCs) around the periphery of the IC. Each I/O pad on between PSR1 and USERCODE is a configuration
the FPGA, except for CCLK, DONE, and the boundary- option and can be performed in ORCA Foundry. The
scan pins (TCK, TDI, TMS, and TDO), is included in the USERCODE is an 11-bit value that the user can set
BSR. The first BSC in the BSR (connected to TDI) is during device configuration and can be written to and
located in the first PIC I/O pad on the left of the top side read from the FPGA via the boundary-scan logic. The
of the FPGA (PTA PIC). The BSR proceeds clockwise USERCODE value replaces the manufacturer field of
around the top, right, bottom, and left sides of the array. the boundary-scan ID code when the USERCODE
The last BSC in the BSR (connected to TDO) is located instruction is issued, allowing users to have configured
on the top of the left side of the array (PL1D). devices identified in a user-defined manner. The manu-
facturer ID field remains available when the IDCODE
The bypass instruction uses a single FF, which resyn- instruction is issued.
chronizes test data that is not part of the current scan
operation. In a bypass instruction, test data received on
TDI is shifted out of the bypass register to TDO. Since
I/O BUFFERS
DATA REGISTERS
BOUNDARY-SCAN REGISTER
IDCODE REGISTER
PSR1 REGISTER (PLCs)

DATA
PSR2 REGISTER (PLCs) MUX
VDD CONFIGURATION REGISTER
(RAM_R, RAM_W)
TDI BYPASS REGISTER
INSTRUCTION DECODER
M TDO
U
INSTRUCTION REGISTER X
RESET
CLOCK DR RESET
VDD SHIFT-DR CLOCK IR
UPDATE-DR SHIFT-IR
UPDATE-IR
TMS
VDD
SELECT
TCK TAP ENABLE
CONTROLLER
VDD
PUR
PRGM
5-5768(F)
Figure 38. ORCA Series Boundary-Scan Circuitry Functional Diagram

Data Sheet
Special Function Blocks (continued) The TAPC generates control signals that allow capture,
shift, and update operations on the instruction and data
ORCA Series TAP Controller (TAPC) registers. In the capture operation, data is loaded into
the register. In the shift operation, the captured data is
The ORCA Series TAP controller (TAPC) is a 1149.1/ shifted out while new data is shifted in. In the update
D1 compatible test access port controller. The 16 JTAG operation, either the instruction register is loaded for
state assignments from the IEEE 1149.1/D1 specifica- instruction decode, or the boundary-scan register is
tion are used. The TAPC is controlled by TCK and TMS. updated for control of outputs.
The TAPC states are used for loading the IR to allow
three basic functions in testing: providing test stimuli The test host generates a test by providing input into
(Update-DR), test execution (Run-Test/Idle), and the ORCA Series TMS input synchronous with TCK.
obtaining test responses (Capture-DR). The TAPC This sequences the TAPC through states in order to
allows the test host to shift in and out both instructions perform the desired function on the instruction register
and test data/results. The inputs and outputs of the or a data register. Figure 39 provides a diagram of the
TAPC are provided in the table below. The outputs are state transitions for the TAPC. The next state is deter-
primarily the control signals to the instruction register mined by the TMS input value.
and the data register.
1 TEST-LOGIC-
Table 15. TAP Controller Input/Outputs RESET
0
1 1 1
Symbol I/O Function 0
RUN-TEST/
IDLE
SELECT-
DR-SCAN
SELECT-
IR-SCAN
TMS I Test Mode Select 0 0
1 1
TCK I Test Clock CAPTURE-DR CAPTURE-IR
0 0
PUR I Powerup Reset
SHIFT-DR 0 SHIFT-IR 0
PRGM I BSCAN Reset
1 1
TRESET O Test Logic Reset 1 1
EXIT1-DR EXIT1-IR
Select O Select IR (High); Select-DR (Low) 0 0
Enable O Test Data Out Enable PAUSE-DR 0 PAUSE-IR 0
Capture-DR O Capture/Parallel Load-DR 1 1
0 0
Capture-IR O Capture/Parallel Load-IR EXIT2-DR EXIT2-IR
Shift-DR O Shift Data Register 1 1
Shift-IR O Shift Instruction Register UPDATE-DR UPDATE-IR

1 0 1 0
Update-DR O Update/Parallel Load-DR
Update-IR O Update/Parallel Load-IR
5-5370(F)
Figure 39. TAP Controller State Transition Diagram
Data Sheet
Special Function Blocks (continued) direction control cell is used to access the 3-state
value. Both cells consist of a flip-flop used to shift scan
Boundary-Scan Cells data which feeds a flip-flop to control the I/O buffer. The
bidirectional data cell is connected serially to the direc-
Figure 40 is a diagram of the boundary-scan cell (BSC) tion control cell to form a boundary-scan shift register.
in the ORCA series PICs. There are four BSCs in each
PIC: one for each pad, except as noted above. The The TAPC signals (capture, update, shiftn, treset, and
BSCs are connected serially to form the BSR. The BSC TCK) and the MODE signal control the operation of the
controls the functionality of the in, out, and 3-state sig- BSC. The bidirectional data cell is also controlled by
nals for each pad. the high out/low in (HOLI) signal generated by the
direction control cell. When HOLI is low, the bidirec-
The BSC allows the I/O to function in either the normal tional data cell receives input buffer data into the BSC.
or test mode. Normal mode is defined as when an out- When HOLI is high, the BSC is loaded with functional
put buffer receives input from the PLC array and pro- data from the PLC.
vides output at the pad or when an input buffer
provides input from the pad to the PLC array. In the test The MODE signal is generated from the decode of the
mode, the BSC executes a boundary-scan operation, instruction register. When the MODE signal is high
such as shifting in scan data from an upstream BSC in (EXTEST), the scan data is propagated to the output
the BSR, providing test stimuli to the pad, capturing buffer. When the MODE signal is low (BYPASS or
test data at the pad, etc. SAMPLE), functional data from the FPGA’s internal
logic is propagated to the output buffer.
The primary functions of the BSC are shifting scan data
serially in the BSR and observing input (p_in), output The boundary-scan description language (BSDL) is
(p_out), and 3-state (p_ts) signals at the pads. The provided for each device in the ORCA Series of FPGAs
BSC consists of two circuits: the bidirectional data cell on the ORCA Foundry CD. The BSDL is generated
is used to access the input and output data, and the from a device profile, pinout, and other boundary-scan
information.
SCAN IN
I/O BUFFER
PAD_IN
p_in
PAD_OUT
BIDIRECTIONAL DATA CELL
0
0
0 D Q D Q 1
1 PAD_TS
p_out 1
HOLI
0
0
D Q D Q 1
p_ts 1
DIRECTION CONTROL CELL
SHIFTN/CAPTURE TCK SCAN OUT UPDATE/TCK MODE
5-2844(F
Figure 40. Boundary-Scan Cell

Data Sheet

Boundary-Scan Timing
To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on
the rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST
instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum fre-
quency allowed for TCK is 10 MHz.
Figure 41 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to
sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is
clocked into the DUT on the rising edge.
TEST-LOGIC-RESET
SELECT-DR-SCAN
RUN-TEST/IDLE
SELECT-IR-SCAN
RUN-TEST/IDLE
CAPTURE-IR
PAUSE-IR
SHIFT-IR
SHIFT-IR
UPDATE-IR
EXIT1-IR
EXIT2-IR
EXIT1-IR
TCK
TMS
TDI
5-5971(F)
Figure 41. Instruction Register Scan Timing Diagram
Data Sheet
Microprocessor Interface (MPI) interrupt the host processor either by a hard interrupt or
by having the host processor poll the microprocessor
The Series 3 FPGAs have a dedicated synchronous interface.
microprocessor interface function block (see The control portion of the microprocessor interface is
Figure 42). The MPI is programmable to operate with available following powerup of the FPGA if the mode
PowerPC MPC800 series microprocessors and Intel* pins specify MPI mode, even if the FPGA is not yet con-
i960* J core processors; see Table 16 and Table 17, figured. The mode pin (M[2:0]) settings can be found in
respectively, for compatible processors. The MPI imple- the FPGA Configuration Modes section of this data
ments an 8-bit interface to the host processor (Pow- sheet, and the setup and use of the MPI for configura-
erPC or i960) that can be used for configuration and tion is discussed in the MPI Setup and Control subsec-
readback of the FPGA as well as for user-defined data tion. For postconfiguration use, the MPI must be
processing and general monitoring of FPGA function. included in the configuration bit stream by using an MPI
In addition to dedicated-function registers, the micro- library element in your design from the ORCA macro
processor interface allows for the control of up to 16 library, or by setting the MP_USER bit of the MPI con-
user registers (RAM or flip-flops) in the FPGA logic. A figuration control register prior to the start of configura-
synchronous/asynchronous handshake procedure is tion (MPI registers are discussed later).
used to control transactions with user logic in the FPGA
* Intel and i960 are registered trademarks of Intel Corporation.
array. There is also capability for the FPGA logic to
D[7:0]IN
TO FPGA
ROUTING
D[7:0]OUT
ORCAORCA 3C/Txxx MPI
DONE
RD_DATA
INIT
D7 D7IN
D7OUT
D6 D6IN
STATUS
D6OUT REGISTER
D5 D5IN
D5OUT
D4 D4IN
D4OUT
D3 D3IN
D3OUT
D2 D2IN
D2OUT
SCRATCHPAD
D1 D1IN REGISTER
D1OUT
D0 D0IN
READBACK
D0OUT DATA REGISTER
A4
READBACK
POWERPC ONLY
A3 ADDR REGISTER
A2 RESET
A1 RD_CFG
A0 CONTROL PRGM
RD REGISTERS
GSR
CS0 TO GSR BLOCK
IRQ
DECODE/CONTROL
CS1
CCLK PART ID
REGISTERS
M3 USER_START
TO FPGA
M2 USER_END ROUTING
M1 WR_CTRL
M0 A[3:0]
MPI_IRQ
RDYRCV
MPI_ACK CLK
MPI_CLK ADS i960 LOGIC
MPI_STRB ALE
W/R
MPI_ALE
MPI_RW
MPI_B1 RD/WR
BT
TS POWERPC LOGIC
CLKOUT
TA
DEVICE PAD
I/O BUFFER
5-5806(F)
Figure 42. MPI Block Diagram

Data Sheet
Microprocessor Interface (MPI) (continued) (read high, write low) signals are set up at the FPGA
pins by the PowerPC. The PowerPC then asserts its
PowerPC System transfer start signal (TS) low. Data is available to the
MPI during a write at the rising clock edge after the
In Figure 43, the ORCA FPGA is a memory-mapped clock cycle during which TS is low. The transfer is
peripheral to the PowerPC processor. The PowerPC acknowledged to the PowerPC by the low asser tion of
interface uses separate address and data buses and the TA signal. The MPI PowerPC interface does not
has several control lines. The ORCA chip select lines, support burst transfers, so the burst inhibit signal, BI, is
CS0 and CS1, are each connected to an address line also asserted low during the transfer acknowledge . The
coming from the PowerPC. In this manner, the FPGA is same process applies to a read from the MPI except
capable of a transaction with the PowerPC whenever that the read data is expected at the FPGA data pins by
the address line connected to CS0 is low, the address the PowerPC at the rising edge of the clock when TA is
line for CS1 is high, and there is a valid address on low. The MPI only drives TA low for one clock cycle.
PowerPC address lines A[27:31]. Other forms of selec- Interrupt requests can be sent to the PowerPC asyn-
tion are possible by using the FPGA chip selects in a chronously to the read/write process. Interrupt requests
different way. For example, PowerPC address bits are sourced by the user-logic in the FPGA. The MPI will
A[0:26] could be decoded to select CS0 and CS1, or if assert the request to the PowerPC as a direct interrupt
the FPGA is the only peripheral to the PowerPC, CS0 signal and/or a pollable bit in the MPI status register
and CS1 could be tied low and high, respectively, to (discussed in the MPI Setup and Control section). The
cause them to always be selected. If the MPI is not MPI will continue to assert the interrupt request until
used for FPGA configuration, decoding logic can be the user-logic deasserts its interrupt request signal.
implemented internal or external to the FPGA. If logic
internal to the FPGA is used, the chip selects must be Table 16. PowerPC/MPI Configuration
routed out on an output pin and then connected exter-
nally to CS0 and/or CS1. If the MPI is to be used for PowerPC ORCA Pin MPI Function
configuration, any decode logic used must be imple- Signal Name I/O
mented external to the FPGA since the FPGA logic has D[0:7] D[7:0] I/O 8-bit data bus
not been configured yet.
A[27:31] A[4:0] I 5-bit MPI address
bus
TO DAISY-
TS RD/MPI_STRB I Transfer start signal
DOUT
CHAINED
8
CCLK DEVICES — CS0 I Active-low MPI
D[7:0] D[7:0] select
A[27:31] A[4:0]
CLKOUT MPI_CLK — CS1 I Active-high MPI
RD/WR MPI_RW select
ORCA
POWERPC TA MPI_ACK
SERIES 3
BI MPI_BI FPGA CLKOUT A7/MPI_CLK I PowerPC interface
IRQx MPI_IRQ clock
TS MPI_STRB
A26 CS0 DONE RD/WR A8/MPI_RW I Read (high)/write
A25 CS1 INIT (low) signal
HDC
LDC TA A9/MPI_ACK O Active-low transfer
acknowledge signal
5-5761(F)
BI A10/MPI_BI O Active-low burst
Note: FPGA shown as a memory-mapped peripheral using CS0 and transfer inhibit
CS1. Other decoding schemes are possible using CS0 and/or signal
CS1.
Any of A11/MPI_IRQ O Active-low interrupt
IRQ[7:0] request signal
Figure 43. PowerPC/MPI
The basic flow of a transaction on the PowerPC/MPI

interface is given below. Pin descriptions are shown in
Table 16 and timing is shown in the Timing Characteris-
tics section of this data sheet. For both read and write
transactions, the address, chip select, and read/write
Data Sheet
Microprocessor Interface (MPI) (continued) set up at the FPGA pins by the i960 at the next rising
edge of the clock. At this same rising clock edge, the
i960 System i960 asserts its address/data strobe (ADS) low. Data is
available to the MPI during a write at the rising clock
Figure 44 shows a schematic for connecting the ORCA edge of the following clock cycle. The transfer is
MPI to supported i960 processors. In the figure, the acknowledged to the i960 by the low assertion of the
FPGA is shown as the only peripheral, with the FPGA ready/recover (RDYRCV) signal. The same process
chip select lines, CS0 and CS1, tied low and high, applies to a read from the MPI except that the read
respectively. The i960 address and data are multi- data is expected at the FPGA data pins by the i960 at
plexed onto the same bus. This precludes memory the rising edge of the clock when RDYRCV is low. The
mapping of the FPGA in the i960 memory space of a MPI only drives RDYRCV low for one clock cycle.
multiperipheral system without some form of address Interrupts can be sent to the i960 asynchronously to
latching to capture and hold the address signals to the read/write process. Interrupt requests are sourced
drive the CS0 and/or CS1 signals. Multiple address sig- by the user-logic in the FPGA. The MPI will assert the
nals could also be decoded and latched to drive the request to the i960 as a direct interrupt signal and/or a
CS0 and/or CS1 signals. If the MPI is not used for
pollable bit in the MPI status register (discussed in the
FPGA configuration, decoding/latching logic can be MPI Setup and Control section). The MPI will continue
implemented internal or external to the FPGA. If logic to assert the interrupt request until the user-logic deas-
internal to the FPGA is used, the chip selects must be serts its interrupt request signal.
routed out an output pin and then connected externally
to CS0 and/or CS1. If the MPI is to be used for configu- Table 17. i960/MPI Configuration
ration, any decode/latch logic used must be imple-
mented external to the FPGA since the FPGA logic has i960 ORCA Pin MPI
not been configured yet. Function
Signal Name I/O
AD[7:0] D[7:0] I/O Multiplexed 5-bit address/
i960 SYSTEM CLOCK 8-bit data bus. The address
appears on D[4:0].
8 DOUT TO DAISY- ALE RDY/RCLK/ I Address latch enable used
AD[7:0] D[7:0] CHAINED
CCLK MPI_ALE to capture address from
DEVICES
CLKIN MPI_CLK AD[4:0] on falling edge of
W/R MPI_RW clock.
RDYRCV MPI_ACK
XINTx MPI_IRQ ADS RD/ I Address/data strobe to
ORCA
i960
ALE MPI_ALE SERIES 3 MPI_STRB indicate start of transac-
ADS MPI_STRB FPGA tion.
BE0 MPI_BE0
BE1 MPI_BE1 — CS0 I Active-low MPI select.
VDD DONE
INIT
— CS1 I Active-high MPI select.
CS1
HDC System A7/ I i960 system clock. This
CS0
LDC clock is sourced by the
Clock MPI_CLK
system and not the i960.
5-5762(F) W/R A8/MPI_RW I Write (high)/read (low)
signal.
Note: FPGA shown as only system peripheral with fixed-chip select
signals. For multiperipheral systems, address decoding and/or RDYRCV A9/ O Active-low ready/recover
latching can be used to implement chip selects. MPI_ACK signal indicating acknowl-
edgment of the transac-
Figure 44. i960/MPI tion.
Any of A11/ O Active-low interrupt
XINT[7:0] MPI_IRQ request signal.
The basic flow of a transaction on the i960/MPI inter- BE0 A0/ I Byte-enable 0 used as
face is given below. Pin descriptions are shown in MPI_BE0 address bit 0 in i960 8-bit
Table 17, and timing is shown in the ORCA Timing mode.
Characteristics section of this data sheet. For both read BE1 A1/ I Byte-enable 1 used as
and write transactions, the address latch enable (ALE) MPI_BE1 address bit 1 in i960 8-bit
is set up by the i960 at the FPGA to the falling edge of mode.
the clock. The address, byte enables, chip selects, and
read/write (read low, write high) signals are normally
Data Sheet
Microprocessor Interface (MPI) (continued) data written by the host processor from the D[7:0] pins
once the USTART signal is asserted. The user logic
MPI Interface to FPGA ends a transaction by asserting an active-high user
end (UEND) signal to the MPI.
The MPI interfaces to the user-programmable FPGA The MPI will insert wait-states in the host processor
logic using a 4-bit address, read/write control signal, bus cycles, holding the host processor until the user-
interrupt request signal, and user start and user end logic completes its task and returns a UEND signal,
handshake signals. Timing numbers are provided so upon which the MPI generates an acknowledge signal.
that the user-logic data transfers can be performed syn- If the host processor is reading from the FPGA, the
chronously with the host processor (PowerPC or i960) user logic must have the read data available on the
interface clock or asynchronously. Table 18 shows the D[7:0] pins of the FPGA when the UEND signal is
internal interface signals between the MPI and the asserted. If the user logic is fast or if the MPI user
FPGA user-programmable logic. All of the signals are address is being decoded for use as a control signal,
connected to the MPI in the upper-left corner of the the MPI transaction time can be minimized by routing
device except for the D[7:0] and CLK signals that come the USTART signal directly to the UEND input of the
directly from the I/O pin. MPI. The timing section of this data sheet contains a
The 4-bit addressing from the MPI to the PLCs allows parameter table with delay, setup, and hold timing
for up to 16 locations to be addressed by the host pro- requirements to operate the user-logic either synchro-
cessor. The user address space of the MPI does not nously or asynchronously with the MPI host interface
address any hard register. Rather, the user is free to clock.
construct registers from FFs, latches, or RAM that can The user-logic may also assert an active-low interrupt
be selected by the addressing. Alternately, the decoded request (UIRQ) to the MPI, which, in turn, asserts an
address signals may be used as control signals for interrupt to the host processor. Assertion of an inter-
other functions such as state machines or timers. rupt request is asynchronous to the host processor
The transaction sequence between the MPI and the clock and any read or write transaction occurring in the
user-logic is as follows. When the host processor ini- MPI. The user-logic is responsible for providing any
tiates a transaction as discussed in the preceding sec- required interrupt vectors for the host processor, and
tions, the MPI outputs the 4-bit user address (UA[3:0]) the user-logic must deassert the interrupt request once
and the read/write control signal (URDWR, which is serviced. If the interrupt request is not deasserted in
read-high, write-low regardless of host processor), and the user logic, it will continue to be asserted to the host
then asserts the user start signal, USTART. During a processor via the MPI_IRQ pin.
write from the host processor, the user logic can accept
Table 18. MPI Internal Interface Signals
Signal MPI I/O Function

UA[3:0] O User Logic Address. Addresses up to 16 unique user registers or use as control
signals.
URDWRN O User Logic Read/Write Control Signal. High indicates a read from user logic by
the host processor, low indicates a write to user-logic by the host processor.
USTART O Active-High User Start Signal. Indicates the start of an MPI transaction between
the host processor and the user logic.
UEND I Active-High User End Signal. Indicates that the user-logic is finished with the
current MPI transaction.
UIRQ I Active-Low Interrupt. Sends request from the user-logic to the host processor.
D[7:0] FPGA I/O User Data. Eight data bits come directly from the FPGA pins—not through the
MPI.
MPI_CLK FPGA I MPI Clock. The MPI clock is sourced by the host processor and comes directly
from the FPGA pin—not through the MPI.
Data Sheet
Microprocessor Interface (MPI) (continued)
MPI Setup and Control

The MPI has a series of addressable registers that provide MPI control and status, configuration and readback data
transfer, FPGA device identification, and a dedicated user scratchpad register. All registers are 8 bits wide. The
address map for these registers and the user-logic address space are shown in Table 19, followed by descriptions
of the register and bit functions. Note that for all registers, the most significant bit is bit 7, and the least significant bit
is bit 0.
Table 19. MPI Setup and Control Registers
Address
Register
(Hex)
00 Control Register 1.
01 Control Register 2.
02 Scratchpad Register.
03 Status Register.
04 Configuration/Readback Data Register.
05 Readback Address Register 1 (bits [7:0]).
06 Readback Address Register 2 (bits [15:8]).
07 Device ID Register 1 (bits [7:0]).
0A Device ID Register 4 (bits [31:24]).
0B—0F Reserved.
10—1F User-definable Address Space.
Control Register 1
The MPI control register 1 is a read/write register. The host processor writes a control byte to configure the MPI. It
is readable by the host processor to verify the status of control bits previously written.
Table 20. MPI Setup and Control Registers Descriptions
Bit # Description
Bit 0 GSR Input. Setting this bit to a 1 invokes a global set/reset on the FPGA. The host processor must
return this bit to a 0 to remove the GSR signal. GSR does not affect the registers at MPI addresses 0
through F hexadecimal or any configuration registers. Default state = 0.
Bit 1 Reserved.
Bit 2 Reserved.
Bit 3 Reserved.
Bit 4 Reserved.
Bit 5 RD_CFG Input. Changing this bit to a 0 after configuration will initiate readback. The host processor
must return this bit to a 1 to remove the RD_CFG signal. Since this bit works exactly like the RD_CFG
input pin, please see the FPGA pin descriptions for more information on this signal. Default state = 1.
Bit 6 Reserved.
Bit 7 PRGM Input. Setting this bit to a 0 causes the FPGA to begin configuration and resets the boundary-
scan circuitry. The host processor must return this bit to a 1 to remove the PRGM signal. Since this bit
works exactly like the PRGM input pin (except that it does not reset the MPI), please see the FPGA pin
descriptions for more information on this signal. Default state = 1.
Data Sheet

Scratchpad Register
The MPI scratchpad register is an 8-bit read/write register with no defined operation. It may be used for any user-
defined function.
Control Register 2
The MPI control register 2 is a read/write register. The host processor writes a control byte to configure the MPI. It
is readable by the host processor to verify the status of control bits it had previously written.
Table 21. MPI Control Register 2
Bit # Bit Name Description

Bit 0 EN_IRQ_CFG Enable IRQ for Configuration Data Request in Daisy-Chain Configuration
Mode. Setting this bit to a 1 prior to configuration enables the IRQ signal to go active
when new data is requested for configuration writes or is available for configuration
reads to/from the configuration data register. A 0 clears the IRQ enable. This bit is
only valid for daisy-chain configuration. Default = 0.
Bit 1 EN_IRQ_ERR Enable IRQ for Bit Stream Error. Setting this bit to a 1 prior to configuration
enables the IRQ signal to go active on the occurrence of a bit stream error during
configuration. A 0 clears the IRQ enable. This bit only has effect while in configura-
tion mode. Default = 0.
Bit 2 EN_IRQ_USR Enable IRQ from the User FPGA Space. Setting this bit to a 1 allows user-defined
circuitry in the FPGA to generate an interrupt to the host processor by sourcing a
logic low on the UIRQ signal in the user logic. Default = 0.
Bit 3 MP_DAISY MPI Daisy-Chain Output Enable. Setting this bit to a 1 enables daisy-chain output
of the configuration data. See the Configuration section of this data sheet for daisy-
chain configuration details. Default = 0.
Bit 4 MP_HOLD_BUS Enable Bus Holding During Daisy-Chain Configuration Mode. Setting this bit to
a 1 will cause the MPI to wait until the FPGA configuration logic has serialized a
byte of configuration data before acknowledging the transaction. The data is only
serialized if the MP_DAISY (bit 3 above) control bit is set to 1. If MP_HOLD_BUS is
set to 0, the MPI will immediately acknowledge a configuration data byte transfer.
Immediate acknowledgment allows the host processor to perform other tasks during
FPGA configuration by polling the MPI status register (or by interrupt) and only write
configuration data when the FPGA is ready. Default = 0.
Bit 5 MP_USER MPI User Mode Enable. Setting this bit to a 1 will enable the MPI for user mode
operation. MP_USER must be set prior to the FPGA DONE signal going high during
configuration. The MPI may also be enabled for user operation via the configuration
bit stream. Default = 0.
Bit 6 Reserved —
Bit 7 Reserved —
Data Sheet

Status Register
The microprocessor interface status register is a read-only register, providing information to the host processor.
Table 22. Status Register
Bit # Description
Bit 0 Reserved.
Bit 1 Data Ready. Set by the MPI, a 1 on this bit during configuration alerts the host processor that the FPGA
is ready for another byte of configuration data. During byte-wide readback, the MPI sets this bit to a 1 to
tell the host processor that a byte of configuration data is available for reading. This bit is cleared by a
host processor access (read or write) to the configuration data register.
Bit 2 IRQ Pending. The MPI sets this bit to 1 to indicate to the host processor that the FPGA has a pending
interrupt request. This bit may be used for the host processor to poll for interrupts if the MPI_IRQ pin out-
put of the FPGA has been masked at the host processor. This bit is set to 0 when the status register is
read. Interrupt requests from the FPGA user space must be cleared in FPGA user logic in addition to
reading this bit.
Bits Bit Stream Error Flags. Bits 3 and 4 are set by the MPI to indicate any error during FPGA configura-
[4:3] tion. See bit 2 of control register 2 for the capability to alert the host processor of an error via the IRQ
signal during configuration. In the truth table below, bit 3 is the LSB (bit on right). These bits are cleared
to 0 when PRGM goes active:
00 = No error
01 = ID error
10 = Checksum error
11 = Stop-bit/alignment error
Bit 5 Reserved.
Bit 6 INIT. This bit reflects the binary value of the FPGA INIT pin.
Bit 7 DONE. This bit reflects the binary value of the FPGA DONE pin.
Configuration Data Register

The MPI configuration data register is a writable register in configuration mode and a readable register in readback
mode. For FPGA configuration, this is where the configuration data bytes are sequentially written by the host pro-
cessor. Similarly, for readback mode, the MPI provides the readback data bytes in this register for the host proces-
sor.
Readback Address Register 1

The MPI readback address register 1 is a writable register used to accept the least significant address byte
(bits [7:0]) of the configuration data location to be read back.
Readback Address Register 2

The MPI readback address register 2 is a writable register used to accept the most significant address byte
(bits [15:8]) of the configuration data location to be read back.
Data Sheet

Device ID Registers
The MPI device ID is broken into four registers holding 1 byte each. The device ID that is available through the MPI
is the same as the boundary-scan ID code, except that the device ID in the MPI has a reverse bit order. There is no
means to overwrite any of the device ID as can be done with the boundary-scan ID, but the MPI scratchpad register
can be used as a personalization register. The format for the entire device ID is shown below followed by family and
device values and the partitioning of the device ID into the four device ID registers.
Table 23. Device ID Code
Version Part* Family Manufacturer MSB

4 bits 10 bits 6 bits 11 bits 1 bit
Example: (First version of OR3C80) 0000 0110100000 110000 00000011101 1
* PLC array size of FPGA.
Table 24 shows the family and device values for all parts covered by this data sheet.
Table 24. Series 3 Family and Device ID Values
Family ID Device ID
Part Name
(Hex) (Hex)
OR3T20 03 0C
OR3T30 03 0E
OR3T55 03 12
OR3C/T80 03 16
OR3T125 03 1C
Table 25 describes the device IDs for all parts covered by this data sheet as they are partitioned into the four regis-
ters found in the MPI.
Table 25. ORCA Series 3 Device ID Descriptions
Device ID Register 1
Bit 0 Logic 1. This bit is always a one.
Bits [7:1] 0011101, the 7 least significant bits of the manufacturer ID.
Bits [3:0] 0000, the 4 most significant bits of the manufacturer ID.
Bits [7:4] The 4 least significant bits of the 10-bit part number.
Bits [5:0] The 6 most significant bits of the 10-bit part number.
Bits [7:6] The 2 least significant bits of the device family code.
Bits [3:0] The 4 most significant bits of the device family code.
Bits [7:4] The 4-bit device version code.
Data Sheet
Programmable Clock Manager (PCM) ner ExpressCLK that feeds the CLKCNTRL blocks on
the two sides adjacent to the PCM, and one to the sys-
The ORCA programmable clock manager (PCM) is a tem clock spine network through general routing. Fig-
special function block that is used to modify or condi- ure 45 shows a high-level block diagram of the PCM.
tion clock signals for optimum system performance. Functionality of the PCM is programmed during opera-
Some of the functions that can be performed with the tion through a read/write interface internal to the FPGA
PCM are clock skew reduction (both internal and board array or via the configuration bit stream. The internal
level), duty-cycle adjustment, clock delay reduction, FPGA interface comprises write enable and read
clock phase adjustment, and clock frequency multipli- enable signals, a 3-bit address bus, an 8-bit input (to
cation/division. Due to the different capabilities the PCM) data bus, and an 8-bit output data bus. There
required by customer application, each PCM contains is also a PCM output signal, LOCK, that indicates a sta-
both a PLL (phase-locked loop) and a DLL (delayed- ble output clock state. These signals are used to pro-
locked loop) mode. By using PLC logic resources in gram a series of registers to configure the PCM
conjunction with the PCM, many other functions, such functional core for the desired functionality.
as frequency synthesis, are possible.
Operation of the PCM is divided into two modes, delay-
There are two PCMs on each Series 3 device, one in locked loop (DLL) and phase-locked loop (PLL). Some
the lower left corner and one in the upper right corner. operations can be performed by either mode and some
Each can drive two different, but interrelated clock net- are specific to a particular mode. These will be
works inside the FPGA. Each PCM can take a clock described in each individual mode section. In general,
input from the ExpressCLK pad in its corner or from DLL mode is preferable to PLL mode for the same
general routing resources. There are also two input function because it is less sensitive to input clock
sources that provide feedback to the PCM from the noise.
PLC array. One of these is a dedicated corner Express-
CLK feedback, and the other is from general routing. In the discussions that follow, the duty cycle is the per-
Each PCM sources two clock outputs, one to the cor- cent of the clock period during which the output clock is
high.
USER CONTROL SIGNALS
PCM-FPGA
INTERFACE
CORNER EXPRESSCLK IN EXPRESSCLK OUT

PCM CORE
FUNCTIONS
GENERAL CLOCKIN SYSTEM CLOCK OUT
(FROM GENERAL ROUTING) (TO GENERAL ROUTING)
FEEDBACK FEEDBACK CLOCK

ExpressCLK FROM ROUTING
5-5828(F)
Figure 45. PCM Block Diagram
Data Sheet
Programmable Clock Manager (PCM) (continued)
PCM Registers
The PCM contains eight user-programmable registers used for configuring the PCM’s functionality. Table 26 shows
the mapping of the registers and their functions. See Figure 46 for more information on the location of PCM ele-
ments that are discussed in the table. The PCM registers are referenced in the discussions that follow. Detailed
explanations of all register bits are supplied following the functional description of the PCM.
Table 26. PCM Registers
Address Function
0 Divider 0 Programming. Programmable divider, DIV0, value and DIV0 reset bit. DIV0 can
divide the input clock to the PCM or can be bypassed.
divide the feedback clock input to the PCM or can be bypassed. Valid only in PLL mode.
divide the output of the tapped delay line or can be bypassed and is only valid for the
ExpressCLK output.
3 DLL 2x Duty-Cycle Programming. DLL mode clock doubler (2x) duty-cycle selection.
4 DLL 1x Duty-Cycle Programming. Depending on the settings in other registers, this regis-
ter is for:
a. PLL mode phase/delay selection;
b. DLL mode 1x duty cycle selection; and
c. DLL mode programmable delay.
5 Mode Programming. DLL/PLL mode selection, DLL 1x/2x clock selection, phase detector
feedback selection.
6 Clock Source Status/Output Clock Selection Programming. Input clock selection, feed-
back clock selection, ExpressCLK output source selection, system clock output source selec-
tion.
7 PCM Control Programming. PCM power, reset, and configuration control.
Data Sheet
PCM
INPUT CHARGE PUMP

CLOCK AND
LOW-PASS FILTER
PHASE
DETECTOR
EXPRESSCLK 0
PAD 1 PROGRAMMABLE
FROM S0 DIVIDER
2 DIV0 0
ROUTING PROGRAMMABLE DELAY
3 S4 LINES (32 TAPS) 1
1 S2 FEEDBACK
0 CLOCK
EXPRESSCLK
0 FEEDBACK
REGISTER 7 PROGRAMMABLE
1...7 1...7 1...7 1...7 1
REGISTER 6 DIVIDER S3
S5 S6 S7 S8 DIV1 2 FROM
ROUTING
REGISTER 5 3
0 0
REGISTER 4
1 1 EXPRESSCLK
REGISTER 3 S4 S4
2 2 OUTPUT
REGISTER 2 PROGRAMMABLE 3
3 DIVIDER
REGISTER 1 DIV2
REGISTER 0 COMBINATORIAL
LOGIC
0
FPGA-PCM INTERFACE 1 SYSTEM CLOCK
S10 OUTPUT
2
0 3
DATA_IN[7:0]
ADDR_IN[2:0]
DATA_OUT[7:0]
WE
RE
LOCK
5-5829(F)
Figure 46. PCM Functional Block Diagram
Data Sheet
Programmable Clock Manager (PCM) 1x Clock Duty-Cycle Adjustment

(continued) A duty-cycle adjusted replica of the input clock can be
constructed in DLL mode. The duty cycle can be
Delay-Locked Loop (DLL) Mode adjusted in 1/32 (3.125%) increments of the input clock
period. DLL 1x clock mode is selected by setting bit 4
DLL mode is used for implementing a delayed clock of register five to a 1, and output clock source selection
(phase adjustment), clock doubling, and duty cycle is selected by setting register six, bits [5:4] to 01 for
adjustment. All DLL functions stem from a delay line ExpressCLK output, and/or bits [7:6] to 01 for system
with 32 taps. The delayed input clock is pulled from var- clock output. The duty-cycle percentage value is
ious taps and processed to implement the desired entered in register four. See register four programming
result. There is no feedback clock in DLL mode, provid- details for more information. Duty cycle values are also
ing a very stable output and a fast lock time for the out- shown in the third column of Table 27.
put clock.
DLL mode is selected by setting bit 0 in PCM register Table 27. DLL Mode Delay/1x Duty Cycle
five to a 0. The settings for the various submodes of Programming Values
DLL mode are described in the following paragraphs. Register 4 [7:0] Delay Duty Cycle
Divider DIV0 may be used with any of the DLL modes 76543210 (CLK_IN/32) (% of CLK_IN)
to divide the input clock by an integer factor of 1 to 8
prior to implementation of the DLL process. 00XXX000 1 3.125
00XXX001 2 6.250
Delayed Clock 00XXX010 3 9.375
A delayed version of the input clock can be constructed 00XXX011 4 12.500
in DLL mode. The output clock can be delayed by incre- 00XXX100 5 15.625
ments of 1/32 of the input clock period. Express CLK 00XXX101 6 18.750
and system CLK outputs in delay modes are selected 00XXX110 7 21.875
by setting register six, bits [5:4] to 10 or 11 for Express- 00XXX111 8 25.000
CLK output, and/or bits [7:6] to 10 for system clock out-
01XXX000 9 28.125
put. The delay value is entered in register four. See
register four programming details for more information. 01XXX001 10 31.250
Delay values are also shown in the second column of 01XXX010 11 34.375
Table 27. 01XXX011 12 37.500
Note that when register six, bits [5:4] are set to 11, the 01XXX100 13 40.625
ExpressCLK output is divided by an integer factor from 01XXX101 14 43.750
1 to 8 while the system clock cannot be divided. The 01XXX110 15 46.875
ExpressCLK divider is provided so that the I/O clocking 01111XXX 16 50.000
provided by the ExpressCLK can operate slower than 10000XXX 17 53.125
the internal system clock. This allows for very fast inter-
10001XXX 18 56.250
nal processing while maintaining slower interface
speeds off-chip for improved noise and power perfor- 10010XXX 19 59.375
mance or to interoperate with slower devices in the sys- 10011XXX 20 62.500
tem. The divisor of the ExpressCLK frequency is 10100XXX 21 65.625
selected in register two. See the register two program- 10101XXX 22 68.750
ming details for more information. 10110XXX 23 71.875
10111XXX 24 75.000
11000XXX 25 78.125
11001XXX 26 81.250
11010XXX 27 84.375
11011XXX 28 87.500
11100XXX 29 90.625
11101XXX 30 93.750
11110XXX 31 96.875
Data Sheet
Programmable Clock Manager (PCM) Clock Delay Minimization

(continued) PLL mode can be used to minimize the effects of the
input buffer and input routing delay on the clock signal.
2x Clock Duty-Cycle Adjustment PLL mode causes a feedback clock signal to align in
phase with the input clock (refer back to the block dia-
A doubled-frequency, duty-cycle adjusted version of
gram in Figure 45) so that the delay between them is
the input clock can be constructed in DLL mode. The
effectively eliminated.
first clock cycle of the 2x clock output occurs when the
input clock is high, and the second cycle occurs when There is a dedicated feedback path from an adjacent
the input clock is low. The duty cycle can be adjusted in middle CLKCNTRL block to the PCM. Using the corner
1/32 (6.25%) increments of the input clock period. ExpressCLK pad as the input to the PCM and using this
Additionally, each of the two doubled-clock cycles that dedicated feedback path, the clock from the Express-
occurs in a single input clock cycle may be adjusted to CLK output of the PCM, as viewed at the CLKCNTRL
have different duty cycles. DLL 2x clock mode is block, will be phase-aligned with the ExpressCLK input
selected by setting bit 4 of register five to a 1, and by to the PCM. These relationships are diagrammed in
setting register six, bits [5:4] to 01 for ExpressCLK out- Figure 47.
put, and/or bits [7:6] to 01 for system clock output. The
A feedback clock can also be input to the PCM from
duty-cycle percentage value is entered in register
general routing. This allows for compensating for delay
three. See register three programming details for more
between the PCM input and a point in the general rout-
information. Duty-cycle values where both cycles of the
ing. The use of this routed-feedback path is not gener-
doubled clock have the same duty cycle are also
ally recommended. Because compensation is based
shown in Table 28.
on the programmable routing, the amount of clock
delay compensation can vary between FPGA lots and
Table 28. DLL Mode Delay/2x Duty Cycle
fabrication processes, and will vary each time that the
Programming Values
feedback line is routed using different resources. Con-
Register 3 [7:0] Duty Cycle tact Lattice for application notes regarding the use of
76543210 (%) routed-feedback delay compensation.
00000000 6.25
00001001 12.50 DELAY
00010010 18.75 COMPENSATION EQUALS DELAY
00011011 25.00 CORNER

EXPRESSCLK
INPUT
00100100 31.25
00101101 37.50 CLKCNTRL
EXPRESSCLK
OUTPUT WITHOUT
00110110 43.75 USING PCM
DELAY IS COMPENSATED
00111111 50.00 CLKCNTRL
EXPRESSCLK
11000000 56.25 OUTPUT
USING PCM
11001001 62.50
11010010 68.75 5-5980(F)
11011011 75.00 Figure 47. ExpressCLK Delay Minimization

11100100 81.25 Using the PCM
11101101 87.50
11110110 93.75
Phase-Locked Loop (PLL) Mode

The PLL mode of the PCM is used for clock multiplica-
tion (1/8x to 64x) and clock delay minimization func-
tions. PLL functions make use of the PCM dividers and
use feedback signals, often from the FPGA array. The
use of feedback is discussed with each PLL submode.
PLL mode is selected by setting bit 0 of register five to
1.
Data Sheet
Programmable Clock Manager (PCM) The multiplied output is selected by setting register six,
bits [5:4] to 10 or 11 for ExpressCLK output and/or bits
(continued)
[7:6] to 10 for system clock output. Note that when reg-
ister six, bits [5:4] are set to 11, the ExpressCLK output
Clock Multiplication
is divided by DIV2, while the system clock cannot be
An output clock that is a multiple (not necessarily an divided. The ExpressCLK divider is provided so that the
integer multiple) of the input clock can be generated in I/O clocking provided by the ExpressCLK can operate
PLL mode. The multiplication ratio is programmed in slower than the internal system clock. This allows for
the division registers DIV0, DIV1, and DIV2. Note that very fast internal processing while maintaining slower
DIV2 applies only to the ExpressCLK output of the interface speeds off-chip for improved noise and power
PCM and any reference to DIV2 is implicitly 1 for the performance or to interoperate with slower devices in
system clock output of the PCM. The clock multiplica- the system.
tion formulas when using ExpressCLK feedback are:
It is also necessary to configure the internal PCM oscil-
DIV1 lator for operation in the proper frequency range.
FExpressCLK_OUT = FINPUT_CLOCK •
DIV0 Table 29 and Table 30 show the settings required for
register four for a given frequency range for Series 3C
FSYSTEM_CLOCK_OUT = FExpressCLK_OUT • DIV2 and 3T devices. In addition, the acquisition time is
shown for each frequency range. This is the time that is
Where the values of DIV0, DIV1, and DIV2 range from
required for the PCM to acquire LOCK. The PCM oscil-
1 to 8.
lator frequency range is chosen based on the desired
The ExpressCLK multiplication range of output clock output frequency at the system clock output. If using
frequencies is, therefore, from 1/8x up to 8x, with the the ExpressCLK output, the equivalent system clock
system clock range up to 8x the ExpressCLK frequency frequency can be selected by multiplying the expected
or 64x the input clock frequency. If system clock feed- ExpressCLK output frequency by the value for DIV2.
back is used, the formulas are: Choose the nominal frequency from the table that is
closest to the desired frequency, and use that value to
DIV1 program register four. Minor adjustments to match the
FSYSTEM_CLOCK_OUT = FINPUT_CLOCK •
DIV0 exact input frequency are then performed automatically
by the PCM.
FExpressCLK_OUT = FSYSTEM_CLOCK/DIV2
The divider values, DIV0, DIV1, and DIV2 are pro-
grammed in registers zero, one, and two, respectively.
Data Sheet
Programmable Clock Manager (PCM)

(continued)
Table 29. PCM Oscillator Frequency Range 3Txxx Table 30. PCM Oscillator Frequency Range 3Cxx
System System
Clock Clock
Output Output
Frequency T Frequency T
Register 4 Min (MHz) Max Acquisition Register 4 Min (MHz) Max Acquisition
76543210 (MHz) NOM (MHz) (µs) 76543210 (MHz) NOM (MHz) (µs)
00XXX010 17.00 58.50 100.00 36.00 00XXX010 10.50 73.00 135.00 36.00
00XXX011 16.10 52.50 89.00 37.00 00XXX011 10.00 68.00 126.00 37.00
00XXX100 15.17 49.00 82.80 38.00 00XXX100 9.50 63.00 117.00 38.00
00XXX101 14.25 45.00 76.50 39.00 00XXX101 9.10 58.50 108.00 39.00
00XXX110 13.33 41.50 70.30 40.00 00XXX110 8.60 53.80 99.00 40.00
00XXX111 12.40 38.00 64.00 41.00 00XXX111 8.10 49.00 90.00 41.00
01XXX000 12.20 36.75 61.30 43.75 01XXX000 7.80 47.70 87.50 43.80
01XXX001 12.10 35.00 58.00 46.50 01XXX001 7.60 46.30 85.00 46.50
01XXX010 11.90 33.00 54.30 49.25 01XXX010 7.30 45.00 82.50 49.30
01XXX011 11.70 31.30 51.00 52.00 01XXX011 7.10 43.60 80.00 52.00
01XXX100 11.10 30.00 49.40 54.75 01XXX100 6.80 42.10 77.50 55.00
01XXX101 10.50 29.15 47.80 57.50 01XXX101 6.50 40.75 75.00 57.50
01XXX110 10.00 28.10 46.20 60.25 01XXX110 6.30 39.40 72.50 60.30
01XXX111 9.40 27.00 44.60 63.00 01XXX111 6.00 38.00 70.00 63.00
10000XXX 9.20 26.25 43.30 65.40 10000XXX 5.90 37.40 68.80 65.40
10001XXX 9.00 25.65 42.30 67.80 10001XXX 5.90 36.70 67.50 67.80
10010XXX 8.80 25.00 41.30 70.10 10010XXX 5.80 36.00 66.30 70.10
10011XXX 8.60 24.45 40.30 72.50 10011XXX 5.80 35.40 65.00 72.50
10100XXX 8.40 23.70 39.00 74.90 10100XXX 5.70 35.00 63.80 74.90
10101XXX 8.10 22.90 37.70 77.30 10101XXX 5.60 34.10 62.50 77.30
10110XXX 7.90 22.20 36.50 79.60 10110XXX 5.60 33.50 61.30 79.60
10111XXX 7.70 21.50 35.20 82.00 10111XXX 5.50 32.80 60.00 82.00
11000XXX 7.60 20.80 34.00 84.30 11000XXX 5.40 32.10 58.80 84.30
11001XXX 7.45 20.10 32.80 86.50 11001XXX 5.40 31.50 57.50 86.50
11010XXX 7.30 19.45 31.60 88.80 11010XXX 5.30 30.70 56.30 88.80
11011XXX 7.20 18.85 30.50 91.00 11011XXX 5.30 30.10 55.00 91.00
11100XXX 6.60 18.30 30.00 93.30 11100XXX 5.20 29.50 53.80 93.30
11101XXX 6.00 17.70 29.40 95.50 11101XXX 5.10 28.80 52.50 95.50
11110XXX 5.50 17.10 28.60 97.80 11110XXX 5.10 28.20 51.30 97.80
11111XXX 5.00 16.50 28.00 100.00 11111XXX 5.00 27.50 50.00 100.00
Note: Use of settings in the first three rows is not recommended. Note: Use of settings in the first three rows is not recommended.
X means don’t care. X means don’t care.
Data Sheet
Programmable Clock Manager (PCM) PCM Operation

(continued)
Several features are available for the control of the
PCM’s overall operation. The PCM may be programma-
PCM/FPGA Internal Interface bly enabled/disabled via bit 0 of register 7. When dis-
abled, the analog power supply of the PCM is turned
Writing and reading the PCM registers is done through
off, conserving power and eliminating the possibility of
a simple asynchronous interface that connects with the
inducing noise into the system power buses. Individual
FPGA routing resources. Reads from the PCM by the
bits (register 7, bits [2:1]) are provided to reset the DLL
FPGA logic are accomplished by setting up the 3-bit
and PLL functions of the PCM. These resets affect only
address, A[2:0], and then applying an active-high read
the logic generating the DLL or PLL function; they do
enable (RE) pulse. The read data will be available as
not reset the divider values (DIV0, DIV1, DIV2) or reg-
long as RE is held high. The address may be changed
isters [7:0]. The global set/reset (GSRN) is also pro-
while RE is high, to read other addresses. When RE
grammably controlled via register 7, bit 7. If register 7,
goes low, the data output bus is 3-stated.
bit 7 is set to 1, GSRN will have no effect on the PCM
Writes to the PCM by the FPGA logic are performed by logic, allowing the clock to operate during a global
applying the write data to the data input bus of the set/reset. This function allows the FPGA to be reset
PCM, applying the 3-bit address to write to, and assert- without affecting a clock that is sent off-chip and used
ing the write enable (WE) signal high. Data will be writ- elsewhere in the system. Bit 6 of register 7 affects the
ten by the high-going transition of the WE pulse. functionality of the PCM during configuration. If set to 1,
this bit enables the PCM to operate during configura-
The read enable (RE) and write enable (WE) signals
tion, after the PCM has been configured. The PCM
may not be active at the same time. For detailed timing
functionality is programmed via the bit stream. If regis-
information and specifications, see the Timing Charac-
ter 7, bit 6 is 0, the PCM cannot function and its power
teristics section of this data sheet.
supply is disabled until after the configuration DONE
The LOCK signal output from the PCM to the FPGA signal goes high.
routing indicates a stable output clock signal from the
When the PCM is powered up via register 7, bit 0, there
PCM. The LOCK signal is high when the PCM output
is a wake-up time associated with its operation. Follow-
clock parameters fall within the programmed values
ing the wake-up time, the PCM will begin to fully func-
and the PCM specifications for jitter. Due to phase cor-
tion, and, following an acquisition time during which the
rections that occur internal to the PCM, the LOCK sig-
output clock may be unstable, the PCM will be in
nal might occasionally pulse low when the output clock
steady-state operation. There is also a shutdown time
is out of specification for only one or two clock cycles
associated with powering off the PCM. The output clock
(high jitter due to temperature, voltage fluctuation, etc.)
will be unstable during this period. Waveforms and tim-
To accommodate these pulses, it is suggested that the
ing parameters can be found in the Timing Characteris-
user integrate the LOCK signal over a period suitable
tics section of this data sheet.
to their application to achieve the desired usage of the
LOCK signal.
The LOCK signal will also pulse high and low during
the acquisition time as the output clock stabilizes. True
LOCK is only achieved when the LOCK signal is a solid
high. Again, it is suggested that the user integrate the
LOCK signal over a time period suitable to the subject
application.
Data Sheet
PCM Detailed Programming

Descriptions of bit fields and individual control bits in the PCM control registers are provided in Table 31. Refer to
Figure 46 for more information on the location of the PCM elements that are discussed. In the following discussion,
the duty cycle is in the percentage of the clock period where the clock is high.
Table 31. PCM Control Registers
Bit # Function
Register 0—Divider 0 Programming
4-Bit Divider, DIV0, Value. This value enables the input clock to immediately be divided by a
Bits [3:0]
value from 1 to 8. A 0 value (the default) indicates that DIV0 is bypassed (no division). Bypass
incurs less delay than dividing by 1. Hexadecimal values greater than 8 for bits [3:0] yield their
modulo 8 value. For example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder
9/8 = 1).
Bits [6:4] Reserved.
Bit 7 DIV 0 Reset Bit. DIV0 may not be reset by GSRN depending on the value of register 7, bit 7.
This bit may be set to 1 to reset DIV0 to its default value. Bit 0 must be set to 0 (the default) to
remove the reset.
Bits [3:0] 4-Bit Divider, DIV1, Value. This value enables the feedback clock to be divided by a value from 1
to 8. A 0 value (the default) indicates that DIV1 is bypassed (no division). Bypass incurs less
delay than dividing by 1. Hexadecimal values greater than 8 for bits [3:0] yield their modulo 8
value. For example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder 9/8 = 1).
Bit 7 DIV1 Reset Bit. DIV1 may not be reset by GSRN, depending on the value of register 7, bit 7.
remove the reset.
Bits [3:0] 4-Bit Divider, DIV2, Value. This value enables the tapped delay line output clock driven onto
ExpressCLK to be divided by a value from 1 to 8. A 0 value (the default) indicates that DIV2 is
bypassed (no division). Bypass incurs less delay than dividing by 1. Hexadecimal values greater
than 8 for bits [3:0] yield their modulo 8 value. For example, if bits [3:0] are 1001 (9 hex), the
result is divide by 1 (remainder 9/8 = 1).
Bit 7 DIV2 Reset Bit. DIV2 may not be reset by GSRN, depending on the value of register 7, bit 7.
remove the reset.
Register 3—DLL 2x Duty-Cycle Programming
Bits [2:0] Duty-cycle selection for the doubled clock period associated with the input clock high. The duty
cycle is (value of bit 6) * 50% + ((value of bits [2:0]) + 1) * 6.25%. See the description for bit 6.
Bits [5:3] Duty-cycle selection for the doubled clock period associated with the input clock low. The duty
cycle is (value of bit 7) * 50% + ((value of bits [2:0]) + 1) * 6.25%. See the description for bit 7.
Bit 6 Master duty-cycle control for the first clock period of the doubled clock: 0 = less than or equal to
50%, 1 = greater than 50%.
Bit 7 Master duty-cycle control for the second clock period of the doubled clock: 0 = less than or equal
to 50%, 1 = greater than 50%. Example: Both clock periods having a 62.5% duty cycle, bits [7:0]
are 11 001 001.
Data Sheet

Table 31. PCM Control Registers (continued)
Bit # Function
Register 4—DLL 1x Duty-Cycle Programming
Bits [2:0] Duty-Cycle/Delay Selection for Duty Cycle/Delays Less Than or Equal to 50%. The duty-
cycle/delay is (value of bits [7:6]) * 25% + ((value of bits [2:0]) + 1) * 3.125%. See the description
for bits [7:6].
Bits [5:3] Duty-Cycle/Delay Selection for Duty Cycle/Delays Greater Than 50%. The duty-cycle/delay
is (value of bits [7:6]) * 25% + ((value of bits [5:3]) + 1) * 3.125%. See the description for bits [7:6].
Bits [7:6] Master Duty Cycle Control:
00: duty cycle 3.125% to 25%
01: duty cycle 28.125% to 50%
10: duty cycle 53.125% to 75%
11: duty cycle 78.125% to 96.875%
Example: A 40.625% duty cycle, bits [7:0] are 01 XXX 100, where X is a don’t care because the
duty cycle is not greater than 50%.
Example: The PCM output clock should be delayed 96.875% (31/32) of the input clock period.
Bits [7:0] are 11110XXX, which is 78.125% from bits [7:6] and 18.75% from bits [5:3]. Bits [2:0]
are don’t care (X) because the delay is greater than 50%.
Register 5—Mode Programming
Bit 0 DLL/PLL Mode Selection Bit. 0 = DLL, 1 = PLL. Default is DLL mode.
Bit 1 Reserved.
Bit 2 PLL Phase Detector Feedback Input Selection Bit. 0 = feedback signal from routing/
ExpressCLK, 1 = feedback from programmable delay line output. Default is 0. Has no effect in
DLL mode.
Bit 3 Reserved.
Bit 4 1x/2x Clock Selection Bit for DLL Mode. 0 = 1x clock output, 1 = 2x clock output. Default is 1x
clock output. Has no effect in PLL mode.
Data Sheet

Table 31. PCM Control Registers (continued)
Bit # Function
ExpressCLK Output Source Selector. Default is 00.
Bits [5:4]
00: PCM input clock, bypass path through PCM
01: DLL output
10: tapped delay line output
11: divided (DIV2) delay line output
Bits [7:6] System Clock Output Source Selector. Default is 00.
00: PCM input clock, bypass path through PCM
01: DLL output
10: tapped delay line output
11: reserved
Register 7—PCM Control Programming
Bit 0 PCM Analog Power Supply Switch. 1 = power supply on, 0 = power supply off.
Bit 1 PCM Reset. A value of 1 resets all PCM logic for PLL and DLL modes.
Bit 2 DLL Reset. A value of 1 resets the clock generation logic for DLL mode. No dividers or user reg-
isters are affected.
Bit 6 PCM Configuration Operation Enable Bit. 0 = normal configuration operation. During configu-
ration (DONE = 0), the PCM analog power supply will be off, the PCM output data bus is 3-stated,
and the LOCK signal is asserted to logic 0. The PCM will power up when DONE = 1.
1 = PCM operation during configuration. The PCM may be powered up (see bit 0) and begin
operation, or continue operation. The setup of the PCM can be performed via the configuration bit
stream.
Bit 7 PCM GSRN Enable Bit. 0 = normal GSRN operation. 1 = GSRN has no effect on PCM logic, so
clock processing will not be interrupted by a chip reset. Default is 0.
Data Sheet
Programmable Clock Manager (PCM) clock setup time and some margin, is the amount less
than one full clock cycle that the output clock is delayed
(continued)
from the input clock.
PCM Applications In some systems, it is desirable to operate logic from
several clocks that operate at different phases. This
The applications discussed below are only a small technique is often used in microprocessor-based sys-
sampling of the possible uses for the PCM. Check the tems to transfer and process data synchronously
Lattice website for additional application notes. between functional areas, but without incurring exces-
sive delays. Figure 48B shows an input clock and an
Clock Phase Adjustment output clock operating 180° out of phase. It also shows
The PCM may be used to adjust the phase of the input a version of the input clock that was shifted approxi-
clock. The result is an output clock which has its active mately 180° using logic gates to create an inverter.
edge either preceding or following the active edge of Note that the inverted clock is really shifted more than
the input clock. Clock phase adjustment is accom- 180° due to the propagation delay of the inverter. The
plished in DLL mode by delaying the clock. This is dis- PCM output clock does not suffer from this delay. Addi-
cussed in the Delay-Locked Loop (DLL) Mode section. tionally, the 180° shifted PCM output could be shifted
Examples of using the delayed clock as an early or late by some smaller amount to effect an early 180° shifted
phase-adjusted clock are outlined in the following para- clock that also accounts for loading effects.
graphs. In terms of degrees of phase shift, the phase of a clock
An output clock that precedes the input clock can be is adjustable in DLL mode with resolution relative to the
used to compensate for clock delay that is largely due delay increment (see Table 27):
to excessive loading. The preceding output clock is Phase Adjustment = (Delay)* 11.25, Delay < 16
really not early relative to the input clock, but is delayed Phase Adjustment = ((Delay)* 11.25) – 360, Delay > 16
almost a full cycle. This is shown in Figure 48A. The
amount of delay that is being compensated for, plus
DLL DELAY CLOCK DELAY AND SETUP

BEING COMPENSATED
INPUT CLOCK
OUTPUT CLOCK
A. Generating an Early Clock
UNINTENDED PHASE
SHIFT DUE TO DLL DELAY
INVERTER DELAY
INPUT CLOCK
PCM OUTPUT CLOCK
INVERTED INPUT CLOCK
B. Multiphase Clock Generation Using the DLL

5-5979(F)
Figure 48. Clock Phase Adjustment Using the PCM

Data Sheet
Programmable Clock Manager (PCM) Resultant signals from the PCM must meet the FPGA
timing specifications. It is possible to specify pulses by
(continued)
using duty-cycle adjustments that are too narrow to
function in the FPGA. For instance, if a 40 MHz clock is
High-Speed Internal Processing with Slow I/Os
doubled to 80 MHz and a 6.25% duty cycle is selected,
The PCM PLL mode provides two outputs, one sent to the result will be a 780 ps pulse that repeats every
the global system clock routing of the FPGA and the 12.5 ns. This pulse falls outside of the clock pulse width
other to the ExpressCLK(s) that serve the FPGA I/Os. specification and is not valid.
The ExpressCLK output of the PCM has a divide capa-
Using divider DIV2, it is possible to specify a clock mul-
bility (DIV2) that the system clock output does not. This
tiplication factor of 64 between the input clock and the
feature allows an input clock to be multiplied up to a
output system clock. As mentioned above, the resultant
higher frequency for high-speed internal processing,
frequency must meet all FPGA timing specifications.
and also allows the ExpressCLK output to be divided
The input clock must also meet the minimum specifica-
down to a lower frequency to accommodate off-FPGA
tions. An input clock rate that is below the PCM clock
data transfers. For example, a 10 MHz input clock may
minimum cannot be used even if the multiplied output is
be multiplied (see Clock Multiplication in the Phase-
within the allowable range.
Locked Loop (PLL) Mode subsection) to 25 MHz (DIV0
= 4, DIV1 = 5, DIV2 = 2) and output to the FPGA The use of the PCM to tweak a clock signal to eliminate
ExpressCLK. This allows the I/Os of the circuit to run at a particular problem, such as a single setup time viola-
25 MHz ((2 * 5)/4 * 10 MHz). The system clock will run tion, is discouraged. A small shift in delay, duty cycle, or
at DIV2 times the ExpressCLK rate, which is 2 times phase to correct a single-point problem is in essence
25 MHz, or 50 MHz. This setup allows for internal pro- an asynchronous patch to a synchronous system, mak-
cessing to occur at twice the rate of on/off device I/O ing the system less stable. This type of local problem,
transfers. as opposed to a global clock control issue like device-
wide clock delay, can usually be eliminated through
more robust design practices. If this type of change is
PCM Cautions made, the designer must be aware that depending on
the extent of the change made, the design may fail to
Cautions do apply when using the PCM. There are a operate correctly in a different speed grade or voltage
number of configurations that are possible in the PCM grade (e.g., 3C vs. 3T), or even in a different production
that are theoretically valid, but may not produce viable lot of the same device.
results. This section describes some of those situa-
tions, and should leave the user with an understanding Divider DIV2 is available in DLL mode for the Express-
of the types of pitfalls that must be avoided when modi- CLK output, but its use is not recommended with duty-
fying clock signals. cycle adjusted clocks.
Data Sheet
FPGA States of Operation Initialization
Prior to becoming operational, the FPGA goes through Upon powerup, the device goes through an initialization
a sequence of states, including initialization, configura- process. First, an internal power-on-reset circuit is trig-
tion, and start-up. Figure 49 outlines these three FPGA gered when power is applied. When VDD reaches the
states. voltage at which portions of the FPGA begin to operate
(2.5 V to 3 V for the OR3Cxx, 2.2 V to 2.7 V for the
OR3Txxx), the I/Os are configured based on the con-
POWERUP
figuration mode, as determined by the mode select
– POWER-ON TIME DELAY
inputs M[2:0]. A time-out delay is initiated when VDD
reaches between 3.0 V and 4.0 V (OR3Cxx) or 2.7 V to
3.0 V (OR3Txxx) to allow the power supply voltage to
INITIALIZATION
– CLEAR CONFIGURATION
stabilize. The INIT and DONE outputs are low. At pow-
MEMORY erup, if VDD does not rise from 2.0 V to VDD in less than
– INIT LOW, HDC HIGH, LDC LOW
25 ms, the user should delay configuration by inputting
a low into INIT, PRGM, or RESET until VDD is greater
RESET, than the recommended minimum operating voltage
BIT INIT,
YES ERROR OR
(4.75 V for OR3Cxx commercial devices and 3.0 V for
YES
PRGM OR3Txxx devices).
LOW
NO NO
At the end of initialization, the default configuration
CONFIGURATION option is that the configuration RAM is written to a low
– M[3:0] MODE IS SELECTED RESET
– CONFIGURATION DATA FRAME OR state. This prevents shorts prior to configuration. As a
PRGM
WRITTEN
– INIT HIGH, HDC HIGH, LDC LOW LOW configuration option, after the first configuration (i.e., at
– DOUT ACTIVE reconfiguration), the user can reconfigure without
clearing the internal configuration RAM first. The
START-UP
active-low, open-drain initialization signal INIT is
– ACTIVE I/O PRGM released and must be pulled high by an external resis-
– RELEASE INTERNAL RESET LOW
– DONE GOES HIGH tor when initialization is complete. To synchronize the
configuration of multiple FPGAs, one or more INIT pins
should be wire-ANDed. If INIT is held low by one or
OPERATION more FPGAs or an external device, the FPGA remains
5-4529(F) in the initialization state. INIT can be used to signal that
the FPGAs are not yet initialized. After INIT goes high
Figure 49. FPGA States of Operation for two internal clock cycles, the mode lines (M[3:0])
are sampled, and the FPGA enters the configuration
state.
The high during configuration (HDC), low during config-
uration (LDC), and DONE signals are active outputs in
the FPGA’s initialization and configuration states. HDC,
LDC, and DONE can be used to provide control of
external logic signals such as reset, bus enable, or
PROM enable during configuration. For parallel master
configuration modes, these signals provide PROM
enable control and allow the data pins to be shared
with user logic signals.
Data Sheet
FPGA States of Operation (continued) not used during the configuration process are
3-stated with internal pull-ups.
If configuration has begun, an assertion of RESET or Warning: During configuration, all OR3Txxx inputs
PRGM initiates an abort, returning the FPGA to the ini- have internal pull-ups enabled. If these inputs are
tialization state. The PRGM and RESET pins must be driven to 5V, they will draw substantial current (≅ 5 ma).
pulled back high before the FPGA will enter the config- This is due to the fact that the inputs are pulled up to
uration state. During the start-up and operating states, 3V.
only the assertion of PRGM causes a reconfiguration.
During configuration, the PIC and PLC latches/FFs are
In the master configuration modes, the FPGA is the held set/reset and the internal BIDI buffers are 3-
source of configuration clock (CCLK). In this mode, the stated. The combinatorial logic begins to function as
initialization state is extended to ensure that, in daisy- the FPGA is configured. Figure 50 shows the general
chain operation, all daisy-chained slave devices are waveform of the initialization, configuration, and start-
ready. Independent of differences in clock rates, master up states.
mode devices remain in the initialization state an addi-
tional six internal clock cycles after INIT goes high. Configuration
When configuration is initiated, a counter in the FPGA
is set to 0 and begins to count configuration clock The ORCA Series FPGA functionality is determined by
cycles applied to the FPGA. As each configuration data the state of internal configuration RAM. This configura-
frame is supplied to the FPGA, it is internally assem- tion RAM can be loaded in a number of different
bled into data words. Each data word is loaded into the modes. In these configuration modes, the FPGA can
internal configuration memory. The configuration load- act as a master or a slave of other devices in the sys-
ing process is complete when the internal length count tem. The decision as to which configuration mode to
equals the loaded length count in the length count field, use is a system design issue. Configuration is dis-
and the required end of configuration frame is written. cussed in detail, including the configuration data format
and the configuration modes used to load the configu-
All OR3Cxx I/Os operate as TTL inputs during configuration data in the FPGA, following a description of the
ration (OR3Txxx I/Os are CMOS-only). All I/Os that are start-up state.
VDD
RESET
PRGM
INIT
M[3:0]
CCLK
HDC
LDC
DONE
USER I/O
INTERNAL
RESET
(gsrn)
INITIALIZATION CONFIGURATION
START-UP
OPERATION
5-4482(F)
Figure 50. Initialization/Configuration/Start-Up Waveforms

Data Sheet
FPGA States of Operation (continued) DONE is an open-drain bidirectional pin that may
include an optional (enabled by default) pull-up resistor
Start-Up to accommodate wired ANDing. The open-drain DONE
signals from multiple FPGAs can be tied together
After configuration, the FPGA enters the start-up (ANDed) with a pull-up (internal or external) and used
phase. This phase is the transition between the config- as an active-high ready signal, an active-low PROM
uration and operational states and begins when the enable, or a reset to other portions of the system.
number of CCLKs received after INIT goes high is When used in SYNC mode, these ANDed DONE pins
equal to the value of the length count field in the config- can be used to synchronize the other two start-up
uration frame and when the end of configuration frame events, since they can all be synchronized to the same
has been written. The system design issue in the start- external signal. This signal will not rise until all FPGAs
up phase is to ensure the user I/Os become active release their DONE pins, allowing the signal to be
without inadvertently activating devices in the system pulled high.
or causing bus contention. A second system design The default for ORCA is the CCLK_SYNC synchro-
concern is the timing of the release of global set/reset nized start-up mode where DONE is released on the
of the PLC latches/FFs. first CCLK rising edge, C1 (see Figure 51). Since this is
There are configuration options that control the relative a synchronized start-up mode, the open-drain DONE
timing of three events: DONE going high, release of the signal can be held low externally to stop the occurrence
set/reset of internal FFs, and user I/Os becoming of the other two start-up events. Once the DONE pin
active. Figure 51 shows the start-up timing for ORCA has been released and pulled up to a high level, the
FPGAs. The system designer determines the relative other two start-up events can be programmed individu-
timing of the I/Os becoming active, DONE going high, ally to either happen immediately or after up to four ris-
and the release of the set/reset of internal FFs. In the ing edges of CCLK (Di, Di + 1, Di + 2, Di + 3, Di + 4).
ORCA Series FPGA, the three events can occur in any The default is for both events to happen immediately
arbitrary sequence. This means that they can occur after DONE is released and pulled high.
before or after each other, or they can occur simulta- A commonly used design technique is to release
neously. DONE one or more clock cycles before allowing the I/O
There are four main start-up modes: CCLK_NOSYNC, to become active. This allows other configuration
CCLK_SYNC, UCLK_NOSYNC, and UCLK_SYNC. devices, such as PROMs, to be disconnected using the
The only difference between the modes starting with DONE signal so that there is no bus contention when
CCLK and those starting with UCLK is that for the the I/Os become active. In addition to controlling the
UCLK modes, a user clock must be supplied to the FPGA during start-up, other start-up techniques that
start-up logic. The timing of start-up events is then avoid contention include using isolation devices
based upon this user clock, rather than CCLK. The dif- between the FPGA and other circuits in the system,
ference between the SYNC and NOSYNC modes is reassigning I/O locations, and maintaining I/Os as 3-
that for SYNC mode, the timing of two of the start-up stated outputs until contentions are resolved.
events, release of the set/reset of internal FFs, and the Each of these start-up options can be selected during
I/Os becoming active is triggered by the rise of the bit stream generation in ORCA Foundry, using
external DONE pin followed by a variable number of Advanced Options. For more information, please see
rising clock edges (either CCLK or UCLK). For the the ORCA Foundry documentation.
NOSYNC mode, the timing of these two events is
based only on either CCLK or UCLK.
Data Sheet
FPGA States of Operation (continued) Reconfiguration

To reconfigure the FPGA when the device is operating
in the system, a low pulse is input into PRGM. The con-
figuration data in the FPGA is cleared, and the I/Os not
used for configuration are 3-stated. The FPGA then
CCLK_NOSYNC samples the mode select inputs and begins reconfigu-
F ration. When reconfiguration is complete, DONE is
DONE released, allowing it to be pulled high.
C1 C2 C3 C4
I/O
C1 C2 C3 C4 Partial Reconfiguration
GSRN
ACTIVE C1 C2 C3 C4 All ORCA device families have been designed to allow
a partial reconfiguration of the FPGA at any time. This
is done by setting a bit stream option in the previous
CCLK_SYNC
configuration sequence that tells the FPGA to not reset
DONE IN all of the configuration RAM during a reconfiguration.
DONE Then only the configuration frames that are to be modi-
C1, C2, C3, OR C4 F fied need to be rewritten, thereby reducing the configu-
I/O
ration time.
Di Di + 1 Di + 2 Di + 3 Di + 4
GSRN
Other bit stream options are also available that allow
ACTIVE Di Di + 1 Di + 2 Di + 3 Di + 4 one portion of the FPGA to remain in operation while a
partial reconfiguration is being done. If this is done, the
user must be careful to not cause contention between
UCLK UCLK_NOSYNC the two configurations (the bit stream resident in the
F FPGA and the partial reconfiguration bit stream) as the
second reconfiguration bit stream is being loaded.
DONE
C1 U1 U2 U3 U4
I/O
U1 U2 U3 U4 Other Configuration Options

GSRN
ACTIVE U1 U2 U3 U4
There are many other configuration options available to
the user that can be set during bit stream generation in
ORCA Foundry. These include options to enable
UCLK_SYNC
boundary scan and/or the microprocessor interface
(MPI) and/or the programmable clock manager (PCM),
DONE IN readback options, and options to control and use the
internal oscillator after configuration.
DONE
C1 U1, U2, U3, OR U4 F Other useful options that affect the next configuration
I/O
(not the current configuration process) include options
Di Di + 1 Di + 2 Di + 3 Di + 4
to disable the global set/reset during configuration, dis-
GSRN able the 3-state of I/Os during configuration, and dis-
ACTIVE Di Di + 1 Di + 2 Di + 3
able the reset of internal RAMs during configuration to
UCLK PERIOD allow for partial configurations (see above). For more
SYNCHRONIZATION UNCERTAINTY information on how to set these and other configuration
Note: F = finished, no more CLKs required. options, please see the ORCA Foundry documenta-
5-2761(F)
tion.
Figure 51. Start-Up Waveforms
Data Sheet
Configuration Data Format Configuration Data Frame
The ORCA Foundry Development System interfaces Configuration data can be presented to the FPGA in
with front-end design entry tools and provides tools to two frame formats: autoincrement and explicit. A
produce a fully configured FPGA. This section dis- detailed description of the frame formats is shown in
cusses using the ORCA Foundry Development System Figure 52, Figure 53, and Table 32. The two modes are
to generate configuration RAM data and then provides similar except that autoincrement mode uses assumed
the details of the configuration frame format. address incrementation to reduce the bit stream size,
and explicit mode requires an address for each data
The ORCA OR3Cxx and OR3Txxx Series FPGAs are frame. In both cases, the header frame begins with a
bit stream compatible. series of 1s and a preamble of 0010, followed by a
24-bit length count field representing the total number
of configuration clocks needed to complete the loading
Using ORCA Foundry to Generate of the FPGAs.
Configuration RAM Data
Following the header frame is a mandatory ID frame.
The configuration data bit stream defines the I/O func- (Note that the ID frame was optional in the ORCA 2C
tionality, logic, and interconnections within the FPGA. and 2C/TxxA Series.)
The bit stream is generated by the development sys- The ID frame contains data used to determine if the bit
tem. The bit stream created by the bit stream genera- stream is being loaded to the correct type of ORCA
tion tool is a series of 1s and 0s used to write the FPGA FPGA (i.e., a bit stream generated for an OR3T55 is
configuration RAM. It can be loaded into the FPGA being sent to an OR3T55). Error checking is always
using one of the configuration modes discussed later. enabled for Series 3 devices, through the use of an
In the bit stream generator, the designer selects 8-bit checksum. One bit in the ID frame also selects
options that affect the FPGA’s functionality. Using the between the autoincrement and explicit address modes
output of the bit stream generator, circuit_name.bit, for this load of the configuration data.
the development system’s download tool can load the A configuration data frame follows the ID frame. A data
configuration data into the ORCA series FPGA evalua- frame starts with a 01-start bit pair and ends with
tion board from a PC or workstation. enough 1-stop bits to reach a byte boundary. If using
Alternatively, a user can program a PROM (such as a autoincrement configuration mode, subsequent data
Serial ROM or a standard EPROM) and load the FPGA frames can follow. If using explicit mode, one or more
from the PROM. The development system’s PROM address frames must follow each data frame, telling the
programming tool produces a file in .mks or .exo for- FPGA at what addresses the preceding data frame is
mat. to be stored (each data frame can be sent to multiple
addresses).
Following all data and address frames is the postam-
ble. The format of the postamble is the same as an
address frame with the highest possible address value
with the checksum set to all ones.
Data Sheet
Configuration Data Format (continued)
CONFIGURATION DATA CONFIGURATION DATA
0 0 1 0 0 1 0 1 0 0
PREAMBLE LENGTH ID FRAME CONFIGURATION CONFIGURATION POSTAMBLE

COUNT DATA FRAME 1 DATA FRAME 2
CONFIGURATION HEADER
5-5759(F)
Figure 52. Serial Configuration Data Format—Autoincrement Mode
CONFIGURATION DATA CONFIGURATION DATA
0 0 1 0 0 1 0 0 0 1 0 0 0 0
PREAMBLE LENGTH ID FRAME CONFIGURATION ADDRESS CONFIGURATION ADDRESS

COUNT DATA FRAME 1 FRAME 1 DATA FRAME 2 FRAME 2 POSTAMBLE
CONFIGURATION HEADER
5-5760(F)
Figure 53. Serial Configuration Data Format—Explicit Mode
Table 32. Configuration Frame Format and Contents

11110010 Preamble
Header 24-bit Length Count Configuration frame length.
11111111 Trailing header—8 bits.
0101 1111 1111 1111 ID frame header.
Configuration Mode 00 = autoincrement, 01 = explicit.
Reserved [41:0] Reserved bits set to 0.
ID Frame
ID 20-bit part ID.
Checksum 8-bit checksum.
11111111 Eight stop bits (high) to separate frames.
01 Data frame header.
Configuration Data Bits Number of data bits depends upon device.
Data
String of 0 bits added to bit stream to make frame header, plus data
Frame Alignment Bits = 0
bits reach a byte boundary.
(repeated for each
data frame) Checksum 8-bit checksum.
00 Address frame header.
Configuration 14 Address Bits 14-bit address of location to start data storage.
Address
Frame Checksum 8-bit checksum.
00 Postamble header.
Postamble 11111111 111111 Dummy address.
1111111111111111 16 stop bits.*
* In MPI configuration mode, the number of stop bits = 32.
Note: For slave parallel mode, the byte containing the preamble must be 11110010. The number of leading header dummy bits must
be (n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n * 8), where n is any positive
integer. The number of stop bits/frame for slave parallel mode must be (x * 8), where x is a positive integer. Note also that the bit
stream generator tool supplies a bit stream that is compatible with all configuration modes, including slave parallel mode.
Data Sheet
Configuration Data Format (continued)

The length and number of data frames and information on the PROM size for the Series 3 FPGAs are given in
Table 33.
Table 33. Configuration Frame Size

Devices OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125
# of Frames 856 984 1240 1496 1880

Data Bits/Frame 202 232 292 352 442
Configuration Data (# of frames x # of data 172,912 228,288 362,080 526,592 830,960
bits/frame)
Maximum Total # Bits/Frame (align bits, 01 224 256 312 376 464
frame start, 8-bit checksum, 8 stop bits)
Maximum Configuration Data (# bits/frame 191,744 251,904 386,880 562,496 872,320
x # of frames)
Maximum PROM Size (bits) 191,912 252,072 387,048 562,664 872,488
(add configuration header and postamble)
Bit Stream Error Checking

There are three different types of bit stream error checking performed in the ORCA Series 3 FPGAs:
ID frame, frame alignment, and CRC checking.
The ID data frame is sent to a dedicated location in the FPGA. This ID frame contains a unique code for the device
for which it was generated. This device code is compared to the internal code of the FPGA. Any differences are
flagged as an ID error. This frame is automatically created by the bit stream generation program in ORCA Foundry.
Each data and address frame in the FPGA begins with a frame start pair of bits and ends with eight stop bits set to
1. If any of the previous stop bits were a 0 when a frame start pair is encountered, it is flagged as a frame align-
ment error.
Error checking is also done on the FPGA for each frame by means of a checksum byte. If an error is found on eval-
uation of the checksum byte, then a checksum/parity error is flagged. The checksum is the XOR of all the data
bytes, from the start of frame up to and including the bytes before the checksum. It applies to the ID, address, and
data frames.
When any of the three possible errors occur, the FPGA is forced into an idle state, forcing INIT low. The FPGA will
remain in this state until either the RESET or PRGM pins are asserted.
If using either of the MPI modes to configure the FPGA, the specific type of bit stream error is written to one of the
MPI registers by the FPGA configuration logic. The PGRM bit of the MPI control register can also be used to reset
out of the error condition and restart configuration.
Data Sheet
FPGA Configuration Modes Master Parallel Mode
There are eight methods for configuring the FPGA. The master parallel configuration mode is generally
Seven of the configuration modes are selected on the used to interface to industry-standard, byte-wide mem-
M0, M1, and M2 inputs. The eighth configuration mode ory, such as the 2764 and larger EPROMs. Figure 54
is accessed through the boundary-scan interface. A provides the connections for master parallel mode. The
fourth input, M3, is used to select the frequency of the FPGA outputs an 18-bit address on A[17:0] to memory
internal oscillator, which is the source for CCLK in and reads 1 byte of configuration data on the rising
some configuration modes. The nominal frequencies of edge of RCLK. The parallel bytes are internally serial-
the internal oscillator are 1.25 MHz and 10 MHz. The ized starting with the least significant bit, D0. D[7:0] of
1.25 MHz frequency is selected when the M3 input is the FPGA can be connected to D[7:0] of the micropro-
unconnected or driven to a high state. cessor only if a standard prom file format is used. If a
.bit or .rbt file is used from ORCA Foundry, then the
There are three basic FPGA configuration modes: user must mirror the bytes in the .bit or .rbt file OR
master, slave, and peripheral. The configuration data leave the .bit or .rbt file unchanged and connect D[7:0]
can be transmitted to the FPGA serially or in parallel of the FPGA to D[0:7] of the microprocessor.
bytes. As a master, the FPGA provides the control sig-
nals out to strobe data in. As a slave device, a clock is
generated externally and provided into the CCLK input. DOUT TO DAISY-
CHAINED
In the three peripheral modes, the FPGA acts as a A[17:0] A[17:0] CCLK DEVICES
microprocessor peripheral. Table 34 lists the functions
of the configuration mode pins. Note that two configura-
tion modes previously available on the OR2Cxx and D[7:0] D[7:0]
OR2C/TxxA devices (master parallel down and syn- ORCA
EPROM SERIES
chronous peripheral) have been removed for Series 3
FPGA
devices. OE DONE
CE
Table 34. Configuration Modes

PROGRAM PRGM
Configuration VDD M2 HDC
M2 M1 M0 CCLK Data VDD OR GND M1 LDC
Mode M0 RCLK
0 0 0 Output Master Serial Serial
0 0 1 Input Slave Parallel Parallel
Figure 54. Master Parallel Configuration Schematic
0 1 0 Output Microprocessor: Parallel
Motorola* Pow-
erPC In master parallel mode, the starting memory address
0 1 1 Output Microprocessor: Parallel is 00000 Hex, and the FPGA increments the address
Intel i960 for each byte loaded.
1 0 0 Output Master Parallel Parallel One master mode FPGA can interface to the memory
1 0 1 Output Async Peripheral Parallel and provide configuration data on DOUT to additional
1 1 0 Reserved FPGAs in a daisy-chain. The configuration data on
1 1 1 Input Slave Serial Serial DOUT is provided synchronously with the falling edge
of CCLK. The frequency of the CCLK output is eight
* Motorola is a registered trademark of Motorola, Inc.
times that of RCLK.
Data Sheet
FPGA Configuration Modes (continued) configuration, the high on the FPGA's DONE disables
the serial ROM.
Master Serial Mode Serial ROMs can also be cascaded to support the con-
figuration of multiple FPGAs or to load a single FPGA
In the master serial mode, the FPGA loads the configu- when configuration data requirements exceed the
ration data from an external serial ROM. The configura- capacity of a single serial ROM. After the last bit from
tion data is either loaded automatically at start-up or on the first serial ROM is read, the serial ROM outputs
a PRGM command to reconfigure. The ATT1700A CEO low and 3-states the DATA output. The next serial
Series Serial PROMs can be used to configure the ROM recognizes the low on CE input and outputs con-
FPGA in the master serial mode. This provides a sim- figuration data on the DATA output. After configuration
ple 4-pin interface in a compact package. is complete, the FPGA’s DONE output into CE disables
Configuration in the master serial mode can be done at the serial ROMs.
powerup and/or upon a configure command. The sys- This FPGA/serial ROM interface is not used in applica-
tem or the FPGA must activate the serial ROM's tions in which a serial ROM stores multiple configura-
RESET/OE and CE inputs. At powerup, the FPGA and tion programs. In these applications, the next
serial ROM each contain internal power-on reset cir- configuration program to be loaded is stored at the
cuitry that allows the FPGA to be configured without ROM location that follows the last address for the previ-
the system providing an external signal. The power-on ous configuration program. The reason the interface in
reset circuitry causes the serial ROM's internal address Figure 55 will not work in this application is that the low
pointer to be reset. After powerup, the FPGA automati- output on the INIT signal would reset the serial ROM
cally enters its initialization phase. address pointer, causing the first configuration to be
The serial ROM/FPGA interface used depends on such reloaded.
factors as the availability of a system reset pulse, avail- In some applications, there can be contention on the
ability of an intelligent host to generate a configure FPGA's DIN pin. During configuration, DIN receives
command, whether a single serial ROM is used or mul- configuration data, and after configuration, it is a user
tiple serial ROMs are cascaded, whether the serial I/O. If there is contention, an early DONE at start-up
ROM contains a single or multiple configuration pro- (selected in ORCA Foundry) may correct the problem.
grams, etc. Because of differing system requirements An alternative is to use LDC to drive the serial ROM's
and capabilities, a single FPGA/serial ROM interface is CE pin. In order to reduce noise, it is generally better to
generally not appropriate for all applications. run the master serial configuration at 1.25 MHz (M3 pin
Data is read in the FPGA sequentially from the serial tied high), rather than 10 MHz, if possible.
ROM. The DATA output from the serial ROM is con-
nected directly into the DIN input of the FPGA. The
TO DAISY-
CCLK output from the FPGA is connected to the CLK CHAINED
input of the serial ROM. During the configuration pro- DATA DIN DOUT DEVICES
cess, CCLK clocks one data bit on each rising edge. CLK CCLK
Since the data and clock are direct connects, the ATT1700A
FPGA/serial ROM design task is to use the system or CE DONE
RESET/OE INIT
FPGA to enable the RESET/OE and CE of the serial
ROM(s). There are several methods for enabling the CEO ORCA
SERIES
serial ROM’s RESET/OE and CE inputs. The serial
DATA
FPGA
ROM’s RESET/OE is programmable to function with
RESET active-high and OE active-low or RESET active- CLK
low and OE active-high. ATT1700A PRGM

CE
M2
In Figure 55, serial ROMs are cascaded to configure RESET/OE M1
multiple daisy-chained FPGAs. The host generates a M0
CEO
500 ns low pulse into the FPGA's PRGM input. The
FPGA’s INIT input is connected to the serial ROMs’ TO MORE
SERIAL ROMs PROGRAM
RESET/OE input, which has been programmed to AS NEEDED
5-4456.1(F)
function with RESET active-low and OE active-high.
The FPGA DONE is routed to the CE pin. The low on
Figure 55. Master Serial Configuration Schematic
DONE enables the serial ROMs. At the completion of
Data Sheet
FPGA Configuration Modes (continued)

DOUT TO DAISY-
Asynchronous Peripheral Mode CHAINED
DEVICES
PRGM CCLK
8
D[7:0]
Figure 56 shows the connections needed for the asyn- RDY/BUSY
chronous peripheral mode. In this mode, the FPGA INIT
DONE
system interface is similar to that of a microprocessor- MICRO-
peripheral interface. The microprocessor generates the PROCESSOR
ADDRESS CS0 ORCA
control signals to write an 8-bit byte into the FPGA. The DECODE LOGIC CS1 SERIES
FPGA control inputs include active-low CS0 and active- FPGA
high CS1 chip selects and WR and RD inputs. The chip BUS RD
CONTROLLER
selects can be cycled or maintained at a static level WR
during the configuration cycle. Each byte of data is writ- VDD M2 HDC
ten into the FPGA’s D[7:0] input pins. D[7:0] of the M1
M0 LDC
FPGA can be connected to D[7:0] of the microproces-
sor only if a standard prom file format is used. If a .bit
or .rbt file is used from ORCA Foundry, then the user Figure 56. Asynchronous Peripheral Configuration
must mirror the bytes in the .bit or .rbt file OR leave the
.bit or .rbt file unchanged and connect D[7:0] of the
FPGA to D[0:7] of the microprocessor. Microprocessor Interface (MPI) Mode
The FPGA provides an RDY/BUSY status output to indi-
The built-in MPI in Series 3 FPGAs is designed for use
cate that another byte can be loaded. A low on RDY/
in configuring the FPGA. Figure 57 and Figure 58 show
BUSY indicates that the double-buffered hold/shift reg-
the glueless interface for FPGA configuration and read-
isters are not ready to receive data, and this pin must
back from the PowerPC and i960 processors, respec-
be monitored to go high before another byte of data
tively. When enabled by the mode pins, the MPI
can be written. The shortest time RDY/BUSY is low
handles all configuration/readback control and hand-
occurs when a byte is loaded into the hold register and
shaking with the host processor. For single FPGA con-
the shift register is empty, in which case the byte is
figuration, the host sets the configuration control
immediately transferred to the shift register. The long-
register PRGM bit to zero then back to a one and, after
est time for RDY/BUSY to remain low occurs when a
reading that the INIT signal is high in the MPI status
byte is loaded into the holding register and the shift
register, transfers data 8 bits at a time to the FPGA’s
register has just started shifting configuration data into
D[7:0] input pins.
configuration RAM.
If configuring multiple FPGAs through daisy-chain
The RDY/BUSY status is also available on the D7 pin by
operation is desired, the MP_DAISY bit must be set in
enabling the chip selects, setting WR high, and apply-
the configuration control register of the MPI. Because
ing RD low, where the RD input provides an output
of the latency involved in a daisy-chain configuration,
enable for the D7 pin when RD is low. The D[6:0] pins
the MP_HOLD_BUS bit may be set to zero rather than
are not enabled to drive when RD is low and, therefore,
one for daisy-chain operation. This allows the MPI to
only act as input pins in asynchronous peripheral
acknowledge the data transfer before the configuration
mode. Optionally, the user can ignore the RDY/BUSY
information has been serialized and transferred on the
status and simply wait until the maximum time it would
FPGA daisy-chain. The early acknowledgment frees
take for the RDY/BUSY line to go high, indicating the
the host processor to perform other system tasks. Con-
FPGA is ready for more data, before writing the next
figuring with the MP_HOLD_BUS bit at zero requires
data byte.
that the host microprocessor poll the RDY/BUSY bit of
the MPI status register and/or use the MPI interrupt
capability to confirm the readiness of the MPI for more
configuration data.
Data Sheet
FPGA Configuration Modes (continued) Configuration readback can also be performed via the
MPI when it is in user mode. The MPI is enabled in user
There are two options for using the host interrupt mode by setting the MP_USER bit to 1 in the configura-
request in configuration mode. The configuration con- tion control register prior to the start of configuration or
trol register offers control bits to enable the interrupt on through a configuration option. To perform readback,
either a bit stream error or to notify the host processor the host processor writes the 14-bit readback start
when the FPGA is ready for more configuration data. address to the readback address registers and sets the
The MPI status register may be used in conjunction RD_CFG bit to 0 in the configuration control register.
with, or in place of, the interrupt request options. The Readback data is returned 8 bits at a time to the read-
status register contains a 2-bit field to indicate the bit back data register and is valid when the DATA_RDY bit
stream error status. As previously mentioned, there is of the status register is 1. There is no error checking
also a bit to indicate the MPI’s readiness to receive during readback. A flow chart of the MPI readback
another byte of configuration data. A flow chart of the operation is shown in Figure 60. The RD_DATA pin
MPI configuration process is shown in Figure 59. The used for dedicated FPGA readback is invalid during
MPI status and configuration register bit maps can be MPI readback.
found in the Special Function Blocks section and MPI
configuration timing information is available in the Tim-
ing Characteristics section of this data sheet.
POWER ON WITH
DOUT TO DAISY- VALID M[3:0]
CHAINED
CCLK DEVICES
8
D[7:0] D[7:0]
A[27:31] A[4:0] WRITE CONFIGURATION
CLKOUT MPI_CLK CONTROL REGISTER BITS
RD/WR MPI_RW
ORCA
POWERPC TA MPI_ACK
SERIES 3
BI MPI_BI FPGA
READ STATUS REGISTER
IRQx MPI_IRQ
TS MPI_STRB
A26 CS0 DONE NO
A25 CS1 INIT INIT = 1?
HDC
LDC
YES
5-5761(F)
Note: FPGA shown as a memory-mapped peripheral using CS0 and READ STATUS REGISTER
CS1. Other decoding schemes are possible using CS0 and/or
CS1.
YES
DONE DONE = 1?
Figure 57. PowerPC/MPI Configuration Schematic
NO
i960 SYSTEM CLOCK
YES
ERROR BIT STREAM ERROR?
8 DOUT TO DAISY-
AD[7:0] D[7:0] CHAINED
CCLK DEVICES
CLKIN MPI_CLK
W/R MPI_RW
NO
RDYRCV MPI_ACK
XINTx MPI_IRQ
ORCA
NO
ALE MPI_ALE SERIES 3 DATA_RDY = 1?
i960
ADS MPI_STRB FPGA
BE0 MPI_BE0
BE1 MPI_BE1 YES
VDD DONE
INIT WRITE DATA TO
CS1
HDC CONFIGURATION DATA REG
CS0
LDC
5-5762(F)
5-5763(F)
Note: FPGA shown as only system peripheral with fixed chip select
signals. For multiperipheral systems, address decoding and/or Figure 59. Configuration Through MPI
latching can be used to implement chip selects.
Figure 58. i960/MPI Configuration Schematic

Data Sheet
ENABLE MICROPROCESSOR
INTERFACE IN USER MODE
SET READBACK ADDRESS
WRITE RD_CFG TO 0
IN CONTROL REGISTER 1
READ STATUS REGISTER
NO
DATA_RDY = 1?
YES
READ DATA REGISTER
NO
ERROR DATA = 0xFF?
YES
READ DATA REGISTER
NO
ERROR DATA = 0xFF?
YES
READ DATA REGISTER
NO START OF FRAME
ERROR
FOUND?
YES
READ UNTIL END OF FRAME
WRITE RD_CFG
TO 1 IN YES FINISHED NO
STOP READBACK?
CONTROL
REGISTER 1
5-5764(F)
Figure 60. Readback Through MPI
Data Sheet
FPGA Configuration Modes (continued) Slave Parallel Mode

The slave parallel mode is essentially the same as the
Slave Serial Mode
slave serial mode except that 8 bits of data are input on
The slave serial mode is primarily used when multiple pins D[7:0] for each CCLK cycle. Due to 8 bits of data
FPGAs are configured in a daisy-chain (see the Daisy- being input per CCLK cycle, the DOUT pin does not
Chaining section). It is also used on the FPGA evalua- contain a valid bit stream for slave parallel mode. As a
tion board that interfaces to the download cable. A result, the lead device cannot be used in the slave
device in the slave serial mode can be used as the lead parallel mode in a daisy-chain configuration.
device in a daisy-chain. Figure 61 shows the connec- Figure 62 is a schematic of the connections for the
tions for the slave serial configuration mode. slave parallel configuration mode. WR and CS0 are
The configuration data is provided into the FPGA’s DIN active-low chip select signals, and CS1 is an active-
input synchronous with the configuration clock CCLK high chip select signal. These chip selects allow the
input. After the FPGA has loaded its configuration data, user to configure multiple FPGAs in slave parallel
it retransmits the incoming configuration data on mode using an 8-bit data bus common to all of the
DOUT. CCLK is routed into all slave serial mode FPGAs. These chip selects can then be used to select
devices in parallel. the FPGA(s) to be configured with a given bit stream.
The chip selects must be active for each valid CCLK
Multiple slave FPGAs can be loaded with identical con- cycle until the device has been completely pro-
figurations simultaneously. This is done by loading the grammed. They can be inactive between cycles but
configuration data into the DIN inputs in parallel. must meet the setup and hold times for each valid pos-
itive CCLK. D[7:0] of the FPGA can be connected to
D[7:0] of the microprocessor only if a standard prom
TO DAISY-
CHAINED file format is used. If a .bit or .rbt file is used from
DOUT DEVICES
ORCA Foundry, then the user must mirror the bytes in
the .bit or .rbt file OR leave the .bit or .rbt file
unchanged and connect D[7:0] of the FPGA to D[0:7]
INIT of the microprocessor.
MICRO- ORCA
PROCESSOR PRGM SERIES
OR FPGA
DOWNLOAD DONE
CABLE CCLK 8
D[7:0]
DIN
DONE
INIT
ORCA
MICRO- CCLK SERIES
VDD FPGA
PROCESSOR PRGM
M2 HDC OR VDD
M1 SYSTEM
M0 LDC
CS1
CS0
5-4485(F)
WR
Figure 61. Slave Serial Configuration Schematic

M2 HDC
M1 LDC
M0
5-4487(F)
Figure 62. Slave Parallel Configuration Schematic
Data Sheet
FPGA Configuration Modes (continued) The loading of configuration data continues after the
lead device has received its configuration data if its
Daisy-Chaining internal frame bit counter has not reached the length
count. When the configuration RAM is full and the num-
Multiple FPGAs can be configured by using a daisy- ber of bits received is less than the length count field,
chain of the FPGAs. Daisy-chaining uses a lead FPGA the FPGA shifts any additional data out on DOUT.
and one or more FPGAs configured in slave serial The configuration data is read into DIN of slave devices
mode. The lead FPGA can be configured in any mode on the positive edge of CCLK, and shifted out DOUT
except slave parallel mode. (Daisy-chaining is available on the negative edge of CCLK. Figure 63 shows the
with the boundary-scan ram_w instruction discussed connections for loading multiple FPGAs in a daisy-
later.) chain configuration.
All daisy-chained FPGAs are connected in series. The generation of CCLK for the daisy-chained devices
Each FPGA reads and shifts the preamble and length that are in slave serial mode differs depending on the
count in on positive CCLK and out on negative CCLK configuration mode of the lead device. A master paral-
edges. lel mode device uses its internal timing generator to
An upstream FPGA that has received the preamble produce an internal CCLK at eight times its memory
and length count outputs a high on DOUT until it has address rate (RCLK). The asynchronous peripheral
received the appropriate number of data frames so that mode device outputs eight CCLKs for each write cycle.
downstream FPGAs do not receive frame start bit If the lead device is configured in slave mode, CCLK
pairs. After loading and retransmitting the preamble must be routed to the lead device and to all of the
and length count to a daisy-chain of slave devices, the daisy-chained devices.
lead device loads its configuration data frames.
CCLK CCLK CCLK

A[17:0] A[17:0] DOUT DIN DOUT DIN DOUT
EPROM ORCA ORCA ORCA
D[7:0] D[7:0] SERIES SERIES SERIES
FPGA FPGA FPGA
MASTER SLAVE #1 SLAVE #2 VDD
OE DONE
CE DONE DONE
PRGM PRGM PRGM

INIT VDD INIT VDD INIT
PROGRAM
VDD M2 HDC M2 HDC M2 HDC VDD
VDD OR M1 LDC LDC
M1 M1 LDC
GND M0 RCLK M0 RCLK M0 RCLK
5-4488(F
Figure 63. Daisy-Chain Configuration Schematic
As seen in Figure 63, the INIT pins for all of the FPGAs are connected together. This is required to guarantee that
powerup and initialization will work correctly. In general, the DONE pins for all of the FPGAs are also connected
together as shown to guarantee that all of the FPGAs enter the start-up state simultaneously. This may not be
required, depending upon the start-up sequence desired.
Data Sheet
Daisy-Chaining with Boundary Scan

Multiple FPGAs can be configured through the JTAG ports by using a daisy-chain of the FPGAs. This daisy-chain-
ing operation is available upon initial configuration after powerup, after a power-on reset, after pulling the program
pin to reset the chip, or during a reconfiguration if the EN_JTAG RAM has been set.
All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in
on the positive TCK and out on the negative TCK edges.
An upstream FPGA that has received the preamble and length count outputs a high on TDO until it has received
the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After load-
ing and retransmitting the preamble and length count to a daisy-chain of downstream devices, the lead device
loads its configuration data frames.
The loading of configuration data continues after the lead device had received its configuration read into TDI of
downstream devices on the positive edge of TCK, and shifted out TDO on the negative edge of TCK. Figure 63
shows the connections for loading multiple FPGAs in a JTAG daisy-chain configuration.
Data Sheet
Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
The ORCA Series FPGAs include circuitry designed to protect the chips from damaging substrate injection cur-
rents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed
during storage, handling, and use to avoid exposure to excessive electrical stress.
Table 35. Absolute Maximum Ratings
Parameter Symbol Min Max Unit

Storage Temperature Tstg –65 150 °C
Supply Voltage with Respect to Ground VDD –0.5 7.0 V
Input Signal with Respect to Ground — –0.5 VDD + 0.3 V
Signal Applied to High-impedance Output — –0.5 VDD + 0.3 V
Maximum Package Body Temperature — — 220 °C
Recommended Operating Conditions

Table 36. Recommended Operating Conditions
OR3Cxx OR3Txxx
Mode Temperature Temperature
Supply Voltage Supply Voltage
Range Range
(VDD) (VDD)
(Ambient) (Ambient)
Commercial 0 °C to 70 °C 5 V ± 5% 0 °C to 70 °C 3.0 V to 3.6 V
Industrial –40 °C to +85 °C 5 V ± 10% –40 °C to +85 °C 3.0 V to 3.6 V
Note: The maximum recommended junction temperature (TJ) during operation is 125 °C.

Data Sheet
Electrical Characteristics
Table 37. Electrical Characteristics
OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Sym- OR3Cxx OR3Txxx

Parameter Test Conditions Unit
bol Min Max Min Max
Input Voltage: Input configured as CMOS
High VIH (includes OR3Txxx) 50% VDD VDD + 0.5 50% VDD VDD + 0.5 V
Low VIL GND – 0.5 20% VDD GND – 0.5 30% VDD V
Input Voltage: OR3Txxx 5 V Tolerant
High VIH — — 50% VDD 5.8 V V
Low VIL — — GND – 0.5 30% VDD V
Input Voltage: Input configured as TTL
High VIH (not valid for OR3Txxx) 2.0 VDD + 0.3 — — V
Low VIL –0.5 0.8 — — V
Output Voltage:
High VOH VDD = min, IOH = 6 mA or 3 mA 2.4 — 2.4 — V
Low VOL VDD = min, IOL = 12 mA or 6 mA — 0.4 — 0.4 V
Input Leakage Current IL VDD = max, VIN = VSS or VDD –10 10 –10 10 µA
Standby Current: IDDSB OR3Cxx (TA = 25 °C,
OR3T20 VDD = 5.0 V) — — — 4.70 mA
OR3T30 OR3Txxx (TA = 25 °C, — — — 4.90 mA
OR3T55 VDD = 3.3 V) — 4.06 — 5.30 mA
OR3C/T80 internal oscillator running, no out- — 4.56 — 5.80 mA
OR3T125 put loads, inputs VDD or GND — — — 6.70 mA
(after configuration)
Standby Current: IDDSB OR3Cxx (TA = 25 °C,
OR3T20 VDD = 5.0 V) — — — 3.52 mA
OR3T30 OR3Txxx (TA = 25 °C, — — — 3.68 mA
OR3T55 VDD = 3.3 V) — 3.05 — 3.98 mA
OR3C/T80 internal oscillator stopped, no — 3.42 — 4.35 mA
OR3T125 output loads, inputs VDD or GND — — — 5.02 mA
(after configuration)
Powerup Current: Ipp Power supply current @ approxi-
OR3T20 mately 1 V, within a recommended — — 1.2 — mA
OR3T30 power supply ramp rate of — — 1.6 — mA
OR3T55 1 ms—200 ms 3.2 — 2.7 — mA
OR3C/T80 5.4 — 4.0 — mA
OR3T125 — — 6.5 — mA
Data Retention Voltage VDR TA = 25 °C 2.3 — 2.3 — V
Input Capacitance CIN OR3Cxx (TA = 25 °C, — 9 — 8 pF
VDD = 5.0 V)
OR3Txxx (TA = 25 °C,
VDD = 3.3 V)
Test frequency = 1 MHz
Output Capacitance COUT OR3Cxx (TA = 25 °C, — 9 — 8 pF
VDD = 5.0 V)
OR3Txxx (TA = 25 °C,
VDD = 3.3 V)
Test frequency = 1 MHz

Data Sheet
Electrical Characteristics (continued)

Table 37. Electrical Characteristics (continued)
OR3Cxx OR3Txxx
Parameter Symbol Test Conditions Unit
Min Max Min Max
DONE Pull-up RDONE — 100 — 100 — kΩ
Resistor*
M[3:0] Pull-up RM — 100 — 100 — kΩ
Resistors*
I/O Pad Static Pull-up IPU OR3Cxx (VDD = 5.25 V, 14.4 50.9 14.4 50.9 µA
Current* VIN = VSS, TA = 0 °C)
OR3Txxx (VDD = 3.6 V,
VIN = VSS, TA = 0 °C)
I/O Pad Static IPD OR3Cxx (VDD = 5.25 V, 26 103 26 103 µA
Pull-down Current VIN = VSS, TA = 0 °C)
OR3Txxx (VDD = 3.6 V,
VIN = VSS, TA = 0 °C)
I/O Pad Pull-up RPU VDD = all, VIN = VSS, TA = 0 °C 100 — 100 — kΩ
Resistor*
I/O Pad Pull-down RPD VDD = all, VIN = VDD, TA = 0 °C 50 — 50 — kΩ
Resistor
* On the OR3Txxx devices, the pull-up resistor will externally pull the pin to a level 1.0 V below VDD.
Note: For 3T devices driven to 5 V.

Data Sheet
Timing Characteristics mercial and industrial devices. Table 40 provides the

same information for the OR3Txxx devices (both com-
Description mercial and industrial). The delay values in this data
sheet and reported by ORCA Foundry are shown as
To define speed grades, the ORCA Series part number 1.00 in the tables. The method for determining the max-
designation (see Ordering Information) uses a single- imum junction temperature is defined in the Package
digit number to designate a speed grade. This number Thermal Characteristics section. Taken cumulatively,
is not related to any single ac parameter. Higher num- the range of parameter values for best-case vs. worst-
bers indicate a faster set of timing parameters. The case processing, supply voltage, and junction tempera-
actual speed sorting is based on testing the delay in a ture can approach 3 to 1.
path consisting of an input buffer, combinatorial delay
through all PLCs in a row, and an output buffer. Other Table 38. Derating for Commercial Devices
tests are then done to verify other delay parameters, (OR3Cxx)
such as routing delays, setup times to FFs, etc.
TJ Power Supply Voltage
The most accurate timing characteristics are reported
(°C) 4.75 V 5.0 V 5.25 V
by the timing analyzer in the ORCA Foundry Develop-
ment System. A timing report provided by the develop- 0 0.81 0.79 0.77
ment system after layout divides path delays into logic 25 0.85 0.83 0.81
and routing delays. The timing analyzer can also pro- 85 1.00 0.97 0.95
vide logic delays prior to layout. While this allows rout- 100 1.05 1.02 1.00
ing budget estimates, there is wide variance in routing 125 1.12 1.09 1.07
delays associated with different layouts.
Table 39. Derating for Industrial Devices (OR3Cxx)
The logic timing parameters noted in the Electrical
Characteristics section of this data sheet are the same TJ Power Supply Voltage
as those in the design tools. In the PFU timing given in (°C) 4.5 V 4.75 V 5.0 V 5.25 V 5.5 V
Table 41—Table 48, symbol names are generally a –40 0.71 0.70 0.68 0.66 0.65
concatenation of the PFU operating mode (as defined 0 0.80 0.78 0.76 0.74 0.73
in Table 3) and the parameter type. The setup, hold, 25 0.84 0.82 0.80 0.78 0.77
and propagation delay parameters, defined below, are 85 1.00 0.97 0.94 0.93 0.91
designated in the symbol name by the SET, HLD, and
100 1.05 1.01 0.99 0.97 0.95
DEL characters, respectively.
125 1.12 1.09 1.06 1.04 1.02
The values given for the parameters are the same as
Table 40. Derating for Commercial/Industrial
those used during production testing and speed bin-
Devices (OR3Txxx)
ning of the devices. The junction temperature and sup-
ply voltage used to characterize the devices are listed TJ Power Supply Voltage
in the delay tables. Actual delays at nominal tempera- (°C) 3.0 V 3.3 V 3.6 V
ture and voltage for best-case processes can be much
better than the values given. –40 0.73 0.66 0.61
0 0.82 0.73 0.68
It should be noted that the junction temperature used in 25 0.87 0.78 0.72
the tables is generally 85 °C. The junction temperature 85 1.00 0.90 0.83
for the FPGA depends on the power dissipated by the
100 1.04 0.94 0.87
device, the package thermal characteristics (ΘJA), and
125 1.10 1.00 0.92
the ambient temperature, as calculated in the following
equation and as discussed further in the Package Note: The derating tables shown above are for a typical critical path
Thermal Characteristics section: that contains 33% logic delay and 66% routing delay. Since the
routing delay derates at a higher rate than the logic delay, paths
TJmax = TAmax + (P • ΘJA) °C with more than 66% routing delay will derate at a higher rate
than shown in the table. The approximate derating values vs.
temperature are 0.26% per °C for logic delay and 0.45% per °C
Note: The user must determine this junction tempera- for routing delay. The approximate derating values vs. voltage
ture to see if the delays from ORCA Foundry are 0.13% per mV for both logic and routing delays at 25 °C.
should be derated based on the following derat-
ing tables.
Table 38 and Table 39 provide approximate power sup-
ply and junction temperature derating for OR3Cxx com-
Data Sheet
Timing Characteristics (continued) The waveform test points are given in the Input/Output
Buffer Measurement Conditions section of this data
In addition to supply voltage, process variation, and sheet. The timing parameters given in the electrical
operating temperature, circuit and process improve- characteristics tables in this data sheet follow industry
ments of the ORCA Series FPGAs over time will result practices, and the values they reflect are described
in significant improvement of the actual performance below.
over those listed for a speed grade. Even though lower Propagation Delay—The time between the specified
speed grades may still be available, the distribution of reference points. The delays provided are the worst
yield to timing parameters may be several speed case of the tphh and tpll delays for noninverting func-
grades higher than that designated on a product brand. tions, tplh and tphl for inverting functions, and tphz and
Design practices need to consider best-case timing tplz for 3-state enable.
parameters (e.g., delays = 0), as well as worst-case
timing. Setup Time—The interval immediately preceding the
transition of a clock or latch enable signal, during which
The routing delays are a function of fan-out and the the data must be stable to ensure it is recognized as
capacitance associated with the CIPs and metal inter- the intended value.
connect in the path. The number of logic elements that
can be driven (fan-out) by PFUs is unlimited, although Hold Time—The interval immediately following the
the delay to reach a valid logic level can exceed timing transition of a clock or latch enable signal, during which
requirements. It is difficult to make accurate routing the data must be held stable to ensure it is recognized
delay estimates prior to design compilation based on as the intended value.
fan-out. This is because the CAE software may delete 3-State Enable—The time from when a 3-state control
redundant logic inserted by the designer to reduce fan- signal becomes active and the output pad reaches the
out, and/or it may also automatically reduce fan-out by high-impedance state.
net splitting.
PFU Timing
Table 41. Combinatorial PFU Timing Characteristics
Speed
Parameter Symbol -4 -5 -6 -7 Unit
Min Max Min Max Min Max Min Max
Combinatorial Delays (TJ = +85 °C, VDD = min):
Four-input Variables (Kz[3:0] to F[z])* F4_DEL — 2.34 — 1.80 — 1.32 — 1.05 ns
Five-input Variables (F5[A:D] to F[0, 2, 4, 6]) F5_DEL — 2.11 — 1.57 — 1.23 — 0.99 ns
Two-level LUT Delay (Kz[3:0] to F w/feedbk)* SWL2_DEL — 4.87 — 3.66 — 2.58 — 2.03 ns
Two-level LUT Delay (F5[A:D] to F w/feedbk) SWL2F5_DEL — 4.69 — 3.51 — 2.48 — 1.94 ns
Three-level LUT Delay (Kz[3:0] to F w/feedbk)* SWL3_DEL — 6.93 — 5.15 — 3.63 — 2.82 ns
Three-level LUT Delay (F5[A:D] to F w/feedbk) SWL3F5_DEL — 6.89 — 5.08 — 3.54 — 2.75 ns
CIN to COUT Delay (logic mode) CO_DEL — 3.47 — 2.65 — 1.79 — 1.43 ns
* Four-input variables’ (KZ[3:0]) path delays are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes.

Data Sheet
Timing Characteristics (continued)
FDBK–DEL
PFU
F4_DEL 8 F[7:0]
KZ[3:0] LUT
F[6, 4,
F5–DEL 4 2, 0]
KZ[3:0], F5[A:D] LUT
F4_DEL/ F[7:0]
F5_DEL
LUT
F4_DEL/
KZ[3:0]
LUT
SWL2_DEL
F4_DEL/ F[7:0]
F5_DEL
LUT
OMUX_DEL O[9:0]
F4_DEL/
F5_DEL
LUT
F4_DEL/
KZ[3:0]
LUT
SWL3_DEL
F4_DEL/ F[7:0]
F5_DEL
LUT
F4_DEL/
F5[A:D] F5_DEL
LUT
SWL2F5_DEL
F4_DEL/ F[7:0]
F5_DEL
LUT
F4_DEL/
F5_DEL
LUT
F4_DEL/
F5[A:D] F5_DEL
LUT
SWL3F5_DEL
Note: See Table 46 for an explanation of FDBK_DEL and OMUX_DEL.

5-5751(F)
Figure 64. Combinatorial PFU Timing

Data Sheet

Table 42. Sequential PFU Timing Characteristics
Speed

Input Requirements
Clock Low Time CLKL_MPW 3.36 — 2.07 — 0.94 — 0.72 — ns
Clock High Time CLKH_MPW 1.61 — 1.06 — 0.54 — 0.45 — ns
Global S/R Pulse Width (GSRN) GSR_MPW 3.36 — 2.07 — 0.94 — 0.72 — ns
Local S/R Pulse Width LSR_MPW 3.36 — 2.07 — 0.94 — 0.72 — ns
Combinatorial Setup Times (TJ = +85 °C, VDD = min):
Four-input Variables to Clock (Kz[3:0] to CLK)* F4_SET 1.99 — 1.47 — 1.08 — 0.85 — ns
Five-input Variables to Clock (F5[A:D] to CLK) F5_SET 1.79 — 1.33 — 1.03 — 0.81 — ns
Data In to Clock (DIN[7:0] to CLK) DIN_SET 0.47 — 0.32 — 0.18 — 0.16 — ns
Carry-in to Clock, DIRECT to REGCOUT (CIN to CLK) CINDIR_SET 1.25 — 0.99 — 0.71 — 0.58 — ns
Clock Enable to Clock (CE to CLK) CE1_SET 2.86 — 2.15 — 1.80 — 1.37 — ns
Clock Enable to Clock (ASWE to CLK) CE2_SET 1.68 — 1.30 — 0.95 — 0.77 — ns
Local Set/Reset to Clock (SYNC) (LSR to CLK) LSR_SET 1.86 — 1.36 — 0.86 — 0.68 — ns
Data Select to Clock (SEL to CLK) SEL_SET 1.37 — 1.00 — 0.92 — 0.70 — ns
Two-level LUT to Clock (Kz[3:0] to CLK w/feedbk)* SWL2_SET 3.98 — 2.99 — 2.13 — 1.63 — ns
Two-level LUT to Clock (F5[A:D] to CLK w/feedbk) SWL2F5_SET 4.06 — 2.97 — 2.29 — 1.68 — ns
Three-level LUT to Clock (Kz[3:0] to CLK w/feedbk)* SWL3_SET 6.49 — 4.81 — 3.42 — 2.64 — ns
Three-level LUT to Clock (F5[A:D] to CLK w/feedbk) SWL3F5_SET 6.39 — 4.73 — 3.34 — 2.57 — ns
Combinatorial Hold Times (TJ = all, VDD = all):
Data In (DIN[7:0] from CLK) DIN_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Carry-in from Clock, DIRECT to REGCOUT (CIN from CINDIR_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
CLK)
Clock Enable (CE from CLK) CE1_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Clock Enable from Clock (ASWE from CLK) CE2_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Local Set/Reset from Clock (sync) (LSR from CLK) LSR_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Data Select from Clock (SEL from CLK) SEL_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
All Others — 0.00 — 0.00 — 0.00 — 0.00 — ns
Output Characteristics
Sequential Delays (TJ = +85 °C, VDD = min):
Local S/R (async) to PFU Out (LSR to Q[7:0], REG- LSR_DEL — 7.02 — 5.29 — 3.64 — 2.90 ns
COUT)
Global S/R to PFU Out (GSRN to Q[7:0], REGCOUT) GSR_DEL — 5.21 — 3.90 — 2.55 — 2.00 ns
Clock to PFU Out—Register (CLK to Q[7:0], REG- REG_DEL — 2.38 — 1.75 — 1.26 — 0.97 ns
COUT)
Clock to PFU Out—Latch (CLK to Q[7:0]) LTCH_DEL — 2.51 — 1.88 — 1.21 — 0.96 ns
Transparent Latch (DIN[7:0] to Q[7:0]) LTCHD_DEL — 2.73 — 2.10 — 1.38 — 1.12 ns
* Four-input variables’ (KZ[3:0]) setup times are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes.
Note: The table shows worst-case delays. ORCA Foundry reports the delays for individual paths within a group of paths representing the same
timing parameter and may accurately report delays that are less than those listed.

Data Sheet

Table 43. Ripple Mode PFU Timing Characteristics
Speed
Parameter
Symbol -4 -5 -6 -7 Unit
(TJ = +85 °C, VDD = min)
Full Ripple Setup Times (byte wide):
Operands to Clock (Kz[1:0] to CLK) RIP_SET 3.50 — 2.50 — 1.96 — 1.48 — ns
Bitwise Operands to Clock (Kz[1:0] to CLK at F[z]) FRIP_SET 1.99 — 1.47 — 1.08 — 0.85 — ns
Fast Carry-in to Clock (FCIN to CLK) FCIN_SET 2.55 — 1.87 — 1.34 — 1.04 — ns
Carry-in to Clock (CIN to CLK) CIN_SET 3.80 — 2.79 — 1.97 — 1.56 — ns
Add/Subtract to Clock (ASWE to CLK) AS_SET 8.82 — 6.18 — 4.68 — 3.50 — ns
Operands to Clock (Kz[1:0] to CLK at REGCOUT) RIPRC_SET 2.09 — 1.61 — 1.19 — 0.93 — ns
Fast Carry-in to Clock (FCIN to CLK at REGCOUT) FCINRC_SET 2.29 — 1.76 — 1.28 — 1.02 — ns
Carry-in to Clock (CIN to CLK at REGCOUT) CINRC_SET 3.09 — 2.36 — 1.73 — 1.35 — ns
Add/Subtract to Clock (ASWE to CLK at REGCOUT) ASRC_SET 8.14 — 5.73 — 4.54 — 3.39 — ns
Full Ripple Hold Times (TJ = all, VDD = all):
Fast Carry-in from Clock (FCIN from CLK at REG- FCINRC_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
COUT)
All Others GENERIC_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Half Ripple Setup Times (nibble wide):
Operands to Clock (Kz[1:0] to CLK) HRIP_SET 3.91 — 2.81 — 2.21 — 1.66 — ns
Bitwise Operands to Clock (Kz[1:0] to CLK at F[z]) HFRIP_SET 1.99 — 1.47 — 1.08 — 0.85 — ns
Fast Carry-in to Clock (FCIN to CLK) HFCIN_SET 2.55 — 1.87 — 1.34 — 1.04 — ns
Carry-in to Clock (CIN to CLK) HCIN_SET 3.80 — 2.79 — 1.97 — 1.56 — ns
Add/Subtract to Clock (ASWE to CLK) HAS_SET 8.82 — 6.18 — 4.68 — 3.50 — ns
Operands to Clock (Kz[1:0] to CLK at REGCOUT) HRIPRC_SET 3.03 — 2.31 — 1.68 — 1.32 — ns
Fast Carry-in to Clock (FCIN to CLK at REGCOUT) HFCINRC_SET 2.29 — 1.76 — 1.28 — 1.02 — ns
Carry-in to Clock (CIN to CLK at REGCOUT) HCINRC_SET 3.09 — 2.36 — 1.73 — 1.35 — ns
Add/Subtract to Clock (ASWE to CLK at REGCOUT) HASRC_SET 8.14 — 5.73 — 4.54 — 3.39 — ns
Half Ripple Hold Times (TJ = all, VDD = all):
Fast Carry-in from Clock (HFCIN from CLK at REG- HFCINRC_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
COUT)
All Others GENERIC_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Note: The table shows worst-case delay for the ripple chain. ORCA Foundry reports the delay for individual paths within the ripple chain that
will be less than or equal to those listed above.

Data Sheet

Table 43. Ripple Mode PFU Timing Characteristics (continued)
Speed
Parameter
(TJ = +85 °C, VDD = min)
Full Ripple Delays (byte wide):
Operands to Carry-out (Kz[1:0] to COUT) RIPCO_DEL — 5.32 — 4.11 — 2.98 — 2.32 ns
Operands to Carry-out (Kz[1:0] to FCOUT) RIPFCO_DEL — 5.30 — 4.10 — 2.98 — 2.32 ns
Operands to PFU Out (Kz[1:0] to F[7:0]) RIP_DEL — 7.37 — 5.60 — 4.18 — 3.10 ns
Bitwise Operands to PFU Out (Kz[1:0] to F[z]) FRIP_DEL — 2.34 — 1.80 — 1.32 — 1.05 ns
Fast Carry-in to Carry-out (FCIN to COUT) FCINCO_DEL — 2.59 — 1.99 — 1.43 — 1.14 ns
Fast Carry-in to Fast Carry-out (FCIN to FCOUT) FCINFCO_DEL — 2.57 — 1.98 — 1.41 — 1.13 ns
Carry-in to Carry-out (CIN to COUT) CINCO_DEL — 3.47 — 2.65 — 1.79 — 1.43 ns
Carry-in to Fast Carry-out (CIN to FCOUT) CINFCO_DEL — 3.46 — 2.64 — 1.78 — 1.43 ns
Fast Carry-in PFU Out (FCIN to F[7:0]) FCIN_DEL — 6.03 — 4.55 — 3.21 — 2.51 ns
Carry-in PFU Out (CIN to F[7:0]) CIN_DEL — 6.91 — 5.21 — 3.53 — 3.05 ns
Add/Subtract to Carry-out (ASWE to COUT) ASCO_DEL — 8.28 — 5.89 — 4.58 — 3.45 ns
Add/Subtract to Carry-out (ASWE to FCOUT) ASFCO_DEL — 8.11 — 5.78 — 4.48 — 3.38 ns
Add/Subtract to PFU Out (ASWE to F[7:0]) AS_DEL — 10.66 — 7.55 — 5.85 — 4.38 ns
Half Ripple Delays (nibble wide):
Operands to Carry-out (Kz[1:0] to COUT) HRIPCO_DEL — 5.32 — 4.11 — 2.98 — 2.32 ns
Operands to Fast Carry-out (Kz[1:0] to FCOUT) HRIPFCO_DEL — 5.30 — 4.10 — 2.98 — 2.32 ns
Operands to PFU Out (Kz[1:0] to F[3:0]) HRIP_DEL — 5.50 — 4.07 — 3.20 — 2.40 ns
Bitwise Operands to PFU Out (Kz[1:0] to F[z]) HFRIP_DEL — 2.34 — 1.80 — 1.32 — 1.05 ns
Fast Carry-in to Carry-out (FCIN to COUT) HFCINCO_DEL — 2.59 — 1.99 — 1.43 — 1.14 ns
Fast Carry-in to Fast Carry-out (FCIN to FCOUT) HFCINFCO_DEL — 2.57 — 1.98 — 1.41 — 1.13 ns
Carry-in to Carry-out (CIN to COUT) HCINCO_DEL — 3.47 — 2.65 — 1.79 — 1.43 ns
Carry-in to Carry-out (CIN to FCOUT) HCINFCO_DEL — 3.46 — 2.64 — 1.78 — 1.43 ns
Fast Carry-in PFU Out (FCIN to F[3:0]) HFCIN_DEL — 3.76 — 2.84 — 2.01 — 1.58 ns
Carry-in PFU Out (CIN to F[3:0]) HCIN_DEL — 4.65 — 3.50 — 2.33 — 2.12 ns
Add/Subtract to Carry-out (ASWE to COUT) HASCO_DEL — 8.28 — 5.89 — 4.58 — 3.45 ns
Add/Subtract to Carry-out (ASWE to FCOUT) HASFCO_DEL — 8.11 — 5.78 — 4.48 — 3.38 ns
Add/Subtract to PFU Out (ASWE to F[3:0]) HAS_DEL — 9.12 — 6.49 — 4.86 — 3.69 ns
Note: The table shows worst-case delay for the ripple chain. ORCA Foundry reports the delay for individual paths within the ripple chain that will
be less than or equal to those listed above.

Data Sheet

Table 44. Synchronous Memory Write Characteristics
Speed
Write Operation for RAM Mode:
Maximum Frequency SMCLK_FRQ — 151.00 — 197.00 — 254.00 — 315.00 MHz
Clock Low Time SMCLKL_MPW 2.34 — 1.80 — 1.32 — 1.05 ns
Clock High Time SMCLKH_MPW 3.79 — 2.77 — 2.13 — 1.62 ns
Clock to Data Valid (CLK to F[6, 4, 2, 0])* MEM_DEL — 10.00 — 7.14 — 5.00 — 4.08 ns
Write Operation Setup Time:
Address to Clock (CIN to CLK) WA4_SET 1.25 — 0.99 — 0.71 — 0.58 — ns
Address to Clock (DIN[7, 5, 3, 1] to CLK) WA_SET 0.72 — 0.52 — 0.35 — 0.28 — ns
Data to Clock (DIN[6, 4, 2, 0] to CLK) WD_SET 0.02 — 0.06 — 0.00 — 0.00 — ns
Write Enable (WREN) to Clock (ASWE to CLK) WE_SET 0.18 — 0.16 — 0.14 — 0.12 — ns
Write-port Enable 0 (WPE0) to Clock (CE to WPE0_SET 2.25 — 1.69 — 1.16 — 0.84 — ns
CLK)
Write-port Enable 1 (WPE1) to Clock (LSR to WPE1_SET 2.79 — 2.13 — 1.58 — 1.31 — ns
CLK)
Write Operation Hold Time:
Address from Clock (CIN from CLK) WA4_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Address from Clock (DIN[7, 5, 3, 1] from CLK) WA_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Data from Clock (DIN[6, 4, 2, 0] from CLK) WD_HLD 0.59 — 0.42 — 0.40 — 0.32 — ns
Write Enable (WREN) from Clock (ASWE from WE_HLD 0.03 — 0.00 — 0.08 — 0.06 — ns
CLK)
Write-port Enable 0 (WPE0) from Clock (CE WPE0_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
from CLK)
Write-port Enable 1 (WPE1) from Clock (LSR WPE1_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
from CLK)
* The RAM is written on the inactive clock edge following the active edge that latches the address, data, and control signals.
WA4_SET WA4_HLD
WA_SET WA_HLD
CIN, DIN[7, 5, 3, 1]
WD_SET WD_HLD
DIN[6, 4, 2, 0]
WE_SET WE_HLD
ASWE (WREN)
WPE0_SET WPE0_HLD
WPE1_SET WPE1_HLD
CE (WPE0),
LSR (WPE1)
TSCH TSCL
CK
MEM_DEL
F[6, 4, 2, 0]
5-4621(F)
Figure 65. Synchronous Memory Write Characteristics

Data Sheet

Table 45. Synchronous Memory Read Characteristics
Speed
Parameter Unit
Symbol -4 -5 -6 -7
(TJ = 85 °C, VDD = min)
Read Operation:
Data Valid After Address (Kz[3:0] to F[6, 4, 2, 0]) RA_DEL — 2.34 — 1.80 — 1.32 — 1.05 ns
Data Valid After Address (F5[A:D] to F[6, 4, 2, 0]) RA4_DEL — 2.11 — 1.57 — 1.23 — 0.99 ns
Read Operation, Clocking Data into Latch/FF:
Address to Clock Setup Time (Kz[3:0] to CLK) RA_SET 1.99 — 1.47 — 1.08 — 0.85 — ns
Address to Clock Setup Time (F5[A:D] to CLK) RA4_SET 1.79 — 1.33 — 1.03 — 0.81 — ns
Address from Clock Hold Time (Kz[3:0] from CLK) RA_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Address from Clock Hold Time (F5[A:D] from CLK) RA4_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Clock to PFU Output—Register (CLK to Q[6, 4, 2, 0]) REG_DEL — 2.38 — 1.75 — 1.26 — 0.97 ns
Read Cycle Delay SMRD_CYC — 10.48 — 7.66 — 7.53 — 5.78 ns
Kz[3:0], F5[A:D]
RA_DEL
RA4_DEL
F[6, 4, 2, 0]
RA_HLD
RA_SET RA4_HLD
RA4_SET
CLK
REG_DEL
SMRD_CYC
Q[3:0]
5-4622(F)
Figure 66. Synchronous Memory Read Cycle

Data Sheet
PLC Timing
Table 46. PFU Output MUX and Direct Routing Timing Characteristics
Speed
Parameter Unit
Symbol -4 -5 -6 -7
(TJ = 85 °C, VDD = min)
PFU Output MUX (Fan-out = 1)
Output MUX Delay (F[7:0]/Q[7:0] to O[9:0]) OMUX_DEL — 0.50 — 0.39 — 0.35 — 0.28 ns
Carry-out MUX Delay (COUT to O9) COO9_DEL — 0.34 — 0.26 — 0.24 — 0.18 ns
Registered Carry-out MUX Delay (REGCOUT RCOO8_DEL — 0.34 — 0.26 — 0.24 — 0.18 ns
to O8)
Direct Routing
PFU Feedback (xSW)* FDBK_DEL — 1.74 — 1.41 — 1.48 — 1.14 ns
PFU to Orthogonal PFU Delay (xSW to xSW) ODIR_DEL — 2.21 — 1.77 — 1.75 — 1.39 ns
PFU to Diagonal PFU Delay (xBID to xSW) DDIR_DEL — 2.69 — 2.19 — 2.53 — 1.98 ns
* This is general feedback using switching segments. See the combinatorial PFU timing table for softwired look-up table feedback timing.
SLIC Timing
Table 47. Supplemental Logic and Interconnect Cell (SLIC) Timing Characteristics
Speed
Parameter Unit
Symbol -4 -5 -6 -7
(TJ = 85 °C, VDD = min)
3-Statable BIDIs
BIDI Delay (BRx to BLx, BLx to BRx) BUF_DEL — 0.84 — 0.70 — 0.94 — 0.77 ns
BIDI Delay (Ox to BRx, Ox to BLx) OBUF_DEL — 0.72 — 0.61 — 0.87 — 0.70 ns
BIDI 3-state Enable/Disable Delay (TRI to BL, BR) TRI_DEL — 2.55 — 1.90 — 1.31 — 1.01 ns
BIDI 3-state Enable/Disable Delay DECTRI_DEL — 3.59 — 2.65 — 1.91 — 1.48 ns
(BL, BR via DEC, TRI to BL, BR)
Decoder
Decoder Delay (BR[9:8], BL[9:8] to DEC) DEC98_DEL — 2.39 — 1.85 — 1.27 — 1.02 ns
Decoder Delay (BR[7:0], BL[7:0] to DEC) DEC_DEL — 2.35 — 1.82 — 1.23 — 0.99 ns

Data Sheet
PIO Timing
Table 48. Programmable I/O (PIO) Timing Characteristics
Speed
Input Delays (TJ = 85 °C, VDD = min)
Input Rise Time IN_RIS — 500 — 500 — 500 — 500 ns
Input Fall Time IN_FAL — 500 — 500 — 500 — 500 ns
PIO Direct Delays:
Pad to In (pad to CLK IN) CKIN_DEL — 1.41 — 1.26 — 0.64 — 0.41 ns
Pad to In (pad to IN1, IN2) IN_DEL — 2.16 — 1.87 — 1.28 — 0.90 ns
Pad to In Delayed (pad to IN1, IN2) IND_DEL — 9.05 — 7.83 — 6.64 — 7.27 ns
PIO Transparent Latch Delays:
Pad to In (pad to IN1, IN2) LATCH_DEL — 4.11 — 3.25 — 2.52 — 1.82 ns
Pad to In Delayed (pad to IN1, IN2) LATCHD_DEL — 10.58 — 9.05 — 7.67 — 7.65 ns
Input Latch/FF Setup Timing:
Pad to ExpressCLK (fast-capture latch/FF) INREGE_SET 5.93 — 4.82 — 3.63 — 3.23 — ns
Pad Delayed to ExpressCLK INREGED_SET 12.86 — 11.03 — 9.18 — 9.68 — ns
(fast-capture latch/FF)
Pad to Clock (input latch/FF) INREG_SET 1.62 — 1.42 — 0.71 — 0.50 — ns
Pad Delayed to Clock (input latch/FF) INREGD_SET 8.57 — 7.36 — 5.91 — 7.06 — ns
Clock Enable to Clock (CE to CLK) INCE_SET 2.03 — 1.64 — 1.29 — 1.00 — ns
Local Set/Reset (sync) to Clock (LSR to CLK) INLSR_SET 1.79 — 1.45 — 1.14 — 0.89 — ns
Input FF/Latch Hold Timing:
Pad from ExpressCLK (fast-capture latch/FF) INREGE_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Pad Delayed from ExpressCLK INREGED_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
(fast-capture latch/FF)
Pad from Clock (input latch/FF) INREG_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Pad Delayed from Clock (input latch/FF) INREGD_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Clock Enable from Clock (CE from CLK) INCE_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Local Set/Reset (sync) from Clock INLSR_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
(LSR from CLK)
Clock-to-in Delay (FF CLK to IN1, IN2) INREG_DEL — 4.05 — 3.14 — 2.53 — 2.05 ns
Clock-to-in Delay (latch CLK to IN1, IN2) INLTCH_DEL — 4.08 — 3.19 — 2.62 — 2.14 ns
Local S/R (async) to IN (LSR to IN1, IN2) INLSR_DEL — 6.11 — 4.76 — 3.81 — 3.17 ns
Local S/R (async) to IN (LSR to IN1, IN2) INLSRL_DEL — 5.89 — 4.66 — 3.57 — 2.98 ns
LatchFF in Latch Mode
Global S/R to In (GSRN to IN1, IN2) INGSR_DEL — 5.38 — 4.22 — 3.44 — 2.88 ns
Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns.

Data Sheet

Table 48. Programmable I/O (PIO) Timing Characteristics (continued)
Speed
Output Delays (TJ = 85 °C, VDD = min, CL = 50 pF)
Output to Pad (OUT2, OUT1 direct to pad):
Fast OUTF_DEL — 5.09 — 4.21 — 2.63 — 2.17 ns
Slewlim OUTSL_DEL — 7.86 — 6.49 — 3.49 — 2.91 ns
Sinklim OUTSI_DEL — 9.41 — 7.98 — 8.08 — 7.32 ns
3-state Enable/Disable Delay (TS to pad):
Fast TSF_DEL — 4.93 — 4.09 — 2.33 — 1.88 ns
Slewlim TSSL_DEL — 7.70 — 6.37 — 3.00 — 2.41 ns
Sinklim TSSI_DEL — 9.25 — 7.86 — 7.95 — 7.23 ns
Local Set/Reset (async) to Pad (LSR to pad):
Fast OUTLSRF_DEL — 9.03 — 7.25 — 4.96 — 3.94 ns
Slewlim OUTLSRSL_DEL — 11.79 — 9.53 — 5.82 — 4.67 ns
Sinklim OUTLSRSI_DEL — 13.35 — 11.02 — 10.38 — 9.10 ns
Global Set/Reset to Pad (GSRN to pad):
Fast OUTGSRF_DEL — 8.30 — 6.69 — 4.39 — 3.46 ns
Slewlim OUTGSRSL_DEL — 11.06 — 8.97 — 5.07 — 3.99 ns
Sinklim OUTGSRSI_DEL — 12.62 — 10.46 — 10.02 — 8.81 ns
Output FF Setup Timing:
Out to ExpressCLK (OUT[2:1] to ECLK) OUTE_SET 0.00 — 0.00 — 0.00 — 0.00 — ns
Out to Clock (OUT[2:1] to CLK) OUT_SET 0.00 — 0.00 — 0.00 — 0.00 — ns
Clock Enable to Clock (CE to CLK) OUTCE_SET 0.91 — 0.67 — 0.56 — 0.45 — ns
Local Set/Reset (sync) to Clock (LSR to CLK) OUTLSR_SET 0.41 — 0.32 — 0.26 — 0.24 — ns
Output FF Hold Timing:
Out from ExpressCLK (OUT[2:1] from ECLK) OUTE_HLD 0.73 — 0.58 — 0.36 — 0.29 — ns
Out from Clock (OUT[2:1] from CLK) OUT_HLD 0.73 — 0.58 — 0.36 — 0.29 — ns
Clock Enable from Clock (CE from CLK) OUTCE_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Local Set/Reset (sync) from Clock (LSR from OUTLSR_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
CLK)
Clock to Pad Delay (ECLK, SCLK to pad):
Fast OUTREGF_DEL — 6.71 — 5.44 — 3.56 — 2.78 ns
Slewlim OUTREGSL_DEL — 9.47 — 7.71 — 4.42 — 3.52 ns
Sinklim OUTREGSI_DEL — 11.03 — 9.20 — 8.98 — 7.94 ns
Additional Delay If Using Open Drain OD_DEL — 0.20 — 0.16 — 0.10 — 0.08 ns

Data Sheet

Table 48. Programmable I/O (PIO) Timing Characteristics (continued)
Speed
PIO Logic Block Delays
Out to Pad (OUT[2:1] via logic to pad):
Fast OUTLF_DEL — 5.09 — 4.21 — 2.63 — 2.17 ns
Slewlim OUTLSL_DEL — 7.86 — 6.49 — 3.49 — 2.91 ns
Sinklim OUTLSI_DEL — 9.41 — 7.98 — 8.08 — 7.32 ns
Outreg to Pad (OUTREG via logic to pad):
Fast OUTRF_DEL — 6.71 — 5.44 — 3.56 — 2.78 ns
Slewlim OUTRSL_DEL — 9.47 — 7.71 — 4.42 — 3.52 ns
Sinklim OUTRSI_DEL — 11.03 — 9.20 — 8.98 — 7.94 ns
Clock to Pad (ECLK, CLK via logic to pad):
Fast OUTCF_DEL — 6.97 — 5.68 — 3.71 — 2.91 ns
Slewlim OUTCSL_DEL — 9.74 — 7.96 — 4.57 — 3.64 ns
Sinklim OUTCSI_DEL — 11.29 — 9.45 — 9.13 — 8.07 ns
3-State FF Delays
3-state Enable/Disable Delay (TS direct to
pad):
Fast TSF_DEL — 4.93 — 4.09 — 2.33 — 1.88 ns
Slewlim TSSL_DEL — 7.70 — 6.37 — 3.00 — 2.41 ns
Sinklim TSSI_DEL — 9.25 — 7.86 — 7.95 — 7.23 ns
Local Set/Reset (async) to Pad (LSR to
pad):
Fast TSLSRF_DEL — 8.25 — 6.65 — 4.24 — 3.39 ns
Slewlim TSLSRSL_DEL — 11.01 — 8.92 — 4.92 — 3.92 ns
Sinklim TSLSRSI_DEL — 12.57 — 10.41 — 9.87 — 8.74 ns
Global Set/Reset to Pad (GSRN to pad):
Fast TSGSRF_DEL — 7.52 — 6.09 — 3.88 — 3.11 ns
Slewlim TSGSRSL_DEL — 10.28 — 8.36 — 4.55 — 3.64 ns
Sinklim TSGSRSI_DEL — 11.84 — 9.85 — 9.51 — 8.45 ns
3-State FF Setup Timing:
TS to ExpressCLK (TS to ECLK) TSE_SET 0.00 — 0.00 — 0.00 — 0.00 — ns
TS to Clock (TS to CLK) TS_SET 0.00 — 0.00 — 0.00 — 0.00 — ns
Local Set/Reset (sync) to Clock (LSR to TSLSR_SET 0.28 — 0.21 — 0.17 — 0.18 — ns
CLK)
3-State FF Hold Timing:
TS from ExpressCLK (TS from ECLK) TSE_HLD 0.85 — 0.68 — 0.44 — 0.34 — ns
TS from Clock (TS from CLK) TS_HLD 0.85 — 0.68 — 0.44 — 0.34 — ns
Local Set/Reset (sync) from Clock TSLSR_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
(LSR from CLK)
Clock to Pad Delay (ECLK, SCLK to pad):
Fast TSREGF_DEL — 5.94 — 4.82 — 2.84 — 2.23 ns
Slewlim TSREGSL_DEL — 8.70 — 7.10 — 3.52 — 2.76 ns
Sinklim TSREGSI_DEL — 10.26 — 8.59 — 8.47 — 7.58 ns

Data Sheet

Special Function Blocks Timing
Table 49. Microprocessor Interface (MPI) Timing Characteristics
Speed
Parameter Symbol –4 –5 –6 –7 Unit
PowerPC Interface Timing (TJ = 85 °C, VDD = min)

Transfer Acknowledge Delay (CLK to TA) TA_DEL — 11.6 — 9.3 — 8.0 — 6.8 ns
Burst Inhibit Delay (CLK to BIN) BI_DEL — 11.6 — 9.3 — 8.0 — 6.8 ns
Transfer Acknowledge Delay to High Impedance TA_DELZ — (2) — (2) — (2) — (2) ns
Burst Inhibit Delay to High Impedance BI_DELZ — (2) — (2) — (2) — (2) ns
Write Data Setup Time (data to TS) WD_SET 0.0 — 0.0 — 0.0 — 0.0 — ns
Write Data Hold Time (data from CLK while MPI_ACK low) WD_HLD 0.0 — 0.0 — 0.0 — 0.0 — ns
Address Setup Time (addr to TS) A_SET 0.0 — 0.0 — 0.0 — 0.0 — ns
Address Hold Time (addr from CLK while MPI_ACK low) A_HLD 0.0 — 0.0 — 0.0 — 0.0 — ns
Read/Write Setup Time (R/W to TS) RW_SET 0.0 — 0.0 — 0.0 — 0.0 — ns
Read/Write Hold Time (R/W from CLK while MPI_ACK low) RW_HLD 0.0 — 0.0 — 0.0 — 0.0 — ns
Chip Select Setup Time (CS0, CS1 to TS) CS_SET 0.3 — .25 — .14 — .12 — ns
Chip Select Hold Time (CS0, CS1 from CLK) CS_HLD 0.0 — 0.0 — 0.0 — 0.0 — ns
User Address Delay (pad to UA[3:0]) UA_DEL — 3.3 — 2.6 — 2.3 — 1.9 ns
User Read/Write Delay (pad to URDWR_DEL) URDWR_DEL — 7.0 — 5.4 — 4.2 — 3.6 ns
i960 Interface Timing (TJ = 85 °C, VDD = min)
Addr/Data Select to ALE (ADS, to ALE low) ADSN_SET 2.0 — 1.8 — 1.6 — 1.4 — ns
Addr/Data Select to ALE (ADS, from ALE low) ADSN_HLD 0.0 — 0.0 — 0.0 — 0.0 — ns
Ready/Receive Delay (CLK to RDYRCV) RDYRCV_DEL — 11.6 — 9.3 — 8.0 — 6.8 ns
Ready/Receive Delay to High Impedance RDYRCV_DELZ — (2) — (2) — (2) — (2) ns
Write Data Setup Time WD_SET (3) — (3) — (3) — (3) — ns
Write Data Hold Time WD_HLD (4) — (4) — (4) — (4) — ns
Address Setup Time (addr to ALE low) A_SET 2.0 — 1.8 — 0.50 — — 0.42 ns
Address Hold Time (addr from ALE low) A_HLD 2.0 — 1.8 — 0.51 — — 0.44 ns
Byte Enable Setup Time (BE0, BE1 to ALE low) BE_SET 2.0 — 1.8 — 0.50 — — 0.42 ns
Byte Enable Hold Time (BE0, BE1 from ALE low) BE_HLD 2.0 — 1.8 — 0.51 — — 0.44 ns
Read/Write Setup Time RW_SET (3) — (3) — (3) — (3) — ns
Read/Write Hold Time RW_HLD (4) — (4) — (4) — (4) — ns
Chip Select Setup Time (CS0, CS1 to CLK)(1) CS_SET 2.0 — 1.8 — 0.45 — — 0.38 ns
Chip Select Hold Time (CS0, CS1 from CLK)(1) CS_HLD 0.0 — 0.0 — 0.0 — 0.0 — ns
User Address Delay (CLK low to UA[3:0]) UA_DEL — 6.6 — 4.3 — 4.1 — 3.5 ns
User Read/Write Delay (pad to URDWR_DEL) URDWR_DEL — 7.0 — 5.4 — 4.2 — 3.6 ns
1. For user system flexibility, CS0 and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when
MPI_STRB is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CS0 and CS1 may go
inactive before the end of the read/write cycle.
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
Notes:
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA.
PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).

Data Sheet

Table 49. Microprocessor Interface (MPI) Timing Characteristics (continued)
Speed
Parameter Symbol –4 –5 –6 –7 Unit
User Logic Delay(5) User Logic Delay — — — — — — — — ns
User Start Delay (MPI_CLK falling to USTART)(6) USTART_DEL — 3.6 — 3.4 — 3.3 — 2.8 ns
User Start Clear Delay (MPI_CLK to USTART) USTARTCLR_DEL — 7.5 — 7.3 — 7.1 — 6.0 ns
User End Delay (USTART low to UEND low)(7) UEND_DEL — — — — — — — — ns
Synchronous User Timing:
User End Setup (UEND to MPI_CLK) UEND_SET 0.00 — 0.00 — 0.00 — 0.00 — ns
User End Hold (UEND to MPI_CLK) UEND_HLD 1.0 — 0.95 — 0.88 — 0.75 — ns
Data Setup for Read (D[7:0] to MPI_CLK)(9) RDS_SET — — — — — — — — ns
Data Hold for Read (D[7:0] from MPI_CLK)(9) RDS_HLD — — — — — — — — ns
Asynchronous User Timing:
User End to Read Data Delay (UEND to RDA_DEL — — — — — — — — ns
D[7:0])(10)
Data Hold from User Start (low)(9) RDA_HLD — — — — — — — — ns
Interrupt Request Pulse Width(8) TUIRQ_PW — — — — — — — — ns
1. For user system flexibility, CS0 and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when
MPI_STRB is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CS0 and CS1 may go
inactive before the end of the read/write cycle.
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
5. User Logic Delay has no predefined value. The user must generate a UEND signal to complete the cycle.
6. USTART_DEL is based on the falling clock edge.
7. There is no specific time associated with this delay. The user must assert UEND low to complete this cycle.
8. The user must assert interrupt request low until a service routine is executed.
9. This should be at least one MPI_CLK cycle.
10. User should set up read data so that RDS_SET and RDS_HLD can be met for the microprocessor timing.
Notes:
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA.
PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).

Data Sheet
UEND_SET RDS_HLD
CS_SET
CS_HLD
RW_SET
A_HLD
A_SET RW_HLD
RDS_SET
MPI_CLK
A[4:0]
MPI_RW (RD/WR)
CS0, CS1
RDA_DEL RDA_HLD
D[7:0]
MPI_STRB (TS)
UA_DEL
UA[3:0]
URDWR_DEL
URDWRN
USTART_DEL USTARTCLR_DEL
USTART
USER LOGIC DELAY UEND_DEL

UEND TA_DELZ
TA_DEL TA_DEL
MPI_ACK (TA)
BI_DEL BI_DEL
MPI_BI (BI)
BI_DELZ
5-5832(F)
Figure 67. MPI PowerPC User Space Read Timing
CS_SET WD_HLD
RW_SET UEND_SET CS_HLD
A_SET RW_HLD
A_HLD
MPI_CLK
A[4:0]
MPI_RW (RD/WR)
CS0, CS1
WD_SET
D[7:0]
MPI_STRB (TS)
UA_DEL
UA[3:0]
URDWR_DEL
URDWRN
USTART

UEND TA_DELZ
TA_DEL TA_DEL
MPI_ACK (TA)
BI_DEL BI_DEL
MPI_BI (BI)
BI_DELZ
5-5840(F)
Figure 68. MPI PowerPC User Space Write Timing

Data Sheet
UEND_SET RDS_HLD
CS_SET
CS_HLD
RW_SET
A_HLD
A_SET RW_HLD
RDS_SET
MPI_CLK
A[4:0]
MPI_RW (RD/WR)
CS0, CS1
RDA_DEL RDA_HLD
D[7:0]
MPI_STRB (TS)
UA_DEL
UA[3:0]
URDWR_DEL
URDWRN
TA_DELZ
TA_DEL TA_DEL
MPI_ACK (TA)
BI_DEL BI_DEL
MPI_BI (BI)
BI_DELZ
5-5832(F).c
Figure 69. MPI PowerPC Internal Read Timing
CS_SET WD_HLD
RW_SET CS_HLD
A_SET RW_HLD
A_HLD
MPI_CLK
A[4:0]
MPI_RW (RD/WR)
CS0, CS1
WD_SET
D[7:0]
MPI_STRB (TS)
UA_DEL
UA[3:0]
URDWR_DEL
URDWRN
TA_DELZ
TA_DEL TA_DEL
MPI_ACK (TA)
BI_DEL BI_DEL
MPI_BI (BI)
BI_DELZ
5-5840(F).e
Figure 70. MPI PowerPC Internal Write Timing

Data Sheet

CS_SET
A_HLD
A_SET
ADSN_HLD
RDS_HLD
ADSN_SET
RDS_SET RW_HLD
RW_SET UEND_SET CS_HLD
MPI_CLK
RDA_DEL RDA_HLD
D[7:0] ADDR DATA
MPI_RW (W/R)
CS0, CS1
BE0, BE1
BE_SET
BE_HLD
MPI_ALE (ALE)
MPI_STRB (ADS)
UA_DEL
UA[3:0]
URDWR_DEL
URDWRN
USTART
UEND RDYRCV_DELZ
RDYRCV_DEL RDYRCV_DEL
MPI_ACK (RDYRCV)
5-5831(F).b
Figure 71. MPI i960 User Space Read Timing
CS_SET
A_HLD
WD_HLD
A_SET ADSN_HLD
RW_HLD
ADSN_SET
RW_SET WD_SET UEND_SET CS_HLD
MPI_CLK
D[7:0] ADDR DATA
MPI_RW (W/R)
CS0, CS1
MPI_ALE (ALE)
MPI_STRB (ADS)
UA_DEL
UA[3:0]
URDWR_DEL
URDWRN
USTART
UEND
MPI_ACK (RDYRCV)
RDYRCV_DELZ
5-5830(F).b
Figure 72. MPI i960 User Space Write Timing

Data Sheet

CS_SET
A_HLD
A_SET
ADSN_HLD RDS_HLD
ADSN_SET RDS_SET RW_HLD
RW_SET CS_HLD
MPI_CLK
RDA_DEL RDA_HLD
D[7:0] ADDR DATA
MPI_RW (W/R)
CS0, CS1
BE0, BE1
BE_SET
BE_HLD
MPI_ALE (ALE)
MPI_STRB (ADS)
UA_DEL
UA[3:0]
URDWR_DEL
URDWRN
RDYRCV_DELZ
MPI_ACK (RDYRCV)
5-5831(F).c
Figure 73. MPI i960 Internal Read Timing
CS_SET
A_HLD
A_SET ADSN_HLD WD_HLD
ADSN_SET RW_HLD
RW_SET WD_SET CS_HLD
MPI_CLK
D[7:0] ADDR DATA
MPI_RW (W/R)
CS0, CS1
MPI_ALE (ALE)
MPI_STRB (ADS)
UA_DEL
UA[3:0]
URDWR_DEL
URDWRN
MPI_ACK (RDYRCV)
RDYRCV_DELZ
5-5830(F).c
Figure 74. MPI i960 Internal Write Timing

Data Sheet

Table 50. Programmable Clock Manager (PCM) Timing Characteristics (Preliminary Information)
OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C ≤TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.
Speed
Input Clock Frequency: FPCMI
OR3Cxx 5 133 5 133 — — — — MHz
OR3Txxx — — 5 133 5 133 5 133 MHz
Output Clock Frequency: FPCMO
OR3Cxx 5 135 5 135 — — — — MHz
OR3Txxx — — 5 100 5 100 5 100 MHz
Input Clock Duty Cycle PCMI_DUTY 30.00 70.00 30.00 70.00 30.00 70.00 30.00 70.00 %
Output Clock Duty Cycle PCMO_DUTY 3.13 96.90 3.13 96.90 3.13 96.90 3.13 96.90 %
Input Frequency Tolerance* FTOL — 26400 — 26400 — 26400 — 26400 ppm
PCM Acquisition Time (CLK In to PCM_ACQ† 36 100 36 100 36 100 36 100 µs
LOCK)
PCM Off Delay (config. Done-L, WE to PCMOFF_DEL — 100.0 — 100.0 — 100.0 — 100.0 ns
PCM power off)
PCM Delay in DLL Mode (propagation PCMDLL-DEL — 1.95 — 1.82 — 1.63 — 1.50 ns
delay)
PCM Delay in PLL Mode (propagation PCMPLL_DEL — 0.00 — 0.00 — 0.00 — 0.00 ns
delay)
PCM Clock In to PCM Clock Out PCMBYE_DEL — 0.47 — 0.36 — 0.26 — 0.24 ns
(CLK In to ECLK)‡
PCM Clock In to PCM Clock Out PCMBYS_DEL — 0.47 — 0.36 — 0.26 — 0.24 ns
(CLK In to SCLK)‡
Routed Clock-in Delay (routing to PCM RTCKD_DEL — 1.30 — 1.10 — 0.90 — TBD ns
phase detect, using DIV0)
System Clock-out Delay (PCM oscilla- PCMSCK_DEL — 2.70 — 2.20 — 1.90 — TBD ns
tor to SCLK output at PCM)
Parameter Symbol fOUT (MHz) PLL Mode DLL Mode Unit
Output Jitter OUTJIT 5—20 250 200 ps
21—30 210 170 ps
31—40 180 145 ps
41—50 155 123 ps
51—60 130 105 ps
61—70 110 90 ps
71—80 95 75 ps
81—90 80 65 ps
91—100 70 55 ps
* Input frequency tolerance is the allowed input clock frequency change in parts per million.
† See Table 29 and Table 30 for acquisition times for individual frequencies.
‡ PLL mode, divider reg = 1111111 (input freq. = output freq.).
Note: All timing values for the PCM are preliminary information.

Data Sheet

Table 51. Boundary-Scan Timing Characteristics

TDI/TMS to TCK Setup Time TS 25.0 — ns
TDI/TMS Hold Time from TCK TH 0.0 — ns
TCK Low Time TCL 50.0 — ns
TCK High Time TCH 50.0 — ns
TCK to TDO Delay TD — 20.0 ns
TCK Frequency TTCK — 10.0 MHz
TCK
TS TH
TMS
TDI
TD
TDO
5-6764(F)
Figure 75. Boundary-Scan Timing Diagram

Data Sheet
Clock Timing
Table 52. ExpressCLK (ECLK) and Fast Clock (FCLK) Timing Characteristics
Speed
Device
(TJ = 85 °C, VDD = min)
Clock Control Timing Delay Through ECLKC_DEL 0.31 — 0.31 — 0.31 — 0.31 — ns
CLKCNTRL (input from corner)
Delay Through CLKCNTRL (input from inter- ECLKM_DEL 1.54 — 1.17 — 1.00 — 0.92 — ns
nal clock controller PAD)
Clock Shutoff Timing:
Setup from Middle ECLK (shut off to CLK) OFFM_SET 0.77 — 0.51 — 0.44 — 0.41 — ns
Hold from Middle ECLK (shut off from CLK) OFFM_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
Setup from Corner ECLK (shut off to CLK) OFFC_SET 0.77 — 0.51 — 0.44 — 0.41 — ns
Hold from Corner ECLK (shut off from CLK) OFFC_HLD 0.00 — 0.00 — 0.00 — 0.00 — ns
ECLK Delay (middle pad): ECLKM_DEL
OR3T20 — — — 2.56 — 2.05 — 1.78 ns
OR3T30 — — — 2.62 — 2.08 — 1.80 ns
OR3T55 — 3.50 — 2.74 — 2.13 — 1.85 ns
OR3C/T80 — 3.67 — 2.86 — 2.19 — 1.90 ns
OR3T125 — — — 3.06 — 2.29 — 1.98 ns
ECLK Delay (corner pad): ECLKC_DEL
OR3T20 — — — 4.48 — 3.85 — 3.36 ns
OR3T30 — — — 4.53 — 3.97 — 3.47 ns
OR3T55 — 5.47 — 4.64 — 4.22 — 3.69 ns
OR3C/T80 — 5.64 — 4.77 — 4.47 — 3.92 ns
OR3T125 — — — 4.96 — 4.85 — 4.27 ns
FCLK Delay (middle pad): FCLKM_DEL
OR3T20 — — — 5.91 — 4.59 — 3.81 ns
OR3T30 — — — 6.12 — 4.66 — 3.89 ns
OR3T55 — 8.24 — 6.59 — 4.83 — 4.06 ns
OR3C/T80 — 8.87 — 7.11 — 5.01 — 4.26 ns
OR3T125 — — — 7.98 — 5.33 — 4.59 ns
FCLK Delay (corner pad): FCLKC_DEL
OR3T20 — — — 7.88 — 6.41 — 5.40 ns
OR3T30 — — — 8.11 — 6.58 — 5.58 ns
OR3T55 — 10.34 — 8.60 — 6.95 — 5.94 ns
OR3C/T80 — 11.01 — 9.15 — 7.34 — 6.33 ns
OR3T125 — — — 10.07 — 7.96 — 6.94 ns
Notes:
The ECLK delays are to all of the PICs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay
includes both the input buffer delay and the clock routing to the PIC clock input.
The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer
delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.

Data Sheet

Table 53. General-Purpose Clock Timing Characteristics (Internally Generated Clock)
Speed
Device
(TJ = 85 °C, VDD = min)
OR3T20 CLK_DEL — — — 4.22 — 3.46 — 2.84 ns
OR3T30 CLK_DEL — — — 4.29 — 3.48 — 2.87 ns
OR3T55 CLK_DEL — 5.34 — 4.41 — 3.53 — 2.93 ns
OR3C/T80 CLK_DEL — 5.49 — 4.52 — 3.57 — 2.98 ns
OR3T125 CLK_DEL — — — 4.80 — 3.71 — 3.13 ns
Notes:
This table represents the delay for an internally generated clock from the clock tree input in one of the four middle PICs (using pSW routing) on
any side of the device which is then distributed to the PFU/PIO clock inputs. If the clock tree input used is located at any other PIC, see the
results reported by ORCA Foundry.
This clock delay is for a fully routed clock tree that uses the general clock network. The delay will be reduced if any of the clock branches are not
used. See pin-to-pin timing in Table 56 for clock delays of clocks input on general I/O pins.

Data Sheet

Table 54. OR3Cxx ExpressCLK to Output Delay (Pin-to-Pin)
OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C; CL = 50 pF.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C;CL = 50
pF.
Speed
Description
Device -4 -5 -6 -7 Unit
(TJ = 85 °C, VDD = min)
ECLK Middle Input Pin→OUTPUT Pin OR3T20 — — — 7.78 — 5.40 — 4.38 ns
(Fast) OR3T30 — — — 7.84 — 5.43 — 4.40 ns
OR3T55 — 9.93 — 7.96 — 5.48 — 4.44 ns
OR3C/T80 — 10.10 — 8.08 — 5.54 — 4.49 ns
OR3T125 — — — 8.28 — 5.64 — 4.58 ns
(Slewlim) OR3T30 — — — 9.83 — 6.10 — 4.93 ns
OR3T55 — 12.37 — 9.95 — 6.15 — 4.97 ns
OR3C/T80 — 12.54 — 10.07 — 6.21 — 5.02 ns
OR3T125 — — — 10.27 — 6.31 — 5.11 ns
(Sinklim) OR3T30 — — — 11.18 — 10.95 — 9.67 ns
OR3T55 — 13.73 — 11.30 — 11.00 — 9.71 ns
OR3C/T80 — 13.90 — 11.42 — 11.06 — 9.76 ns
OR3T125 — — — 11.62 — 11.16 — 9.85 ns
Additional Delay if ECLK Corner Pin Used OR3T20 — — — 1.91 — 1.80 — 1.58 ns
OR3T30 — — — 1.91 — 1.90 — 1.67 ns
OR3T55 — 1.97 — 1.91 — 2.09 — 1.84 ns
OR3C/T80 — 1.97 — 1.91 — 2.28 — 2.02 ns
OR3T125 — — — 1.90 — 2.57 — 2.29 ns
Notes:
Timing is without the use of the programmable clock manager (PCM).
This clock delay is for a fully routed clock tree that uses the ExpressCLK network. It includes both the input buffer delay, the clock routing to the
PIO CLK input, the clock→Q of the FF, and the delay through the output buffer. The given timing requires that the input clock pin be located at
one of the six ExpressCLK inputs of the device, and that a PIO FF be used.
PIO FF
D Q OUTPUT (50 pF LOAD)
CLKCNTRL
ECLK
ECLK
5-4846(F).a
Figure 76. ExpressCLK to Output Delay

Data Sheet

Table 55. OR3Cxx Fast Clock (FCLK) to Output Delay (Pin-to-Pin)
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C;
CL = 50 pF.
Speed
Description
(TJ = 85 °C, VDD = min)
Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs)
ECLK Middle Input Pin →OUTPUT Pin OR3T20 — — — 11.13 — 7.94 — 6.40 ns
(Fast) OR3T30 — — — 11.35 — 8.01 — 6.48 ns
OR3T55 — 14.68 — 11.81 — 8.18 — 6.66 ns
OR3C/T80 — 15.30 — 12.33 — 8.36 — 6.85 ns
OR3T125 — — — 13.20 — 8.68 — 7.19 ns
(Slewlim) OR3T30 — — — 13.33 — 8.68 — 7.01 ns
OR3T55 — 17.11 — 13.80 — 8.85 — 7.19 ns
OR3C/T80 — 17.74 — 14.32 — 9.04 — 7.38 ns
OR3T125 — — — 15.19 — 9.35 — 7.72 ns
(Sinklim) OR3T30 — — — 14.68 — 13.53 — 11.75 ns
OR3T55 — 18.47 — 15.15 — 13.70 — 11.93 ns
OR3C/T80 — 19.10 — 15.67 — 13.88 — 12.12 ns
OR3T125 — — — 16.54 — 14.20 — 12.46 ns
Additional Delay if ECLK Corner Pin OR3T20 — — — 1.97 — 1.82 — 1.60 ns
Used OR3T30 — — — 1.99 — 1.92 — 1.69 ns
OR3T55 — 2.10 — 2.01 — 2.12 — 1.88 ns
OR3C/T80 — 2.14 — 2.04 — 2.33 — 2.07 ns
OR3T125 — — — 2.09 — 2.63 — 2.39 ns
Notes:
Timing is without the use of the programmable clock manager (PCM).
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the
PIO CLK input, the clock→Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not
used. The given timing requires that the input clock pin be located at one of the six ExpressCLK inputs of the device and that a PIO FF be used.
PIO FF
CLKCNTRL
ECLK
FCLK
5-4846(F).b
Figure 77. Fast Clock to Output Delay

Data Sheet

Table 56. OR3Cxx General System Clock (SCLK) to Output Delay (Pin-to-Pin)
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C;
CL = 50 pF.
Speed
Description
(TJ = 85 °C, VDD = min)
Output On Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs)
Clock Input Pin (mid-PIC) →OUTPUT Pin (Fast) OR3T20 — — — 11.35 — 7.74 — 6.10 ns
OR3T30 — — — 11.63 — 7.93 — 6.27 ns
OR3T55 — 14.91 — 12.17 — 8.28 — 6.59 ns
OR3C/T80 — 15.71 — 12.80 — 8.66 — 6.95 ns
OR3T125 — — — 13.69 — 9.24 — 7.49 ns
Clock Input Pin (mid-PIC) →OUTPUT Pin OR3T20 — — — 13.34 — 8.42 — 6.63 ns
(Slewlim) OR3T30 — — — 13.62 — 8.60 — 6.80 ns
OR3T55 — 17.34 — 14.16 — 8.95 — 7.12 ns
OR3C/T80 — 18.14 — 14.79 — 9.34 — 7.48 ns
OR3T125 — — — 15.68 — 9.91 — 8.02 ns
Clock Input Pin (mid-PIC) →OUTPUT Pin OR3T20 — — — 14.69 — 13.26 — 11.37 ns
(Sinklim) OR3T30 — — — 14.97 — 13.45 — 11.54 ns
OR3T55 — 18.70 — 15.51 — 13.80 — 11.86 ns
OR3C/T80 — 19.51 — 16.14 — 14.18 — 12.22 ns
OR3T125 — — — 17.03 — 14.76 — 12.76 ns
Additional Delay if Non-mid-PIC Used as Clock OR3T20 — — — 0.16 — 0.18 — 0.17 ns
Pin OR3T30 — — — 0.20 — 0.21 — 0.20 ns
OR3T55 — 0.41 — 0.36 — 0.37 — 0.35 ns
OR3C/T80 — 0.63 — 0.55 — 0.57 — 0.55 ns
OR3T125 — — — 1.11 — 1.05 — 1.02 ns
Output Not on Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs)
Additional Delay if Output Not on Same Side as OR3T20 — — — 0.16 — 0.18 — 0.17 ns
Input Clock Pin OR3T30 — — — 0.20 — 0.21 — 0.20 ns
OR3T55 — 0.41 — 0.36 — 0.37 — 0.35 ns
OR3C/T80 — 0.63 — 0.55 — 0.57 — 0.55 ns
OR3T125 — — — 1.11 — 1.05 — 1.02 ns
Note:
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the
PIO CLK input, the clock→Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not
used. The given timing requires that the input clock pin be located at one of the four center PICs on any side of the device and that a PIO FF be
used. For clock pins located at any other PIO, see the results reported by ORCA Foundry.
PIO FF
SCLK
5-4846(F)
Figure 78. System Clock to Output Delay

Data Sheet

Table 57. OR3C/Txxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin)
Speed
Description
(TJ = 85 °C, VDD = min)
Input to ECLK Setup Time (middle OR3T20 — — 1.34 — 0.88 — 0.83 — ns
ECLK pin) OR3T30 — — 1.30 — 0.86 — 0.82 — ns
OR3T55 1.36 — 1.22 — 0.83 — 0.80 — ns
OR3C/T80 1.25 — 1.14 — 0.80 — 0.77 — ns
OR3T125 — — 1.03 — 0.76 — 0.74 — ns
Input to ECLK Setup Time (middle OR3T20 — — 6.30 — 5.32 — 5.98 — ns
ECLK pin, delayed data input) OR3T30 — — 6.27 — 5.30 — 5.97 — ns
OR3T55 6.91 — 6.19 — 5.27 — 5.95 — ns
OR3C/T80 6.79 — 6.11 — 5.24 — 5.93 — ns
OR3T125 — — 6.00 — 5.20 — 5.90 — ns
Input to ECLK Setup Time (corner OR3T20 — — 0.00 — 0.00 — 0.00 — ns
ECLK pin) OR3T30 — — 0.00 — 0.00 — 0.00 — ns
OR3T55 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3C/T80 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3T125 — — 0.00 — 0.00 — 0.00 — ns
Input to ECLK Setup Time (corner OR3T20 — — 4.39 — 3.51 — 4.41 — ns
OR3T55 4.94 — 4.28 — 3.18 — 4.11 — ns
OR3C/T80 4.82 — 4.21 — 2.98 — 3.91 — ns
OR3T125 — — 4.10 — 2.63 — 3.61 — ns
Input to ECLK Hold Time (middle OR3T20 — — 0.00 — 0.00 — 0.00 — ns
ECLK pin) OR3T30 — — 0.00 — 0.00 — 0.00 — ns
OR3T55 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3C/T80 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3T125 — — 0.00 — 0.00 — 0.00 — ns
Input to ECLK Hold Time (middle OR3T20 — — 0.00 — 0.00 — 0.00 — ns
OR3T55 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3C/T80 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3T125 — — 0.00 — 0.00 — 0.00 — ns
Note:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
The ECLK delays are to all of the PIOs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay
includes both the input buffer delay and the clock routing to the PIO clock input.

Data Sheet

Table 57. OR3C/Txxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin) (continued)
Speed
Description
(TJ = 85 °C, VDD = min)
Input to ECLK Hold Time (corner OR3T20 — — 0.00 — 0.00 — 0.00 — ns
ECLK pin) OR3T30 — — 0.00 — 0.00 — 0.00 — ns
OR3T55 0.00 — 0.00 — 0.80 — 1.10 — ns
OR3C/T80 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3T125 — — 0.00 — 0.00 — 0.00 — ns
Input to ECLK Hold Time (corner OR3T20 — — 0.00 — 0.00 — 0.00 — ns
OR3T55 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3C/T80 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3T125 — — 0.00 — 0.00 — 0.00 — ns
Notes:
The ECLK delays are to all of the PIOs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay
includes both the input buffer delay and the clock routing to the PIO clock input.
PIO ECLK LATCH
INPUT D Q
CLKCNTRL
CLK
ECLK
5-4847(F).b
Figure 79. Input to ExpressCLK Setup/Hold Time

Data Sheet

Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin)
Speed
Description
(TJ = 85 °C, VDD = min)
Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs)
Input to FCLK Setup Time (middle OR3T20 — — 0.00 — 0.00 — 0.00 — ns
ECLK pin) OR3T30 — — 0.00 — 0.00 — 0.00 — ns
OR3T55 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3C/T80 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3T125 — — 0.00 — 0.00 — 0.00 — ns
Input to FCLK Setup Time (middle OR3T20 — — 0.80 — 0.58 — 2.20 — ns
OR3T55 0.29 — 0.62 — 0.51 — 2.11 — ns
OR3C/T80 0.14 — 0.50 — 0.46 — 2.06 — ns
OR3T125 — — 0.22 — 0.33 — 1.90 — ns
Input to FCLK Setup Time (corner OR3T20 — — 0.00 — 0.00 — 0.00 — ns
ECLK pin) OR3T30 — — 0.00 — 0.00 — 0.00 — ns
OR3T55 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3C/T80 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3T125 — — 0.00 — 0.00 — 0.00 — ns
Input to FCLK Setup Time (corner OR3T20 — — 0.00 — 0.00 — 0.00 — ns
OR3T55 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3C/T80 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3T125 — — 0.00 — 0.00 — 0.00 — ns
Input to FCLK Hold Time (middle OR3T20 — — 4.29 — 3.72 — 3.27 — ns
ECLK pin) OR3T30 — — 4.50 — 3.80 — 3.35 — ns
OR3T55 6.33 — 4.97 — 3.96 — 3.52 — ns
OR3C/T80 6.95 — 5.49 — 4.15 — 3.72 — ns
OR3T125 — — 6.36 — 4.47 — 4.05 — ns
Notes:

Data Sheet

Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin) (continued)
Speed
Description
(TJ = 85 °C, VDD = min)
Input to FCLK Hold Time (middle OR3T20 — — 0.00 — 0.00 — 0.00 — ns
OR3T55 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3C/T80 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3T125 — — 0.00 — 0.00 — 0.00 — ns
Input to FCLK Hold Time (corner OR3T20 — — 6.26 — 5.54 — 4.88 — ns
ECLK pin) OR3T30 — — 6.49 — 5.72 — 5.04 — ns
OR3T55 8.43 — 6.98 — 6.09 — 5.40 — ns
OR3C/T80 9.09 — 7.53 — 6.47 — 5.79 — ns
OR3T125 — — 8.45 — 7.10 — 6.40 — ns
Input to FCLK Hold Time (corner OR3T20 — — 0.00 — 0.00 — 0.00 — ns
OR3T55 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3C/T80 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3T125 — — 0.00 — 0.00 — 0.00 — ns
Notes:
PIO FF
INPUT D Q
CLKCNTRL
ECLK
FCLK
5-4847(F).a
Figure 80. Input to Fast Clock Setup/Hold Time

Data Sheet

Table 59. OR3C/Txxx Input to General System Clock (SCLK) Setup/Hold Time (Pin-to-Pin)
Speed
Description
(TJ = 85 °C, VDD = min)
Input to SCLK Setup Time OR3T20 — — 0.00 — 0.00 — 0.00 — ns
OR3T30 — — 0.00 — 0.00 — 0.00 — ns
OR3T55 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3C/T80 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3T125 — — 0.00 — 0.00 — 0.00 — ns
Input to SCLK Setup Time OR3T20 — — 1.33 — 1.47 — 3.09 — ns
(delayed data input) OR3T30 — — 1.22 — 1.40 — 3.03 — ns
OR3T55 0.99 — 1.09 — 1.33 — 2.97 — ns
OR3C/T80 0.79 — 0.93 — 1.26 — 2.91 — ns
OR3T125 — — 0.78 — 1.19 — 2.86 — ns
Input to SCLK Hold Time OR3T20 — — 4.74 — 3.64 — 3.04 — ns
OR3T30 — — 5.01 — 3.83 — 3.22 — ns
OR3T55 6.82 — 5.56 — 4.18 — 3.54 — ns
OR3C/T80 7.62 — 6.19 — 4.56 — 3.89 — ns
OR3T125 — — 7.07 — 5.14 — 4.44 — ns
Input to SCLK Hold Time OR3T20 — — 0.00 — 0.00 — 0.00 — ns
(delayed data input) OR3T30 — — 0.00 — 0.00 — 0.00 — ns
OR3T55 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3C/T80 0.00 — 0.00 — 0.00 — 0.00 — ns
OR3T125 — — 0.00 — 0.00 — 0.00 — ns
Additional Hold Time if Non- OR3T20 — — 0.16 — 0.18 — 0.17 — ns
mid-PIC Used as SCLK Pin OR3T30 — — 0.20 — 0.21 — 0.20 — ns
(no delay on data input) OR3T55 0.41 — 0.36 — 0.37 — 0.35 — ns
OR3C/T80 0.63 — 0.55 — 0.57 — 0.55 — ns
OR3T125 — — 1.11 — 1.05 — 1.02 — ns
Notes:
This clock delay is for a fully routed clock tree that uses the clock network. It includes both the input buffer delay and the clock routing to the PIO
FF CLK input. The delay will be reduced if any of the clock branches are not used. The given setup (delayed and no delay) and hold (delayed)
timing allows the input clock pin to be located in any PIO on any side of the device, but a PIO FF must be used. The hold (no delay) timing
assumes the clock pin is located at one of the four middle PICs on any side of the device and that a PIO FF is used. If the clock pin is located
elsewhere, then the last parameter in the table must be added to the hold (no delay) timing.
PIO FF
INPUT D Q
SCLK
5-4847(F)
Figure 81. Input to System Clock Setup/Hold Time

Data Sheet

Configuration Timing
Table 60. General Configuration Mode Timing Characteristics

All Configuration Modes
M[3:0] Setup Time to INIT High TSMODE 0.00 — ns
M[3:0] Hold Time from INIT High THMODE 600.00 — ns
RESET Pulse Width Low to Start Reconfiguration TRW 50.00 — ns
PRGM Pulse Width Low to Start Reconfiguration TPGW 50.00 — ns
Master and Asynchronous Peripheral Modes
Power-on Reset Delay TPO 15.70 52.40 ms
CCLK Period (M3 = 0) TCCLK 60.00 200.00 ns
(M3 = 1) 480.00 1600.00 ns
Configuration Latency (autoincrement mode): TCL
OR3T20 (M3 = 0) 11.50 38.40* ms
(M3 = 1) 92.10 307.00* ms
OR3T30 (M3 = 0) 15.10 50.40* ms
(M3 = 1) 121.00 403.30* ms
OR3T55 (M3 = 0) 23.20 77.40* ms
(M3 = 1) 185.00 619.00* ms
OR3C/T80 (M3 = 0) 33.70 113.00* ms
(M3 = 1) 270.00 900.00* ms
OR3T125 (M3 = 0) 52.30 175.00* ms
(M3 = 1) 418.00 1395.00* ms
Microprocessor (MPI) Mode
OR3T20 27413 — write cycles
OR3C/T80 76317 — write cycles
Partial Reconfiguration (explicit mode): TPR
OR3C/T80 51 — write cycles
Slave Serial Mode
CCLK Period TCCLK
OR3Cxx 40 — ns
OR3Txxx 15 — ns
OR3T20 2.80 — ms
OR3T30 3.80 — ms
OR3T55 5.80 — ms
OR3C80 22.50 — ms
OR3T80 8.40 — ms
OR3T125 13.09 — ms
* Not applicable to asynchronous peripheral mode.

Data Sheet

Table 60. General Configuration Mode Timing Characteristics (continued)

Slave Parallel Mode
CCLK Period: TCCLK
OR3Cxx 40.00 — ns
OR3Txxx 15.00 — ns
Configuration Latency (normal mode): TCL
OR3T20 0.36 — ms
OR3T30 0.47 — ms
OR3T55 0.72 — ms
OR3C80 2.81 — ms
OR3T80 1.05 — ms
OR3T125 1.64 — ms
Partial Reconfiguration (explicit mode): TPR
OR3T20 0.48 — µs/frame
OR3C80 2.04 — µs/frame
INIT Timing
INIT High to CCLK Delay: TINIT_CCLK
Slave Parallel 1.00 — µs
Slave Serial 1.00 — µs
Master Serial:
(M3 = 1) 1.00 3.40 µs
(M3 = 0) 0.50 2.00 µs
Master Parallel:
(M3 = 1) 4.80 16.20 µs
(M3 = 0) 1.00 3.60 µs
Initialization Latency (PRGM high to INIT high): TIL
OR3T20 0.21 0.68 ms
OR3T30 0.24 0.79 ms
OR3T55 0.30 1.00 ms
OR3C/T80 0.36 1.20 ms
OR3T125 0.45 1.50 ms
INIT High to WR, Asynchronous Peripheral TINIT_WR 2.00 — µs
Note: TPO is triggered when VDD reaches between 3.0 V to 4.0 V for the OR3Cxx and between 2.7 V and 3.0 V for the OR3Txxx.

Data Sheet
VDD
TPO + T IL
PRGM
TIL TPGW
INIT
TINIT_CLK
TCCLK
CCLK
THMODE
TSMODE
M[3:0]
TCL
DONE
5-4531(F)
Figure 82. General Configuration Mode Timing Diagram

Data Sheet

Table 61. Master Serial Configuration Mode Timing Characteristics

DIN Setup Time* TS 60.00 — ns
DIN Hold Time TH 0.00 — ns
CCLK Frequency (M3 = 0) FC 5.00 16.67 MHz
CCLK Frequency (M3 = 1) FC 0.63 2.08 MHz
CCLK to DOUT Delay TD — 5.00 ns
* Data gets clocked out from an external serial ROM. The clock to data delay of the serial ROM must be less than the CCLK frequency since the
data available out of the serial ROM must be setup and waiting to be clocked into the FPGA before the next CCLK rising edge.
Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN.
CCLK
TS TH
DIN BIT N
TD
DOUT BIT N
5-4532(F)
Figure 83. Master Serial Configuration Mode Timing Diagram

Data Sheet

Table 62. Master Parallel Configuration Mode Timing Characteristics

RCLK to Address Valid TAV — 60.00 ns
D[7:0] Setup Time to RCLK High TS 60.00 — ns
D[7:0] Hold Time to RCLK High TH 0.00 — ns
RCLK Low Time (M3 = 0) TCL 7.00 7.00 CCLK cycles
RCLK High Time (M3 = 0) TCH 1.00 1.00 CCLK cycles
RCLK Low Time (M3 = 1) TCL 7.00 7.00 CCLK cycles
RCLK High Time (M3 = 1) TCH 1.00 1.00 CCLK cycles
CCLK to DOUT TD — 5.00 ns
Notes:
The RCLK period consists of seven CCLKs for RCLK low and one CCLK for RCLK high.
Serial data is transmitted out on DOUT 1.5 CCLK cycles after the byte is input on D[7:0].
A[17:0]
TAV TCH TCL
RCLK
TS TH
D[7:0] BYTE N BYTE N + 1
CCLK
DOUT D0 D1 D2 D3 D4 D5 D6 D7
TD
5-6764(F)
Figure 84. Master Parallel Configuration Mode Timing Diagram

Data Sheet

Table 63. Asynchronous Peripheral Configuration Mode Timing Characteristics

WR, CS0, and CS1 Pulse Width TWR 50.00 — ns
D[7:0] Setup Time: TS
3Cxx 20.00 — ns
3Txxx 10.50 — ns
D[7:0] Hold Time TH 0.00 — ns
RDY Delay TRDY — 40.00 ns
RDY Low TB 1.00 8.00 CCLK Periods
Earliest WR After RDY Goes High* TWR2 0.00 — ns
RD to D7 Enable/Disable TDEN — 40.00 ns
* This parameter is valid whether the end of not RDY is determined from the RDY pin or from the D7 pin.
Notes:
Serial data is transmitted out on DOUT on the falling edge of CCLK after the byte is input on D[7:0].
D[6:0] timing is the same as the write data portion of the D7 waveform because D[6:0] are not enabled by RD.
CS0
CS1
TWR
WR
TS TH TWR2
D7 WRITE DATA
TDEN TDEN
RD
RDY
TB
TRDY
CCLK
TD
DOUT PREVIOUS BYTE D7 D0 D1 D2 D3
5-4533(F)
Figure 85. Asynchronous Peripheral Configuration Mode Timing Diagram

Data Sheet

Table 64. Slave Serial Configuration Mode Timing Characteristics

DIN Setup Time: TS
3Cxx 20.00 — ns
3Txxx 10.50 — ns
DIN Hold Time TH 0.00 — ns
CCLK High Time: TCH
3Cxx 20.00 — ns
3Txxx 7.00 — ns
CCLK Low Time: TCL
3Cxx 20.00 — ns
3Txxx 7.00 — ns
CCLK Frequency: FC
3Cxx — 25.00 MHz
3Txxx — 66.00 MHz
Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN.
DIN BIT N
TS TH
CCLK
TD TCL TCH
DOUT BIT N
5-4535(F).
Figure 86. Slave Serial Configuration Mode Timing Diagram

Data Sheet

Table 65. Slave Parallel Configuration Mode Timing Characteristics

CS0, CS1, WR Setup Time TS1 40.00 — ns
CS0, CS1, WR Hold Time TH1 20.00 — ns
D[7:0] Setup Time: TS2
3Cxx 20.00 — ns
3Txxx 7.00 — ns
D[7:0] Hold Time TH2 0.00 — ns
CCLK High Time: TCH
3Cxx 20.00 — ns
3Txxx 7.00 — ns
CCLK Low Time: TCL
3Cxx 20.00 — ns
3Txxx 7.00 — ns
CCLK Frequency: FC
3Cxx — 25.00 MHz
3Txxx — 66.00 MHz
Note: Daisy-chaining of FPGAs is not supported in this mode.
CS0
CS1
WR
TS1 TH1
TCL TCH
CCLK
TS2 TH2
D[7:0]
5-2848(F)
Figure 87. Slave Parallel Configuration Mode Timing Diagram

Data Sheet

Microprocessor Interface (MPI) Configuration Timing Characteristics
For configuration timing using the MPI, consult Table 49. See Figures 67 through 74 for MPI timing diagrams.

Data Sheet
Readback Timing
Table 66. Readback Timing Characteristics

RD_CFG to CCLK Setup Time TS 50.00 — ns
RD_CFG High Width to Abort Readback TRBA 2 — CCLK cycles
CCLK Low Time TCL 40.00 — ns
CCLK High Time TCH 40.00 — ns
CCLK Frequency FC — 12.50 MHz
CCLK to RD_DATA Delay TD — 40.00 ns
TRBA
RD_CFG
TCL
TS
CCLK
TCH
TD
RD_DATA BIT 0 BIT 1 BIT 0
5-4536(F)
Figure 88. Readback Timing Diagram

Data Sheet
Input/Output Buffer Measurement Conditions
VCC GND
TO THE OUTPUT UNDER TEST 1 kΩ
50 pF TO THE OUTPUT UNDER TEST
50 pF
A. Load Used to Measure Propagation Delay B. Load Used to Measure Rising/Falling Edges
Note: Switch to VDD for TPLZ/TPZL; switch to GND for TPHZ/TPZH.
5-3234(F)
Figure 89. ac Test Loads
ts[i]
out[i] PAD ac TEST LOADS (SHOWN ABOVE)

OUT
VDD
out[i] VDD/2
VSS
PAD 1.5 V
OUT 0.0 V
TPLL
TPHH
5-3233.a(F)
Figure 90. Output Buffer Delays
PAD in[i]
IN
3.0 V
PAD IN 1.5 V
0.0 V
VDD
in[i] VDD/2
VSS
TPLL
TPHH
5-3235(F)
Figure 91. Input Buffer Delays

Data Sheet
Output Buffer Characteristics

OR3Cxx
70 50
IOL IOL
60
OUTPUT CURRENT, IO (mA) 40
OUTPUT CURRENT, IO (mA)

50
30
40
30
20
IOH
20
IOH
10
10
0 0
0 1 2 3 4 5 0 1 2 3 4 5
OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE, VO (V)

5-4634(F) 5-4635(C)
Figure 92. Sinklim (TJ = 25 °C, VDD = 5.0 V) Figure 95. Sinklim (TJ = 125 °C, VDD = 4.5 V)
250 150
225 IOL
IOL
125
200

175
100
150
125 75
100
IOH 50
75 IOH
50
25
25
0 0
0 1 2 3 4 5 0 1 2 3 4

5-4636(F) 5-4637(F)
Figure 93. Slewlim (TJ = 25 °C, VDD = 5.0 V) Figure 96. Slewlim (TJ = 125 °C, VDD = 4.5 V)
250 175
225
IOL 150
200
IOL
175 125
150
100
125
100 75
IOH
75
50
50 IOH
25
25
0
0
0 1 2 3 4 5 0 1 2 3 4
5-4638(F)
5-4639(F)
Figure 94. Fast (TJ = 25 °C, VDD = 5.0 V) Figure 97. Fast (TJ = 125 °C, VDD = 4.5 V)
Data Sheet
Output Buffer Characteristics (continued)

OR3Txxx
110 90
100 80
IOL
IOL
90
70

80
60
70
60 50
IOH
50 40
IOH
40
30
30
20
20
10
10
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0

5-6865(F) 5-6866(F)
Figure 98. Sinklim (TJ = 25 °C, VDD = 3.3 V) Figure 101. Sinklim (TJ = 125 °C, VDD = 3.0 V)
140 120
IOL IOL
120
100

100
80
80
60
60
IOH IOH
40
40
20 20
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0

5-6967(F) 5-6868(F)
Figure 99. Slewlim (TJ = 25 °C, VDD = 3.3 V) Figure 102. Slewlim (TJ = 125 °C, VDD = 3.0 V)
140 120
IOL IOL
120
100
100
80
80
60
60
IOH IOH
40
40
20 20
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0

5-6867(F) 5-6868(F)
Figure 100. Fast (TJ = 25 °C, VDD = 3.3 V) Figure 103. Fast (TJ = 125 °C, VDD = 3.0 V)
Data Sheet
Estimating Power Dissipation The power dissipated by an input buffer is estimated

as:
OR3Cxx PCMOS = 0.17 mW/MHz
The total operating power dissipated is estimated by The ac power dissipation from an output or bidirec-
summing the standby (IDDSB), internal, and external tional is estimated by the following:
power dissipated. The internal and external power is POUT = (CL + 8.8 pF) x VDD2 x F Watts
the power consumed in the PLCs and PICs, respec-
tively. In general, the standby power is small and may where the unit for CL is farads, and the unit for F is Hz.
be neglected. The total operating power is as follows: As an example of estimating power dissipation, sup-
PT = Σ PPLC + Σ PPIC pose that a fully utilized OR3C80 has an average of six
outputs for each of the 484 PFUs, that 10 clock
The internal operating power is made up of two parts: brances are used so that the clock is driven to the
clock generation and PFU output power. The PFU out- entire PLC array, that 150 of the 484 PFUs have FFs
put power can be estimated based upon the number of clocked at 40 MHz, and that the PFUoutputs have an
PFU outputs switching when driving an average fan-out average activity factor of 20%.
of two:
Twenty TTL-configured inputs, 20 CMOS-configured
PPFU = 0.136 mW/MHz inputs, 32 outputs driving 30 pF loads, and 16 biderec-
For each PFU output that switches, 0.136 mW/MHz tional I/Os driving 50 pF loads are also generated from
needs to be multiplied times the frequency (in MHz) the 40 MHz clock with an average activity factor of
that the output switches. Generally, this can be esti- 20%. All of the ouptut PIOs are registered, and 30 of
mated by using one-half the clock rate, multiplied by the input PIOs are registered. The worst-case (VDD =
some activity factor; for example, 20%. 5.25 V) power dissipation is estimated as follows:
The power dissipated by the clock generation circuitry PPFU = 484 x 6 (0.136 mW/MHz x 20 MHz x 20%)
is based upon four parts: the fixed clock power, the = 1579.78 mW
power/clock branch row or column, the clock power dis- PCLK = [40 X [0.224 mW/MHz + (0.288 mW/MHz/Branch)
sipated in each PFU that uses this particular clock, and (10 Branches)
the power from the subset of those PFUs that are con- + (0.033 mW/MHz/PFU) (150 PFUs)
figured as synchronous memory. Therefore, the clock + (0.008 mW/MHz/PIO) (58 PIOs)]
power can be calculated for the four parts using the fol- = 340.72 mW
lowing equations: PTTL = 20 x [2.2 mW + (0.17 mW/MHz x 20 MHz x 20%)]
= 57.6 mW
OR3C80 Clock Power PCMOS = 20 x [0.17 mW x 20 MHz x 20%]
P = [0.224 mW/MHz = 13.6 mW
+ (0.288 mW/MHz/Branch) (# Branches) POUT = 32 x [(30 pF + 8.8 pF) x (5.25)2 x 20 MHz x 20%]
+ (0.033 mW/MHz/PFU) (# PFUs) = 136.89 mW
+ (0.008 mW/MHz/PIO (# PIOs)] PBID = 16 x [(50 pF + 8.8 pF) x (5.25)2 x 20 MHz x 20%]
For a quick estimate, the worst-case (typical circuit) = 103.72 mW
OR3C80 clock power ≈ 21.06 mW/MHz. Total = 2.23 W
The power dissipated in a PIC is the sum of the power

dissipated in the four PIOs in the PIC. This consists of
power dissipated by inputs and ac power dissipated by
outputs. The power dissipated in each PIO depends on
whether it is configured as an input, output, or input/
output. If a PIO is operating as an output, then there is
a power dissipation component for PIN, as well as
POUT. This is because the output feeds back to the
input.
The power dissipated by a TTL input buffer is estimated
as:
PTTL = 2.2 mW + 0.17 mW/MHz

Data Sheet
Estimating Power Dissipation (continued) OR3T55 Clock Power

P = [0.88 mW/MHz
OR3Txxx (Preliminary Information) + (0.102 mW/MHz/Branch) (# Branches)
+ (0.015 mW/MHz/PFU) (# PFUs)
The total operating power dissipated is estimated by + (0.004 mW/MHz/PIO (# PIOs)]
summing the standby (IDDSB), internal, and external
power dissipated. The internal and external power is For a quick estimate, the worst-case (typical circuit)
the power consumed in the PLCs and PICs, respec- OR3T55 clock power ≈ 6.58 mW/MHz.
tively. In general, the standby power is small and may OR3T80 Clock Power
be neglected. The total operating power is as follows:
P = [0.107 mW/MHz
PT = Σ PPLC + Σ PPIC + (0.124 mW/MHz/Branch) (# Branches)
The internal operating power is made up of two parts: + (0.015 mW/MHz/PFU) (# PFUs)
clock generation and PFU output power. The PFU out- + (0.004 mW/MHz/PIO (# PIOs)]
put power can be estimated based upon the number of For a quick estimate, the worst-case (typical circuit)
PFU outputs switching when driving an average fan-out OR3T80 clock power ≈ 9.47 mW/MHz.
of two:
PPFU = 0.068 mW/MHz OR3T125 Clock Power
For each PFU output that switches, 0.068 mW/MHz P = [0.167 mW/MHz
needs to be multiplied times the frequency (in MHz) + (0.193 mW/MHz/Branch) (# Branches)
that the output switches. Generally, this can be esti- + (0.015 mW/MHz/PFU) (# PFUs)
mated by using one-half the clock rate, multiplied by + (0.004 mW/MHz/PIO (# PIOs)]
some activity factor; for example, 20%. For a quick estimate, the worst-case (typical circuit)
The power dissipated by the clock generation circuitry OR3T125 clock power ≈ 15.44 mW/MHz.
is based upon four parts: the fixed clock power, the The power dissipated in a PIC is the sum of the power
power/clock branch row or column, the clock power dis- dissipated in the four PIOs in the PIC. This consists of
sipated in each PFU that uses this particular clock, and power dissipated by inputs and ac power dissipated by
the power from the subset of those PFUs configured as outputs. The power dissipated in each PIO depends on
synchronous memory. Therefore, the clock power can whether it is configured as an input, output, or input/
be calculated for the four parts using the following output. If a PIO is operating as an output, then there is
equations. a power dissipation component for PIN, as well as
POUT. This is because the output feeds back to the
OR3T20 Clock Power input.
P = [0.38 mW/MHz The power dissipated by an input buffer (VIH = VDD –
+ (0.045 mW/MHz/Branch) (# Branches) 0.3 V or higher) is estimated as:
+ (0.004 mW/MHz/PIO (# PIOs)] PIN = 0.09 mW/MHz
For a quick estimate, the worst-case (typical circuit) The ac power dissipation from an output or bidirec-
OR3T20 clock power ≈ 2.92 mW/MHz. tional is estimated by the following:
OR3T30 Clock Power POUT = (CL + 8.8 pF) x VDD2 x F Watts
P = [0.53 mW/MHz where the unit for CL is farads, and the unit for F is Hz.
+ (0.061 mW/MHz/Branch) (# Branches)
+ (0.004 mW/MHz/PIO (# PIOs)]
For a quick estimate, the worst-case (typical circuit)
OR3T30 clock power ≈ 3.98 mW/MHz.

Data Sheet
Estimating Power Dissipation (continued)

As an example of estimating power dissipation, suppose that a fully utilized OR3T80 has an average of
six outputs for each of the 484 PFUs, that 12 clock branches are used so that the clock is driven to the entire PLC
array, that 250 of the 484 PFUs have FFs clocked at 40 MHz, and that the PFU outputs have an average activity
factor of 20%.
Eighty inputs, 40 of them used as 5 V tolerant inputs, 50 outputs driving 30 pF loads, and 30 bidirectional
I/Os driving 50 pF loads are also generated from the
40 MHz clock with an average activity factor of 20%. All of the output PIOs are registered, and 30 of the input PIOs
are registered.
The worst-case (VDD = 3.6 V) power dissipation is estimated as follows:
PPFU = 484 x 6 (0.068 mW/MHz x 20 MHz x 20%)
= 789.9 mW
PCLK = [0.107 mW/MHz + (0.09 mW/MHz – Branch)
(12 Branches)
+ (0.015 mW/MHz – PFU) (250 PFUs)
+ (0.004 mW/MHz/PIO) (110 PIOs)]
= 230.43 mW
PIN = 80 x [0.09 mW/MHz x 20 MHz x 20%]
= 28.8 mW
POUT = 50 x [(30 pF + 8.8 pF) x (3.6)2 x 20 MHz x 20%]
= 100.57 mW
PBID = 30 x [(50 pF + 8.8 pF) x (3.6)2 x 20 MHz x 20%]
= 91.45 mW
TOTAL = 1.241 W

Data Sheet
Pin Information
Pin Descriptions
This section describes the pins found on the Series 3 FPGAs. Any pin not described in this table is a user-program-
mable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.
If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled
after configuration.
Table 67. Pin Descriptions
Symbol I/O Description

Dedicated Pins
VDD — Positive power supply.
GND — Ground supply.
VDD5 — 5 V tolerant select. VDD5 pin locations are shown for package compatibility with
OR2TxxA devices. Connections to 5 V power sources are not used for 5 V tolerant
I/Os in the OR3Txxx devices.
RESET I During configuration, RESET forces the restart of configuration and a pull-up is
enabled. After configuration, RESET can be used as a general FPGA input or as a
direct input, which causes all PLC latches/FFs to be asynchronously set/reset.
CCLK I In the master and asynchronous peripheral modes, CCLK is an output which
strobes configuration data in. In the slave or synchronous peripheral mode, CCLK
is input synchronous with the data on DIN or D[7:0]. In microprocessor mode, CCLK
is used internally and output for daisy-chain operation.
DONE I As an input, a low level on DONE delays FPGA start-up after configuration (see
Note).
O As an active-high, open-drain output, a high level on this signal indicates that config-
uration is complete. DONE has an optional pull-up resistor.
PRGM I PRGM is an active-low input that forces the restart of configuration and resets the
boundary-scan circuitry. This pin always has an active pull-up.
RD_CFG I This pin must be held high during device initialization until the INIT pin goes high.
This pin always has an active pull-up.
During configuration, RD_CFG is an active-low input that activates the TS_ALL func-
tion and 3-states all of the I/O.
After configuration, RD_CFG can be selected (via a bit stream option) to activate the
TS_ALL function as described above, or, if readback is enabled via a bit stream
option, a high-to-low transition on RD_CFG will initiate readback of the configuration
data, including PFU output states, starting with frame address 0.
RD_DATA/TDO O RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides con-
figuration data out. If used in boundary scan, TDO is test data out.
Special-Purpose Pins
M0, M1, M2 I During powerup and initialization, M0—M2 are used to select the configuration
mode with their values latched on the rising edge of INIT; see Table 34 for the config-
uration modes. During configuration, a pull-up is enabled.
I/O After configuration, these pins are user-programmable I/O (see Note).
Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the
activation of all user I/Os) is controlled by a second set of options.

Data Sheet
Pin Information (continued)

Table 67. Pin Descriptions (continued)

Special-Purpose Pins (continued)
M3 I During powerup and initialization, M3 is used to select the speed of the internal oscillator dur-
ing configuration with their values latched on the rising edge of INIT. When M3 is low, the oscil-
lator frequency is 10 MHz. When M3 is high, the oscillator is 1.25 MHz. During configuration,
a pull-up is enabled.
I/O After configuration, this pin is a user-programmable I/O pin (see Note).
TDI, TCK, I If boundary scan is used, these pins are test data in, test clock, and test mode select inputs. If
TMS boundary scan is not selected, all boundary-scan functions are inhibited once configuration is
complete. Even if boundary scan is not used, either TCK or TMS must be held at logic 1 dur-
ing configuration. Each pin has a pull-up enabled during configuration.
I/O After configuration, these pins are user-programmable I/O (see Note).
RDY/RCLK/ O During configuration in peripheral mode, RDY/RCLK indicates another byte can be written to
MPI_ALE the FPGA. If a read operation is done when the device is selected, the same status is also
available on D7 in asynchronous peripheral mode.
O During the master parallel configuration mode, RCLK is a read output signal to an external
memory. This output is not normally used.
I In i960 microprocessor mode, this pin acts as the address latch enable (ALE) input.
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
HDC O High During Configuration is output high until configuration is complete. It is used as a control
output, indicating that configuration is not complete.
LDC O Low During Configuration is output low until configuration is complete. It is used as a control out-
put, indicating that configuration is not complete.
INIT I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is
enabled, but an external pull-up resistor is recommended. As an active-low open-drain out-
put, INIT is held low during power stabilization and internal clearing of memory. As an active-
low input, INIT holds the FPGA in the wait-state before the start of configuration.

Data Sheet


CS0, CS1 I CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor
configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During config-
uration, a pull-up is enabled.
I/O After configuration, these pins are user-programmable I/O pins (see Note).
RD/ I RD is used in the asynchronous peripheral configuration mode. A low on RD changes D7 into
MPI_STRB a status output. As a status indication, a high indicates ready, and a low indicates busy. WR
and RD should not be used simultaneously. If they are, the write strobe overrides.
I This pin is also used as the microprocessor interface (MPI) data transfer strobe. For
PowerPC, it is the transfer start (TS). For i960, it is the address/data strobe (ADS).
WR I WR is used in the asynchronous peripheral configuration mode. When the FPGA is selected,
a low on the write strobe, WR, loads the data on D[7:0] inputs into an internal data buffer. WR
and RD should not be used simultaneously. If they are, the write strobe overrides.
A[17:0] O During master parallel configuration mode, A[17:0] address the configuration EPROM. In
microprocessor interface (MPI) mode, many of the A[n] pins have alternate uses as described
below. See the Special Function Blocks section for more MPI information. During configura-
tion, if not in master parallel or an MPI configuration mode, these pins are 3-stated with a pull-
up enabled.
I/O After configuration, the pins are user-programmable I/O pins (see Note).

Data Sheet


A11/MPI_IRQ O MPI active-low interrupt request output.
A10/MPI_BI O PowerPC mode MPI burst inhibit output.
A9/MPI_ACK O In PowerPC mode MPI operation, this is the active-high transfer acknowledge (TA) output. For
i960 MPI operation, it is the active-low ready/record (RDYRCV) output.
A8/MPI_RW I In PowerPC mode MPI operation, this is the active-low write/active-high read control signals.
For i960 operation, it is the active-high write/active-low read control signal.
A7/MPI_CLK I This is the clock used for the synchronous MPI interface. For PowerPC, it is the CLKOUT
signal. For i960, it is the system clock that is chosen for the i960 external bus interface.
A[4:0] I For PowerPC operation, these are the PowerPC address inputs. The address bit mapping (in
PowerPC/FPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/A[3], A[27]/A[4]. Note
that A[27]/A[4] is the MSB of the address. The A[4:2] inputs are not used in i960 MPI mode.
A[1:0]/ I For i960 operation, MPI_BE[1:0] provide the i960 byte enable signals, BE[1:0], that are used as
MPI_BE[1:0] address bits A[1:0] in i960 byte-wide operation.
D[7:0] I During master parallel, peripheral, and slave parallel configuration modes, D[7:0] receive con-
figuration data, and each pin has a pull-up enabled. During serial configuration modes, D0 is
the DIN input. D[7:0] are also the data pins for PowerPC microprocessor mode and the
address/data pins for i960 microprocessor mode.
I/O After configuration, the pins are user-programmable I/O pins (see Note).
DIN I During slave serial or master serial configuration modes, DIN accepts serial configuration
data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. Dur-
ing configuration, a pull-up is enabled.
DOUT O During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained
slave LCA devices. Data out on DOUT changes on the falling edge of CCLK.
I/O After configuration, DOUT is a user-programmable I/O pin (see Note).

Data Sheet
Package Compatibility
Table 68 provides the number of user I/Os available for the ORCA Series 3 FPGAs for each available package.
Each package has six dedicated configuration pins.
Tables 70—75 provide the package pin and pin function for the ORCA Series 3 FPGAs and packages. The bond
pad name is identified in the PIC nomenclature used in the ORCA Foundry design editor.
When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the
number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).
When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device pad col-
umn for the FPGA. The tables provide no information on unused pads.
Table 68. ORCA I/Os Summary

208-Pin 240-Pin 256-Pin 352-Pin 432-Pin 600-Pin
Device
SQFP/SQPF2 SQFP/SQFP2 PBGA PBGA EBGA EBGA
OR3T20
User I/Os* 171 192 192 192 — —
VDD/VSS 31 40 26 48 — —
Configuration 6 6 6 6 — —
Unused 0 2 32 106 — —
OR3T30
User I/Os* 171 192 221 224 — —
VDD/VSS 31 40 26 48 — —
Unused 0 2 3 74 — —
OR3T55
User I/Os* 171 192 223 288 — —
VDD/VSS 31 42 26 48 — —
Unused 0 0 1 10 — —
OR3C/T80
User I/Os* 171 192 — 298 342 —
VDD/VSS 31 42 — 48 84 —
Configuration 6 6 — 6 6 —
Unused 0 0 — 0 0 —
OR3T125
User I/Os* 171 192 — 298 342 448
VDD/VSS 31 42 — 48 84 140
Configuration 6 6 — 6 6 6
Unused 0 0 — 0 0 6
*User I/O count includes four ExpressCLK inputs.

Data Sheet
Compatibility with OR2C/TxxA Series

The pinouts shown for the OR3Cxx and OR3Txxx devices are consistent with the OR2C/TxxA Series for all devices
offered in the same packages. This includes the following pins: VDD, VSS, VDD5 (OR2TxxA Series only), and all con-
figuration pins.
The following restrictions apply:
1. There are two configuration modes supported in the OR2C/TxxA Series that are not supported in Series 3: mas-
ter parallel down and synchronous peripheral modes. The Series 3 FPGAs have two new microprocessor inter-
face (MPI) configuration modes that are unavailable in the OR2C/TxxA Series.
2. There are four pins—one per each device side—that are user I/O in the OR2C/TxxA Series which can only be
used as fast dedicated clocks or global inputs in Series 3. These pins are also used to drive the ExpressCLK to
the I/O FFs on their given side of the device. These four middle ExpressCLK pins should not be used to connect
to a programmable clock manager (PCM). A corner ExpressCLK input should be used instead (see item 3
below). See Table 69 for a list of these pins in each package.
3. There are two other pins that are user I/O in both the OR2C/TxxA and Series 3 but also have optional added
functionality. Each of these pins drives the ExpressCLKs on two sides of the device. They also have fast connec-
tivity to the programmable clock manager (PCM). See Table 69 for a list of these pins in each package.
Table 69. Series 3 ExpressCLK Pins
Pin Name/ 208-Pin 240-Pin 256-Pin 352-Pin 432-Pin 600-Pin

Package SQFP/SQFP2 SQFP/SQFP2 PBGA PBGA EBGA EBGA
I-ECKL 22 26 K3 N2 R29 U33
I-ECKB 80 91 W11 AE14 AH16 AM18
I-ECKR 131 152 K18 N23 T2 V2
I-ECKT 178 207 B11 B14 C15 C17
I/O-SECKLL 49 56 W1 AB4 AG29 AK34
I/O-SECKUR 159 184 A19 A25 D5 D5

Data Sheet

Table 70. OR3T20, OR3T30, OR3T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout
OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125

Pin Pad Pad Pad Pad Pad Function
1 VSS VSS VSS VSS VSS VSS
3 PL1D PL1D PL1D PL1D PL1D I/O
4 PL1A PL2D PL2D PL2D PL2D I/O-A0/MPI_BE0
6 PL2C PL5D PL3A PL4A PL5D I/O
7 PL2A PL7D PL4A PL5A PL7D I/O-A1/MPI_BE1
8 PL3D PL8A PL5A PL6A PL8A I/O-A2
9 PL3C PL9D PL6D PL7D PL9D I/O
10 PL3B PL9B PL6B PL7B PL9B I/O
11 PL3A PL9A PL6A PL7A PL9A I/O-A3
12 VDD VDD VDD VDD VDD VDD
14 PL4C PL10A PL7C PL8A PL10A I/O
15 PL4B PL11D PL7B PL9D PL11D I/O
16 PL4A PL11A PL7A PL9B PL11A I/O-A4
17 PL5D PL12D PL8D PL9A PL12D I/O-A5
18 PL5C PL12A PL8C PL10C PL12A I/O
19 PL5B PL13D PL8B PL10B PL13D I/O
22 PECKL PECKL PECKL PECKL PECKL I-ECKL
23 PL6C PL14C PL9C PL11C PL14C I/O
25 PL6A PL14A PL9A PL11A PL14A I/O-A7/MPI_CLK
30 PL7A PL15A PL10A PL12A PL15A I/O-A8/MPI_RW
32 PL8D PL16D PL11D PL13D PL16D I/O-A9/MPI_ACK
33 PL8C PL16A PL11C PL13B PL16A I/O
34 PL8B PL17D PL11B PL13A PL17D I/O
35 PL8A PL17A PL11A PL14C PL17A I/O-A10/MPI_BI
36 PL9D PL18D PL12D PL14B PL18D I/O
37 PL9C PL18A PL12C PL15C PL18A I/O
38 PL9B PL19D PL12B PL15B PL19D I/O
39 PL9A PL19A PL12A PL15A PL19A I/O-A11/MPI_IRQ

Data Sheet

Table 70. OR3T20, OR3T30, OR3T55, OR3C/T80, and OR3T125, 208-Pin SQFP/SQFP2 Pinout (continued)

41 PL10D PL20D PL13D PL16D PL20D I/O-A12
42 PL10C PL20B PL13B PL16B PL20B I/O
43 PL10B PL21D PL14D PL17D PL21D I/O
44 PL10A PL21B PL14B PL17B PL21B I/O-A13
46 PL11A PL24A PL16D PL19D PL24A I/O-A14
48 PL12C PL27D PL17A PL21D PL27D I/O
49 PL12B PL27A PL18C PL21A PL27A I/O-SECKLL
52 PCCLK PCCLK PCCLK PCCLK PCCLK CCLK
55 PB1A PB1A PB1A PB1A PB1A I/O-A16
56 PB1B PB2A PB1D PB2A PB2A I/O
57 PB1C PB2D PB2A PB2D PB2D I/O
58 PB1D PB3D PB2D PB3D PB3D I/O
59 PB2A PB4D PB3D PB4D PB4D I/O-A17
61 PB3A PB6D PB5B PB6B PB6D I/O
62 PB3B PB7D PB5D PB6D PB7D I/O
63 PB3C PB8D PB6B PB7B PB8D I/O
66 PB4A PB10A PB7A PB8A PB10A I/O
67 PB4B PB10D PB7B PB8D PB10D I/O
68 PB4C PB11A PB7C PB9A PB11A I/O
69 PB4D PB11D PB7D PB9C PB11D I/O
70 PB5A PB12A PB8A PB9D PB12A I/O
71 PB5B PB12D PB8B PB10A PB12D I/O
72 PB5C PB13A PB8C PB10B PB13A I/O
76 PB6B PB14B PB9B PB11B PB14B I/O
77 PB6C PB14C PB9C PB11C PB14C I/O

Data Sheet

Table 70. OR3T20, OR3T30, OR3T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout (continued)

80 PECKB PECKB PECKB PECKB PECKB I-ECKB
86 PB8B PB16D PB11B PB13B PB16D I/O
87 PB8C PB17A PB11C PB13C PB17A I/O
88 PB8D PB17D PB11D PB14A PB17D I/O
89 PB9A PB18A PB12A PB14B PB18A I/O-HDC
90 PB9B PB18D PB12B PB14D PB18D I/O
91 PB9C PB19A PB12C PB15A PB19A I/O
94 PB10A PB20A PB13A PB16A PB20A I/O-LDC
96 PB10C PB22A PB14A PB17A PB22A I/O
98 PB11A PB24A PB15A PB18A PB24A I/O-INIT
100 PB11D PB26A PB17A PB20A PB26A I/O
101 PB12A PB27D PB18A PB21D PB27D I/O
104 PDONE PDONE PDONE PDONE PDONE DONE
106 PRESETN PRESETN PRESETN PRESETN PRESETN RESET
107 PPRGMN PPRGMN PPRGMN PPRGMN PPRGMN PRGM
108 PR12A PR28A PR18A PR22A PR28A I/O-M0
109 PR12D PR27A PR18D PR21A PR27A I/O
110 PR11A PR26A PR17B PR20A PR26A I/O
111 PR11B PR25A PR16A PR19A PR25A I/O
112 PR10A PR22D PR15D PR18D PR22D I/O-M1
113 PR10B PR21A PR14A PR17A PR21A I/O
114 PR10C PR21D PR14D PR17D PR21D I/O
115 PR10D PR20A PR13A PR16A PR20A I/O

Data Sheet


118 PR9B PR19D PR12B PR15D PR19D I/O
119 PR9C PR18A PR12C PR14A PR18A I/O
120 PR9D PR18D PR12D PR14C PR18D I/O
121 PR8A PR17A PR11A PR14D PR17A I/O-M3
122 PR8B PR17D PR11B PR13A PR17D I/O
123 PR8C PR16A PR11C PR13B PR16A I/O
124 PR8D PR16D PR11D PR13D PR16D I/O
126 PR7A PR15A PR10A PR12A PR15A I/O
127 PR7B PR15B PR10B PR12B PR15B I/O
128 PR7C PR15C PR10C PR12C PR15C I/O
131 PECKR PECKR PECKR PECKR PECKR I-ECKR
137 PR5B PR13D PR8B PR10C PR13D I/O
138 PR5C PR12A PR8C PR10D PR12A I/O
139 PR5D PR12D PR8D PR9B PR12D I/O
140 PR4A PR11A PR7A PR9C PR11A I/O-CS1
141 PR4B PR11D PR7B PR9D PR11D I/O
145 PR3A PR9A PR6A PR7A PR9A I/O-CS0
147 PR3C PR8B PR5B PR6B PR8B I/O
149 PR2A PR7A PR4A PR5A PR7A I/O-RD/MPI_STRB
150 PR2C PR5A PR4D PR5D PR5A I/O
152 PR1A PR3A PR2A PR3A PR3A I/O-WR
156 PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN RD_CFG

Data Sheet


159 PT12D PT28D PT18D PT22D PT28D I/O-SECKUR
160 PT12A PT27A PT17D PT21A PT27A I/O-RDY/RCLK/MPI_ALE
161 PT11D PT25D PT16D PT19D PT25D I/O

162 PT11C PT25A PT16A PT19A PT25A I/O
163 PT11A PT24D PT15D PT18D PT24D I/O-D7
165 PT10C PT22D PT14A PT17A PT22D I/O
166 PT10B PT21D PT13D PT16D PT21D I/O
167 PT10A PT20D PT13B PT16B PT20D I/O-D6
170 PT9C PT19A PT12C PT15B PT19A I/O
171 PT9B PT18D PT12B PT15A PT18D I/O
172 PT9A PT18A PT12A PT14C PT18A I/O-D5
173 PT8D PT17D PT11D PT14B PT17D I/O
174 PT8C PT17A PT11C PT13D PT17A I/O
175 PT8B PT16D PT11B PT13C PT16D I/O
176 PT8A PT16A PT11A PT13A PT16A I/O-D4
178 PECKT PECKT PECKT PECKT PECKT I-ECKT
179 PT7C PT15C PT10C PT12C PT15C I/O
180 PT7B PT15B PT10B PT12B PT15B I/O
188 PT5D PT13D PT8D PT10D PT13D I/O-D1
189 PT5C PT13A PT8C PT10B PT13A I/O
190 PT5B PT12D PT8B PT10A PT12D I/O
191 PT5A PT12A PT8A PT9C PT12A I/O-D0/DIN
193 PT4C PT11A PT7C PT8D PT11A I/O
194 PT4B PT10D PT7B PT8C PT10D I/O
195 PT4A PT10A PT7A PT8A PT10A I/O-DOUT
Data Sheet


199 PT3B PT7A PT5C PT6C PT7A I/O
200 PT3A PT6A PT5A PT6A PT6A I/O-TDI
201 PT2D PT5A PT4A PT5A PT5A I/O
202 PT2A PT4A PT3A PT4A PT4A I/O-TMS
203 PT1D PT3A PT2C PT3A PT3A I/O
206 PT1A PT1A PT1A PT1A PT1A I/O-TCK
208 PRD_DATA PRD_DATA PRD_DATA PRD_DATA PRD_DATA RD_DATA/TDO

Data Sheet

Table 71. OR3T20, OR3T30, OR3T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout

4 PL1C PL1B PL1C PL1C PL1C I/O
5 PL1B PL1A PL1B PL1B PL1B I/O
6 PL1A PL2D PL2D PL2D PL2D I/O-A0/MPI_BE0
9 PL2C PL3C PL3A PL4A PL5D I/O
10 PL2B PL3B PL4D PL5D PL6D I/O
11 PL2A PL3A PL4A PL5A PL7D I/O-A1/MPI_BE1
12 PL3D PL4D PL5A PL6A PL8A I/O-A2
13 PL3C PL4C PL6D PL7D PL9D I/O
18 PL4C PL5C PL7C PL8A PL10A I/O
19 PL4B PL5B PL7B PL9D PL11D I/O
20 PL4A PL5A PL7A PL9B PL11A I/O-A4
21 PL5D PL6D PL8D PL9A PL12D I/O-A5
22 PL5C PL6C PL8C PL10C PL12A I/O
23 PL5B PL6B PL8B PL10B PL13D I/O
26 PECKL PECKL PECKL PECKL PECKL I-ECKL
29 PL6A PL7A PL9A PL11A PL14A I/O-A7/MPI_CLK
34 PL7A PL8A PL10A PL12A PL15A I/O-A8/MPI_RW
36 PL8D PL9D PL11D PL13D PL16D I/O-A9/MPI_ACK
37 PL8C PL9C PL11C PL13B PL16A I/O
38 PL8B PL9B PL11B PL13A PL17D I/O
39 PL8A PL9A PL11A PL14C PL17A I/O-A10/MPI_BI

Data Sheet


40 PL9D PL10D PL12D PL14B PL18D I/O
41 PL9C PL10C PL12C PL15C PL18A I/O
43 PL9A PL10A PL12A PL15A PL19A I/O-A11/MPI_IRQ
45 PL10D PL11D PL13D PL16D PL20D I/O-A12
46 PL10C PL11C PL13B PL16B PL20B I/O
47 PL10B PL11B PL14D PL17D PL21D I/O
48 PL10A PL11A PL14B PL17B PL21B I/O-A13
49 PL11D PL12D PL14A PL17A PL21A I/O
50 PL11C PL12C PL15D PL18D PL22D I/O
52 PL11A PL12A PL16D PL19D PL24A I/O-A14
55 PL12C PL13A PL17A PL21D PL27D I/O
56 PL12B PL14C PL18C PL21A PL27A I/O-SECKLL
59 PCCLK PCCLK PCCLK PCCLK PCCLK CCLK
63 PB1A PB1A PB1A PB1A PB1A I/O-A16
64 PB1B PB1D PB1D PB2A PB2A I/O
65 PB1C PB2A PB2A PB2D PB2D I/O
68 PB2A PB3A PB3D PB4D PB4D I/O-A17
69 PB2B PB3B PB4D PB5D PB5D I/O
70 PB2C PB3C PB5A PB6A PB6A I/O
71 PB2D PB3D PB5B PB6B PB6D I/O
72 PB3A PB4A PB5D PB6D PB7D I/O
73 PB3B PB4B PB6A PB7A PB8A I/O
74 PB3C PB4C PB6B PB7B PB8D I/O
78 PB4B PB5B PB7B PB8D PB10D I/O

Data Sheet


79 PB4C PB5C PB7C PB9A PB11A I/O
80 PB4D PB5D PB7D PB9C PB11D I/O
81 PB5A PB6A PB8A PB9D PB12A I/O
82 PB5B PB6B PB8B PB10A PB12D I/O
83 PB5C PB6C PB8C PB10B PB13A I/O
91 PECKB PECKB PECKB PECKB PECKB I-ECKB
97 PB8B PB9B PB11B PB13B PB16D I/O
98 PB8C PB9C PB11C PB13C PB17A I/O
99 PB8D PB9D PB11D PB14A PB17D I/O
100 PB9A PB10A PB12A PB14B PB18A I/O-HDC
101 PB9B PB10B PB12B PB14D PB18D I/O
102 PB9C PB10C PB12C PB15A PB19A I/O
105 PB10A PB11A PB13A PB16A PB20A I/O-LDC
108 PB10D PB12B PB14D PB17D PB23D I/O
109 PB11A PB12C PB15A PB18A PB24A I/O-INIT
112 PB11D PB13B PB16D PB19D PB25D I/O
113 VSS — VSS VSS VSS VSS
114 PB12A PB13D PB17A PB20A PB26A I/O
115 PB12B PB14A PB17D PB21A PB27A I/O
116 PB12C PB14B PB18A PB21D PB27D I/O

Data Sheet


119 PDONE PDONE PDONE PDONE PDONE DONE
122 PRESETN PRESETN PRESETN PRESETN PRESETN RESET
123 PPRGMN PPRGMN PPRGMN PPRGMN PPRGMN PRGM
125 PR12B PR14D PR18C PR22D PR28D I/O
126 PR12C PR13A PR18D PR21A PR27A I/O
127 PR12D PR13D PR17B PR20A PR26A I/O
130 PR11B PR12B PR16D PR19D PR24A I/O
131 PR11C PR12C PR15A PR18A PR23A I/O
132 PR11D PR12D PR15C PR18C PR23D I/O
133 PR10A PR11A PR15D PR18D PR22D I/O-M1
134 PR10B PR11B PR14A PR17A PR21A I/O
135 PR10C PR11C PR14D PR17D PR21D I/O
136 PR10D PR11D PR13A PR16A PR20A I/O
139 PR9B PR10B PR12B PR15D PR19D I/O
140 PR9C PR10C PR12C PR14A PR18A I/O
141 PR9D PR10D PR12D PR14C PR18D I/O
142 PR8A PR9A PR11A PR14D PR17A I/O-M3
143 PR8B PR9B PR11B PR13A PR17D I/O
144 PR8C PR9C PR11C PR13B PR16A I/O
152 PECKR PECKR PECKR PECKR PECKR I-ECKR

Data Sheet


158 PR5B PR6B PR8B PR10C PR13D I/O
159 PR5C PR6C PR8C PR10D PR12A I/O
160 PR5D PR6D PR8D PR9B PR12D I/O
161 PR4A PR5A PR7A PR9C PR11A I/O-CS1
162 PR4B PR5B PR7B PR9D PR11D I/O
163 PR4C PR5C PR7C PR8A PR10A I/O
166 PR3A PR4A PR6A PR7A PR9A I/O-CS0
168 PR3C PR4C PR5B PR6B PR8B I/O
170 PR2A PR3A PR4A PR5A PR7A I/O-RD/MPI_STRB
171 PR2B PR3B PR4B PR5B PR6A I/O
172 PR2C PR3C PR4D PR5D PR5A I/O
173 PR2D PR3D PR3A PR4A PR4A I/O
175 PR1A PR2A PR2A PR3A PR3A I/O-WR
176 PR1B PR2D PR2C PR2A PR2A I/O
177 PR1C PR1A PR1A PR1A PR1A I/O
180 PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN RD_CFG
184 PT12D PT14D PT18D PT22D PT28D I/O-SECKUR
185 PT12C PT14C PT18B PT22A PT28A I/O
186 PT12B PT14A PT18A PT21D PT27D I/O
187 PT12A PT13D PT17D PT21A PT27A I/O-RDY/RCLK/MPI_ALE
188 VSS — VSS VSS VSS VSS

189 PT11D PT13B PT16D PT19D PT25D I/O
190 PT11C PT13A PT16C PT19C PT25C I/O
191 PT11B PT12D PT16A PT19A PT25A I/O
192 PT11A PT12C PT15D PT18D PT24D I/O-D7
193 PT10D PT12A PT14D PT17D PT23D I/O
194 PT10C PT11D PT14A PT17A PT22D I/O
195 PT10B PT11C PT13D PT16D PT21D I/O

Data Sheet


196 PT10A PT11B PT13B PT16B PT20D I/O-D6
199 PT9C PT10C PT12C PT15B PT19A I/O
200 PT9B PT10B PT12B PT15A PT18D I/O
201 PT9A PT10A PT12A PT14C PT18A I/O-D5
203 PT8C PT9C PT11C PT13D PT17A I/O
204 PT8B PT9B PT11B PT13C PT16D I/O
207 PECKT PECKT PECKT PECKT PECKT I-ECKT
217 PT5D PT6D PT8D PT10D PT13D I/O-D1
218 PT5C PT6C PT8C PT10B PT13A I/O
219 PT5B PT6B PT8B PT10A PT12D I/O
220 PT5A PT6A PT8A PT9C PT12A I/O-D0/DIN
222 PT4C PT5C PT7C PT8D PT11A I/O
223 PT4B PT5B PT7B PT8C PT10D I/O
224 PT4A PT5A PT7A PT8A PT10A I/O-DOUT
227 PT3C PT4C PT6A PT7A PT8A I/O
228 PT3B PT4B PT5C PT6C PT7A I/O
229 PT3A PT4A PT5A PT6A PT6A I/O-TDI
231 PT2C PT3C PT4A PT5A PT5A I/O
232 PT2B PT3B PT3D PT4D PT4D I/O
233 PT2A PT3A PT3A PT4A PT4A I/O-TMS

Data Sheet


235 PT1D PT2D PT2C PT3A PT3A I/O
238 PT1A PT1A PT1A PT1A PT1A I/O-TCK
240 PRD_DATA PRD_DATA PRD_DATA PRD_DATA PRD_DATA RD_DATA/TDO

Data Sheet

Table 72. OR3T20, OR3T30, and OR3T55 256-Pin PBGA Pinout
OR3T20 OR3T30 OR3T55 OR3T20 OR3T30 OR3T55

Pin Pad Pad Pad Function Pin Pad Pad Pad Function
B1 VDD VDD VDD VDD T1 PL10B PL11B PL14D I/O
C2 PL1D PL1D PL1D I/O P4 PL10A PL11A PL14B I/O-A13
D2 PL1C PL1B PL1C I/O R3 PL11D PL12D PL14A I/O
D3 PL1B PL1A PL1B I/O T2 PL11C PL12C PL15D I/O
E4 PL1A PL2D PL2D I/O-A0/MPI_BE0 U1 PL11B PL12B PL15B I/O
C1 — PL2C PL2C I/O T3 PL11A PL12A PL16D I/O-A14
D1 — PL2B PL2B I/O U2 — PL13D PL17D I/O
E3 — PL2A PL2A I/O V1 PL12D PL13C PL17C I/O
E2 PL2D PL3D PL3D I/O T4 PL12C PL13B PL17B I/O
E1 PL2C PL3C PL3A I/O U3 — PL13A PL17A I/O
F3 PL2B PL3B PL4D I/O V2 — PL14D PL18D I/O
G4 PL2A PL3A PL4A I/O-A1/MPI_BE1 W1 PL12B PL14C PL18C I/O-SECKLL
F2 — — PL5D I/O V3 — PL14B PL18B I/O
F1 PL3D PL4D PL5A I/O-A2 W2 PL12A PL14A PL18A I/O-A15
G3 PL3C PL4C PL6D I/O Y1 PCCLK PCCLK PCCLK CCLK
G2 PL3B PL4B PL6B I/O W3 — — — NC
G1 PL3A PL4A PL6A I/O-A3 Y2 PB1A PB1A PB1A I/O-A16
H3 PL4D PL5D PL7D I/O W4 — PB1C PB1C I/O
H2 PL4C PL5C PL7C I/O V4 PB1B PB1D PB1D I/O
H1 PL4B PL5B PL7B I/O U5 PB1C PB2A PB2A I/O
J4 PL4A PL5A PL7A I/O-A4 Y3 PB1D PB2B PB2B I/O
J3 PL5D PL6D PL8D I/O-A5 Y4 — PB2C PB2C I/O
J2 PL5C PL6C PL8C I/O V5 — PB2D PB2D I/O
J1 PL5B PL6B PL8B I/O W5 PB2A PB3A PB3D I/O-A17
K2 PL5A PL6A PL8A I/O-A6 Y5 PB2B PB3B PB4D I/O
K3 PECKL PECKL PECKL I-ECKL V6 PB2C PB3C PB5A I/O
K1 PL6C PL7C PL9C I/O U7 PB2D PB3D PB5B I/O
L1 PL6B PL7B PL9B I/O W6 PB3A PB4A PB5D I/O
L2 PL6A PL7A PL9A I/O-A7/MPI_CLK Y6 PB3B PB4B PB6A I/O
L3 PL7D PL8D PL10D I/O V7 PB3C PB4C PB6B I/O
L4 PL7C PL8C PL10C I/O W7 PB3D PB4D PB6D I/O
M1 PL7B PL8B PL10B I/O Y7 PB4A PB5A PB7A I/O
M2 PL7A PL8A PL10A I/O-A8/MPI_RW V8 PB4B PB5B PB7B I/O
M3 PL8D PL9D PL11D I/O-A9/MPI_ACK W8 PB4C PB5C PB7C I/O
M4 PL8C PL9C PL11C I/O Y8 PB4D PB5D PB7D I/O
N1 PL8B PL9B PL11B I/O U9 PB5A PB6A PB8A I/O
N2 PL8A PL9A PL11A I/O-A10/MPI_BI V9 PB5B PB6B PB8B I/O
N3 PL9D PL10D PL12D I/O W9 PB5C PB6C PB8C I/O
P1 PL9C PL10C PL12C I/O Y9 PB5D PB6D PB8D I/O
P2 PL9B PL10B PL12B I/O W10 PB6A PB7A PB9A I/O
R1 PL9A PL10A PL12A I/O-A11/MPI_IRQ V10 PB6B PB7B PB9B I/O
P3 PL10D PL11D PL13D I/O-A12 Y10 PB6C PB7C PB9C I/O
R2 PL10C PL11C PL13B I/O Y11 PB6D PB7D PB9D I/O
Data Sheet

Table 72. OR3T20, OR3T30, and OR3T55 256-Pin PBGA Pinout (continued)

W11 PECKB PECKB PECKB I-ECKB R19 PR11D PR12D PR15C I/O
V11 PB7B PB8B PB10B I/O R20 PR10A PR11A PR15D I/O-M1
U11 PB7C PB8C PB10C I/O P18 PR10B PR11B PR14A I/O
Y12 PB7D PB8D PB10D I/O P19 PR10C PR11C PR14D I/O
W12 PB8A PB9A PB11A I/O P20 PR10D PR11D PR13A I/O
V12 PB8B PB9B PB11B I/O N18 PR9A PR10A PR12A I/O-M2
U12 PB8C PB9C PB11C I/O N19 PR9B PR10B PR12B I/O
Y13 PB8D PB9D PB11D I/O N20 PR9C PR10C PR12C I/O
W13 PB9A PB10A PB12A I/O-HDC M17 PR9D PR10D PR12D I/O
V13 PB9B PB10B PB12B I/O M18 PR8A PR9A PR11A I/O-M3
Y14 PB9C PB10C PB12C I/O M19 PR8B PR9B PR11B I/O
W14 PB9D PB10D PB12D I/O M20 PR8C PR9C PR11C I/O
Y15 PB10A PB11A PB13A I/O-LDC L19 PR8D PR9D PR11D I/O
V14 PB10B PB11B PB13B I/O L18 PR7A PR8A PR10A I/O
W15 PB10C PB11C PB13C I/O L20 PR7B PR8B PR10B I/O
Y16 PB10D PB11D PB13D I/O K20 PR7C PR8C PR10C I/O
U14 — PB12A PB14A I/O K19 PR7D PR8D PR10D I/O
V15 — PB12B PB14D I/O K18 PECKR PECKR PECKR I-ECKR
W16 PB11A PB12C PB15A I/O-INIT K17 PR6B PR7B PR9B I/O
Y17 — — PB15D I/O J20 PR6C PR7C PR9C I/O
V16 — PB12D PB16A I/O J19 PR6D PR7D PR9D I/O
W17 PB11B PB13A PB16D I/O J18 PR5A PR6A PR8A I/O
Y18 PB11C PB13B PB17A I/O J17 PR5B PR6B PR8B I/O
U16 PB11D PB13C PB17C I/O H20 PR5C PR6C PR8C I/O
V17 PB12A PB13D PB17D I/O H19 PR5D PR6D PR8D I/O
W18 PB12B PB14A PB18A I/O H18 PR4A PR5A PR7A I/O-CS1
Y19 PB12C PB14B PB18B I/O G20 PR4B PR5B PR7B I/O
V18 PB12D PB14C PB18C I/O G19 PR4C PR5C PR7C I/O
W19 — PB14D PB18D I/O F20 PR4D PR5D PR7D I/O
Y20 PDONE PDONE PDONE DONE G18 PR3A PR4A PR6A I/O-CS0
W20 PRESETN PRESETN PRESETN RESET F19 PR3B PR4B PR6B I/O
V19 PPRGMN PPRGMN PPRGMN PRGM E20 PR3C PR4C PR5B I/O
U19 PR12A PR14A PR18A I/O-M0 G17 PR3D PR4D PR5D I/O
U18 — PR14C PR18C I/O F18 PR2A PR3A PR4A I/O-RD/MPI_STRB
T17 — PR14D PR18D I/O E19 PR2B PR3B PR4B I/O
V20 — PR13A PR17A I/O D20 PR2C PR3C PR4D I/O
U20 PR12B PR13B PR17B I/O E18 PR2D PR3D PR3A I/O
T18 PR12C PR13C PR17C I/O D19 PR1A PR2A PR2A I/O-WR
T19 PR12D PR13D PR17D I/O C20 PR1B PR2B PR2B I/O
T20 PR11A PR12A PR16A I/O E17 PR1C PR2C PR2C I/O
R18 PR11B PR12B PR16D I/O D18 PR1D PR2D PR2D I/O
P17 PR11C PR12C PR15A I/O C19 — PR1A PR1A I/O

Data Sheet


B20 — PR1B PR1B I/O B7 PT4A PT5A PT7A I/O-DOUT
C18 — PR1C PR1C I/O A6 PT3D PT4D PT6D I/O
B19 — PR1D PR1D I/O C7 PT3C PT4C PT6A I/O
A20 PRD_CFGN PRD_CFGN PRD_CFGN RD_CFG B6 PT3B PT4B PT5C I/O
A19 PT12D PT14D PT18D I/O-SECKUR A5 PT3A PT4A PT5A I/O-TDI
B18 — PT14C PT18C I/O D7 PT2D PT3D PT4D I/O
B17 PT12C PT14B PT18B I/O C6 PT2C PT3C PT4A I/O
C17 PT12B PT14A PT18A I/O B5 PT2B PT3B PT3D I/O
D16 PT12A PT13D PT17D I/O-RDY/RCLK/MPI_ALE A4 PT2A PT3A PT3A I/O-TMS
A18 — PT13C PT17A I/O C5 — PT2D PT2D I/O
A17 PT11D PT13B PT16D I/O B4 PT1D PT2C PT2C I/O
C16 PT11C PT13A PT16C I/O A3 PT1C PT2B PT2B I/O
B16 PT11B PT12D PT16A I/O D5 PT1B PT2A PT2A I/O
A16 PT11A PT12C PT15D I/O-D7 C4 — PT1D PT1D I/O
C15 — PT12B PT15A I/O B3 — PT1C PT1C I/O
D14 PT10D PT12A PT14D I/O B2 — PT1B PT1B I/O
B15 PT10C PT11D PT14A I/O A2 PT1A PT1A PT1A I/O-TCK
A15 PT10B PT11C PT13D I/O C3 PRD_DATA PRD_DATA PRD_DATA RD_DATA/TDO
C14 PT10A PT11B PT13B I/O-D6 A1 VSS VSS VSS VSS
B14 PT9D PT11A PT13A I/O D4 VSS VSS VSS VSS
A14 PT9C PT10D PT12D I/O D8 VSS VSS VSS VSS
C13 — PT10C PT12C I/O D13 VSS VSS VSS VSS
B13 PT9B PT10B PT12B I/O D17 VSS VSS VSS VSS
A13 PT9A PT10A PT12A I/O-D5 H4 VSS VSS VSS VSS
D12 PT8D PT9D PT11D I/O H17 VSS VSS VSS VSS
C12 PT8C PT9C PT11C I/O N4 VSS VSS VSS VSS
B12 PT8B PT9B PT11B I/O N17 VSS VSS VSS VSS
A12 PT8A PT9A PT11A I/O-D4 U4 VSS VSS VSS VSS
B11 PECKT PECKT PECKT I-ECKT U8 VSS VSS VSS VSS
C11 PT7C PT8C PT10C I/O U13 VSS VSS VSS VSS
A11 PT7B PT8B PT10B I/O U17 VSS VSS VSS VSS
A10 PT7A PT8A PT10A I/O-D3 J9 VSS VSS VSS VSS*
B10 PT6D PT7D PT9D I/O J10 VSS VSS VSS VSS*
C10 PT6C PT7C PT9C I/O J11 VSS VSS VSS VSS*
D10 PT6B PT7B PT9B I/O J12 VSS VSS VSS VSS*
A9 PT6A PT7A PT9A I/O-D2 K9 VSS VSS VSS VSS*
B9 PT5D PT6D PT8D I/O-D1 K10 VSS VSS VSS VSS*
C9 PT5C PT6C PT8C I/O K11 VSS VSS VSS VSS*
D9 PT5B PT6B PT8B I/O K12 VSS VSS VSS VSS*
A8 PT5A PT6A PT8A I/O-D0/DIN L9 VSS VSS VSS VSS*
B8 PT4D PT5D PT7D I/O L10 VSS VSS VSS VSS*
C8 PT4C PT5C PT7C I/O L11 VSS VSS VSS VSS*
A7 PT4B PT5B PT7B I/O L12 VSS VSS VSS VSS*
Data Sheet


M9 VSS VSS VSS VSS* F17 VDD VDD VDD VDD
M10 VSS VSS VSS VSS* K4 VDD VDD VDD VDD
M11 VSS VSS VSS VSS* L17 VDD VDD VDD VDD
M12 VSS VSS VSS VSS* R4 VDD VDD VDD VDD
D6 VDD VDD VDD VDD R17 VDD VDD VDD VDD
D11 VDD VDD VDD VDD U6 VDD VDD VDD VDD
D15 VDD VDD VDD VDD U10 VDD VDD VDD VDD
F4 VDD VDD VDD VDD U15 VDD VDD VDD VDD
* Thermally enhanced connection.

Data Sheet

Table 73. OR3T20, OR3T30, OR3T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout

Pin Function
Pad Pad Pad Pad Pad
B1 PL1D PL1D PL1D PL1D PL1D I/O
C2 — PL1C PL1C PL1C PL1C I/O
C1 PL1C PL1B PL1B PL1B PL1B I/O
D2 PL1B PL1A PL1A PL1A PL1A I/O
D3 PL1A PL2D PL2D PL2D PL2D I/O-A0/MPI_BE0
D1 — PL2C PL2C PL2A PL2A I/O
E2 — PL2B PL2B PL3D PL3D I/O
E4 — — — PL3B PL3B I/O
E3 — PL2A PL2A PL3A PL3A I/O
E1 PL2D PL3D PL3D PL4D PL4D I/O
F2 — — PL3C PL4C PL4C I/O
G4 PL2C PL3C PL3B PL4B PL4B I/O
F3 — — PL3A PL4A PL5D I/O
F1 PL2B PL3B PL4D PL5D PL6D I/O
G2 — — PL4C PL5C PL6C I/O
G1 — — PL4B PL5B PL6B I/O
G3 PL2A PL3A PL4A PL5A PL7D I/O-A1/MPI_BE1
H2 — — PL5D PL6D PL8D I/O
J4 — — PL5C PL6C PL8C I/O
H1 — — PL5B PL6B PL8B I/O
H3 PL3D PL4D PL5A PL6A PL8A I/O-A2
J2 — — PL6D PL7D PL9D I/O
J1 PL3C PL4C PL6C PL7C PL9C I/O
K2 PL3B PL4B PL6B PL7B PL9B I/O
J3 PL3A PL4A PL6A PL7A PL9A I/O-A3
K1 PL4D PL5D PL7D PL8D PL10D I/O
K4 PL4C PL5C PL7C PL8A PL10A I/O
L2 PL4B PL5B PL7B PL9D PL11D I/O
K3 PL4A PL5A PL7A PL9B PL11A I/O-A4
L1 PL5D PL6D PL8D PL9A PL12D I/O-A5
M2 PL5C PL6C PL8C PL10C PL12A I/O
M1 PL5B PL6B PL8B PL10B PL13D I/O
L3 PL5A PL6A PL8A PL10A PL13A I/O-A6
N2 PECKL PECKL PECKL PECKL PECKL I-ECKL
M4 PL6C PL7C PL9C PL11C PL14C I/O
N1 PL6B PL7B PL9B PL11B PL14B I/O
M3 PL6A PL7A PL9A PL11A PL14A I/O-A7/MPI_CLK
P2 PL7D PL8D PL10D PL12D PL15D I/O
P4 PL7C PL8C PL10C PL12C PL15C I/O
P1 PL7B PL8B PL10B PL12B PL15B I/O
N3 PL7A PL8A PL10A PL12A PL15A I/O-A8/MPI_RW
R2 PL8D PL9D PL11D PL13D PL16D I/O-A9/MPI_ACK

Data Sheet

Table 73. OR3T20, OR3T30, OR3T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued)

Pin Function
Pad Pad Pad Pad Pad
P3 PL8C PL9C PL11C PL13B PL16A I/O
R1 PL8B PL9B PL11B PL13A PL17D I/O
T2 PL8A PL9A PL11A PL14C PL17A I/O-A10/MPI_BI
R3 PL9D PL10D PL12D PL14B PL18D I/O
T1 PL9C PL10C PL12C PL15C PL18A I/O
R4 PL9B PL10B PL12B PL15B PL19D I/O
U2 PL9A PL10A PL12A PL15A PL19A I/O-A11/MPI_IRQ
T3 PL10D PL11D PL13D PL16D PL20D I/O-A12
U1 — — PL13C PL16C PL20C I/O
U4 PL10C PL11C PL13B PL16B PL20B I/O
V2 — — PL13A PL16A PL20A I/O
U3 PL10B PL11B PL14D PL17D PL21D I/O
V1 — — PL14C PL17C PL21C I/O
W2 PL10A PL11A PL14B PL17B PL21B I/O-A13
W1 — — PL14A PL17A PL21A I/O
V3 PL11D PL12D PL15D PL18D PL22D I/O
Y2 PL11C PL12C PL15C PL18C PL22C I/O
W4 PL11B PL12B PL15B PL18B PL23D I/O
Y1 — — PL15A PL18A PL24D I/O
W3 PL11A PL12A PL16D PL19D PL24A I/O-A14
AA2 — — PL16C PL19C PL25C I/O
Y4 — — PL16B PL19B PL25B I/O
AA1 — — PL16A PL19A PL25A I/O
Y3 — PL13D PL17D PL20D PL26D I/O
AB2 PL12D PL13C PL17C PL20C PL26C I/O
AB1 PL12C PL13B PL17B PL20A PL26A I/O
AA3 — PL13A PL17A PL21D PL27D I/O
AC2 — PL14D PL18D PL21C PL27C I/O
AB4 PL12B PL14C PL18C PL21A PL27A I/O-SECKLL
AC1 — PL14B PL18B PL22D PL28D I/O
AB3 — — — PL22C PL28C I/O
AD2 — — — PL22B PL28B I/O
AC3 PL12A PL14A PL18A PL22A PL28A I/O-A15
AD1 PCCLK PCCLK PCCLK PCCLK PCCLK CCLK
AF2 PB1A PB1A PB1A PB1A PB1A I/O-A16
AE3 — — — PB1B PB1B I/O
AF3 — PB1B PB1B PB1C PB1C I/O
AE4 — PB1C PB1C PB1D PB1D I/O
AD4 PB1B PB1D PB1D PB2A PB2A I/O
AF4 PB1C PB2A PB2A PB2D PB2D I/O
AE5 — — PB2B PB3A PB3A I/O
AC5 PB1D PB2B PB2C PB3C PB3C I/O
AD5 — — PB2D PB3D PB3D I/O
Data Sheet


Pin Function
Pad Pad Pad Pad Pad
AF5 — PB2C PB3A PB4A PB4A I/O
AE6 — PB2D PB3B PB4B PB4B I/O
AC7 — — PB3C PB4C PB4C I/O
AD6 PB2A PB3A PB3D PB4D PB4D I/O-A17
AF6 — — PB4A PB5A PB5A I/O
AE7 — — PB4B PB5B PB5B I/O
AF7 — — PB4C PB5C PB5C I/O
AE8 — — PB5A PB6A PB6A I/O
AC9 PB2B PB3B PB5B PB6B PB6D I/O
AF8 PB2C PB3C PB5C PB6C PB7A I/O
AD8 PB2D PB3D PB5D PB6D PB7D I/O
AE9 PB3A PB4A PB6A PB7A PB8A I/O
AF9 PB3B PB4B PB6B PB7B PB8D I/O
AE10 PB3C PB4C PB6C PB7C PB9A I/O
AF10 PB4A PB5A PB7A PB8A PB10A I/O
AC10 PB4B PB5B PB7B PB8D PB10D I/O
AE11 PB4C PB5C PB7C PB9A PB11A I/O
AD10 PB4D PB5D PB7D PB9C PB11D I/O
AF11 PB5A PB6A PB8A PB9D PB12A I/O
AE12 PB5B PB6B PB8B PB10A PB12D I/O
AF12 PB5C PB6C PB8C PB10B PB13A I/O
AC12 PB6B PB7B PB9B PB11B PB14B I/O
AF13 PB6C PB7C PB9C PB11C PB14C I/O
AE14 PECKB PECKB PECKB PECKB PECKB I-ECKB
AC14 PB7B PB8B PB10B PB12B PB15B I/O
AF14 PB7C PB8C PB10C PB12C PB15C I/O
AD14 PB8B PB9B PB11B PB13B PB16D I/O
AF15 PB8C PB9C PB11C PB13C PB17A I/O
AE16 PB8D PB9D PB11D PB14A PB17D I/O
AD15 PB9A PB10A PB12A PB14B PB18A I/O-HDC
AF16 PB9B PB10B PB12B PB14D PB18D I/O
AC15 PB9C PB10C PB12C PB15A PB19A I/O
AE17 PB9D PB10D PB12D PB15D PB19D I/O
AD16 PB10A PB11A PB13A PB16A PB20A I/O-LDC
AF17 — — PB13B PB16B PB20D I/O

Data Sheet


Pin Function
Pad Pad Pad Pad Pad
AC17 PB10B PB11B PB13C PB16C PB21A I/O
AE18 PB10C PB11C PB13D PB16D PB21D I/O
AD17 PB10D PB11D PB14A PB17A PB22A I/O
AF18 — PB12A PB14B PB17B PB23A I/O
AE19 — — PB14C PB17C PB23C I/O
AF19 — PB12B PB14D PB17D PB23D I/O
AD18 PB11A PB12C PB15A PB18A PB24A I/O-INIT
AF20 — — PB15D PB18D PB24D I/O
AD19 — PB12D PB16A PB19A PB25A I/O
AF21 PB11B PB13A PB16D PB19D PB25D I/O
AD20 PB11C PB13B PB17A PB20A PB26A I/O
AE22 PB11D PB13C PB17B PB20B PB26B I/O
AF22 PB12A PB13D PB17C PB20D PB26D I/O
AD21 PB12B PB14A PB17D PB21A PB27A I/O
AE23 — — — PB21B PB27B I/O
AC22 PB12C PB14B PB18A PB21D PB27D I/O
AF23 PB12D PB14C PB18B PB22A PB28A I/O
AD22 — PB14D PB18C PB22B PB28B I/O
AE24 — — — PB22C PB28C I/O
AF24 PDONE PDONE PDONE PDONE PDONE DONE
AE26 PRESETN PRESETN PRESETN PRESETN PRESETN RESET
AD25 PPRGMN PPRGMN PPRGMN PPRGMN PPRGMN PRGM
AD26 PR12A PR14A PR18A PR22A PR28A I/O-M0
AC25 — PR14B PR18B PR22C PR28C I/O
AC24 — PR14C PR18C PR22D PR28D I/O
AC26 — PR14D PR18D PR21A PR27A I/O
AB25 — PR13A PR17A PR21D PR27D I/O
AB23 PR12B PR13B PR17B PR20A PR26A I/O
AB24 PR12C PR13C PR17C PR20B PR26B I/O
AB26 PR12D PR13D PR17D PR20D PR26D I/O
AA25 PR11A PR12A PR16A PR19A PR25A I/O
Y23 — — PR16B PR19B PR25B I/O
AA24 PR11B PR12B PR16C PR19C PR25C I/O
AA26 — — PR16D PR19D PR24A I/O
Y25 PR11C PR12C PR15A PR18A PR23A I/O
Y26 — — PR15B PR18B PR23B I/O
Y24 PR11D PR12D PR15C PR18C PR23D I/O

Data Sheet


Pin Function
Pad Pad Pad Pad Pad
W25 PR10A PR11A PR15D PR18D PR22D I/O-M1
V23 PR10B PR11B PR14A PR17A PR21A I/O
W26 — — PR14B PR17B PR21B I/O
W24 — — PR14C PR17C PR21C I/O
V25 PR10C PR11C PR14D PR17D PR21D I/O
V26 PR10D PR11D PR13A PR16A PR20A I/O
U25 — — PR13B PR16B PR20B I/O
V24 — — PR13C PR16C PR20C I/O
U26 — — PR13D PR16D PR20D I/O
U23 PR9A PR10A PR12A PR15A PR19A I/O-M2
T25 PR9B PR10B PR12B PR15D PR19D I/O
U24 PR9C PR10C PR12C PR14A PR18A I/O
T26 PR9D PR10D PR12D PR14C PR18D I/O
R25 PR8A PR9A PR11A PR14D PR17A I/O-M3
R26 PR8B PR9B PR11B PR13A PR17D I/O
T24 PR8C PR9C PR11C PR13B PR16A I/O
P25 PR8D PR9D PR11D PR13D PR16D I/O
R23 PR7A PR8A PR10A PR12A PR15A I/O
P26 PR7B PR8B PR10B PR12B PR15B I/O
R24 PR7C PR8C PR10C PR12C PR15C I/O
N25 PR7D PR8D PR10D PR12D PR15D I/O
N23 PECKR PECKR PECKR PECKR PECKR I-ECKR
N26 PR6B PR7B PR9B PR11B PR14B I/O
P24 PR6C PR7C PR9C PR11C PR14C I/O
M25 PR6D PR7D PR9D PR11D PR14D I/O
N24 PR5A PR6A PR8A PR10A PR13A I/O
M26 PR5B PR6B PR8B PR10C PR13D I/O
L25 PR5C PR6C PR8C PR10D PR12A I/O
M24 PR5D PR6D PR8D PR9B PR12D I/O
L26 PR4A PR5A PR7A PR9C PR11A I/O-CS1
M23 PR4B PR5B PR7B PR9D PR11D I/O
K25 PR4C PR5C PR7C PR8A PR10A I/O
L24 PR4D PR5D PR7D PR8D PR10D I/O
K26 PR3A PR4A PR6A PR7A PR9A I/O-CS0
K23 — — PR6B PR7B PR9B I/O
J25 PR3B PR4B PR6C PR7C PR9C I/O
K24 — — PR6D PR7D PR9D I/O
J26 PR3C PR4C PR5A PR6A PR8A I/O
H25 — — PR5B PR6B PR8B I/O
H26 PR3D PR4D PR5C PR6C PR8C I/O
J24 — — PR5D PR6D PR8D I/O
G25 PR2A PR3A PR4A PR5A PR7A I/O-RD/MPI_STRB

Data Sheet


Pin Function
Pad Pad Pad Pad Pad
H23 PR2B PR3B PR4B PR5B PR6A I/O
G26 — — PR4C PR5C PR6C I/O
H24 PR2C PR3C PR4D PR5D PR5A I/O
F25 PR2D PR3D PR3A PR4A PR4A I/O
G23 — — PR3B PR4B PR4B I/O
F26 — — PR3C PR4C PR4C I/O
G24 — — PR3D PR4D PR4D I/O
E25 PR1A PR2A PR2A PR3A PR3A I/O-WR
E26 PR1B PR2B PR2B PR3B PR3B I/O
F24 — — — PR3D PR3D I/O
D25 PR1C PR2C PR2C PR2A PR2A I/O
E23 PR1D PR2D PR2D PR2D PR2D I/O
D26 — PR1A PR1A PR1A PR1A I/O
E24 — PR1B PR1B PR1B PR1B I/O
C25 — PR1C PR1C PR1C PR1C I/O
D24 — PR1D PR1D PR1D PR1D I/O
C26 PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN RD_CFG
A25 PT12D PT14D PT18D PT22D PT28D I/O-SECKUR
B24 — PT14C PT18C PT22C PT28C I/O
A24 — — — PT22B PT28B I/O
B23 PT12C PT14B PT18B PT22A PT28A I/O
C23 PT12B PT14A PT18A PT21D PT27D I/O
A23 PT12A PT13D PT17D PT21A PT27A I/O-RDY/RCLK/
MPI_ALE
B22 — PT13C PT17C PT20D PT26D I/O
D22 PT11D PT13B PT17B PT20C PT26C I/O
C22 PT11C PT13A PT17A PT20A PT26A I/O
A22 PT11B PT12D PT16D PT19D PT25D I/O
B21 — — PT16C PT19C PT25C I/O
D20 — — PT16B PT19B PT25B I/O
C21 — — PT16A PT19A PT25A I/O
A21 PT11A PT12C PT15D PT18D PT24D I/O-D7
B20 — — PT15C PT18C PT24C I/O
A20 — PT12B PT15B PT18B PT24B I/O
C20 — — PT15A PT18A PT24A I/O
B19 PT10D PT12A PT14D PT17D PT23D I/O
D18 — — PT14C PT17C PT23C I/O
A19 PT10C PT11D PT14B PT17B PT23B I/O
C19 — — PT14A PT17A PT22D I/O
B18 PT10B PT11C PT13D PT16D PT21D I/O
A18 — — PT13C PT16C PT21A I/O
B17 PT10A PT11B PT13B PT16B PT20D I/O-D6

Data Sheet


Pin Function
Pad Pad Pad Pad Pad
C18 PT9D PT11A PT13A PT16A PT20A I/O
A17 PT9C PT10D PT12D PT15D PT19D I/O
D17 — PT10C PT12C PT15B PT19A I/O
B16 PT9B PT10B PT12B PT15A PT18D I/O
C17 PT9A PT10A PT12A PT14C PT18A I/O-D5
A16 PT8D PT9D PT11D PT14B PT17D I/O
B15 PT8C PT9C PT11C PT13D PT17A I/O
A15 PT8B PT9B PT11B PT13C PT16D I/O
C16 PT8A PT9A PT11A PT13A PT16A I/O-D4
B14 PECKT PECKT PECKT PECKT PECKT I-ECKT
D15 PT7C PT8C PT10C PT12C PT15C I/O
A14 PT7B PT8B PT10B PT12B PT15B I/O
B13 PT6D PT7D PT9D PT11D PT14D I/O
D13 PT6C PT7C PT9C PT11C PT14C I/O
A13 PT6B PT7B PT9B PT11B PT14B I/O
B12 PT5D PT6D PT8D PT10D PT13D I/O-D1
C13 PT5C PT6C PT8C PT10B PT13A I/O
A12 PT5B PT6B PT8B PT10A PT12D I/O
B11 PT5A PT6A PT8A PT9C PT12A I/O-D0/DIN
C12 PT4D PT5D PT7D PT9B PT11D I/O
A11 PT4C PT5C PT7C PT8D PT11A I/O
D12 PT4B PT5B PT7B PT8C PT10D I/O
B10 PT4A PT5A PT7A PT8A PT10A I/O-DOUT
C11 PT3D PT4D PT6D PT7D PT9D I/O
D10 — — PT6B PT7B PT8D I/O
B9 PT3C PT4C PT6A PT7A PT8A I/O
C10 PT3B PT4B PT5D PT6D PT7D I/O
B8 — — PT5B PT6B PT6D I/O
A8 PT3A PT4A PT5A PT6A PT6A I/O-TDI
C9 — — PT4D PT5D PT5D I/O
B7 PT2D PT3D PT4C PT5C PT5C I/O
A7 PT2C PT3C PT4A PT5A PT5A I/O
C8 — — PT3D PT4D PT4D I/O
B6 PT2B PT3B PT3C PT4C PT4C I/O
A6 PT2A PT3A PT3A PT4A PT4A I/O-TMS
C7 — PT2D PT2D PT3D PT3D I/O

Data Sheet


Pin Function
Pad Pad Pad Pad Pad
B5 PT1D PT2C PT2C PT3A PT3A I/O
A5 PT1C PT2B PT2B PT2D PT2D I/O
C6 — — — PT2C PT2C I/O
B4 — — — PT2B PT2B I/O
D5 PT1B PT2A PT2A PT2A PT2A I/O
A4 — PT1D PT1D PT1D PT1D I/O
C5 — PT1C PT1C PT1C PT1C I/O
B3 — PT1B PT1B PT1B PT1B I/O
C4 PT1A PT1A PT1A PT1A PT1A I/O-TCK
A3 PRD_DATA PRD_DATA PRD_DATA PRD_DATA PRD_DATA RD_DATA/TDO
A1 VSS VSS VSS VSS VSS VSS
AC13 VSS VSS VSS VSS VSS VSS
AD24 VSS VSS VSS VSS VSS VSS
AD3 VSS VSS VSS VSS VSS VSS
AE1 VSS VSS VSS VSS VSS VSS
AF1 VSS VSS VSS VSS VSS VSS
B2 VSS VSS VSS VSS VSS VSS
C24 VSS VSS VSS VSS VSS VSS
C3 VSS VSS VSS VSS VSS VSS
D14 VSS VSS VSS VSS VSS VSS
H4 VSS VSS VSS VSS VSS VSS
J23 VSS VSS VSS VSS VSS VSS
N4 VSS VSS VSS VSS VSS VSS
P23 VSS VSS VSS VSS VSS VSS
V4 VSS VSS VSS VSS VSS VSS
W23 VSS VSS VSS VSS VSS VSS

Data Sheet


Pin Function
Pad Pad Pad Pad Pad
L11 VSS VSS VSS VSS VSS VSS*
M11 VSS VSS VSS VSS VSS VSS*
N11 VSS VSS VSS VSS VSS VSS*
P11 VSS VSS VSS VSS VSS VSS*
R11 VSS VSS VSS VSS VSS VSS*
T11 VSS VSS VSS VSS VSS VSS*
AA23 VDD VDD VDD VDD VDD VDD
AA4 VDD VDD VDD VDD VDD VDD
AC11 VDD VDD VDD VDD VDD VDD

Data Sheet


Pin Function
Pad Pad Pad Pad Pad
D11 VDD VDD VDD VDD VDD VDD
F23 VDD VDD VDD VDD VDD VDD
F4 VDD VDD VDD VDD VDD VDD
L23 VDD VDD VDD VDD VDD VDD
L4 VDD VDD VDD VDD VDD VDD
T23 VDD VDD VDD VDD VDD VDD
T4 VDD VDD VDD VDD VDD VDD
*Thermally enhanced connection.

Data Sheet

Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout
OR3C/T80 OR3T125 OR3C/T80 OR3T125

Pin Function Pin Function
Pad Pad Pad Pad
E4 PRD_CFGN PRD_CFGN RD_CFG U2 PR12A PR15A I/O
D3 PR1D PR1D I/O U3 PR13D PR16D I/O
D2 PR1C PR1C I/O V1 PR13C PR16B I/O
D1 PR1B PR1B I/O V2 PR13B PR16A I/O
F4 PR1A PR1A I/O V3 PR13A PR17D I/O
E3 PR2D PR2D I/O W1 PR14D PR17A I/O-M3
E2 PR2C PR2C I/O V4 PR14C PR18D I/O
E1 PR2B PR2B I/O W2 PR14B PR18B I/O
F3 PR2A PR2A I/O W3 PR14A PR18A I/O
F2 PR3D PR3D I/O Y2 PR15D PR19D I/O
F1 PR3C PR3C I/O W4 PR15A PR19A I/O-M2
H4 PR3B PR3B I/O Y3 PR16D PR20D I/O
G3 PR3A PR3A I/O-WR AA1 PR16C PR20C I/O
G2 PR4D PR4D I/O AA2 PR16B PR20B I/O
G1 PR4C PR4C I/O Y4 PR16A PR20A I/O
J4 PR4B PR4B I/O AA3 PR17D PR21D I/O
H3 PR4A PR4A I/O AB1 PR17C PR21C I/O
H2 PR5D PR5A I/O AB2 PR17B PR21B I/O
J3 PR5C PR6C I/O AB3 PR17A PR21A I/O
K4 PR5B PR6A I/O AC1 PR18D PR22D I/O-M1
J2 PR5A PR7A I/O-RD/MPI_STRB AC2 PR18C PR23D I/O
J1 PR6D PR8D I/O AB4 PR18B PR23B I/O
K3 PR6C PR8C I/O AC3 PR18A PR23A I/O
K2 PR6B PR8B I/O AD2 PR19D PR24A I/O
K1 PR6A PR8A I/O AD3 PR19C PR25C I/O
L3 PR7D PR9D I/O AC4 PR19B PR25B I/O
M4 PR7C PR9C I/O AE1 PR19A PR25A I/O
L2 PR7B PR9B I/O AE2 PR20D PR26D I/O
L1 PR7A PR9A I/O-CS0 AE3 PR20C PR26C I/O
M3 PR8D PR10D I/O AD4 PR20B PR26B I/O
N4 PR8A PR10A I/O AF1 PR20A PR26A I/O
M2 PR9D PR11D I/O AF2 PR21D PR27D I/O
N3 PR9C PR11A I/O-CS1 AF3 PR21C PR27C I/O
N2 PR9B PR12D I/O AG1 PR21B PR27B I/O
P4 PR9A PR12C I/O AG2 PR21A PR27A I/O
N1 PR10D PR12A I/O AG3 PR22D PR28D I/O
P3 PR10C PR13D I/O AF4 PR22C PR28C I/O
P2 PR10B PR13C I/O AH1 PR22B PR28B I/O
P1 PR10A PR13A I/O AH2 PR22A PR28A I/O-M0
R3 PR11D PR14D I/O AH3 PPRGMN PPRGMN PRGM
R2 PR11C PR14C I/O AG4 PRESETN PRESETN RESET
R1 PR11B PR14B I/O AH5 PDONE PDONE DONE
T2 PECKR PECKR I-ECKR AJ4 PB22D PB28D I/O
T4 PR12D PR15D I/O AK4 PB22C PB28C I/O
T3 PR12C PR15C I/O AL4 PB22B PB28B I/O
U1 PR12B PR15B I/O AH6 PB22A PB28A I/O
Data Sheet

Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout (continued)

Pad Pad Pad Pad
AJ5 PB21D PB27D I/O AL19 PB10A PB12D I/O
AK5 PB21C PB27C I/O AH18 PB9D PB12A I/O
AL5 PB21B PB27B I/O AK19 PB9C PB11D I/O
AJ6 PB21A PB27A I/O AJ19 PB9B PB11B I/O
AK6 PB20D PB26D I/O AK20 PB9A PB11A I/O
AL6 PB20C PB26C I/O AH19 PB8D PB10D I/O
AH8 PB20B PB26B I/O AJ20 PB8B PB10B I/O
AJ7 PB20A PB26A I/O AL21 PB8A PB10A I/O
AK7 PB19D PB25D I/O AK21 PB7D PB9D I/O
AL7 PB19C PB25C I/O AH20 PB7C PB9A I/O
AH9 PB19B PB25B I/O AJ21 PB7B PB8D I/O
AJ8 PB19A PB25A I/O AL22 PB7A PB8A I/O
AK8 PB18D PB24D I/O AK22 PB6D PB7D I/O
AJ9 PB18C PB24C I/O AJ22 PB6C PB7A I/O
AH10 PB18B PB24B I/O AL23 PB6B PB6D I/O
AK9 PB18A PB24A I/O-INIT AK23 PB6A PB6A I/O
AL9 PB17D PB23D I/O AH22 PB5D PB5D I/O
AJ10 PB17C PB23C I/O AJ23 PB5C PB5C I/O
AK10 PB17B PB23A I/O AK24 PB5B PB5B I/O
AL10 PB17A PB22A I/O AJ24 PB5A PB5A I/O
AJ11 PB16D PB21D I/O AH23 PB4D PB4D I/O-A17
AH12 PB16C PB21A I/O AL25 PB4C PB4C I/O
AK11 PB16B PB20D I/O AK25 PB4B PB4B I/O
AL11 PB16A PB20A I/O-LDC AJ25 PB4A PB4A I/O
AJ12 PB15D PB19D I/O AH24 PB3D PB3D I/O
AH13 PB15B PB19B I/O AL26 PB3C PB3C I/O
AK12 PB15A PB19A I/O AK26 PB3B PB3B I/O
AJ13 PB14D PB18D I/O AJ26 PB3A PB3A I/O
AK13 PB14C PB18B I/O AL27 PB2D PB2D I/O
AH14 PB14B PB18A I/O-HDC AK27 PB2C PB2C I/O
AL13 PB14A PB17D I/O AJ27 PB2B PB2B I/O
AJ14 PB13D PB17B I/O AH26 PB2A PB2A I/O
AK14 PB13C PB17A I/O AL28 PB1D PB1D I/O
AL14 PB13B PB16D I/O AK28 PB1C PB1C I/O
AJ15 PB13A PB16A I/O AJ28 PB1B PB1B I/O
AK15 PB12D PB15D I/O AH27 PB1A PB1A I/O-A16
AL15 PB12C PB15C I/O AG28 PCCLK PCCLK CCLK
AK16 PB12B PB15B I/O AH29 PL22A PL28A I/O-A15
AH16 PECKB PECKB I-ECKB AH30 PL22B PL28B I/O
AJ16 PB11D PB14D I/O AH31 PL22C PL28C I/O
AL17 PB11C PB14C I/O AF28 PL22D PL28D I/O
AK17 PB11B PB14B I/O AG29 PL21A PL27A I/O-SECKLL
AJ17 PB11A PB14A I/O AG30 PL21B PL27B I/O
AL18 PB10D PB13D I/O AG31 PL21C PL27C I/O
AK18 PB10C PB13B I/O AF29 PL21D PL27D I/O
AJ18 PB10B PB13A I/O AF30 PL20A PL26A I/O
Data Sheet


Pad Pad Pad Pad
AF31 PL20B PL26B I/O N28 PL8A PL10A I/O
AD28 PL20C PL26C I/O M29 PL8C PL10C I/O
AE29 PL20D PL26D I/O L31 PL8D PL10D I/O
AE30 PL19A PL25A I/O L30 PL7A PL9A I/O-A3
AE31 PL19B PL25B I/O M28 PL7B PL9B I/O
AC28 PL19C PL25C I/O L29 PL7C PL9C I/O
AD29 PL19D PL24A I/O-A14 K31 PL7D PL9D I/O
AD30 PL18A PL24D I/O K30 PL6A PL8A I/O-A2
AC29 PL18B PL23D I/O K29 PL6B PL8B I/O
AB28 PL18C PL22C I/O J31 PL6C PL8C I/O
AC30 PL18D PL22D I/O J30 PL6D PL8D I/O
AC31 PL17A PL21A I/O K28 PL5A PL7D I/O-A1/MPI_BE1
AB29 PL17B PL21B I/O-A13 J29 PL5B PL6B I/O
AB30 PL17C PL21C I/O H30 PL5C PL6C I/O
AB31 PL17D PL21D I/O H29 PL5D PL6D I/O
AA29 PL16A PL20A I/O J28 PL4A PL5D I/O
Y28 PL16B PL20B I/O G31 PL4B PL4B I/O
AA30 PL16C PL20C I/O G30 PL4C PL4C I/O
AA31 PL16D PL20D I/O-A12 G29 PL4D PL4D I/O
Y29 PL15A PL19A I/O-A11/MPI_IRQ H28 PL3A PL3A I/O
W28 PL15B PL19D I/O F31 PL3B PL3B I/O
Y30 PL15C PL18A I/O F30 PL3C PL3C I/O
W29 PL14A PL18C I/O F29 PL3D PL3D I/O
W30 PL14B PL18D I/O E31 PL2A PL2A I/O
V28 PL14C PL17A I/O-A10/MPI_BI E30 PL2B PL2B I/O
W31 PL14D PL17C I/O E29 PL2C PL2C I/O
V29 PL13A PL17D I/O F28 PL2D PL2D I/O-A0/MPI_BE0
V30 PL13B PL16A I/O D31 PL1A PL1A I/O
V31 PL13C PL16C I/O D30 PL1B PL1B I/O
U29 PL13D PL16D I/O-A9/MPI_ACK D29 PL1C PL1C I/O
U30 PL12A PL15A I/O-A8/MPI_RW E28 PL1D PL1D I/O
U31 PL12B PL15B I/O D27 PRD_DATA PRD_DATA RD_DATA/TDO
T30 PL12C PL15C I/O C28 PT1A PT1A I/O-TCK
T28 PL12D PL15D I/O B28 PT1B PT1B I/O
T29 PL11A PL14A I/O-A7/MPI_CLK A28 PT1C PT1C I/O
R31 PL11B PL14B I/O D26 PT1D PT1D I/O
R30 PL11C PL14C I/O C27 PT2A PT2A I/O
R29 PECKL PECKL I-ECKL B27 PT2B PT2B I/O
P31 PL10A PL13A I/O-A6 A27 PT2C PT2C I/O
P30 PL10B PL13D I/O C26 PT2D PT2D I/O
P29 PL10C PL12A I/O B26 PT3A PT3A I/O
N31 PL10D PL12C I/O A26 PT3B PT3B I/O
P28 PL9A PL12D I/O-A5 D24 PT3C PT3C I/O
N30 PL9B PL11A I/O-A4 C25 PT3D PT3D I/O
N29 PL9C PL11C I/O B25 PT4A PT4A I/O-TMS
M30 PL9D PL11D I/O A25 PT4B PT4B I/O
Data Sheet


Pad Pad Pad Pad
D23 PT4C PT4C I/O C11 PT16C PT21A I/O
C24 PT4D PT4D I/O A10 PT16D PT21D I/O
B24 PT5A PT5A I/O B10 PT17A PT22D I/O
C23 PT5B PT5B I/O C10 PT17B PT23B I/O
D22 PT5C PT5C I/O A9 PT17C PT23C I/O
B23 PT5D PT5D I/O B9 PT17D PT23D I/O
A23 PT6A PT6A I/O-TDI D10 PT18A PT24A I/O
C22 PT6B PT6D I/O C9 PT18B PT24B I/O
B22 PT6C PT7A I/O B8 PT18C PT24C I/O
A22 PT6D PT7D I/O C8 PT18D PT24D I/O-D7
C21 PT7A PT8A I/O D9 PT19A PT25A I/O
D20 PT7B PT8D I/O A7 PT19B PT25B I/O
B21 PT7C PT9A I/O B7 PT19C PT25C I/O
A21 PT7D PT9D I/O C7 PT19D PT25D I/O
C20 PT8A PT10A I/O-DOUT D8 PT20A PT26A I/O
D19 PT8C PT10D I/O A6 PT20B PT26B I/O
B20 PT8D PT11A I/O B6 PT20C PT26C I/O
C19 PT9A PT11C I/O C6 PT20D PT26D I/O
B19 PT9B PT11D I/O A5 PT21A PT27A I/O-RDY/RCLK/MPI_ALE
D18 PT9C PT12A I/O-D0/DIN B5 PT21B PT27B I/O
A19 PT9D PT12C I/O C5 PT21C PT27C I/O
C18 PT10A PT12D I/O D6 PT21D PT27D I/O
B18 PT10B PT13A I/O A4 PT22A PT28A I/O
A18 PT10C PT13C I/O B4 PT22B PT28B I/O
C17 PT10D PT13D I/O-D1 C4 PT22C PT28C I/O
B17 PT11A PT14A I/O-D2 D5 PT22D PT28D I/O-SECKUR
A17 PT11B PT14B I/O A12 VSS VSS VSS
B16 PT11C PT14C I/O A16 VSS VSS VSS
D16 PT11D PT14D I/O A2 VSS VSS VSS
C16 PT12A PT15A I/O-D3 A20 VSS VSS VSS
A15 PT12B PT15B I/O A24 VSS VSS VSS
B15 PT12C PT15C I/O A29 VSS VSS VSS
C15 PECKT PECKT I-ECKT A3 VSS VSS VSS
A14 PT13A PT16A I/O-D4 A30 VSS VSS VSS
B14 PT13B PT16B I/O A8 VSS VSS VSS
C14 PT13C PT16D I/O AD1 VSS VSS VSS
A13 PT13D PT17A I/O AD31 VSS VSS VSS
D14 PT14A PT17B I/O AJ1 VSS VSS VSS
B13 PT14B PT17D I/O AJ2 VSS VSS VSS
C13 PT14C PT18A I/O-D5 AJ30 VSS VSS VSS
B12 PT14D PT18B I/O AJ31 VSS VSS VSS
D13 PT15A PT18D I/O AK1 VSS VSS VSS
C12 PT15B PT19A I/O AK29 VSS VSS VSS
A11 PT15D PT19D I/O AK3 VSS VSS VSS
B11 PT16A PT20A I/O AK31 VSS VSS VSS
D12 PT16B PT20D I/O-D6 AL12 VSS VSS VSS

Data Sheet


Pad Pad Pad Pad
AL16 VSS VSS VSS AH17 VDD VDD VDD
AL30 VSS VSS VSS AJ29 VDD VDD VDD
AL8 VSS VSS VSS AJ3 VDD VDD VDD
B1 VSS VSS VSS AK2 VDD VDD VDD
B29 VSS VSS VSS AK30 VDD VDD VDD
B3 VSS VSS VSS AL1 VDD VDD VDD
B31 VSS VSS VSS AL31 VDD VDD VDD
C1 VSS VSS VSS B2 VDD VDD VDD
C2 VSS VSS VSS B30 VDD VDD VDD
C30 VSS VSS VSS C29 VDD VDD VDD
C31 VSS VSS VSS C3 VDD VDD VDD
H1 VSS VSS VSS D11 VDD VDD VDD
H31 VSS VSS VSS D15 VDD VDD VDD
M1 VSS VSS VSS D17 VDD VDD VDD
M31 VSS VSS VSS D21 VDD VDD VDD
T1 VSS VSS VSS D25 VDD VDD VDD
T31 VSS VSS VSS D28 VDD VDD VDD
Y1 VSS VSS VSS D4 VDD VDD VDD
Y31 VSS VSS VSS D7 VDD VDD VDD
A1 VDD VDD VDD G28 VDD VDD VDD
A31 VDD VDD VDD G4 VDD VDD VDD
AA28 VDD VDD VDD L28 VDD VDD VDD
AA4 VDD VDD VDD L4 VDD VDD VDD
AE28 VDD VDD VDD R28 VDD VDD VDD
AE4 VDD VDD VDD R4 VDD VDD VDD
AH11 VDD VDD VDD U28 VDD VDD VDD
AH15 VDD VDD VDD U4 VDD VDD VDD

Data Sheet

Table 75. OR3T125 600-Pin EBGA Pinout
OR3T125 OR3T125
Pad Pad
E4 PRD_CFGN RD_CFG R2 PR12C I/O
E3 PR1D I/O R1 PR12B I/O
E2 PR1C I/O T4 PR12A I/O
F5 PR1B I/O T3 PR13D I/O
F4 PR1A I/O T2 PR13C I/O
F3 PR2D I/O U2 PR13B I/O
F2 PR2C I/O U4 PR13A I/O
G5 PR2B I/O U5 PR14D I/O
G4 PR2A I/O U3 PR14C I/O
G3 PR3D I/O U1 PR14B I/O
G2 PR3C I/O V2 PECKR I-ECKR
H5 PR3B I/O V4 PR15D I/O
H4 PR3A I/O-WR V5 PR15C I/O
H3 PR4D I/O V3 PR15B I/O
H2 PR4C I/O W2 PR15A I/O
J5 PR4B I/O W3 PR16D I/O
J4 PR4A I/O W4 PR16C I/O
J3 PR5D I/O W5 PR16B I/O
J2 PR5C I/O Y2 PR16A I/O
J1 PR5B I/O Y3 PR17D I/O
K5 PR5A I/O Y4 PR17C I/O
K4 PR6D I/O AA1 PR17B I/O
K3 PR6C I/O AA2 PR17A I/O-M3
K2 PR6B I/O AA3 PR18D I/O
K1 PR6A I/O AA4 PR18C I/O
L4 PR7D I/O AA5 PR18B I/O
L3 PR7C I/O AB1 PR18A I/O
L2 PR7B I/O AB2 PR19D I/O
L1 PR7A I/O-RD/MPI_STRB AB3 PR19C I/O
M5 PR8D I/O AB4 PR19B I/O
M4 PR8C I/O AB5 PR19A I/O-M2
M3 PR8B I/O AC2 PR20D I/O
M2 PR8A I/O AC3 PR20C I/O
M1 PR9D I/O AC4 PR20B I/O
N5 PR9C I/O AC5 PR20A I/O
N4 PR9B I/O AD1 PR21D I/O
N3 PR9A I/O-CS0 AD2 PR21C I/O
N2 PR10D I/O AD3 PR21B I/O
P4 PR10C I/O AD4 PR21A I/O
P5 PR10B I/O AD5 PR22D I/O-M1
P3 PR10A I/O AE1 PR22C I/O
P2 PR11D I/O AE2 PR22B I/O
P1 PR11C I/O AE3 PR22A I/O
R4 PR11B I/O AE4 PR23D I/O
R5 PR11A I/O-CS1 AF1 PR23C I/O
R3 PR12D I/O AF2 PR23B I/O

Data Sheet

Table 75. OR3T125 600-Pin EBGA Pinout (continued)
OR3T125 OR3T125
Pad Pad
AF3 PR23A I/O AP10 PB23C I/O
AF4 PR24D I/O AR10 PB23B I/O
AF5 PR24C I/O AM11 PB23A I/O
AG1 PR24B I/O AN11 PB22D I/O
AG2 PR24A I/O AP11 PB22C I/O
AG3 PR25D I/O AR11 PB22B I/O
AG4 PR25C I/O AL12 PB22A I/O
AG5 PR25B I/O AM12 PB21D I/O
AH2 PR25A I/O AN12 PB21C I/O
AH3 PR26D I/O AP12 PB21B I/O
AH4 PR26C I/O AR12 PB21A I/O
AH5 PR26B I/O AL13 PB20D I/O
AJ2 PR26A I/O AM13 PB20C I/O
AJ3 PR27D I/O AN13 PB20B I/O
AJ4 PR27C I/O AP13 PB20A I/O-LDC
AJ5 PR27B I/O AM14 PB19D I/O
AK2 PR27A I/O AL14 PB19C I/O
AK3 PR28D I/O AN14 PB19B I/O
AK4 PR28C I/O AP14 PB19A I/O
AK5 PR28B I/O AR14 PB18D I/O
AL2 PR28A I/O-M0 AM15 PB18C I/O
AL3 PPRGMN PRGM AL15 PB18B I/O
AL4 PRESETN RESET AN15 PB18A I/O-HDC
AM5 PDONE DONE AP15 PB17D I/O
AN5 PB28D I/O AR15 PB17C I/O
AP5 PB28C I/O AM16 PB17B I/O
AL6 — I/O AN16 PB17A I/O
AM6 PB28B I/O AP16 PB16D I/O
AN6 PB28A I/O AP17 PB16C I/O
AP6 PB27D I/O AM17 PB16B I/O
AL7 PB27C I/O AL17 PB16A I/O
AM7 PB27B I/O AN17 PB15D I/O
AN7 PB27A I/O AR17 PB15C I/O
AP7 PB26D I/O AP18 PB15B I/O
AL8 PB26C I/O AM18 PECKB I-ECKB
AM8 PB26B I/O AL18 PB14D I/O
AN8 PB26A I/O AN18 PB14C I/O
AL9 PB25C I/O AN19 PB14A I/O
AM9 PB25B I/O AM19 PB13D I/O
AN9 PB25A I/O AL19 PB13C I/O
AR9 PB24C I/O AN20 PB13A I/O
AL10 PB24B I/O AM20 PB12D I/O
AM10 PB24A I/O-INIT AR21 PB12C I/O
AN10 PB23D I/O AP21 PB12B I/O
Data Sheet

OR3T125 OR3T125
Pad Pad
AN21 PB12A I/O AL32 PCCLK CCLK
AM21 PB11D I/O AL33 PL28A I/O-A15
AL21 PB11C I/O AL34 PL28B I/O
AR22 PB11B I/O AK31 PL28C I/O
AP22 PB11A I/O AK32 PL28D I/O
AN22 PB10D I/O AK33 — I/O
AM22 PB10C I/O AK34 PL27A I/O-SECKLL
AL22 PB10B I/O AJ31 PL27B I/O
AP23 PB10A I/O AJ32 PL27C I/O
AN23 PB9D I/O AJ33 PL27D I/O
AM23 PB9C I/O AJ34 PL26A I/O
AL23 PB9B I/O AH31 PL26B I/O
AR24 PB9A I/O AH32 PL26C I/O
AP24 PB8D I/O AH33 PL26D I/O
AN24 PB8C I/O AH34 PL25A I/O
AM24 PB8B I/O AG31 PL25B I/O
AL24 PB8A I/O AG32 PL25C I/O
AR25 PB7D I/O AG33 PL25D I/O
AP25 PB7C I/O AG34 PL24A I/O-A14
AN25 PB7B I/O AG35 PL24B I/O
AM25 PB7A I/O AF31 PL24C I/O
AR26 PB6D I/O AF32 PL24D I/O
AP26 PB6C I/O AF33 PL23A I/O
AN26 PB6B I/O AF34 PL23B I/O
AM26 PB6A I/O AF35 PL23C I/O
AL26 PB5D I/O AE32 PL23D I/O
AR27 PB5C I/O AE33 PL22A I/O
AP27 PB5B I/O AE34 PL22B I/O
AN27 PB5A I/O AE35 PL22C I/O
AM27 PB4D I/O-A17 AD31 PL22D I/O
AL27 PB4C I/O AD32 PL21A I/O
AP28 PB4B I/O AD33 PL21B I/O-A13
AN28 PB4A I/O AD34 PL21C I/O
AM28 PB3D I/O AD35 PL21D I/O
AL28 PB3C I/O AC31 PL20A I/O
AP29 PB3B I/O AC32 PL20B I/O
AN29 PB3A I/O AC33 PL20C I/O
AM29 PB2D I/O AC34 PL20D I/O-A12
AL29 PB2C I/O AB32 PL19A I/O-A11/MPI_IRQ
AP30 PB2B I/O AB31 PL19B I/O
AN30 PB2A I/O AB33 PL19C I/O
AM30 PB1D I/O AB34 PL19D I/O
AL30 PB1C I/O AB35 PL18A I/O
AP31 — I/O AA32 PL18B I/O
AN31 PB1B I/O AA31 PL18C I/O
AM31 PB1A I/O-A16 AA33 PL18D I/O

Data Sheet

OR3T125 OR3T125
Pad Pad
AA34 PL17A I/O-A10/MPI_BI K33 PL6C I/O
AA35 PL17B I/O K32 PL6D I/O
Y32 PL17C I/O K31 PL5A I/O
Y33 PL17D I/O J35 PL5B I/O
Y34 PL16A I/O J34 PL5C I/O
W34 PL16B I/O J33 PL5D I/O
W32 PL16C I/O J32 PL4A I/O
W31 PL16D I/O-A9/MPI_ACK J31 PL4B I/O
W33 PL15A I/O-A8/MPI_RW H34 PL4C I/O
W35 PL15B I/O H33 PL4D I/O
V34 PL15C I/O H32 PL3A I/O
V32 PL15D I/O H31 PL3B I/O
V31 PL14A I/O-A7/MPI_CLK G34 PL3C I/O
V33 PL14B I/O G33 PL3D I/O
U34 PL14C I/O G32 PL2A I/O
U33 PECKL I-ECKL G31 PL2B I/O
U32 PL13A I/O-A6 F34 PL2C I/O
U31 PL13B I/O F33 PL2D I/O-A0/MPI_BE0
T34 PL13C I/O F32 PL1A I/O
T33 PL13D I/O F31 PL1B I/O
T32 PL12A I/O E34 PL1C I/O
R35 PL12B I/O E33 — I/O
R34 PL12C I/O E32 PL1D I/O
R33 PL12D I/O-A5 D31 PRD_DATA RD_DATA/TDO
R32 PL11A I/O-A4 C31 PT1A I/O-TCK
R31 PL11B I/O B31 — I/O
P35 PL11C I/O E30 PT1B I/O
P34 PL11D I/O D30 PT1C I/O
P33 PL10A I/O C30 PT1D I/O
P32 PL10B I/O B30 PT2A I/O
P31 PL10C I/O E29 PT2B I/O
N34 PL10D I/O D29 PT2C I/O
N33 PL9A I/O-A3 C29 PT2D I/O
N32 PL9B I/O B29 PT3A I/O
N31 PL9C I/O E28 PT3B I/O
M35 PL9D I/O D28 PT3C I/O
M34 PL8A I/O-A2 C28 PT3D I/O
M33 PL8B I/O B28 PT4A I/O-TMS
M32 PL8C I/O E27 PT4B I/O
M31 PL8D I/O D27 PT4C I/O
L35 PL7A I/O C27 PT4D I/O
L34 PL7B I/O B27 PT5A I/O
L33 PL7C I/O A27 PT5B I/O
L32 PL7D I/O-A1/MPI_BE1 E26 PT5C I/O
K35 PL6A I/O D26 PT5D I/O
K34 PL6B I/O C26 PT6A I/O-TDI

Data Sheet

OR3T125 OR3T125
Pad Pad
B26 PT6B I/O C15 PT17D I/O
A26 PT6C I/O D15 PT18A I/O-D5
D25 PT6D I/O E15 PT18B I/O
C25 PT7A I/O A14 PT18C I/O
B25 PT7B I/O B14 PT18D I/O
A25 PT7C I/O C14 PT19A I/O
E24 PT7D I/O D14 PT19B I/O
D24 PT8A I/O E14 PT19C I/O
C24 PT8B I/O B13 PT19D I/O
B24 PT8C I/O C13 PT20A I/O
A24 PT8D I/O D13 PT20B I/O
E23 PT9A I/O E13 PT20C I/O
D23 PT9B I/O A12 PT20D I/O-D6
C23 PT9C I/O B12 PT21A I/O
B23 PT9D I/O C12 PT21B I/O
D22 PT10A I/O-DOUT D12 PT21C I/O
E22 PT10B I/O E12 PT21D I/O
C22 PT10C I/O A11 PT22A I/O
B22 PT10D I/O B11 PT22B I/O
A22 PT11A I/O C11 PT22C I/O
D21 PT11B I/O D11 PT22D I/O
E21 PT11C I/O A10 PT23A I/O
C21 PT11D I/O B10 PT23B I/O
B21 PT12A I/O-D0/DIN C10 PT23C I/O
A21 PT12B I/O D10 PT23D I/O
D20 PT12C I/O E10 PT24A I/O
C20 PT12D I/O A9 PT24B I/O
B20 PT13A I/O B9 PT24C I/O
B19 PT13B I/O C9 PT24D I/O-D7
D19 PT13C I/O D9 PT25A I/O
E19 PT13D I/O-D1 E9 PT25B I/O
C19 PT14A I/O-D2 B8 PT25C I/O
A19 PT14B I/O C8 PT25D I/O
B18 PT14C I/O D8 PT26A I/O
D18 PT14D I/O E8 PT26B I/O
E18 PT15A I/O-D3 B7 PT26C I/O
C18 PT15B I/O C7 PT26D I/O
B17 PT15C I/O D7 PT27A I/O-RDY/RCLK/MPI_ALE
C17 PECKT I-ECKT E7 PT27B I/O
D17 PT16A I/O-D4 B6 PT27C I/O
E17 PT16B I/O C6 PT27D I/O
B16 PT16C I/O D6 PT28A I/O
C16 PT16D I/O E6 PT28B I/O
D16 PT17A I/O B5 PT28C I/O
A15 PT17B I/O C5 — I/O
B15 PT17C I/O D5 PT28D I/O-SECKUR

Data Sheet

OR3T125 OR3T125
Pad Pad
A13 VSS VSS B3 VSS VSS
A28 VSS VSS C1 VSS VSS
A7 VSS VSS D1 VSS VSS
A8 VSS VSS D2 VSS VSS
AC1 VSS VSS D3 VSS VSS
AC35 VSS VSS D33 VSS VSS
AH1 VSS VSS D34 VSS VSS
AH35 VSS VSS D35 VSS VSS
AJ1 VSS VSS G1 VSS VSS
AJ35 VSS VSS G35 VSS VSS
AM1 VSS VSS H1 VSS VSS
AM2 VSS VSS H35 VSS VSS
AM3 VSS VSS N1 VSS VSS
AM33 VSS VSS N35 VSS VSS
AM34 VSS VSS T1 VSS VSS
AM35 VSS VSS T35 VSS VSS
AN1 VSS VSS Y1 VSS VSS
AN2 VSS VSS Y35 VSS VSS
AN32 VSS VSS A1 VDD VDD
AP3 VSS VSS A30 VDD VDD
AR13 VSS VSS A5 VDD VDD
AR16 VSS VSS A6 VDD VDD
AR20 VSS VSS AE31 VDD VDD
AR23 VSS VSS AE5 VDD VDD
AR28 VSS VSS AK1 VDD VDD
AR29 VSS VSS AK35 VDD VDD
AR3 VSS VSS AL1 VDD VDD

Data Sheet

OR3T125 OR3T125
Pad Pad
AL35 VDD VDD C3 VDD VDD
AL5 VDD VDD C33 VDD VDD
AM32 VDD VDD D32 VDD VDD
AM4 VDD VDD D4 VDD VDD
AN3 VDD VDD E1 VDD VDD
AN33 VDD VDD E11 VDD VDD
AP1 VDD VDD E16 VDD VDD
AR1 VDD VDD E35 VDD VDD
AR18 VDD VDD E5 VDD VDD
AR19 VDD VDD F1 VDD VDD
AR2 VDD VDD F35 VDD VDD
AR30 VDD VDD L31 VDD VDD
AR31 VDD VDD L5 VDD VDD
AR34 VDD VDD T31 VDD VDD
AR35 VDD VDD T5 VDD VDD
AR5 VDD VDD U35 VDD VDD
AR6 VDD VDD V1 VDD VDD
B1 VDD VDD V35 VDD VDD
B2 VDD VDD W1 VDD VDD
B34 VDD VDD Y31 VDD VDD
B35 VDD VDD Y5 VDD VDD

Data Sheet
Package Thermal Characteristics ψJC
There are four thermal parameters that are in common This JEDEC designated parameter correlates the junc-
use: ΘJA, ψJC, ΘJC, and ΘJB. It should be noted that all tion temperature to the case temperature. It is generally
the parameters are affected, to varying degrees, by used to infer the junction temperature while the device
package design (including paddle size) and choice of is operating in the system. It is not considered a true
materials, the amount of copper in the test board or thermal resistance, and it is defined by:
system board, and system airflow.
TJ – TC
ψ JC = -------------------
Table 76 contains the currently available thermal speci- -
Q
fications for FPGA packages mounted on both JEDEC
and non-JEDEC test boards. The thermal values for the where TC is the case temperature at top dead center,
newer package types correspond to those packages TJ is the junction temperature, and Q is the chip power.
mounted on a JEDEC four-layer board. The values for During the ΘJA measurements described above,
the older packages, however, correspond to those besides the other parameters measured, an additional
packages mounted on a non-JEDEC, single-layer, temperature reading, TC, is made with a thermocouple
sparse copper board (see Note 2). It should also be attached at top-dead-center of the case. ψJC is also
noted that the values for the older packages are con- expressed in units of °C/watt.
sidered conservative.
ΘJC
ΘJA
This is the thermal resistance from junction to case. It
This is the thermal resistance from junction to ambient is most often used when attaching a heat sink to the
(a.k.a. theta-JA, R-theta, etc.). top of the package. It is defined by:
TJ – TA TJ – TC
Θ JA = -------------------
- Θ JC = -------------------
-
Q Q
where TJ is the junction temperature, TA is the ambient The parameters in this equation have been defined
air temperature, and Q is the chip power. above. However, the measurements are performed
Experimentally, ΘJA is determined when a special ther- with the case of the part pressed against a water-
mal test die is assembled into the package of interest, cooled heat sink so as to draw most of the heat gener-
and the part is mounted on the thermal test board. The ated by the chip out the top of the package. It is this dif-
diodes on the test chip are separately calibrated in an ference in the measurement process that differentiates
oven. The package/board is placed either in a JEDEC ΘJC from ψJC. ΘJC is a true thermal resistance and is
natural convection box or in the wind tunnel, the latter expressed in units of °C/watt.
for forced convection measurements. A controlled
amount of power (Q) is dissipated in the test chip’s
heater resistor, the chip’s temperature (TJ) is deter- ΘJB
mined by the forward drop on the diodes, and the ambi-
This is the thermal resistance from junction to board
ent temperature (TA) is noted. Note that ΘJA is
(a.k.a. ΘJL). It is defined by:
expressed in units of °C/watt.
TJ – TB
Θ JB = -------------------
-
Q
where TB is the temperature of the board adjacent to a
lead measured with a thermocouple. The other param-
eters on the right-hand side have been defined above.
This is considered a true thermal resistance, and the
measurement is made with a water-cooled heat sink
pressed against the board so as to draw most of the
heat out of the leads. Note that ΘJB is expressed in
units of °C/watt, and that this parameter and the way it
is measured is still in JEDEC committee.

Data Sheet
Package Thermal Characteristics (continued)
FPGA Maximum Junction Temperature

Once the power dissipated by the FPGA has been determined (see the Estimating Power Dissipation section), the
maximum junction temperature of the FPGA can be found. This is needed to determine if speed derating of the
device from the 85 °C junction temperature used in all of the delay tables is needed. Using the maximum ambient
temperature, TAmax, and the power dissipated by the device, Q (expressed in °C), the maximum junction tempera-
ture is approximated by:
TJmax = TAmax + (Q • ΘJA)
Table 76 lists the plastic package thermal characteristics for the ORCA Series FPGAs.
Table 76. Plastic Package Thermal Characteristics for the ORCA Series1
ΘJA (°C/W) TA = 70 °C max
Package 0 fpm 200 fpm 500 fpm TJ = 125 °C max
@ 0 fpm (W)
208-Pin SQFP1 26.5 23.0 21.0 2.1
208-Pin SQFP21 12.8 10.3 9.1 4.3
240-Pin SQFP1 25.5 22.5 21.0 2.2
240-Pin SQFP21 13.0 10.0 9.0 4.2
256-Pin PBGA1, 2 22.5 19.0 17.5 2.4
256-Pin PBGA1, 3 26.0 22.0 20.5 2.1
352-Pin PBGA1, 2 19.0 16.0 15.0 2.9
352-Pin PBGA1, 3 25.5 22.0 20.5 2.1
432-Pin EBGA1 11.0 8.5 7.5 5.0
600-Pin EBGA1 11.0 8.5 7.5 5.5
1. Mounted on 4-layer JEDEC standard test board with two power/ground planes.
2. With thermal balls connected to board ground plane.
3. Without thermal balls connected to board ground plane.

Data Sheet
Package Coplanarity represent the contributions of all components of a

package, which include the bond wires, all internal
The coplanarity limits of the ORCA Series 3 packages package routing, and the external leads.
are as follows. Four inductances in nH are listed: LSW and LSL, the
self-inductance of the lead; and LMW and LML, the
Table 77. Package Coplanarity mutual inductance to the nearest neighbor lead. These
parameters are important in determining ground
Coplanarity Limit
Package Type bounce noise and inductive crosstalk noise. Three
(mils)
capacitances in pF are listed: CM, the mutual capaci-
EBGA 8.0 tance of the lead to the nearest neighbor lead; and C1
PBGA 8.0 and C2, the total capacitance of the lead to all other
SQFP/SQFP2 4.0 leads (all other leads are assumed to be grounded).
3.15 These parameters are important in determining capaci-
tive crosstalk and the capacitive loading effect of the
lead. The lead resistance value, RW, is in MΩ.
Package Parasitics The parasitic values in Table 78 are for the circuit
model of bond wire and package lead parasitics. If the
The electrical performance of an IC package, such as mutual capacitance value is not used in the designer’s
signal quality and noise sensitivity, is directly affected model, then the value listed as mutual capacitance
by the package parasitics. Table 78 lists eight parasitics should be added to each of the C1 and C2 capacitors.
associated with the ORCA packages. These parasitics
Table 78. Package Parasitics
Package Type LSW LMW RW C1 C2 CM LSL LML

208-Pin SQFP 4 2 200 1 1 1 7—10 4—6
208-Pin SQFP2 4 2 200 1 1 1 6—9 4—6
240-Pin SQFP 4 2 200 1 1 1 8—12 5—8
240-Pin SQFP2 4 2 200 1 1 1 7—11 4—7
256-Pin PBGA 5 2 220 1 1 1 5—8 2—4
352-Pin PBGA 5 2 220 1.5 1.5 1.5 7—12 3—6
432-Pin EBGA 4 1.5 500 1 1 0.3 3—5.5 0.5—1
600-Pin EBGA 4 1.5 500 1 1 0.4 3—6 0.5—1
LSW RW LSL BOARD PAD

PAD N
C1 C2
LMW CM LML
PAD N + 1
LSW RW LSL
C1 C2
5-3862(F).a
Figure 104. Package Parasitics

Data Sheet
Package Outline Diagrams
Terms and Definitions

Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived
by the application of the allowance and the tolerance.
Design Size: The design size of a dimension is the actual size of the design, including an allowance for fit
and tolerance.
Typical (TYP): When specified after a dimension, this indicates the repeated design size if a tolerance is
specified or repeated basic size if a tolerance is not specified.
Reference (REF): The reference dimension is an untoleranced dimension used for informational purposes only.
It is a repeated dimension or one that can be derived from other values in the drawing.
Minimum (MIN) or
Maximum (MAX): Indicates the minimum or maximum allowable size of a dimension.

Data Sheet
Package Outline Diagrams (continued)
208-Pin SQFP
Dimensions are in millimeters.
30.60 ± 0.20
1.30 REF
28.00 ± 0.20
PIN #1 IDENTIFIER ZONE

208 157
0.25
1 156 GAGE PLANE
SEATING PLANE
0.50/0.75
DETAIL A
28.00
± 0.20
30.60
± 0.20
0.090/0.200
0.17/0.27
52 105 0.10 M
DETAIL B
53 104
DETAIL A DETAIL B
3.40 ± 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TYP 0.25 MIN
Note: The dimensions in this outline diagram are intended for informational purposes only.

Data Sheet
208-Pin SQFP2
30.60 ± 0.20
28.00 ± 0.20
21.0 REF
PIN #1 IDENTIFIER ZONE 1.30 REF

208 157
156
0.25
GAGE PLANE
SEATING PLANE
21.0 0.50/0.75
REF
28.00
± 0.20 DETAIL A
30.60
± 0.20
0.090/0.200
0.17/0.2
105 0.10 M
53 104 DETAIL B
EXPOSED HEAT SINK APPEARS ON BOTTOM
SURFACE: CHIP BONDED FACE UP. (SEE DETAIL C.)
DETAIL A DETAIL B
3.40 ± 0.20
4.10 MAX
SEATING PLANE
0.08 5-3828(F)
0.50 TYP
0.25 MIN
CHIP BONDED FACE UP
CHIP
COPPER HEAT SINK
DETAIL C (SQFP2 CHIP-UP)

5-3828(F).a

Data Sheet
240-Pin SQFP
34.60 ± 0.20
32.00 ± 0.20
PIN #1 IDENTIFIER ZONE 1.30 REF

240 181
1 180
0.25
GAGE PLANE
SEATING PLANE
0.50/0.75
DETAIL A
32.00
± 0.20
34.60
± 0.20
0.090/0.200
0.17/0.27
0.10 M
DETAIL B
60 121
61 120
DETAIL A DETAIL B
3.40 ± 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TYP
0.25 MIN
Note: The dimensions in this outline diagram are intended for informational purposes only.

Data Sheet
240-Pin SQFP2
34.60 ± 0.20
32.00 ± 0.20
24.2 REF
1.30 REF
PIN #1 IDENTIFIER ZONE
240 181
1 180
0.25
GAGE PLANE
SEATING PLANE
0.50/0.75
24.2
DETAIL A
REF
32.00
± 0.20
34.60
± 0.20
0.090/0.200
0.17/0.27
0.10 M
DETAIL B
60 121
61 120
EXPOSED HEAT SINK APPEARS ON BOTTOM
SURFACE: CHIP BONDED FACE UP. (SEE DETAIL C.)
DETAIL A DETAIL B
3.40 ± 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TYP
0.25 MIN
CHIP BONDED FACE UP
CHIP
COPPER HEAT SINK
DETAIL C (SQFP2 CHIP-UP)

5-3825(F).a

Data Sheet
256-Pin PBGA
27.00 ± 0.20
+0.70
A1 BALL 24.00 –0.00
IDENTIFIER ZONE
+0.70
24.00
–0.00
27.00
± 0.20
MOLD
COMPOUND
PWB
0.36 ± 0.04 1.17 ± 0.05 2.13 ± 0.19
SEATING PLANE
0.20
SOLDER BALL
0.60 ± 0.10
19 SPACES @ 1.27 = 24.13
Y
W
V
U
T
R 0.75 ± 0.15
P
N
M
L 19 SPACES
K @ 1.27 = 24.13
J
H
G
F
CENTER ARRAY E
FOR THERMAL D
ENHANCEMENT
C
(OPTIONAL)
(SEE NOTE BELOW) B
A
A1 BALL 1 2 3 4 5 6 7 8 9 10 12 14 16 18 20
11 13 15 17 19
CORNER
5-4406(F)
Note: Although the 16 thermal enhancement balls are stated as an option, they are standard on the 256 FPGA package.

Data Sheet
352-Pin PBGA
35.00 ± 0.20
+0.70
30.00 –0.00
A1 BALL
IDENTIFIER ZONE
+0.70
30.00
–0.00
35.00
± 0.20
MOLD
COMPOUND
PWB
0.56 ± 0.06 1.17 ± 0.05

2.33 ± 0.21
SEATING PLANE
0.20
0.60 ± 0.10 SOLDER BALL
25 SPACES @ 1.27 = 31.75
AF
AE
AD
AC
AB
AA
Y 0.75 ± 0.15
W
V
U
T
R
P 25 SPACES
N @ 1.27 = 31.75
M
L
K
J
H
CENTER ARRAY G
FOR THERMAL F
ENHANCEMENT E
(OPTIONAL) D
C
(SEE NOTE BELOW) B
A
A1 BALL 1 2 3 4 5 6 7 8 9 10 12 14 16 18 20 22 24 26
11 13 15 17 19 21 23 25
CORNER
5-4407(F)
Note: Although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 FPGA package.

Data Sheet
432-Pin EBGA
40.00 ± 0.10
A1 BALL
IDENTIFIER ZONE
40.00
± 0.10
0.91 ± 0.06
1.54 ± 0.13
SEATING PLANE
0.20
SOLDER BALL
0.63 ± 0.07
30 SPACES @ 1.27 = 38.10
AL
AK
AJ
AH
AG
AF
AE
AD
AC 0.75 ± 0.15
AB
AA
Y
W
V
U
T 30 SPACES
R @ 1.27 = 38.10
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
A1 BALL
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
CORNER
5-4409(F)

Data Sheet
600-Pin EBGA
45.00 ± 0.10
A1 BALL
IDENTIFIER ZONE
45.00
± 0.10
0.91 ± 0.06
1.54 ± 0.13
SEATING PLANE
0.20
SOLDER BALL
0.63 ± 0.07
34 SPACES @ 1.27 = 43.18
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF 0.75 ± 0.15
AE
AD
AC
AB
AA
Y
V
W 34 SPACES
U @ 1.27 = 43.18
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
A1 BALL 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
CORNER
5-4408(F)

Data Sheet
Ordering Information
OR3XXXX X XX XXX X XX
Device Family Packing Designator

OR3T20 DB = Dry Packed Tray
OR3T30
OR3T55 Grade
OR3T20 Blank = Commercial
OR3C80 I = Industrial
OR3T80 Pin/Ball Count
OR3T125
Speed Grade Package Type
BA = Plastic Ball Grid Array (PBGA)
BC = Enhanced Ball Grid Array (EBGA)
PS = Power Quad Shrink Flat Package (SQFP2)
S = Shrink Quad Flat Package (SQFP)
Table 79. Ordering Information

Commercial
Speed Package Pin/Ball Packing
Device Family Part Number Grade
Grade Type Count Designator
OR3C80 OR3C805PS208-DB 5 SQFP2 208 C DB
OR3C805PS240-DB 5 SQFP2 240 C DB
OR3C805BA352-DB 5 PBGA 352 C DB
OR3C804BA352-DB 4 PBGA 352 C DB
OR3T20 OR3T207S208-DB 7 SQFP 208 C DB
OR3T207S240-DB 7 SQFP 240 C DB
OR3T207BA256-DB 7 PBGA 256 C DB
OR3T30 OR3T307S208-DB 7 SQFP 208 C DB

Data Sheet
Commercial
OR3T55 OR3T557PS208-DB 7 SQFP2 208 C DB
OR3T557PS240-DB 7 SQFP2 240 C DB
OR3T807BC432-DB 7 EBGA 432 C DB

Data Sheet
Industrial

OR3C80 OR3C804PS208I-DB 4 SQFP2 208 I DB
OR3C804PS240I-DB 4 SQFP2 240 I DB
OR3C804BA352I-DB 4 PBGA 352 I DB
OR3T20 OR3T206S208I-DB 6 SQFP 208 I DB
OR3T206S240I-DB 6 SQFP 240 I DB
OR3T206BA352I-DB 6 PBGA 352 I DB
OR3T30 OR3T306S208I-DB 6 SQFP 208 I DB
OR3T306S240I-DB 6 SQFP 240 I DB
OR3T55 OR3T556PS208I-DB 6 SQFP2 208 I DB
OR3T556PS240I-DB 6 SQFP2 240 I DB
OR3T806BC432I-DB 6 EBGA 432 I DB

Data Sheet
Table 80. Index Master Parallel Mode 92

Master Serial Mode 93
A Microprocessor Interface (MPI) Mode 94
Absolute Maximum Ratings 100 Slave Parallel Mode 97
AND-OR-INVERT (AOI) 7 Slave Serial Mode 97
AND-OR-INVERT (AOI) (see also Supplemental Logic Data Format 89
Interconnect Cell (SLIC)) 1 Data Frame 89
Architecture Using ORCA Foundry to Generate RAM Data 89
Overview 7–10 FPGA States of Operation
Configuration 86
B Initialization 85
Bidirectional Buffers (BIDIs) (see Routing) Other Configuration Options 88
Bit Stream Error Checking 91 Partial Reconfiguration 88
Boundary Scan (see Special Function Blocks) Reconfiguration 88
Start-Up 87
C
Clock Control (CLKCNTRL) (see Special Function I
Blocks) IEEE Standard 1149 57, 61
Clock Distribution Network 50–53 Initialization (see FPGA States of Operation)
CLKCNTRL 52 Input/Output Buffers
ExpressCLK 50 Measurement Conditions 143
Inputs 53 Output Buffer Characteristics
Fast Clock 50, 53 OR3Cxx 143
Global Control Signals 50 OR3Txxx 145
In the PICs
ExpressCLK 52 L
System Clock 52 Look-Up Table (LUT) Operating Modes 13–20
In the PLC Array Adder-Subtractor Submode 17
Fast Clock 51 Counter Submode 17
System Clock 51 Equality Comparators 18
PFU Clock Sources 50 Half-Logic Mode 16
Selecting Clock Input Pins 53 Logic Mode 14
System Clock 50 Memory Mode 19
To the PLC Array Multiplier Submode 18
Fast Clock 52 Ripple Mode 16
System Clock 52
Configuration (see FPGA States of Operation or FPGA M
Configuration) Maximum Ratings (see Absolute Maximum Ratings)
Microprocessor Interface (MPI) 64–71
D i960 System 66
Demultiplexing (see PICs, Input Demultiplexing) 40 Interface to FPGA 67
PowerPC System 65
E Multiplexing (see Output Multiplexing)
Electrical Characteristics 101, 102
ExpressCLK 1 O
ExpressCLK (see Clock Distribution Network) 50 ORCA Foundry Development System 27
Overview 9
F Output Multiplexing 41
Fast Clock (see Clock Distribution Network)
5 V Tolerant I/O 37 P
Flexible Input Structure (FINS) 1, 29 PAL (see also Supplemental Logic and Interconnect
FPGA Configuration Cell (SLIC)) 1
Configuration Modes 92 PIC Routing (see Routing)
Asynchronous Peripheral Mode 94 Pin Information
Daisy-Chaining 98 432-Pin EBGA Pinout 182, 183, 184, 185, 186, 187,

Data Sheet
188, 189, 190, 191, 192, 193 Clock (and Global CE and LSR) Routing Segments
Package Compatibility ??–154 33
Pin Descriptions 149, 153 Configurable Interconnect Points (CIPs) 27
Power DIssipation Control Signal and Fast-Carry Routing 30
OR3Txxx 147 Flexible Input Structure (FINS) 29
Power Dissipation 146–?? Inter-PLC Routing Resources 31
OR3Cxx 146 Interquad Routing 47
Programmable Clock Manager (PCM) ??–84 Minimizing Routing Delay 33
Clock Delay 76 Overview 8
Clock Multiplication 77 PFU Output Switching 29
DLL Mode 75 PIC Interquad (MID) Routing 49
PCM Cautions 84 Programmable Corner Cell Routing 48
PCM Detailed Programming 80 SLIC Connectivity 30
PCM Operation 79 Switching Routing Segments (xSW) 29
PCM/FPGA Internal Interface 79
PLL Mode 76 S
Registers 73 Soft-wired LUTs (see also Look-Up Table Operating
Programmable Function Unit (PFU) 11 Modes)
Twin-quad Architecture 1, 9, 16, 21 Soft-wired LUTs (SWLs) 1, 9, 14, 15
Programmable Input/Output Cells (PICs) 36–46 Special Function Blocks
5 V Tolerant I/O 37 Boundary Scan ??–63
Architecture 45 Boundary-Scan Cells 62
Control Inputs 13, 25 Boundary-Scan Timing 63
ASWE 13 Single Function Blocks 54
CE 13 Clock Control (CLKCNTRL) 56
CLK 13 Global 3-State Control (TS_ALL) 55
GSRN 13, 26 Global Set/Reset (GSRN) 55
LSR 13 Internal Oscillator 55
SEL 13 Readback Logic 54
Input Demultiplexing 40 Start-Up Logic 56
Inputs 38 Start-Up (see FPGA States of Operation)
Output Multiplexing 41 Supplemental Logic and Interconnect Cell (SLIC) 1, 21–
Outputs 41 24
Open-Drain Output Option 41 System Clock (see Clock Distribution Network) 50
Propagation Delays 41
Overview 36 T
PIO 36 Timing Characteristics
PIO Logic 43 Clock Timing 123
PIO Options 37 Derating 103
PIO Register Control Signals 43 Description 103
Zero-Hold Input 39 General Configuration Mode Timing 133, 134
Programmable Logic Cells (PLCs) 11–35 PFU Timing 104
Architecture 34 PIO Timing 112, 114
Latches/Flip-Flops 25, 26 PLC Timing 111
Routing 27 Readback Timing 142
Propagation Delays (see PICs, Outputs) Tolerant I/O (see 5 V Tolerant I/O) 37
Twin-quad Architecture (see PFU) 1
R
RAM (see also FPGA Configuration) 89
Dual-port 6, 13, 20
Single-port 6, 13, 20
Recommended Operating Conditions 100
Reconfiguration (see FPGA States of Operation)
Routing
3-Statable Bidirectional Buffers 27
BIDI Routing 27, 30

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Data Sheet

ORCA® Series 3C and 3T

Table 1. ORCA Series 3 (3C and 3T) FPGAs

Features ......................................................................1 PCM Cautions ........................................................ 84

■ Parallel readback of configuration data capability with

Table 2. ORCA Series 3 System Performance

Description PLC Logic

Description (continued) innovative programmable clock manager. These func-

Description (continued) The OR3T55 array in Figure 1 has PLCs arranged in

Figure 1. OR3T55 Array

Programmable Logic Cells

static random access memory (SRAM) and can be used

Each latch/FF can accept data from its associated LUT.

Programmable Logic Cells (continued)

Figure 3. Simplified PFU Diagram

Programmable Logic Cells (continued)

Look-Up Table Operating Modes

Table 3. Look-Up Table Operating Modes

PFU Control Inputs

Programmable Logic Cells (continued)

Mode CLK LSR CE ASWE SEL

at the LUTs associated latch/FF, or multiplexed with the

Programmable Logic Cells (continued)

F4 4-INPUT LUT F5 5-INPUT LUT

Figure 5. Softwired LUT Topology Examples

In the following discussions, the notations LUT K7/K3

Programmable Logic Cells (continued)

carry-in is to be propagated to the carry-out of the cur- F7

mented by one for a down counter. If an up/down

Programmable Logic Cells (continued)

PFU can affect an 8 x 1 bit (4 x 1 for half-ripple mode)

If larger than 8 bits, the carry-out signal can be cas-

Table 5. Ripple Mode Equality Comparator

Equality ORCA Foundry True, if

Programmable Logic Cells (continued)

Figure 9. Memory Mode

PFU PFU PFU PFU

SLIC SLIC SLIC SLIC

Figure 10. Memory Mode Expansion Example—128 x 8 RAM

Programmable Logic Cells (continued)

BRI7 BRI7 BL07

BRI6 BL06 BRI6 BL06

BRI2 BL02 BRI3 BL03

Figure 12. Buffer Mode

Programmable Logic Cells (continued)

BLI9 BRI8 BL08

BRI3 BL03 BRI3 BL03

BRI2 BL02 BRI2 BL02

BRI1 BL01 BRI1 BL01

BRI0 BL00 BRI0 BL00

Figure 13. Buffer-Buffer-Decoder Mode

Programmable Logic Cells (continued)

HIGH Z WHEN LOW

BRI1 BL01 BLI2

BRI0 BL00 BLI1

CE/ASWE SEL CE/ASWE

Key: C = configuration data.

Programmable Logic Cells (continued)

PLC Routing Resources INDEPENDENT CIP