Preliminary Product Brief

November 1997

Optimized Reconfigurable Cell Array (ORCA®)

OR3Cxxx/OR3Txxx Series Field-Programmable Gate Arrays

Features ■ Abundant hierarchical routing resources based on rout-

ing two data nibbles and two control lines per set provide
for faster place and route implementations and less rout-
■ High-performance, cost-effective, 0.35 µm 4-level metal ing delay.
technology, with a migration plan to 0.25 µm technology
(4- or 5-input look-up table delay of 1.7 ns with ■ TTL or CMOS input levels programmable per pin for the
-5 speed grade in 0.35 µm). OR3Cxxx (5.0 V) devices.
■ Up to 186,000 usable gates in 0.35 µm, expanding to ■ Individually programmable drive capability: 12 mA sink/
320,000 usable gates in 0.25 µm. 6 mA source or 6 mA sink/3 mA source.
■ Up to 452 user I/Os in 0.35 µm. (OR3Txxx I/Os are 5 V ■ Built-in boundary scan (IEEE† 1149.1 JTAG) and 3-state
tolerant to allow interconnection to both 3.3 V and 5 V all I/O pins (TS_ALL) testability functions.
devices, selectable on a per-pin basis.) ■ Enhanced system clock routing for low-skew, high-speed
■ New twin-quad programmable function unit (PFU) archi- clocks originating on-chip or at any I/O.
tecture with eight 16-bit look-up tables (LUTs) per PFU, ■ Up to four new ExpressCLK inputs allow extremely fast
organized in two nibbles for use in nibble- or byte-wide clocking of signals on- and off-chip plus access to inter-
functions. Allows for mixed arithmetic and logic functions nal general clock routing.
in a single PFU. ■ New StopCLK feature to glitchlessly stop/start the
■ Nine user registers per PFU, one following each LUT, ExpressCLKs independently by user command.
plus one extra. All have programmable clock enable and ■ New programmable I/O (PIO) has:
local set/reset, plus a global set/reset that can be dis- — Fast-capture input latch and input flip-flop (FF)/latch
abled per PFU.
for reduced input setup time and zero hold time.
■ New Flexible INput Structure (FINS) of the PFUs pro- — Capability to (de)multiplex I/O signals.
vides a routability enhancement for LUTs with shared — Fast access to SLIC for decodes and PAL-like func-
inputs and the logic flexibility of LUTs with independent
tions.
inputs.
— Output FF and two-signal function generator to
■ Fast-carry logic and routing to adjacent PFUs for nibble-, reduce CLK to output propagation delay.
byte-wide, or longer arithmetic functions, with the new
— Fast open-drain drive capability
option to register the PFU carry-out.
■ New soft-wired LUTs (SWL) allow fast cascading of up to
three levels of LUT logic in a single PFU for up to 40% * PAL is a trademark of Advanced Micro Devices, Inc.
speed improvement (-5 speed grade). † IEEE is a registered trademark of The Institute of Electrical and
■ New supplemental logic and interconnect cell (SLIC) Electronics Engineers, Inc.
provides 3-statable buffers, up to 10-bit decoder, and
PAL*-like AND-OR-INVERT (AOI) in each programmable
logic cell (PLC).

Table 1. Lucent Technologies’ ORCA OR3Cxxx/OR3Txxx Series FPGAs

Usable Process
Device Registers Max User RAM User I/Os Array Size
Gates‡ Technology
OR3C/3T30 24K—48K 2212 25K 228 14 x 14 0.35 µm/4 LM
OR3C/3T55 40K—80K 3492 41K 292 18 x 18 0.35 µm/4 LM
OR3C/3T80 58K—116K 5060 62K 356 22 x 22 0.35 µm/4 LM
OR3T125 92K—186K 7952 100K 452 28 x 28 0.25 µm/4 LM
OR3T165 120K—244K 10240 131K 516 32 x 32 0.25 µm/4 LM
OR3T225 166K—340K 14212 185K 612 38 x 38 0.25 µm/4 LM
‡ The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and
12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast capture latch, output logic,
CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512
gates) per PFU.
 Preliminary Product Brief
ORCA OR3Cxxx/OR3Txxx Series FPGAs November 1997

System-Level Features ■ New programmable clock manager (PCM) adjusts

clock phase and duty cycle for input clock rates from
System-level features reduce glue logic requirements 5 MHz to 80 MHz. The PCM may be combined with
and make a system on a chip possible. These features FPGA logic to create complex functions, such as dig-
in the ORCA OR3C/Txxx include: ital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers or clock doublers. Two
■ Full PCI Local Bus compliance PCMs are provided per device.
■ New dual-use microprocessor interface (MPI) can be ■ True internal 3-state, bidirectional buses with simple
used for configuration, readback, device control, and control provided by the new SLIC.
device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to i960 * and ■ 32 x 4 RAM per PFU, configurable as single- or dual-
PowerPC† processors with user-configurable port at >170 MHz (-5 speed). Create large, fast RAM/
address space provided. ROM blocks (128 x 8 in only eight PFUs) using the
new SLIC decoders as bank drivers.
■ New parallel readback of configuration data capabil-
ity with the built-in microprocessor interface. * i960 is a trademark of Intel Corporation.
† PowerPC is a registered trademark of International Business
Machines Corporation.

Table 2. ORCA OR3C/Txxx System Performance

Speed
Parameter # PFUs Unit
-4 -5 -6
16-bit Loadable Up/Down Counter 2 86 113 153 MHz
16-bit Accumulator 2 86 113 153 MHz
8 x 8 Parallel Multiplier:
Multiplier Mode, Unpipelined1 11.5 24 32 42 MHz
ROM Mode, Unpipelined2 8 60 81 108 MHz
Multiplier Mode, Pipelined3 15 112 166 250 MHz
32 x 16 RAM (synchronous):
Single-port, 3-state Bus4 4 126 175 235 MHz
Dual-port5 4 126 177 245 MHz
128 x 8 RAM (synchronous):
Single-port, 3-state Bus4 8 126 174 229 MHz
Dual-port5 8 126 174 229 MHz
8-bit Address Decode (internal):
Using Soft-wired LUTs 0.25 4.56 3.43 2.53 ns
Using SLICs6 0 2.21 1.72 1.29 ns
32-bit Address Decode (internal):
Using Soft-wired LUTs 2 14.75 11.13 8.11 ns
Using SLICs7 0 5.62 4.33 3.29 ns
36-bit Parity Check (internal) 2 14.75 11.13 8.11 ns
1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 x 4 RAMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 PFUs contain only pipelining registers).
4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 x 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
Note: Shaded values are advance information and apply only to OR3Txxx devices.

2 Lucent Technologies Inc.

Preliminary Product Brief
November 1997 ORCA OR3Cxxx/OR3Txxx Series FPGAs

Support The PFU is organized in a twin-quad fashion: two sets

of four LUTs and FFs that can be controlled indepen-
■ ORCA Foundry Development System support. dently. LUTs may also be combined for use in arith-
■ Supported by industry-standard CAE tools for design metic functions using fast-carry chain logic in either
entry, synthesis, simulation, and timing analysis. 4-bit or 8-bit modes. The carry-out of either mode may
be registered in the ninth FF for pipelining. Each PFU
may also be configured as a synchronous 32 x 4
Description single- or dual-port RAM or ROM. The FFs (or latches)
may obtain input from LUT outputs or directly from
invertible PFU inputs, or they can be tied high or tied
FPGA Overview low. The FFs also have programmable clock polarity,
clock enables, and local set/reset.
The ORCA OR3C/Txxx FPGAs are a new generation
of SRAM-based FPGAs built on the successful OR2C/ The SLIC is connected to PLC routing resources and to
TxxA FPGA Series from Lucent Technologies Micro- the outputs of the PFU. It contains 3-state, bidirectional
electronics Group, with enhancements and innovations buffers and logic to perform up to a 10-bit AND function
geared toward today’s high-speed designs and tomor- for decoding, or an AND-OR with optional INVERT to
row’s systems on a single chip. Designed from the start perform PAL-like functions. The 3-state drivers in the
to be synthesis friendly and to reduce place and route SLIC and their direct connections to the PFU outputs
times while maintaining the complete routability of the make fast, true 3-state buses possible within the
ORCA 2C/2T devices, the OR3C/Txxx Series more FPGA, reducing required routing and allowing for real-
than doubles the logic available in each logic block and world system performance.
incorporates system-level features that can further
reduce logic requirements and increase system speed.
ORCA OR3C/Txxx devices contain many new patented PIC Logic
enhancements and are offered in a variety of pack-
ages, speed grades, and temperature ranges. The OR3C/Txxx PIC addresses the demand for ever-
increasing system clock speeds. Each PIC contains
The ORCA OR3C/Txxx Series FPGAs consist of three four programmable inputs/outputs (PIOs) and routing
basic elements: programmable logic cells (PLCs), pro- resources. On the input side, each PIO contains a fast
grammable input/output cells (PICs), and system-level capture latch that is clocked by an ExpressCLK. This
features. An array of PLCs is surrounded by PICs. latch is followed by a latch/FF that is clocked by a sys-
Each PLC contains a programmable function unit tem clock from the internal general clock routing. The
(PFU), a supplemental logic and interconnect cell combination provides for very low setup requirements
(SLIC), local routing resources, and configuration and zero hold times for signals coming on-chip. It may
RAM. Most of the FPGA logic is performed in the PFU also be used to demultiplex an input signal, such as a
(see Figure 1), but decoders, PAL-like functions, and multiplexed address/data signal, and register the sig-
3-state buffering can be performed in the SLIC (see nals without explicitly building a demultiplexer. Two
Figure 2). The PICs provide device inputs and outputs input signals are available to the PLC array from each
and can be used to register signals and to perform PIO, and the ORCA 2C/2T capability to use any input
input demultiplexing, output multiplexing, and other pin as a clock or other global input is maintained.
functions on two output signals (see Figure 3). Some of
the system-level functions include the new micropro- On the output side of each PIO, two outputs from the
cessor interface (MPI) and the programmable clock PLC array can be routed to each output flip-flop, and
manager (PCM). logic can be associated with each I/O pad. The output
logic associated with each pad allows for multiplexing
of output signals and other functions of two output sig-
PLC Logic nals.
The output FF, in combination with output signal multi-
Each PFU within a PLC contains eight 4-input (16-bit) plexing, is particularly useful for registering address
look-up tables (LUTs), eight latches/flip-flops (FFs), signals to be multiplexed with data, allowing a full clock
and one additional flip-flop that may be used indepen- cycle for the data to propagate to the output. The I/O
dently or with arithmetic functions. buffer associated with each pad is very similar to the
ORCA 2C/2T Series buffer with a new, fast, open-drain
option for ease of use on system buses.

Lucent Technologies Inc. 3

 Preliminary Product Brief
ORCA OR3Cxxx/OR3Txxx Series FPGAs November 1997

Description (continued)
F7
F5D REG7
0 Q7
DIN7 D0
K7_0 K7 D1
A 0 DSEL
K7_1 CE
B CK
K7_2 S/R
C F6
K7_3
D
REG6 Q6
K6_0 K6 DIN6 D0
A 0 D1
K6_1 DSEL
B CE
K6_2
C CK
K6_3 S/R
D
F5MODE67 F5

K5 REG5
K5_0 DIN5 Q5
A D0
K5_1 0 D1
B DSEL
K5_2
C CE
K5_3 CK
D
S/R
K4
K4_0
A
K4_1
B F4
K4_2
C
K4_3
D REG4
DIN4 Q4
D0
F5C 0 D1
F5MODE45 DSEL
0 CE
CK
CLK S/R
0
SEL
0
CIN COUT
0
CE
1
1 FF8
REGCOUT
D
ASWE CE
1 1 CK
S/R

1
0

LSR 0
0
0
F3
F5B REG3
0 DIN3 D0 Q3
K3_0 K3 D1
A 0 DSEL
K3_1 CE
B CK
K3_2 S/R
C F2
K3_3
D
REG2
K2_0 K2 DIN2 D0 Q2
K2_1 A 0 D1
B DSEL
K2_2 CE
C CK
K2_3 S/R
D F5MODE23
F1

K1 REG1
K1_0 DIN1 Q1
A D0
K1_1 D1
B 0 DSEL
K1_2
C CE
K1_3 CK
D
S/R
K0
K0_0
A
K0_1
B F0
K0_2
C
K0_3
D REG0
DIN0 Q0
D0
F5A 0 D1
F5MODE01 DSEL
0 CE
CK
S/R 5-5743
Note: All multiplexers without select inputs are configuration selector multiplexers.

Figure 1. Simplified PFU Diagram

4 Lucent Technologies Inc.
Preliminary Product Brief
November 1997 ORCA OR3Cxxx/OR3Txxx Series FPGAs

Description (continued)
BRI9 BL09
I9
BR09
BLI9

BRI8 BL08
I8
BR08
BLI8

BRI7 BL07
I7
BR07
BLI7

BRI6 BL06
I6
BR06
BLI6

BRI5 BL05
I5
BR05
BLI5
DEC
BRI4 BL04
I4
BR04
BLI4

TRI

0/1 0/1

DEC
HIGH Z WHEN LOW

0/1

0/1
BRI3 BL03
I3
BR03
BLI3

BRI2 BL02
I2
BR02
BLI2

BRI1 BL01
I1
BR01
BLI1

BRI0 BL00
I0
BR00
BLI0
5-5744

Figure 2. SLIC All Modes Diagram

Lucent Technologies Inc. 5

 Preliminary Product Brief
ORCA OR3Cxxx/OR3Txxx Series FPGAs November 1997

Description (continued) Routing

System Features The abundant routing resources of the ORCA 3C/3T

FPGAs are organized to route signals individually or as
The OR3C/Txxx Series also provides system-level buses with related control signals. Clocks are routed on
functionality by means of its dual-use microprocessor a low-skew, high-speed distribution network and may
interface (MPI) and its innovative programmable clock be sourced from PLC logic, externally from any I/O
manager (PCM). These functional blocks allow for easy pad, or from the very fast ExpressCLK pins. Express-
glueless system interfacing and the capability to adjust CLKs may be glitchlessly and independently enabled
to varying conditions in today’s high-speed systems. and disabled with a programmable control signal using
the new StopCLK feature. The improved PIC routing
The MPI provides a glueless interface between the resources are now similar to the patented intra-PLC
FPGA and PowerPC and i960 microprocessors. It can routing resources and provide great flexibility in moving
be used for configuration and readback, as well as for signals to and from the PIOs. This flexibility translates
monitoring FPGA status. The MPI also provides a gen- into an improved capability to route designs at the
eral-purpose microprocessor interface to the FPGA required speeds when the I/O signals have been
user-defined logic following configuration. locked to specific pins.
Two PCMs are provided on each ORCA 3C/T device.
Each PCM can be used to manipulate the frequency,
phase, and duty cycle of a clock signal. Clocks may be Configuration
input from the dedicated corner ExpressCLK input (in
the same corner as the PCM block) or from general The FPGA’s functionality is determined by internal con-
routing. Output clocks from the PCM can be sent to the figuration RAM. The FPGA’s internal initialization/con-
system clock spines, and/or to the ExpressCLK and figuration circuitry loads the configuration data at
Fast Clock spines on the edges of the device adjacent powerup or under system control. The RAM is loaded
to the PCM. ExpressCLK/Fast Clock and system clock by using one of several configuration modes. The con-
output frequencies can differ by up to a factor of 8 to figuration data resides externally in an EEPROM or any
allow slow I/O clocking with fast internal processing (or other storage media. Serial EEPROMs provide a sim-
vice versa). Each PCM is capable of manipulating ple, low pin count method for configuring FPGAs. A
clocks from 5 MHz to 80 MHz. Frequencies can be new, easy method for configuring the devices is
adjusted from 1/8x to 64x the input clock frequency, through the microprocessor interface.
and duty cycles and phase delays can be adjusted
from 3.125% to 96.875%.

PIO LOGIC
AND
NAND
OR
NOR
XOR
XNOR
PMUX PULL-DOWN

OUT1OUTREG UP
OUT2OUTREG DOWN CLKIN
OUT1 OUT1OUT2 NONE
D0
0 PD D Q D1 Q IN1
TO ROUTING

PAD
FROM ROUTING

OUT2 ECLK NORMAL CK

TS SCLK INVERTED CK
0 LEVEL MODE
ECLK 1 SP
D Q TTL SD
SCLK CK BUFFER MODE CMOS 1 INREGMODE LSR
SP RESET
CE LATCHFF
LSR SET FAST RESET
LATCH
SLEW SET
1 FF
SINK IN2
LSR
CE_OVER_LSR
LSR_OVER_CE
0 ASYNC

ENABLE_GSR
DISABLE_GSR
5-5805

Figure 3. OR3Cxx Programmable Input/Output (PIO) Image from ORCA Foundry

6 Lucent Technologies Inc.
Preliminary Product Brief
November 1997 ORCA OR3Cxxx/OR3Txxx Series FPGAs

Description (continued) Timing and simulation output files from ORCA Foundry
are also compatible with many third-party analysis
ORCA Foundry Development System tools. Its bit stream generator is then used to generate
the configuration data which is loaded into the FPGA’s
The ORCA Foundry Development System is used to internal configuration RAM.
process a design from a netlist to a configured FPGA. When using the bit stream generator, the user selects
This system is used to map a design onto the ORCA options that affect the functionality of the FPGA. Com-
architecture and then place and route it using ORCA bined with the front-end tools, ORCA Foundry pro-
Foundry’s timing-driven tools. The development system duces configuration data that implements the various
also includes interfaces to, and libraries for, other popu- logic and routing options discussed in this product
lar CAE tools for design entry, synthesis, simulation, brief.
and timing analysis.
The ORCA Foundry Development System interfaces to
front-end design entry tools and provides the tools to
Additional Information
produce a configured FPGA. In the design flow, the
Contact your local Lucent Technologies’ representative
user defines the functionality of the FPGA at two points
for additional information regarding the ORCA
in the design flow: at design entry and at the bit stream
OR3Cxxx/OR3Txxx FPGA devices, or visit our website.
generation stage.
Following design entry, the development system’s map,
place, and route tools translate the netlist into a routed
FPGA. A static timing analysis tool is provided to deter-
mine device speed and a back-annotated netlist can be
created to allow simulation.

Lucent Technologies Inc. 7

 Preliminary Product Brief
ORCA OR3Cxxx/OR3Txxx Series FPGAs November 1997

Ordering Information
Example: OR3C80-4 PS 240
DEVICE TYPE TEMPERATURE RANGE
SPEED GRADE NUMBER OF PINS
PACKAGE TYPE

OR3C80, -4 Speed Grade, 240-pin Power Quad Shrink Flat Package (SQFP2), Commercial Temperature.

Table 3. Voltage Options

Device Voltage
OR3Cxx 5.0
OR3Txxx 3.3

Table 4. Temperature Options

Symbol Description Temperature

(Blank) Commercial 0 °C to 70 °C
I Industrial –40 °C to +85 °C

Table 5. Package Options

Symbol Description
BA Plastic Ball Grid Array (PBGA)
BC Enhanced Ball Grid Array (EBGA)
PS Power Quad Shrink Flat Package (SQFP2)

Table 6. ORCA OR3C/Txxx Series Package Matrix

208-Pin 240-Pin 256-Pin 352-Pin 432-Pin 600-Pin
Packages EIAJ/SQFP2 EIAJ/SQFP2 PBGA PBGA EBGA EBGA
PS208 PS240 BA256 BA352 BC432 BC600
OR3C/T55 CI CI CI CI — —
OR3C/T80 CI CI — CI CI CI
OR3T125 CI CI — — CI CI
Key: C = commercial, I = industrial.

For FPGA technical applications support, please call 1-800-327-9374 or e-mail orcafpga@lucent.com. Outside North America, please call 1-610-712-4331.
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET: http://www.lucent.com/micro/fpga
E-MAIL: docmaster@micro.lucent.com
U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Bracknell),
FRANCE: (33) 1 41 45 77 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki),
ITALY: (39) 2 6601 1800 (Milan), SPAIN: (34) 1 807 1441 (Madrid)

Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information. ORCA is a registered trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc.

Copyright © 1997 Lucent Technologies Inc.

All Rights Reserved
Printed in U.S.A.

November 1997
PN98-012FPGA (Replaces PN96-208FPGA)
Printed On
Recycled Paper