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Module #04 - Operators

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Module #04 - Operators

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gyan
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© © All Rights Reserved
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Module #04 : Verilog HDL Operators

4.1: Arithmetic Operator:


- These perform arithmetic operations.
- The + and - can be used as either unary (-z) or binary (x-y) operators

Operators:
+ (addition) Example 4.1:
- (subtraction)
* (multiplication) c = a + b;
/ (division) d = a – b;
% (modulus) count = (count + 1) % 16 ;

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 1


Module #04 : Verilog HDL Operators

4.2: Relational Operator:


- Relational operators compare two operands and return a single bit 1or 0.
- These operators synthesize into comparators.
- Wire and reg variables are positive. Thus (-3’b001) = = 3’b111 and (-3d001)>3’b110.
- However for integers -1< 6
Example 4.2:
Operators:
if (x = = y)
< (less than) e = 1;
<= (less than or equal to) else
> (greater than) e = 0;
>= (greater than or equal to)
== (equal to) Equivalent Statement -
!= (not equal to) e = (x == y);

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 2


Module #04 : Verilog HDL Operators

4.3: Bit-wise Operator:


- Bit-wise operators do a bit-by-bit comparison between two operands.

Operators: Example 4.3:

~ (bitwise NOT) module and2(a, b, c);


& (bitwise AND) input a;
| (bitwise OR) input b;
^ (bitwise XOR) output c;
~^ or ^~(bitwise XNOR) assign c = a & b;
endmodule

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 3


Module #04 : Verilog HDL Operators

4.4: Logical Operator:


- Logical operators return a single bit 1 or 0. They are the same as bit-wise operators only for
single bit operands.
- They can work on expressions, integers or groups of bits, and treat all values that are nonzero as “1”.
- Logical operators are typically used in conditional (if ... else) statements since they work with expressions.

Operators: Example 4.4:

! (logical NOT) wire[7:0] x, y, z; // x, y and z are multibit variables.


&& (logical AND) reg a;
|| (logical OR) if ((x == y) && (z))
a = 1; // a = 1 if x equals y, and z is nonzero.
else a = !x; // a =0 if x is anything but nonzero

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 4


Module #04 : Verilog HDL Operators

4.5: Reduction Operator:


- Reduction operators operate on all the bits of an operand vector and return a single-bit value. These are the
unary (one argument) form of the bit-wise operators.

Operators: Example 4.5:

& (reduction AND) module chk_zero (a, z);


| (reduction OR) input [2:0] a;
~& (reduction NAND) output z;
~| (reduction NOR) assign z = ~| a; // Reduction NOR
^ (reduction XOR) endmodule
~^ or ^~ (reduction XNOR)

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 5


Module #04 : Verilog HDL Operators

4.6: Shift Operator:


- Shift operators shift the first operand by the number of bits specified by the second operand. Vacated
positions are filled with zeros for both left and right shifts (There is no sign extension).

Operators: Example 4.6:

<< (shift left) assign c = a << 2; /* c = a shifted left 2 bits; vacant positions are
>> (shift right) filled with 0’s */

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 6


Module #04 : Verilog HDL Operators

4.7: Concatenation Operator:


- The concatenation operator combines two or more operands to form a larger vector.

Operators: Example 4.7:

{ }(concatenation) wire [1:0] a, b;


wire [2:0] x;
wire [3;0] y, Z;
Wire [2:0]count;
assign x = {1’b0, a}; // x[2]=0, x[1]=a[1], x[0]=a[0]
assign y = {a, b}; /* y[3]=a[1], y[2]=a[0], y[1]=b[1], y[0]=b[0] */

assign {count, y} = x + Z; // Concatenation of a result

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 7


Module #04 : Verilog HDL Operators

4.8: Replication Operator:


- The replication operator makes multiple copies of an item

Operators: Example 4.8:

{n{item}} (n fold replication of an item) wire [1:0] a, b; wire [5:0] x, y, z;


assign x = {4{1’b0}, a}; // Equivalent to x = {0,0,0,0,a }
assign y = {2{a}, {b}}; //Equivalent to y = {a, a, b}
assign z = {6{1’b1}};

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 8


Module #04 : Verilog HDL Operators

4.9: Conditional Operator: “?”


- Conditional operator is like those in C/C++. They evaluate one of the two expressions based on a
condition.
- It will synthesize to a multiplexer (MUX).
- Operated on 3 operands (Ternary Operator)

Operators: Example 4.9:

(condition) ? (result if condition true): assign a = (g) ? x : y;


(result if condition false) assign a = (inc = = 2) ? a+1 : a-1;
/* if (inc), a = a+1, else a = a-1 */

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 9


Module #04 : Verilog HDL Operators

4.10: Operator Precedence:


- Table Below shows the precedence of operators from highest to lowest.
- Operators on the same level evaluate from left to right.
- It is strongly recommended to use parentheses to define order of precedence and improve the readability
of your code.

26-11-2022 VLSI Excellence - Gyan Chand Dhaka 10

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